1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "core_types.h"
27 #include "clk_mgr_internal.h"
28 #include "rv1_clk_mgr.h"
29 #include "dce100/dce_clk_mgr.h"
30 #include "dce112/dce112_clk_mgr.h"
31 #include "rv1_clk_mgr_vbios_smu.h"
32 #include "rv1_clk_mgr_clk.h"
33
rv1_init_clocks(struct clk_mgr * clk_mgr)34 static void rv1_init_clocks(struct clk_mgr *clk_mgr)
35 {
36 memset(&(clk_mgr->clks), 0, sizeof(struct dc_clocks));
37 }
38
rv1_determine_dppclk_threshold(struct clk_mgr_internal * clk_mgr,struct dc_clocks * new_clocks)39 static int rv1_determine_dppclk_threshold(struct clk_mgr_internal *clk_mgr, struct dc_clocks *new_clocks)
40 {
41 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
42 bool dispclk_increase = new_clocks->dispclk_khz > clk_mgr->base.clks.dispclk_khz;
43 int disp_clk_threshold = new_clocks->max_supported_dppclk_khz;
44 bool cur_dpp_div = clk_mgr->base.clks.dispclk_khz > clk_mgr->base.clks.dppclk_khz;
45
46 /* increase clock, looking for div is 0 for current, request div is 1*/
47 if (dispclk_increase) {
48 /* already divided by 2, no need to reach target clk with 2 steps*/
49 if (cur_dpp_div)
50 return new_clocks->dispclk_khz;
51
52 /* request disp clk is lower than maximum supported dpp clk,
53 * no need to reach target clk with two steps.
54 */
55 if (new_clocks->dispclk_khz <= disp_clk_threshold)
56 return new_clocks->dispclk_khz;
57
58 /* target dpp clk not request divided by 2, still within threshold */
59 if (!request_dpp_div)
60 return new_clocks->dispclk_khz;
61
62 } else {
63 /* decrease clock, looking for current dppclk divided by 2,
64 * request dppclk not divided by 2.
65 */
66
67 /* current dpp clk not divided by 2, no need to ramp*/
68 if (!cur_dpp_div)
69 return new_clocks->dispclk_khz;
70
71 /* current disp clk is lower than current maximum dpp clk,
72 * no need to ramp
73 */
74 if (clk_mgr->base.clks.dispclk_khz <= disp_clk_threshold)
75 return new_clocks->dispclk_khz;
76
77 /* request dpp clk need to be divided by 2 */
78 if (request_dpp_div)
79 return new_clocks->dispclk_khz;
80 }
81
82 return disp_clk_threshold;
83 }
84
ramp_up_dispclk_with_dpp(struct clk_mgr_internal * clk_mgr,struct dc * dc,struct dc_clocks * new_clocks,bool safe_to_lower)85 static void ramp_up_dispclk_with_dpp(
86 struct clk_mgr_internal *clk_mgr,
87 struct dc *dc,
88 struct dc_clocks *new_clocks,
89 bool safe_to_lower)
90 {
91 int i;
92 int dispclk_to_dpp_threshold = rv1_determine_dppclk_threshold(clk_mgr, new_clocks);
93 bool request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz;
94
95 /* this function is to change dispclk, dppclk and dprefclk according to
96 * bandwidth requirement. Its call stack is rv1_update_clocks -->
97 * update_clocks --> dcn10_prepare_bandwidth / dcn10_optimize_bandwidth
98 * --> prepare_bandwidth / optimize_bandwidth. before change dcn hw,
99 * prepare_bandwidth will be called first to allow enough clock,
100 * watermark for change, after end of dcn hw change, optimize_bandwidth
101 * is executed to lower clock to save power for new dcn hw settings.
102 *
103 * below is sequence of commit_planes_for_stream:
104 *
105 * step 1: prepare_bandwidth - raise clock to have enough bandwidth
106 * step 2: lock_doublebuffer_enable
107 * step 3: pipe_control_lock(true) - make dchubp register change will
108 * not take effect right way
109 * step 4: apply_ctx_for_surface - program dchubp
110 * step 5: pipe_control_lock(false) - dchubp register change take effect
111 * step 6: optimize_bandwidth --> dc_post_update_surfaces_to_stream
112 * for full_date, optimize clock to save power
113 *
114 * at end of step 1, dcn clocks (dprefclk, dispclk, dppclk) may be
115 * changed for new dchubp configuration. but real dcn hub dchubps are
116 * still running with old configuration until end of step 5. this need
117 * clocks settings at step 1 should not less than that before step 1.
118 * this is checked by two conditions: 1. if (should_set_clock(safe_to_lower
119 * , new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz) ||
120 * new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz)
121 * 2. request_dpp_div = new_clocks->dispclk_khz > new_clocks->dppclk_khz
122 *
123 * the second condition is based on new dchubp configuration. dppclk
124 * for new dchubp may be different from dppclk before step 1.
125 * for example, before step 1, dchubps are as below:
126 * pipe 0: recout=(0,40,1920,980) viewport=(0,0,1920,979)
127 * pipe 1: recout=(0,0,1920,1080) viewport=(0,0,1920,1080)
128 * for dppclk for pipe0 need dppclk = dispclk
129 *
130 * new dchubp pipe split configuration:
131 * pipe 0: recout=(0,0,960,1080) viewport=(0,0,960,1080)
132 * pipe 1: recout=(960,0,960,1080) viewport=(960,0,960,1080)
133 * dppclk only needs dppclk = dispclk /2.
134 *
135 * dispclk, dppclk are not lock by otg master lock. they take effect
136 * after step 1. during this transition, dispclk are the same, but
137 * dppclk is changed to half of previous clock for old dchubp
138 * configuration between step 1 and step 6. This may cause p-state
139 * warning intermittently.
140 *
141 * for new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz, we
142 * need make sure dppclk are not changed to less between step 1 and 6.
143 * for new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz,
144 * new display clock is raised, but we do not know ratio of
145 * new_clocks->dispclk_khz and clk_mgr_base->clks.dispclk_khz,
146 * new_clocks->dispclk_khz /2 does not guarantee equal or higher than
147 * old dppclk. we could ignore power saving different between
148 * dppclk = displck and dppclk = dispclk / 2 between step 1 and step 6.
149 * as long as safe_to_lower = false, set dpclk = dispclk to simplify
150 * condition check.
151 * todo: review this change for other asic.
152 **/
153 if (!safe_to_lower)
154 request_dpp_div = false;
155
156 /* set disp clk to dpp clk threshold */
157
158 clk_mgr->funcs->set_dispclk(clk_mgr, dispclk_to_dpp_threshold);
159 clk_mgr->funcs->set_dprefclk(clk_mgr);
160
161
162 /* update request dpp clk division option */
163 for (i = 0; i < dc->res_pool->pipe_count; i++) {
164 struct pipe_ctx *pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
165
166 if (!pipe_ctx->plane_state)
167 continue;
168
169 pipe_ctx->plane_res.dpp->funcs->dpp_dppclk_control(
170 pipe_ctx->plane_res.dpp,
171 request_dpp_div,
172 true);
173 }
174
175 /* If target clk not same as dppclk threshold, set to target clock */
176 if (dispclk_to_dpp_threshold != new_clocks->dispclk_khz) {
177 clk_mgr->funcs->set_dispclk(clk_mgr, new_clocks->dispclk_khz);
178 clk_mgr->funcs->set_dprefclk(clk_mgr);
179 }
180
181
182 clk_mgr->base.clks.dispclk_khz = new_clocks->dispclk_khz;
183 clk_mgr->base.clks.dppclk_khz = new_clocks->dppclk_khz;
184 clk_mgr->base.clks.max_supported_dppclk_khz = new_clocks->max_supported_dppclk_khz;
185 }
186
rv1_update_clocks(struct clk_mgr * clk_mgr_base,struct dc_state * context,bool safe_to_lower)187 static void rv1_update_clocks(struct clk_mgr *clk_mgr_base,
188 struct dc_state *context,
189 bool safe_to_lower)
190 {
191 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
192 struct dc *dc = clk_mgr_base->ctx->dc;
193 struct dc_debug_options *debug = &dc->debug;
194 struct dc_clocks *new_clocks = &context->bw_ctx.bw.dcn.clk;
195 struct pp_smu_funcs_rv *pp_smu = NULL;
196 bool send_request_to_increase = false;
197 bool send_request_to_lower = false;
198 int display_count;
199
200 bool enter_display_off = false;
201
202 ASSERT(clk_mgr->pp_smu);
203
204 if (dc->work_arounds.skip_clock_update)
205 return;
206
207 pp_smu = &clk_mgr->pp_smu->rv_funcs;
208
209 display_count = clk_mgr_helper_get_active_display_cnt(dc, context);
210
211 if (display_count == 0)
212 enter_display_off = true;
213
214 if (enter_display_off == safe_to_lower) {
215 /*
216 * Notify SMU active displays
217 * if function pointer not set up, this message is
218 * sent as part of pplib_apply_display_requirements.
219 */
220 if (pp_smu->set_display_count)
221 pp_smu->set_display_count(&pp_smu->pp_smu, display_count);
222 }
223
224 if (new_clocks->dispclk_khz > clk_mgr_base->clks.dispclk_khz
225 || new_clocks->phyclk_khz > clk_mgr_base->clks.phyclk_khz
226 || new_clocks->fclk_khz > clk_mgr_base->clks.fclk_khz
227 || new_clocks->dcfclk_khz > clk_mgr_base->clks.dcfclk_khz)
228 send_request_to_increase = true;
229
230 if (should_set_clock(safe_to_lower, new_clocks->phyclk_khz, clk_mgr_base->clks.phyclk_khz)) {
231 clk_mgr_base->clks.phyclk_khz = new_clocks->phyclk_khz;
232 send_request_to_lower = true;
233 }
234
235 // F Clock
236 if (debug->force_fclk_khz != 0)
237 new_clocks->fclk_khz = debug->force_fclk_khz;
238
239 if (should_set_clock(safe_to_lower, new_clocks->fclk_khz, clk_mgr_base->clks.fclk_khz)) {
240 clk_mgr_base->clks.fclk_khz = new_clocks->fclk_khz;
241 send_request_to_lower = true;
242 }
243
244 //DCF Clock
245 if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
246 clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
247 send_request_to_lower = true;
248 }
249
250 if (should_set_clock(safe_to_lower,
251 new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
252 clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
253 send_request_to_lower = true;
254 }
255
256 /* make sure dcf clk is before dpp clk to
257 * make sure we have enough voltage to run dpp clk
258 */
259 if (send_request_to_increase) {
260 /*use dcfclk to request voltage*/
261 if (pp_smu->set_hard_min_fclk_by_freq &&
262 pp_smu->set_hard_min_dcfclk_by_freq &&
263 pp_smu->set_min_deep_sleep_dcfclk) {
264 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));
265 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));
266 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));
267 }
268 }
269
270 /* dcn1 dppclk is tied to dispclk */
271 /* program dispclk on = as a w/a for sleep resume clock ramping issues */
272 if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)
273 || new_clocks->dispclk_khz == clk_mgr_base->clks.dispclk_khz) {
274 ramp_up_dispclk_with_dpp(clk_mgr, dc, new_clocks, safe_to_lower);
275 clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
276 send_request_to_lower = true;
277 }
278
279 if (!send_request_to_increase && send_request_to_lower) {
280 /*use dcfclk to request voltage*/
281 if (pp_smu->set_hard_min_fclk_by_freq &&
282 pp_smu->set_hard_min_dcfclk_by_freq &&
283 pp_smu->set_min_deep_sleep_dcfclk) {
284 pp_smu->set_hard_min_fclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->fclk_khz));
285 pp_smu->set_hard_min_dcfclk_by_freq(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_khz));
286 pp_smu->set_min_deep_sleep_dcfclk(&pp_smu->pp_smu, khz_to_mhz_ceil(new_clocks->dcfclk_deep_sleep_khz));
287 }
288 }
289 }
290
rv1_enable_pme_wa(struct clk_mgr * clk_mgr_base)291 static void rv1_enable_pme_wa(struct clk_mgr *clk_mgr_base)
292 {
293 struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
294 struct pp_smu_funcs_rv *pp_smu = NULL;
295
296 if (clk_mgr->pp_smu) {
297 pp_smu = &clk_mgr->pp_smu->rv_funcs;
298
299 if (pp_smu->set_pme_wa_enable)
300 pp_smu->set_pme_wa_enable(&pp_smu->pp_smu);
301 }
302 }
303
304 static struct clk_mgr_funcs rv1_clk_funcs = {
305 .init_clocks = rv1_init_clocks,
306 .get_dp_ref_clk_frequency = dce12_get_dp_ref_freq_khz,
307 .update_clocks = rv1_update_clocks,
308 .enable_pme_wa = rv1_enable_pme_wa,
309 };
310
311 static struct clk_mgr_internal_funcs rv1_clk_internal_funcs = {
312 .set_dispclk = rv1_vbios_smu_set_dispclk,
313 .set_dprefclk = dce112_set_dprefclk
314 };
315
rv1_clk_mgr_construct(struct dc_context * ctx,struct clk_mgr_internal * clk_mgr,struct pp_smu_funcs * pp_smu)316 void rv1_clk_mgr_construct(struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu)
317 {
318 struct dc_debug_options *debug = &ctx->dc->debug;
319 struct dc_bios *bp = ctx->dc_bios;
320
321 clk_mgr->base.ctx = ctx;
322 clk_mgr->pp_smu = pp_smu;
323 clk_mgr->base.funcs = &rv1_clk_funcs;
324 clk_mgr->funcs = &rv1_clk_internal_funcs;
325
326 clk_mgr->dfs_bypass_disp_clk = 0;
327
328 clk_mgr->dprefclk_ss_percentage = 0;
329 clk_mgr->dprefclk_ss_divider = 1000;
330 clk_mgr->ss_on_dprefclk = false;
331 clk_mgr->base.dprefclk_khz = 600000;
332
333 if (bp->integrated_info)
334 clk_mgr->base.dentist_vco_freq_khz = bp->integrated_info->dentist_vco_freq;
335 if (bp->fw_info_valid && clk_mgr->base.dentist_vco_freq_khz == 0) {
336 clk_mgr->base.dentist_vco_freq_khz = bp->fw_info.smu_gpu_pll_output_freq;
337 if (clk_mgr->base.dentist_vco_freq_khz == 0)
338 clk_mgr->base.dentist_vco_freq_khz = 3600000;
339 }
340
341 if (!debug->disable_dfs_bypass && bp->integrated_info)
342 if (bp->integrated_info->gpu_cap_info & DFS_BYPASS_ENABLE)
343 clk_mgr->dfs_bypass_enabled = true;
344
345 dce_clock_read_ss_info(clk_mgr);
346 }
347
348
349