1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2 /* Copyright(c) 2019-2020 Realtek Corporation 3 */ 4 5 #include "cam.h" 6 #include "chan.h" 7 #include "debug.h" 8 #include "efuse.h" 9 #include "fw.h" 10 #include "mac.h" 11 #include "pci.h" 12 #include "ps.h" 13 #include "reg.h" 14 #include "util.h" 15 16 static const u32 rtw89_mac_mem_base_addrs_ax[RTW89_MAC_MEM_NUM] = { 17 [RTW89_MAC_MEM_AXIDMA] = AXIDMA_BASE_ADDR, 18 [RTW89_MAC_MEM_SHARED_BUF] = SHARED_BUF_BASE_ADDR, 19 [RTW89_MAC_MEM_DMAC_TBL] = DMAC_TBL_BASE_ADDR, 20 [RTW89_MAC_MEM_SHCUT_MACHDR] = SHCUT_MACHDR_BASE_ADDR, 21 [RTW89_MAC_MEM_STA_SCHED] = STA_SCHED_BASE_ADDR, 22 [RTW89_MAC_MEM_RXPLD_FLTR_CAM] = RXPLD_FLTR_CAM_BASE_ADDR, 23 [RTW89_MAC_MEM_SECURITY_CAM] = SECURITY_CAM_BASE_ADDR, 24 [RTW89_MAC_MEM_WOW_CAM] = WOW_CAM_BASE_ADDR, 25 [RTW89_MAC_MEM_CMAC_TBL] = CMAC_TBL_BASE_ADDR, 26 [RTW89_MAC_MEM_ADDR_CAM] = ADDR_CAM_BASE_ADDR, 27 [RTW89_MAC_MEM_BA_CAM] = BA_CAM_BASE_ADDR, 28 [RTW89_MAC_MEM_BCN_IE_CAM0] = BCN_IE_CAM0_BASE_ADDR, 29 [RTW89_MAC_MEM_BCN_IE_CAM1] = BCN_IE_CAM1_BASE_ADDR, 30 [RTW89_MAC_MEM_TXD_FIFO_0] = TXD_FIFO_0_BASE_ADDR, 31 [RTW89_MAC_MEM_TXD_FIFO_1] = TXD_FIFO_1_BASE_ADDR, 32 [RTW89_MAC_MEM_TXDATA_FIFO_0] = TXDATA_FIFO_0_BASE_ADDR, 33 [RTW89_MAC_MEM_TXDATA_FIFO_1] = TXDATA_FIFO_1_BASE_ADDR, 34 [RTW89_MAC_MEM_CPU_LOCAL] = CPU_LOCAL_BASE_ADDR, 35 [RTW89_MAC_MEM_BSSID_CAM] = BSSID_CAM_BASE_ADDR, 36 [RTW89_MAC_MEM_TXD_FIFO_0_V1] = TXD_FIFO_0_BASE_ADDR_V1, 37 [RTW89_MAC_MEM_TXD_FIFO_1_V1] = TXD_FIFO_1_BASE_ADDR_V1, 38 }; 39 rtw89_mac_mem_write(struct rtw89_dev * rtwdev,u32 offset,u32 val,enum rtw89_mac_mem_sel sel)40 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset, 41 u32 val, enum rtw89_mac_mem_sel sel) 42 { 43 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 44 u32 addr = mac->mem_base_addrs[sel] + offset; 45 46 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 47 rtw89_write32(rtwdev, mac->indir_access_addr, val); 48 } 49 rtw89_mac_mem_read(struct rtw89_dev * rtwdev,u32 offset,enum rtw89_mac_mem_sel sel)50 static u32 rtw89_mac_mem_read(struct rtw89_dev *rtwdev, u32 offset, 51 enum rtw89_mac_mem_sel sel) 52 { 53 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 54 u32 addr = mac->mem_base_addrs[sel] + offset; 55 56 rtw89_write32(rtwdev, mac->filter_model_addr, addr); 57 return rtw89_read32(rtwdev, mac->indir_access_addr); 58 } 59 rtw89_mac_check_mac_en_ax(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)60 static int rtw89_mac_check_mac_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 61 enum rtw89_mac_hwmod_sel sel) 62 { 63 u32 val, r_val; 64 65 if (sel == RTW89_DMAC_SEL) { 66 r_val = rtw89_read32(rtwdev, R_AX_DMAC_FUNC_EN); 67 val = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN); 68 } else if (sel == RTW89_CMAC_SEL && mac_idx == 0) { 69 r_val = rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN); 70 val = B_AX_CMAC_EN; 71 } else if (sel == RTW89_CMAC_SEL && mac_idx == 1) { 72 r_val = rtw89_read32(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND); 73 val = B_AX_CMAC1_FEN; 74 } else { 75 return -EINVAL; 76 } 77 if (r_val == RTW89_R32_EA || r_val == RTW89_R32_DEAD || 78 (val & r_val) != val) 79 return -EFAULT; 80 81 return 0; 82 } 83 rtw89_mac_write_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 val)84 int rtw89_mac_write_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 val) 85 { 86 u8 lte_ctrl; 87 int ret; 88 89 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 90 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 91 if (ret) 92 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 93 94 rtw89_write32(rtwdev, R_AX_LTE_WDATA, val); 95 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0xC00F0000 | offset); 96 97 return ret; 98 } 99 rtw89_mac_read_lte(struct rtw89_dev * rtwdev,const u32 offset,u32 * val)100 int rtw89_mac_read_lte(struct rtw89_dev *rtwdev, const u32 offset, u32 *val) 101 { 102 u8 lte_ctrl; 103 int ret; 104 105 ret = read_poll_timeout(rtw89_read8, lte_ctrl, (lte_ctrl & BIT(5)) != 0, 106 50, 50000, false, rtwdev, R_AX_LTE_CTRL + 3); 107 if (ret) 108 rtw89_err(rtwdev, "[ERR]lte not ready(W)\n"); 109 110 rtw89_write32(rtwdev, R_AX_LTE_CTRL, 0x800F0000 | offset); 111 *val = rtw89_read32(rtwdev, R_AX_LTE_RDATA); 112 113 return ret; 114 } 115 rtw89_mac_dle_dfi_cfg(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_ctrl * ctrl)116 int rtw89_mac_dle_dfi_cfg(struct rtw89_dev *rtwdev, struct rtw89_mac_dle_dfi_ctrl *ctrl) 117 { 118 u32 ctrl_reg, data_reg, ctrl_data; 119 u32 val; 120 int ret; 121 122 switch (ctrl->type) { 123 case DLE_CTRL_TYPE_WDE: 124 ctrl_reg = R_AX_WDE_DBG_FUN_INTF_CTL; 125 data_reg = R_AX_WDE_DBG_FUN_INTF_DATA; 126 ctrl_data = FIELD_PREP(B_AX_WDE_DFI_TRGSEL_MASK, ctrl->target) | 127 FIELD_PREP(B_AX_WDE_DFI_ADDR_MASK, ctrl->addr) | 128 B_AX_WDE_DFI_ACTIVE; 129 break; 130 case DLE_CTRL_TYPE_PLE: 131 ctrl_reg = R_AX_PLE_DBG_FUN_INTF_CTL; 132 data_reg = R_AX_PLE_DBG_FUN_INTF_DATA; 133 ctrl_data = FIELD_PREP(B_AX_PLE_DFI_TRGSEL_MASK, ctrl->target) | 134 FIELD_PREP(B_AX_PLE_DFI_ADDR_MASK, ctrl->addr) | 135 B_AX_PLE_DFI_ACTIVE; 136 break; 137 default: 138 rtw89_warn(rtwdev, "[ERR] dfi ctrl type %d\n", ctrl->type); 139 return -EINVAL; 140 } 141 142 rtw89_write32(rtwdev, ctrl_reg, ctrl_data); 143 144 ret = read_poll_timeout_atomic(rtw89_read32, val, !(val & B_AX_WDE_DFI_ACTIVE), 145 1, 1000, false, rtwdev, ctrl_reg); 146 if (ret) { 147 rtw89_warn(rtwdev, "[ERR] dle dfi ctrl 0x%X set 0x%X timeout\n", 148 ctrl_reg, ctrl_data); 149 return ret; 150 } 151 152 ctrl->out_data = rtw89_read32(rtwdev, data_reg); 153 return 0; 154 } 155 rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_quota * quota)156 int rtw89_mac_dle_dfi_quota_cfg(struct rtw89_dev *rtwdev, 157 struct rtw89_mac_dle_dfi_quota *quota) 158 { 159 struct rtw89_mac_dle_dfi_ctrl ctrl; 160 int ret; 161 162 ctrl.type = quota->dle_type; 163 ctrl.target = DLE_DFI_TYPE_QUOTA; 164 ctrl.addr = quota->qtaid; 165 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 166 if (ret) { 167 rtw89_warn(rtwdev, "[ERR] dle dfi quota %d\n", ret); 168 return ret; 169 } 170 171 quota->rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, ctrl.out_data); 172 quota->use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, ctrl.out_data); 173 return 0; 174 } 175 rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev * rtwdev,struct rtw89_mac_dle_dfi_qempty * qempty)176 int rtw89_mac_dle_dfi_qempty_cfg(struct rtw89_dev *rtwdev, 177 struct rtw89_mac_dle_dfi_qempty *qempty) 178 { 179 struct rtw89_mac_dle_dfi_ctrl ctrl; 180 u32 ret; 181 182 ctrl.type = qempty->dle_type; 183 ctrl.target = DLE_DFI_TYPE_QEMPTY; 184 ctrl.addr = qempty->grpsel; 185 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 186 if (ret) { 187 rtw89_warn(rtwdev, "[ERR] dle dfi qempty %d\n", ret); 188 return ret; 189 } 190 191 qempty->qempty = FIELD_GET(B_AX_DLE_QEMPTY_GRP, ctrl.out_data); 192 return 0; 193 } 194 dump_err_status_dispatcher_ax(struct rtw89_dev * rtwdev)195 static void dump_err_status_dispatcher_ax(struct rtw89_dev *rtwdev) 196 { 197 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_IMR=0x%08x ", 198 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 199 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ALWAYS_ISR=0x%08x\n", 200 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 201 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_IMR=0x%08x ", 202 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 203 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ALWAYS_ISR=0x%08x\n", 204 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 205 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_IMR=0x%08x ", 206 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 207 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ALWAYS_ISR=0x%08x\n", 208 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 209 } 210 rtw89_mac_dump_qta_lost_ax(struct rtw89_dev * rtwdev)211 static void rtw89_mac_dump_qta_lost_ax(struct rtw89_dev *rtwdev) 212 { 213 struct rtw89_mac_dle_dfi_qempty qempty; 214 struct rtw89_mac_dle_dfi_quota quota; 215 struct rtw89_mac_dle_dfi_ctrl ctrl; 216 u32 val, not_empty, i; 217 int ret; 218 219 qempty.dle_type = DLE_CTRL_TYPE_PLE; 220 qempty.grpsel = 0; 221 qempty.qempty = ~(u32)0; 222 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 223 if (ret) 224 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 225 else 226 rtw89_info(rtwdev, "DLE group0 empty: 0x%x\n", qempty.qempty); 227 228 for (not_empty = ~qempty.qempty, i = 0; not_empty != 0; not_empty >>= 1, i++) { 229 if (!(not_empty & BIT(0))) 230 continue; 231 ctrl.type = DLE_CTRL_TYPE_PLE; 232 ctrl.target = DLE_DFI_TYPE_QLNKTBL; 233 ctrl.addr = (QLNKTBL_ADDR_INFO_SEL_0 ? QLNKTBL_ADDR_INFO_SEL : 0) | 234 u32_encode_bits(i, QLNKTBL_ADDR_TBL_IDX_MASK); 235 ret = rtw89_mac_dle_dfi_cfg(rtwdev, &ctrl); 236 if (ret) 237 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 238 else 239 rtw89_info(rtwdev, "qidx%d pktcnt = %d\n", i, 240 u32_get_bits(ctrl.out_data, 241 QLNKTBL_DATA_SEL1_PKT_CNT_MASK)); 242 } 243 244 quota.dle_type = DLE_CTRL_TYPE_PLE; 245 quota.qtaid = 6; 246 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 247 if (ret) 248 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 249 else 250 rtw89_info(rtwdev, "quota6 rsv/use: 0x%x/0x%x\n", 251 quota.rsv_pgnum, quota.use_pgnum); 252 253 val = rtw89_read32(rtwdev, R_AX_PLE_QTA6_CFG); 254 rtw89_info(rtwdev, "[PLE][CMAC0_RX]min_pgnum=0x%x\n", 255 u32_get_bits(val, B_AX_PLE_Q6_MIN_SIZE_MASK)); 256 rtw89_info(rtwdev, "[PLE][CMAC0_RX]max_pgnum=0x%x\n", 257 u32_get_bits(val, B_AX_PLE_Q6_MAX_SIZE_MASK)); 258 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT); 259 rtw89_info(rtwdev, "[PLE][CMAC0_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 260 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 261 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG=0x%08x\n", 262 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG)); 263 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0=0x%08x\n", 264 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0)); 265 rtw89_info(rtwdev, "R_AX_CCA_CONTROL=0x%08x\n", 266 rtw89_read32(rtwdev, R_AX_CCA_CONTROL)); 267 268 if (!rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL)) { 269 quota.dle_type = DLE_CTRL_TYPE_PLE; 270 quota.qtaid = 7; 271 ret = rtw89_mac_dle_dfi_quota_cfg(rtwdev, "a); 272 if (ret) 273 rtw89_warn(rtwdev, "%s: query DLE fail\n", __func__); 274 else 275 rtw89_info(rtwdev, "quota7 rsv/use: 0x%x/0x%x\n", 276 quota.rsv_pgnum, quota.use_pgnum); 277 278 val = rtw89_read32(rtwdev, R_AX_PLE_QTA7_CFG); 279 rtw89_info(rtwdev, "[PLE][CMAC1_RX]min_pgnum=0x%x\n", 280 u32_get_bits(val, B_AX_PLE_Q7_MIN_SIZE_MASK)); 281 rtw89_info(rtwdev, "[PLE][CMAC1_RX]max_pgnum=0x%x\n", 282 u32_get_bits(val, B_AX_PLE_Q7_MAX_SIZE_MASK)); 283 val = rtw89_read32(rtwdev, R_AX_RX_FLTR_OPT_C1); 284 rtw89_info(rtwdev, "[PLE][CMAC1_RX]B_AX_RX_MPDU_MAX_LEN=0x%x\n", 285 u32_get_bits(val, B_AX_RX_MPDU_MAX_LEN_MASK)); 286 rtw89_info(rtwdev, "R_AX_RSP_CHK_SIG_C1=0x%08x\n", 287 rtw89_read32(rtwdev, R_AX_RSP_CHK_SIG_C1)); 288 rtw89_info(rtwdev, "R_AX_TRXPTCL_RESP_0_C1=0x%08x\n", 289 rtw89_read32(rtwdev, R_AX_TRXPTCL_RESP_0_C1)); 290 rtw89_info(rtwdev, "R_AX_CCA_CONTROL_C1=0x%08x\n", 291 rtw89_read32(rtwdev, R_AX_CCA_CONTROL_C1)); 292 } 293 294 rtw89_info(rtwdev, "R_AX_DLE_EMPTY0=0x%08x\n", 295 rtw89_read32(rtwdev, R_AX_DLE_EMPTY0)); 296 rtw89_info(rtwdev, "R_AX_DLE_EMPTY1=0x%08x\n", 297 rtw89_read32(rtwdev, R_AX_DLE_EMPTY1)); 298 299 dump_err_status_dispatcher_ax(rtwdev); 300 } 301 rtw89_mac_dump_l0_to_l1(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)302 void rtw89_mac_dump_l0_to_l1(struct rtw89_dev *rtwdev, 303 enum mac_ax_err_info err) 304 { 305 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 306 u32 dbg, event; 307 308 dbg = rtw89_read32(rtwdev, R_AX_SER_DBG_INFO); 309 event = u32_get_bits(dbg, B_AX_L0_TO_L1_EVENT_MASK); 310 311 switch (event) { 312 case MAC_AX_L0_TO_L1_RX_QTA_LOST: 313 rtw89_info(rtwdev, "quota lost!\n"); 314 mac->dump_qta_lost(rtwdev); 315 break; 316 default: 317 break; 318 } 319 } 320 rtw89_mac_dump_dmac_err_status(struct rtw89_dev * rtwdev)321 void rtw89_mac_dump_dmac_err_status(struct rtw89_dev *rtwdev) 322 { 323 const struct rtw89_chip_info *chip = rtwdev->chip; 324 u32 dmac_err; 325 int i, ret; 326 327 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 328 if (ret) { 329 rtw89_warn(rtwdev, "[DMAC] : DMAC not enabled\n"); 330 return; 331 } 332 333 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 334 rtw89_info(rtwdev, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err); 335 rtw89_info(rtwdev, "R_AX_DMAC_ERR_IMR=0x%08x\n", 336 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR)); 337 338 if (dmac_err) { 339 rtw89_info(rtwdev, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n", 340 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1)); 341 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n", 342 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1)); 343 if (chip->chip_id == RTL8852C) { 344 rtw89_info(rtwdev, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n", 345 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG)); 346 rtw89_info(rtwdev, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n", 347 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG)); 348 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n", 349 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN)); 350 rtw89_info(rtwdev, "R_AX_PLE_DBGERR_STS=0x%08x\n", 351 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS)); 352 } 353 } 354 355 if (dmac_err & B_AX_WDRLS_ERR_FLAG) { 356 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_IMR=0x%08x\n", 357 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR)); 358 rtw89_info(rtwdev, "R_AX_WDRLS_ERR_ISR=0x%08x\n", 359 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR)); 360 if (chip->chip_id == RTL8852C) 361 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 362 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1)); 363 else 364 rtw89_info(rtwdev, "R_AX_RPQ_RXBD_IDX=0x%08x\n", 365 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX)); 366 } 367 368 if (dmac_err & B_AX_WSEC_ERR_FLAG) { 369 if (chip->chip_id == RTL8852C) { 370 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR=0x%08x\n", 371 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR)); 372 rtw89_info(rtwdev, "R_AX_SEC_ERR_ISR=0x%08x\n", 373 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG)); 374 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 375 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 376 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 377 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 378 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 379 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 380 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 381 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 382 rtw89_info(rtwdev, "R_AX_SEC_DEBUG1=0x%08x\n", 383 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1)); 384 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 385 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 386 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 387 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 388 389 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 390 B_AX_DBG_SEL0, 0x8B); 391 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL, 392 B_AX_DBG_SEL1, 0x8B); 393 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, 394 B_AX_SEL_0XC0_MASK, 1); 395 for (i = 0; i < 0x10; i++) { 396 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 397 B_AX_SEC_DBG_PORT_FIELD_MASK, i); 398 rtw89_info(rtwdev, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n", 399 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2)); 400 } 401 } else if (chip->chip_id == RTL8922A) { 402 rtw89_info(rtwdev, "R_BE_SEC_ERROR_FLAG=0x%08x\n", 403 rtw89_read32(rtwdev, R_BE_SEC_ERROR_FLAG)); 404 rtw89_info(rtwdev, "R_BE_SEC_ERROR_IMR=0x%08x\n", 405 rtw89_read32(rtwdev, R_BE_SEC_ERROR_IMR)); 406 rtw89_info(rtwdev, "R_BE_SEC_ENG_CTRL=0x%08x\n", 407 rtw89_read32(rtwdev, R_BE_SEC_ENG_CTRL)); 408 rtw89_info(rtwdev, "R_BE_SEC_MPDU_PROC=0x%08x\n", 409 rtw89_read32(rtwdev, R_BE_SEC_MPDU_PROC)); 410 rtw89_info(rtwdev, "R_BE_SEC_CAM_ACCESS=0x%08x\n", 411 rtw89_read32(rtwdev, R_BE_SEC_CAM_ACCESS)); 412 rtw89_info(rtwdev, "R_BE_SEC_CAM_RDATA=0x%08x\n", 413 rtw89_read32(rtwdev, R_BE_SEC_CAM_RDATA)); 414 rtw89_info(rtwdev, "R_BE_SEC_DEBUG2=0x%08x\n", 415 rtw89_read32(rtwdev, R_BE_SEC_DEBUG2)); 416 } else { 417 rtw89_info(rtwdev, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n", 418 rtw89_read32(rtwdev, R_AX_SEC_DEBUG)); 419 rtw89_info(rtwdev, "R_AX_SEC_ENG_CTRL=0x%08x\n", 420 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL)); 421 rtw89_info(rtwdev, "R_AX_SEC_MPDU_PROC=0x%08x\n", 422 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC)); 423 rtw89_info(rtwdev, "R_AX_SEC_CAM_ACCESS=0x%08x\n", 424 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS)); 425 rtw89_info(rtwdev, "R_AX_SEC_CAM_RDATA=0x%08x\n", 426 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA)); 427 rtw89_info(rtwdev, "R_AX_SEC_CAM_WDATA=0x%08x\n", 428 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA)); 429 rtw89_info(rtwdev, "R_AX_SEC_TX_DEBUG=0x%08x\n", 430 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG)); 431 rtw89_info(rtwdev, "R_AX_SEC_RX_DEBUG=0x%08x\n", 432 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG)); 433 rtw89_info(rtwdev, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n", 434 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT)); 435 rtw89_info(rtwdev, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n", 436 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT)); 437 } 438 } 439 440 if (dmac_err & B_AX_MPDU_ERR_FLAG) { 441 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n", 442 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR)); 443 rtw89_info(rtwdev, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n", 444 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR)); 445 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n", 446 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR)); 447 rtw89_info(rtwdev, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n", 448 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR)); 449 } 450 451 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) { 452 if (chip->chip_id == RTL8922A) { 453 rtw89_info(rtwdev, "R_BE_INTERRUPT_MASK_REG=0x%08x\n", 454 rtw89_read32(rtwdev, R_BE_INTERRUPT_MASK_REG)); 455 rtw89_info(rtwdev, "R_BE_INTERRUPT_STS_REG=0x%08x\n", 456 rtw89_read32(rtwdev, R_BE_INTERRUPT_STS_REG)); 457 } else { 458 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n", 459 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR)); 460 rtw89_info(rtwdev, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n", 461 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR)); 462 } 463 } 464 465 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) { 466 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 467 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 468 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 469 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 470 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 471 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 472 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 473 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 474 } 475 476 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) { 477 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 478 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n", 479 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR)); 480 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n", 481 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR)); 482 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n", 483 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR)); 484 rtw89_info(rtwdev, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n", 485 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR)); 486 } else { 487 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n", 488 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR)); 489 rtw89_info(rtwdev, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n", 490 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1)); 491 } 492 } 493 494 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) { 495 rtw89_info(rtwdev, "R_AX_WDE_ERR_IMR=0x%08x\n", 496 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR)); 497 rtw89_info(rtwdev, "R_AX_WDE_ERR_ISR=0x%08x\n", 498 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR)); 499 rtw89_info(rtwdev, "R_AX_PLE_ERR_IMR=0x%08x\n", 500 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR)); 501 rtw89_info(rtwdev, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n", 502 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR)); 503 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_0=0x%08x\n", 504 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0)); 505 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_1=0x%08x\n", 506 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1)); 507 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_2=0x%08x\n", 508 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2)); 509 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_0=0x%08x\n", 510 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0)); 511 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_1=0x%08x\n", 512 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1)); 513 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_2=0x%08x\n", 514 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2)); 515 if (chip->chip_id == RTL8922A) { 516 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_3=0x%08x\n", 517 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_3)); 518 rtw89_info(rtwdev, "R_BE_WD_CPUQ_OP_STATUS=0x%08x\n", 519 rtw89_read32(rtwdev, R_BE_WD_CPUQ_OP_STATUS)); 520 rtw89_info(rtwdev, "R_BE_PLE_CPUQ_OP_3=0x%08x\n", 521 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_3)); 522 rtw89_info(rtwdev, "R_BE_PL_CPUQ_OP_STATUS=0x%08x\n", 523 rtw89_read32(rtwdev, R_BE_PL_CPUQ_OP_STATUS)); 524 } else { 525 rtw89_info(rtwdev, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n", 526 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS)); 527 rtw89_info(rtwdev, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n", 528 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS)); 529 if (chip->chip_id == RTL8852C) { 530 rtw89_info(rtwdev, "R_AX_RX_CTRL0=0x%08x\n", 531 rtw89_read32(rtwdev, R_AX_RX_CTRL0)); 532 rtw89_info(rtwdev, "R_AX_RX_CTRL1=0x%08x\n", 533 rtw89_read32(rtwdev, R_AX_RX_CTRL1)); 534 rtw89_info(rtwdev, "R_AX_RX_CTRL2=0x%08x\n", 535 rtw89_read32(rtwdev, R_AX_RX_CTRL2)); 536 } else { 537 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n", 538 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0)); 539 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n", 540 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1)); 541 rtw89_info(rtwdev, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n", 542 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2)); 543 } 544 } 545 } 546 547 if (dmac_err & B_AX_PKTIN_ERR_FLAG) { 548 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_IMR=0x%08x\n", 549 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR)); 550 rtw89_info(rtwdev, "R_AX_PKTIN_ERR_ISR=0x%08x\n", 551 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR)); 552 } 553 554 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) { 555 if (chip->chip_id == RTL8922A) { 556 rtw89_info(rtwdev, "R_BE_DISP_HOST_IMR=0x%08x\n", 557 rtw89_read32(rtwdev, R_BE_DISP_HOST_IMR)); 558 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR1=0x%08x\n", 559 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR1)); 560 rtw89_info(rtwdev, "R_BE_DISP_CPU_IMR=0x%08x\n", 561 rtw89_read32(rtwdev, R_BE_DISP_CPU_IMR)); 562 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR2=0x%08x\n", 563 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR2)); 564 rtw89_info(rtwdev, "R_BE_DISP_OTHER_IMR=0x%08x\n", 565 rtw89_read32(rtwdev, R_BE_DISP_OTHER_IMR)); 566 rtw89_info(rtwdev, "R_BE_DISP_ERROR_ISR0=0x%08x\n", 567 rtw89_read32(rtwdev, R_BE_DISP_ERROR_ISR0)); 568 } else { 569 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n", 570 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR)); 571 rtw89_info(rtwdev, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n", 572 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR)); 573 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n", 574 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR)); 575 rtw89_info(rtwdev, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n", 576 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR)); 577 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n", 578 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR)); 579 rtw89_info(rtwdev, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n", 580 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR)); 581 } 582 } 583 584 if (dmac_err & B_AX_BBRPT_ERR_FLAG) { 585 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) { 586 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n", 587 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR)); 588 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n", 589 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR)); 590 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 591 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 592 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 593 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 594 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 595 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 596 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 597 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 598 } else { 599 rtw89_info(rtwdev, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n", 600 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR)); 601 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n", 602 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR)); 603 rtw89_info(rtwdev, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n", 604 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR)); 605 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n", 606 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR)); 607 rtw89_info(rtwdev, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n", 608 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR)); 609 } 610 if (chip->chip_id == RTL8922A) { 611 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_IMR=0x%08x\n", 612 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_IMR)); 613 rtw89_info(rtwdev, "R_BE_LA_ERRFLAG_ISR=0x%08x\n", 614 rtw89_read32(rtwdev, R_BE_LA_ERRFLAG_ISR)); 615 } 616 } 617 618 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG) { 619 if (chip->chip_id == RTL8922A) { 620 rtw89_info(rtwdev, "R_BE_HAXI_IDCT_MSK=0x%08x\n", 621 rtw89_read32(rtwdev, R_BE_HAXI_IDCT_MSK)); 622 rtw89_info(rtwdev, "R_BE_HAXI_IDCT=0x%08x\n", 623 rtw89_read32(rtwdev, R_BE_HAXI_IDCT)); 624 } else if (chip->chip_id == RTL8852C) { 625 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n", 626 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK)); 627 rtw89_info(rtwdev, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n", 628 rtw89_read32(rtwdev, R_AX_HAXI_IDCT)); 629 } 630 } 631 632 if (dmac_err & B_BE_P_AXIDMA_ERR_INT) { 633 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT_MSK=0x%08x\n", 634 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT_MSK, 635 RTW89_MAC_MEM_AXIDMA)); 636 rtw89_info(rtwdev, "R_BE_PL_AXIDMA_IDCT=0x%08x\n", 637 rtw89_mac_mem_read(rtwdev, R_BE_PL_AXIDMA_IDCT, 638 RTW89_MAC_MEM_AXIDMA)); 639 } 640 641 if (dmac_err & B_BE_MLO_ERR_INT) { 642 rtw89_info(rtwdev, "R_BE_MLO_ERR_IDCT_IMR=0x%08x\n", 643 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_IMR)); 644 rtw89_info(rtwdev, "R_BE_PKTIN_ERR_ISR=0x%08x\n", 645 rtw89_read32(rtwdev, R_BE_MLO_ERR_IDCT_ISR)); 646 } 647 648 if (dmac_err & B_BE_PLRLS_ERR_INT) { 649 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_IMR=0x%08x\n", 650 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_IMR)); 651 rtw89_info(rtwdev, "R_BE_PLRLS_ERR_ISR=0x%08x\n", 652 rtw89_read32(rtwdev, R_BE_PLRLS_ERR_ISR)); 653 } 654 } 655 rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev * rtwdev,u8 band)656 static void rtw89_mac_dump_cmac_err_status_ax(struct rtw89_dev *rtwdev, 657 u8 band) 658 { 659 const struct rtw89_chip_info *chip = rtwdev->chip; 660 u32 offset = 0; 661 u32 cmac_err; 662 int ret; 663 664 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL); 665 if (ret) { 666 if (band) 667 rtw89_warn(rtwdev, "[CMAC] : CMAC1 not enabled\n"); 668 else 669 rtw89_warn(rtwdev, "[CMAC] : CMAC0 not enabled\n"); 670 return; 671 } 672 673 if (band) 674 offset = RTW89_MAC_AX_BAND_REG_OFFSET; 675 676 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset); 677 rtw89_info(rtwdev, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band, 678 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset)); 679 rtw89_info(rtwdev, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band, 680 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset)); 681 rtw89_info(rtwdev, "R_AX_CK_EN [%d]=0x%08x\n", band, 682 rtw89_read32(rtwdev, R_AX_CK_EN + offset)); 683 684 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) { 685 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band, 686 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset)); 687 rtw89_info(rtwdev, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band, 688 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset)); 689 } 690 691 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) { 692 rtw89_info(rtwdev, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band, 693 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset)); 694 rtw89_info(rtwdev, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band, 695 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset)); 696 } 697 698 if (cmac_err & B_AX_DMA_TOP_ERR_IND) { 699 if (chip->chip_id == RTL8852C) { 700 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band, 701 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset)); 702 rtw89_info(rtwdev, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band, 703 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset)); 704 } else { 705 rtw89_info(rtwdev, "R_AX_DLE_CTRL [%d]=0x%08x\n", band, 706 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset)); 707 } 708 } 709 710 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) { 711 if (chip->chip_id == RTL8852C) { 712 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band, 713 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset)); 714 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 715 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 716 } else { 717 rtw89_info(rtwdev, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band, 718 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset)); 719 } 720 } 721 722 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) { 723 rtw89_info(rtwdev, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band, 724 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset)); 725 rtw89_info(rtwdev, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band, 726 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset)); 727 } 728 729 if (cmac_err & B_AX_WMAC_TX_ERR_IND) { 730 if (chip->chip_id == RTL8852C) { 731 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band, 732 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset)); 733 rtw89_info(rtwdev, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band, 734 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset)); 735 } else { 736 rtw89_info(rtwdev, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band, 737 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset)); 738 } 739 rtw89_info(rtwdev, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band, 740 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset)); 741 } 742 743 rtw89_info(rtwdev, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band, 744 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset)); 745 } 746 rtw89_mac_dump_err_status_ax(struct rtw89_dev * rtwdev,enum mac_ax_err_info err)747 static void rtw89_mac_dump_err_status_ax(struct rtw89_dev *rtwdev, 748 enum mac_ax_err_info err) 749 { 750 if (err != MAC_AX_ERR_L1_ERR_DMAC && 751 err != MAC_AX_ERR_L0_PROMOTE_TO_L1 && 752 err != MAC_AX_ERR_L0_ERR_CMAC0 && 753 err != MAC_AX_ERR_L0_ERR_CMAC1 && 754 err != MAC_AX_ERR_RXI300) 755 return; 756 757 rtw89_info(rtwdev, "--->\nerr=0x%x\n", err); 758 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 759 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 760 rtw89_info(rtwdev, "R_AX_SER_DBG_INFO =0x%08x\n", 761 rtw89_read32(rtwdev, R_AX_SER_DBG_INFO)); 762 rtw89_info(rtwdev, "DBG Counter 1 (R_AX_DRV_FW_HSK_4)=0x%08x\n", 763 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_4)); 764 rtw89_info(rtwdev, "DBG Counter 2 (R_AX_DRV_FW_HSK_5)=0x%08x\n", 765 rtw89_read32(rtwdev, R_AX_DRV_FW_HSK_5)); 766 767 rtw89_mac_dump_dmac_err_status(rtwdev); 768 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_0); 769 rtw89_mac_dump_cmac_err_status_ax(rtwdev, RTW89_MAC_1); 770 771 rtwdev->hci.ops->dump_err_status(rtwdev); 772 773 if (err == MAC_AX_ERR_L0_PROMOTE_TO_L1) 774 rtw89_mac_dump_l0_to_l1(rtwdev, err); 775 776 rtw89_info(rtwdev, "<---\n"); 777 } 778 rtw89_mac_suppress_log(struct rtw89_dev * rtwdev,u32 err)779 static bool rtw89_mac_suppress_log(struct rtw89_dev *rtwdev, u32 err) 780 { 781 struct rtw89_ser *ser = &rtwdev->ser; 782 u32 dmac_err, imr, isr; 783 int ret; 784 785 if (rtwdev->chip->chip_id == RTL8852C) { 786 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL); 787 if (ret) 788 return true; 789 790 if (err == MAC_AX_ERR_L1_ERR_DMAC) { 791 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR); 792 imr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR); 793 isr = rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR); 794 795 if ((dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) && 796 ((isr & imr) & B_AX_B0_ISR_ERR_CMDPSR_FRZTO)) { 797 set_bit(RTW89_SER_SUPPRESS_LOG, ser->flags); 798 return true; 799 } 800 } else if (err == MAC_AX_ERR_L1_RESET_DISABLE_DMAC_DONE) { 801 if (test_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 802 return true; 803 } else if (err == MAC_AX_ERR_L1_RESET_RECOVERY_DONE) { 804 if (test_and_clear_bit(RTW89_SER_SUPPRESS_LOG, ser->flags)) 805 return true; 806 } 807 } 808 809 return false; 810 } 811 rtw89_mac_get_err_status(struct rtw89_dev * rtwdev)812 u32 rtw89_mac_get_err_status(struct rtw89_dev *rtwdev) 813 { 814 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 815 u32 err, err_scnr; 816 int ret; 817 818 ret = read_poll_timeout(rtw89_read32, err, (err != 0), 1000, 100000, 819 false, rtwdev, R_AX_HALT_C2H_CTRL); 820 if (ret) { 821 rtw89_warn(rtwdev, "Polling FW err status fail\n"); 822 return ret; 823 } 824 825 err = rtw89_read32(rtwdev, R_AX_HALT_C2H); 826 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 827 828 err_scnr = RTW89_ERROR_SCENARIO(err); 829 if (err_scnr == RTW89_WCPU_CPU_EXCEPTION) 830 err = MAC_AX_ERR_CPU_EXCEPTION; 831 else if (err_scnr == RTW89_WCPU_ASSERTION) 832 err = MAC_AX_ERR_ASSERTION; 833 else if (err_scnr == RTW89_RXI300_ERROR) 834 err = MAC_AX_ERR_RXI300; 835 836 if (rtw89_mac_suppress_log(rtwdev, err)) 837 return err; 838 839 rtw89_fw_st_dbg_dump(rtwdev); 840 mac->dump_err_status(rtwdev, err); 841 842 return err; 843 } 844 EXPORT_SYMBOL(rtw89_mac_get_err_status); 845 rtw89_mac_set_err_status(struct rtw89_dev * rtwdev,u32 err)846 int rtw89_mac_set_err_status(struct rtw89_dev *rtwdev, u32 err) 847 { 848 struct rtw89_ser *ser = &rtwdev->ser; 849 u32 halt; 850 int ret = 0; 851 852 if (err > MAC_AX_SET_ERR_MAX) { 853 rtw89_err(rtwdev, "Bad set-err-status value 0x%08x\n", err); 854 return -EINVAL; 855 } 856 857 ret = read_poll_timeout(rtw89_read32, halt, (halt == 0x0), 1000, 858 100000, false, rtwdev, R_AX_HALT_H2C_CTRL); 859 if (ret) { 860 rtw89_err(rtwdev, "FW doesn't receive previous msg\n"); 861 return -EFAULT; 862 } 863 864 rtw89_write32(rtwdev, R_AX_HALT_H2C, err); 865 866 if (ser->prehandle_l1 && 867 (err == MAC_AX_ERR_L1_DISABLE_EN || err == MAC_AX_ERR_L1_RCVY_EN)) 868 return 0; 869 870 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, B_AX_HALT_H2C_TRIGGER); 871 872 return 0; 873 } 874 EXPORT_SYMBOL(rtw89_mac_set_err_status); 875 hfc_reset_param(struct rtw89_dev * rtwdev)876 static int hfc_reset_param(struct rtw89_dev *rtwdev) 877 { 878 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 879 struct rtw89_hfc_param_ini param_ini = {NULL}; 880 u8 qta_mode = rtwdev->mac.dle_info.qta_mode; 881 882 switch (rtwdev->hci.type) { 883 case RTW89_HCI_TYPE_PCIE: 884 param_ini = rtwdev->chip->hfc_param_ini[qta_mode]; 885 param->en = 0; 886 break; 887 default: 888 return -EINVAL; 889 } 890 891 if (param_ini.pub_cfg) 892 param->pub_cfg = *param_ini.pub_cfg; 893 894 if (param_ini.prec_cfg) 895 param->prec_cfg = *param_ini.prec_cfg; 896 897 if (param_ini.ch_cfg) 898 param->ch_cfg = param_ini.ch_cfg; 899 900 memset(¶m->ch_info, 0, sizeof(param->ch_info)); 901 memset(¶m->pub_info, 0, sizeof(param->pub_info)); 902 param->mode = param_ini.mode; 903 904 return 0; 905 } 906 hfc_ch_cfg_chk(struct rtw89_dev * rtwdev,u8 ch)907 static int hfc_ch_cfg_chk(struct rtw89_dev *rtwdev, u8 ch) 908 { 909 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 910 const struct rtw89_hfc_ch_cfg *ch_cfg = param->ch_cfg; 911 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 912 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 913 914 if (ch >= RTW89_DMA_CH_NUM) 915 return -EINVAL; 916 917 if ((ch_cfg[ch].min && ch_cfg[ch].min < prec_cfg->ch011_prec) || 918 ch_cfg[ch].max > pub_cfg->pub_max) 919 return -EINVAL; 920 if (ch_cfg[ch].grp >= grp_num) 921 return -EINVAL; 922 923 return 0; 924 } 925 hfc_pub_info_chk(struct rtw89_dev * rtwdev)926 static int hfc_pub_info_chk(struct rtw89_dev *rtwdev) 927 { 928 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 929 const struct rtw89_hfc_pub_cfg *cfg = ¶m->pub_cfg; 930 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 931 932 if (info->g0_used + info->g1_used + info->pub_aval != cfg->pub_max) { 933 if (rtwdev->chip->chip_id == RTL8852A) 934 return 0; 935 else 936 return -EFAULT; 937 } 938 939 return 0; 940 } 941 hfc_pub_cfg_chk(struct rtw89_dev * rtwdev)942 static int hfc_pub_cfg_chk(struct rtw89_dev *rtwdev) 943 { 944 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 945 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 946 947 if (pub_cfg->grp0 + pub_cfg->grp1 != pub_cfg->pub_max) 948 return -EFAULT; 949 950 return 0; 951 } 952 hfc_ch_ctrl(struct rtw89_dev * rtwdev,u8 ch)953 static int hfc_ch_ctrl(struct rtw89_dev *rtwdev, u8 ch) 954 { 955 const struct rtw89_chip_info *chip = rtwdev->chip; 956 const struct rtw89_page_regs *regs = chip->page_regs; 957 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 958 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 959 int ret = 0; 960 u32 val = 0; 961 962 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 963 if (ret) 964 return ret; 965 966 ret = hfc_ch_cfg_chk(rtwdev, ch); 967 if (ret) 968 return ret; 969 970 if (ch > RTW89_DMA_B1HI) 971 return -EINVAL; 972 973 val = u32_encode_bits(cfg[ch].min, B_AX_MIN_PG_MASK) | 974 u32_encode_bits(cfg[ch].max, B_AX_MAX_PG_MASK) | 975 (cfg[ch].grp ? B_AX_GRP : 0); 976 rtw89_write32(rtwdev, regs->ach_page_ctrl + ch * 4, val); 977 978 return 0; 979 } 980 hfc_upd_ch_info(struct rtw89_dev * rtwdev,u8 ch)981 static int hfc_upd_ch_info(struct rtw89_dev *rtwdev, u8 ch) 982 { 983 const struct rtw89_chip_info *chip = rtwdev->chip; 984 const struct rtw89_page_regs *regs = chip->page_regs; 985 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 986 struct rtw89_hfc_ch_info *info = param->ch_info; 987 const struct rtw89_hfc_ch_cfg *cfg = param->ch_cfg; 988 u32 val; 989 u32 ret; 990 991 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 992 if (ret) 993 return ret; 994 995 if (ch > RTW89_DMA_H2C) 996 return -EINVAL; 997 998 val = rtw89_read32(rtwdev, regs->ach_page_info + ch * 4); 999 info[ch].aval = u32_get_bits(val, B_AX_AVAL_PG_MASK); 1000 if (ch < RTW89_DMA_H2C) 1001 info[ch].used = u32_get_bits(val, B_AX_USE_PG_MASK); 1002 else 1003 info[ch].used = cfg[ch].min - info[ch].aval; 1004 1005 return 0; 1006 } 1007 hfc_pub_ctrl(struct rtw89_dev * rtwdev)1008 static int hfc_pub_ctrl(struct rtw89_dev *rtwdev) 1009 { 1010 const struct rtw89_chip_info *chip = rtwdev->chip; 1011 const struct rtw89_page_regs *regs = chip->page_regs; 1012 const struct rtw89_hfc_pub_cfg *cfg = &rtwdev->mac.hfc_param.pub_cfg; 1013 u32 val; 1014 int ret; 1015 1016 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1017 if (ret) 1018 return ret; 1019 1020 ret = hfc_pub_cfg_chk(rtwdev); 1021 if (ret) 1022 return ret; 1023 1024 val = u32_encode_bits(cfg->grp0, B_AX_PUBPG_G0_MASK) | 1025 u32_encode_bits(cfg->grp1, B_AX_PUBPG_G1_MASK); 1026 rtw89_write32(rtwdev, regs->pub_page_ctrl1, val); 1027 1028 val = u32_encode_bits(cfg->wp_thrd, B_AX_WP_THRD_MASK); 1029 rtw89_write32(rtwdev, regs->wp_page_ctrl2, val); 1030 1031 return 0; 1032 } 1033 hfc_get_mix_info_ax(struct rtw89_dev * rtwdev)1034 static void hfc_get_mix_info_ax(struct rtw89_dev *rtwdev) 1035 { 1036 const struct rtw89_chip_info *chip = rtwdev->chip; 1037 const struct rtw89_page_regs *regs = chip->page_regs; 1038 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1039 struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1040 struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1041 struct rtw89_hfc_pub_info *info = ¶m->pub_info; 1042 u32 val; 1043 1044 val = rtw89_read32(rtwdev, regs->pub_page_info1); 1045 info->g0_used = u32_get_bits(val, B_AX_G0_USE_PG_MASK); 1046 info->g1_used = u32_get_bits(val, B_AX_G1_USE_PG_MASK); 1047 val = rtw89_read32(rtwdev, regs->pub_page_info3); 1048 info->g0_aval = u32_get_bits(val, B_AX_G0_AVAL_PG_MASK); 1049 info->g1_aval = u32_get_bits(val, B_AX_G1_AVAL_PG_MASK); 1050 info->pub_aval = 1051 u32_get_bits(rtw89_read32(rtwdev, regs->pub_page_info2), 1052 B_AX_PUB_AVAL_PG_MASK); 1053 info->wp_aval = 1054 u32_get_bits(rtw89_read32(rtwdev, regs->wp_page_info1), 1055 B_AX_WP_AVAL_PG_MASK); 1056 1057 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1058 param->en = val & B_AX_HCI_FC_EN ? 1 : 0; 1059 param->h2c_en = val & B_AX_HCI_FC_CH12_EN ? 1 : 0; 1060 param->mode = u32_get_bits(val, B_AX_HCI_FC_MODE_MASK); 1061 prec_cfg->ch011_full_cond = 1062 u32_get_bits(val, B_AX_HCI_FC_WD_FULL_COND_MASK); 1063 prec_cfg->h2c_full_cond = 1064 u32_get_bits(val, B_AX_HCI_FC_CH12_FULL_COND_MASK); 1065 prec_cfg->wp_ch07_full_cond = 1066 u32_get_bits(val, B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1067 prec_cfg->wp_ch811_full_cond = 1068 u32_get_bits(val, B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1069 1070 val = rtw89_read32(rtwdev, regs->ch_page_ctrl); 1071 prec_cfg->ch011_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH011_MASK); 1072 prec_cfg->h2c_prec = u32_get_bits(val, B_AX_PREC_PAGE_CH12_MASK); 1073 1074 val = rtw89_read32(rtwdev, regs->pub_page_ctrl2); 1075 pub_cfg->pub_max = u32_get_bits(val, B_AX_PUBPG_ALL_MASK); 1076 1077 val = rtw89_read32(rtwdev, regs->wp_page_ctrl1); 1078 prec_cfg->wp_ch07_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH07_MASK); 1079 prec_cfg->wp_ch811_prec = u32_get_bits(val, B_AX_PREC_PAGE_WP_CH811_MASK); 1080 1081 val = rtw89_read32(rtwdev, regs->wp_page_ctrl2); 1082 pub_cfg->wp_thrd = u32_get_bits(val, B_AX_WP_THRD_MASK); 1083 1084 val = rtw89_read32(rtwdev, regs->pub_page_ctrl1); 1085 pub_cfg->grp0 = u32_get_bits(val, B_AX_PUBPG_G0_MASK); 1086 pub_cfg->grp1 = u32_get_bits(val, B_AX_PUBPG_G1_MASK); 1087 } 1088 hfc_upd_mix_info(struct rtw89_dev * rtwdev)1089 static int hfc_upd_mix_info(struct rtw89_dev *rtwdev) 1090 { 1091 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1092 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1093 int ret; 1094 1095 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1096 if (ret) 1097 return ret; 1098 1099 mac->hfc_get_mix_info(rtwdev); 1100 1101 ret = hfc_pub_info_chk(rtwdev); 1102 if (param->en && ret) 1103 return ret; 1104 1105 return 0; 1106 } 1107 hfc_h2c_cfg_ax(struct rtw89_dev * rtwdev)1108 static void hfc_h2c_cfg_ax(struct rtw89_dev *rtwdev) 1109 { 1110 const struct rtw89_chip_info *chip = rtwdev->chip; 1111 const struct rtw89_page_regs *regs = chip->page_regs; 1112 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1113 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1114 u32 val; 1115 1116 val = u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1117 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1118 1119 rtw89_write32_mask(rtwdev, regs->hci_fc_ctrl, 1120 B_AX_HCI_FC_CH12_FULL_COND_MASK, 1121 prec_cfg->h2c_full_cond); 1122 } 1123 hfc_mix_cfg_ax(struct rtw89_dev * rtwdev)1124 static void hfc_mix_cfg_ax(struct rtw89_dev *rtwdev) 1125 { 1126 const struct rtw89_chip_info *chip = rtwdev->chip; 1127 const struct rtw89_page_regs *regs = chip->page_regs; 1128 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1129 const struct rtw89_hfc_pub_cfg *pub_cfg = ¶m->pub_cfg; 1130 const struct rtw89_hfc_prec_cfg *prec_cfg = ¶m->prec_cfg; 1131 u32 val; 1132 1133 val = u32_encode_bits(prec_cfg->ch011_prec, B_AX_PREC_PAGE_CH011_MASK) | 1134 u32_encode_bits(prec_cfg->h2c_prec, B_AX_PREC_PAGE_CH12_MASK); 1135 rtw89_write32(rtwdev, regs->ch_page_ctrl, val); 1136 1137 val = u32_encode_bits(pub_cfg->pub_max, B_AX_PUBPG_ALL_MASK); 1138 rtw89_write32(rtwdev, regs->pub_page_ctrl2, val); 1139 1140 val = u32_encode_bits(prec_cfg->wp_ch07_prec, 1141 B_AX_PREC_PAGE_WP_CH07_MASK) | 1142 u32_encode_bits(prec_cfg->wp_ch811_prec, 1143 B_AX_PREC_PAGE_WP_CH811_MASK); 1144 rtw89_write32(rtwdev, regs->wp_page_ctrl1, val); 1145 1146 val = u32_replace_bits(rtw89_read32(rtwdev, regs->hci_fc_ctrl), 1147 param->mode, B_AX_HCI_FC_MODE_MASK); 1148 val = u32_replace_bits(val, prec_cfg->ch011_full_cond, 1149 B_AX_HCI_FC_WD_FULL_COND_MASK); 1150 val = u32_replace_bits(val, prec_cfg->h2c_full_cond, 1151 B_AX_HCI_FC_CH12_FULL_COND_MASK); 1152 val = u32_replace_bits(val, prec_cfg->wp_ch07_full_cond, 1153 B_AX_HCI_FC_WP_CH07_FULL_COND_MASK); 1154 val = u32_replace_bits(val, prec_cfg->wp_ch811_full_cond, 1155 B_AX_HCI_FC_WP_CH811_FULL_COND_MASK); 1156 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1157 } 1158 hfc_func_en_ax(struct rtw89_dev * rtwdev,bool en,bool h2c_en)1159 static void hfc_func_en_ax(struct rtw89_dev *rtwdev, bool en, bool h2c_en) 1160 { 1161 const struct rtw89_chip_info *chip = rtwdev->chip; 1162 const struct rtw89_page_regs *regs = chip->page_regs; 1163 struct rtw89_hfc_param *param = &rtwdev->mac.hfc_param; 1164 u32 val; 1165 1166 val = rtw89_read32(rtwdev, regs->hci_fc_ctrl); 1167 param->en = en; 1168 param->h2c_en = h2c_en; 1169 val = en ? (val | B_AX_HCI_FC_EN) : (val & ~B_AX_HCI_FC_EN); 1170 val = h2c_en ? (val | B_AX_HCI_FC_CH12_EN) : 1171 (val & ~B_AX_HCI_FC_CH12_EN); 1172 rtw89_write32(rtwdev, regs->hci_fc_ctrl, val); 1173 } 1174 rtw89_mac_hfc_init(struct rtw89_dev * rtwdev,bool reset,bool en,bool h2c_en)1175 int rtw89_mac_hfc_init(struct rtw89_dev *rtwdev, bool reset, bool en, bool h2c_en) 1176 { 1177 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 1178 const struct rtw89_chip_info *chip = rtwdev->chip; 1179 u32 dma_ch_mask = chip->dma_ch_mask; 1180 u8 ch; 1181 u32 ret = 0; 1182 1183 if (reset) 1184 ret = hfc_reset_param(rtwdev); 1185 if (ret) 1186 return ret; 1187 1188 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 1189 if (ret) 1190 return ret; 1191 1192 mac->hfc_func_en(rtwdev, false, false); 1193 1194 if (!en && h2c_en) { 1195 mac->hfc_h2c_cfg(rtwdev); 1196 mac->hfc_func_en(rtwdev, en, h2c_en); 1197 return ret; 1198 } 1199 1200 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1201 if (dma_ch_mask & BIT(ch)) 1202 continue; 1203 ret = hfc_ch_ctrl(rtwdev, ch); 1204 if (ret) 1205 return ret; 1206 } 1207 1208 ret = hfc_pub_ctrl(rtwdev); 1209 if (ret) 1210 return ret; 1211 1212 mac->hfc_mix_cfg(rtwdev); 1213 if (en || h2c_en) { 1214 mac->hfc_func_en(rtwdev, en, h2c_en); 1215 udelay(10); 1216 } 1217 for (ch = RTW89_DMA_ACH0; ch < RTW89_DMA_H2C; ch++) { 1218 if (dma_ch_mask & BIT(ch)) 1219 continue; 1220 ret = hfc_upd_ch_info(rtwdev, ch); 1221 if (ret) 1222 return ret; 1223 } 1224 ret = hfc_upd_mix_info(rtwdev); 1225 1226 return ret; 1227 } 1228 1229 #define PWR_POLL_CNT 2000 pwr_cmd_poll(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * cfg)1230 static int pwr_cmd_poll(struct rtw89_dev *rtwdev, 1231 const struct rtw89_pwr_cfg *cfg) 1232 { 1233 u8 val = 0; 1234 int ret; 1235 u32 addr = cfg->base == PWR_INTF_MSK_SDIO ? 1236 cfg->addr | SDIO_LOCAL_BASE_ADDR : cfg->addr; 1237 1238 ret = read_poll_timeout(rtw89_read8, val, !((val ^ cfg->val) & cfg->msk), 1239 1000, 1000 * PWR_POLL_CNT, false, rtwdev, addr); 1240 1241 if (!ret) 1242 return 0; 1243 1244 rtw89_warn(rtwdev, "[ERR] Polling timeout\n"); 1245 rtw89_warn(rtwdev, "[ERR] addr: %X, %X\n", addr, cfg->addr); 1246 rtw89_warn(rtwdev, "[ERR] val: %X, %X\n", val, cfg->val); 1247 1248 return -EBUSY; 1249 } 1250 rtw89_mac_sub_pwr_seq(struct rtw89_dev * rtwdev,u8 cv_msk,u8 intf_msk,const struct rtw89_pwr_cfg * cfg)1251 static int rtw89_mac_sub_pwr_seq(struct rtw89_dev *rtwdev, u8 cv_msk, 1252 u8 intf_msk, const struct rtw89_pwr_cfg *cfg) 1253 { 1254 const struct rtw89_pwr_cfg *cur_cfg; 1255 u32 addr; 1256 u8 val; 1257 1258 for (cur_cfg = cfg; cur_cfg->cmd != PWR_CMD_END; cur_cfg++) { 1259 if (!(cur_cfg->intf_msk & intf_msk) || 1260 !(cur_cfg->cv_msk & cv_msk)) 1261 continue; 1262 1263 switch (cur_cfg->cmd) { 1264 case PWR_CMD_WRITE: 1265 addr = cur_cfg->addr; 1266 1267 if (cur_cfg->base == PWR_BASE_SDIO) 1268 addr |= SDIO_LOCAL_BASE_ADDR; 1269 1270 val = rtw89_read8(rtwdev, addr); 1271 val &= ~(cur_cfg->msk); 1272 val |= (cur_cfg->val & cur_cfg->msk); 1273 1274 rtw89_write8(rtwdev, addr, val); 1275 break; 1276 case PWR_CMD_POLL: 1277 if (pwr_cmd_poll(rtwdev, cur_cfg)) 1278 return -EBUSY; 1279 break; 1280 case PWR_CMD_DELAY: 1281 if (cur_cfg->val == PWR_DELAY_US) 1282 udelay(cur_cfg->addr); 1283 else 1284 fsleep(cur_cfg->addr * 1000); 1285 break; 1286 default: 1287 return -EINVAL; 1288 } 1289 } 1290 1291 return 0; 1292 } 1293 rtw89_mac_pwr_seq(struct rtw89_dev * rtwdev,const struct rtw89_pwr_cfg * const * cfg_seq)1294 static int rtw89_mac_pwr_seq(struct rtw89_dev *rtwdev, 1295 const struct rtw89_pwr_cfg * const *cfg_seq) 1296 { 1297 int ret; 1298 1299 for (; *cfg_seq; cfg_seq++) { 1300 ret = rtw89_mac_sub_pwr_seq(rtwdev, BIT(rtwdev->hal.cv), 1301 PWR_INTF_MSK_PCIE, *cfg_seq); 1302 if (ret) 1303 return -EBUSY; 1304 } 1305 1306 return 0; 1307 } 1308 1309 static enum rtw89_rpwm_req_pwr_state rtw89_mac_get_req_pwr_state(struct rtw89_dev * rtwdev)1310 rtw89_mac_get_req_pwr_state(struct rtw89_dev *rtwdev) 1311 { 1312 enum rtw89_rpwm_req_pwr_state state; 1313 1314 switch (rtwdev->ps_mode) { 1315 case RTW89_PS_MODE_RFOFF: 1316 state = RTW89_MAC_RPWM_REQ_PWR_STATE_BAND0_RFOFF; 1317 break; 1318 case RTW89_PS_MODE_CLK_GATED: 1319 state = RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED; 1320 break; 1321 case RTW89_PS_MODE_PWR_GATED: 1322 state = RTW89_MAC_RPWM_REQ_PWR_STATE_PWR_GATED; 1323 break; 1324 default: 1325 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1326 break; 1327 } 1328 return state; 1329 } 1330 rtw89_mac_send_rpwm(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state,bool notify_wake)1331 static void rtw89_mac_send_rpwm(struct rtw89_dev *rtwdev, 1332 enum rtw89_rpwm_req_pwr_state req_pwr_state, 1333 bool notify_wake) 1334 { 1335 u16 request; 1336 1337 spin_lock_bh(&rtwdev->rpwm_lock); 1338 1339 request = rtw89_read16(rtwdev, R_AX_RPWM); 1340 request ^= request | PS_RPWM_TOGGLE; 1341 request |= req_pwr_state; 1342 1343 if (notify_wake) { 1344 request |= PS_RPWM_NOTIFY_WAKE; 1345 } else { 1346 rtwdev->mac.rpwm_seq_num = (rtwdev->mac.rpwm_seq_num + 1) & 1347 RPWM_SEQ_NUM_MAX; 1348 request |= FIELD_PREP(PS_RPWM_SEQ_NUM, 1349 rtwdev->mac.rpwm_seq_num); 1350 1351 if (req_pwr_state < RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1352 request |= PS_RPWM_ACK; 1353 } 1354 rtw89_write16(rtwdev, rtwdev->hci.rpwm_addr, request); 1355 1356 spin_unlock_bh(&rtwdev->rpwm_lock); 1357 } 1358 rtw89_mac_check_cpwm_state(struct rtw89_dev * rtwdev,enum rtw89_rpwm_req_pwr_state req_pwr_state)1359 static int rtw89_mac_check_cpwm_state(struct rtw89_dev *rtwdev, 1360 enum rtw89_rpwm_req_pwr_state req_pwr_state) 1361 { 1362 bool request_deep_mode; 1363 bool in_deep_mode; 1364 u8 rpwm_req_num; 1365 u8 cpwm_rsp_seq; 1366 u8 cpwm_seq; 1367 u8 cpwm_status; 1368 1369 if (req_pwr_state >= RTW89_MAC_RPWM_REQ_PWR_STATE_CLK_GATED) 1370 request_deep_mode = true; 1371 else 1372 request_deep_mode = false; 1373 1374 if (rtw89_read32_mask(rtwdev, R_AX_LDM, B_AX_EN_32K)) 1375 in_deep_mode = true; 1376 else 1377 in_deep_mode = false; 1378 1379 if (request_deep_mode != in_deep_mode) 1380 return -EPERM; 1381 1382 if (request_deep_mode) 1383 return 0; 1384 1385 rpwm_req_num = rtwdev->mac.rpwm_seq_num; 1386 cpwm_rsp_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, 1387 PS_CPWM_RSP_SEQ_NUM); 1388 1389 if (rpwm_req_num != cpwm_rsp_seq) 1390 return -EPERM; 1391 1392 rtwdev->mac.cpwm_seq_num = (rtwdev->mac.cpwm_seq_num + 1) & 1393 CPWM_SEQ_NUM_MAX; 1394 1395 cpwm_seq = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_SEQ_NUM); 1396 if (cpwm_seq != rtwdev->mac.cpwm_seq_num) 1397 return -EPERM; 1398 1399 cpwm_status = rtw89_read16_mask(rtwdev, rtwdev->hci.cpwm_addr, PS_CPWM_STATE); 1400 if (cpwm_status != req_pwr_state) 1401 return -EPERM; 1402 1403 return 0; 1404 } 1405 rtw89_mac_power_mode_change(struct rtw89_dev * rtwdev,bool enter)1406 void rtw89_mac_power_mode_change(struct rtw89_dev *rtwdev, bool enter) 1407 { 1408 enum rtw89_rpwm_req_pwr_state state; 1409 unsigned long delay = enter ? 10 : 150; 1410 int ret; 1411 int i; 1412 1413 if (enter) 1414 state = rtw89_mac_get_req_pwr_state(rtwdev); 1415 else 1416 state = RTW89_MAC_RPWM_REQ_PWR_STATE_ACTIVE; 1417 1418 for (i = 0; i < RPWM_TRY_CNT; i++) { 1419 rtw89_mac_send_rpwm(rtwdev, state, false); 1420 ret = read_poll_timeout_atomic(rtw89_mac_check_cpwm_state, ret, 1421 !ret, delay, 15000, false, 1422 rtwdev, state); 1423 if (!ret) 1424 break; 1425 1426 if (i == RPWM_TRY_CNT - 1) 1427 rtw89_err(rtwdev, "firmware failed to ack for %s ps mode\n", 1428 enter ? "entering" : "leaving"); 1429 else 1430 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, 1431 "%d time firmware failed to ack for %s ps mode\n", 1432 i + 1, enter ? "entering" : "leaving"); 1433 } 1434 } 1435 rtw89_mac_notify_wake(struct rtw89_dev * rtwdev)1436 void rtw89_mac_notify_wake(struct rtw89_dev *rtwdev) 1437 { 1438 enum rtw89_rpwm_req_pwr_state state; 1439 1440 state = rtw89_mac_get_req_pwr_state(rtwdev); 1441 rtw89_mac_send_rpwm(rtwdev, state, true); 1442 } 1443 rtw89_mac_power_switch(struct rtw89_dev * rtwdev,bool on)1444 static int rtw89_mac_power_switch(struct rtw89_dev *rtwdev, bool on) 1445 { 1446 #define PWR_ACT 1 1447 const struct rtw89_chip_info *chip = rtwdev->chip; 1448 const struct rtw89_pwr_cfg * const *cfg_seq; 1449 int (*cfg_func)(struct rtw89_dev *rtwdev); 1450 int ret; 1451 u8 val; 1452 1453 if (on) { 1454 cfg_seq = chip->pwr_on_seq; 1455 cfg_func = chip->ops->pwr_on_func; 1456 } else { 1457 cfg_seq = chip->pwr_off_seq; 1458 cfg_func = chip->ops->pwr_off_func; 1459 } 1460 1461 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 1462 __rtw89_leave_ps_mode(rtwdev); 1463 1464 val = rtw89_read32_mask(rtwdev, R_AX_IC_PWR_STATE, B_AX_WLMAC_PWR_STE_MASK); 1465 if (on && val == PWR_ACT) { 1466 rtw89_err(rtwdev, "MAC has already powered on\n"); 1467 return -EBUSY; 1468 } 1469 1470 ret = cfg_func ? cfg_func(rtwdev) : rtw89_mac_pwr_seq(rtwdev, cfg_seq); 1471 if (ret) 1472 return ret; 1473 1474 if (on) { 1475 set_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1476 set_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1477 set_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1478 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_TP_MAJOR); 1479 } else { 1480 clear_bit(RTW89_FLAG_POWERON, rtwdev->flags); 1481 clear_bit(RTW89_FLAG_DMAC_FUNC, rtwdev->flags); 1482 clear_bit(RTW89_FLAG_CMAC0_FUNC, rtwdev->flags); 1483 clear_bit(RTW89_FLAG_CMAC1_FUNC, rtwdev->flags); 1484 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 1485 rtw89_write8(rtwdev, R_AX_SCOREBOARD + 3, MAC_AX_NOTIFY_PWR_MAJOR); 1486 rtw89_set_entity_state(rtwdev, false); 1487 } 1488 1489 return 0; 1490 #undef PWR_ACT 1491 } 1492 rtw89_mac_pwr_off(struct rtw89_dev * rtwdev)1493 void rtw89_mac_pwr_off(struct rtw89_dev *rtwdev) 1494 { 1495 rtw89_mac_power_switch(rtwdev, false); 1496 } 1497 cmac_func_en_ax(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)1498 static int cmac_func_en_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 1499 { 1500 u32 func_en = 0; 1501 u32 ck_en = 0; 1502 u32 c1pc_en = 0; 1503 u32 addrl_func_en[] = {R_AX_CMAC_FUNC_EN, R_AX_CMAC_FUNC_EN_C1}; 1504 u32 addrl_ck_en[] = {R_AX_CK_EN, R_AX_CK_EN_C1}; 1505 1506 func_en = B_AX_CMAC_EN | B_AX_CMAC_TXEN | B_AX_CMAC_RXEN | 1507 B_AX_PHYINTF_EN | B_AX_CMAC_DMA_EN | B_AX_PTCLTOP_EN | 1508 B_AX_SCHEDULER_EN | B_AX_TMAC_EN | B_AX_RMAC_EN | 1509 B_AX_CMAC_CRPRT; 1510 ck_en = B_AX_CMAC_CKEN | B_AX_PHYINTF_CKEN | B_AX_CMAC_DMA_CKEN | 1511 B_AX_PTCLTOP_CKEN | B_AX_SCHEDULER_CKEN | B_AX_TMAC_CKEN | 1512 B_AX_RMAC_CKEN; 1513 c1pc_en = B_AX_R_SYM_WLCMAC1_PC_EN | 1514 B_AX_R_SYM_WLCMAC1_P1_PC_EN | 1515 B_AX_R_SYM_WLCMAC1_P2_PC_EN | 1516 B_AX_R_SYM_WLCMAC1_P3_PC_EN | 1517 B_AX_R_SYM_WLCMAC1_P4_PC_EN; 1518 1519 if (en) { 1520 if (mac_idx == RTW89_MAC_1) { 1521 rtw89_write32_set(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1522 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1523 B_AX_R_SYM_ISO_CMAC12PP); 1524 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1525 B_AX_CMAC1_FEN); 1526 } 1527 rtw89_write32_set(rtwdev, addrl_ck_en[mac_idx], ck_en); 1528 rtw89_write32_set(rtwdev, addrl_func_en[mac_idx], func_en); 1529 } else { 1530 rtw89_write32_clr(rtwdev, addrl_func_en[mac_idx], func_en); 1531 rtw89_write32_clr(rtwdev, addrl_ck_en[mac_idx], ck_en); 1532 if (mac_idx == RTW89_MAC_1) { 1533 rtw89_write32_clr(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1534 B_AX_CMAC1_FEN); 1535 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 1536 B_AX_R_SYM_ISO_CMAC12PP); 1537 rtw89_write32_clr(rtwdev, R_AX_AFE_CTRL1, c1pc_en); 1538 } 1539 } 1540 1541 return 0; 1542 } 1543 dmac_func_en_ax(struct rtw89_dev * rtwdev)1544 static int dmac_func_en_ax(struct rtw89_dev *rtwdev) 1545 { 1546 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1547 u32 val32; 1548 1549 if (chip_id == RTL8852C) 1550 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1551 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1552 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1553 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1554 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1555 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1556 B_AX_DMAC_CRPRT | B_AX_H_AXIDMA_EN); 1557 else 1558 val32 = (B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | 1559 B_AX_MAC_SEC_EN | B_AX_DISPATCHER_EN | 1560 B_AX_DLE_CPUIO_EN | B_AX_PKT_IN_EN | 1561 B_AX_DMAC_TBL_EN | B_AX_PKT_BUF_EN | 1562 B_AX_STA_SCH_EN | B_AX_TXPKT_CTRL_EN | 1563 B_AX_WD_RLS_EN | B_AX_MPDU_PROC_EN | 1564 B_AX_DMAC_CRPRT); 1565 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val32); 1566 1567 val32 = (B_AX_MAC_SEC_CLK_EN | B_AX_DISPATCHER_CLK_EN | 1568 B_AX_DLE_CPUIO_CLK_EN | B_AX_PKT_IN_CLK_EN | 1569 B_AX_STA_SCH_CLK_EN | B_AX_TXPKT_CTRL_CLK_EN | 1570 B_AX_WD_RLS_CLK_EN | B_AX_BBRPT_CLK_EN); 1571 if (chip_id == RTL8852BT) 1572 val32 |= B_AX_AXIDMA_CLK_EN; 1573 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val32); 1574 1575 return 0; 1576 } 1577 chip_func_en_ax(struct rtw89_dev * rtwdev)1578 static int chip_func_en_ax(struct rtw89_dev *rtwdev) 1579 { 1580 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 1581 1582 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 1583 rtw89_write32_set(rtwdev, R_AX_SPS_DIG_ON_CTRL0, 1584 B_AX_OCP_L1_MASK); 1585 1586 return 0; 1587 } 1588 sys_init_ax(struct rtw89_dev * rtwdev)1589 static int sys_init_ax(struct rtw89_dev *rtwdev) 1590 { 1591 int ret; 1592 1593 ret = dmac_func_en_ax(rtwdev); 1594 if (ret) 1595 return ret; 1596 1597 ret = cmac_func_en_ax(rtwdev, 0, true); 1598 if (ret) 1599 return ret; 1600 1601 ret = chip_func_en_ax(rtwdev); 1602 if (ret) 1603 return ret; 1604 1605 return ret; 1606 } 1607 1608 const struct rtw89_mac_size_set rtw89_mac_size = { 1609 .hfc_preccfg_pcie = {2, 40, 0, 0, 1, 0, 0, 0}, 1610 .hfc_prec_cfg_c0 = {2, 32, 0, 0, 0, 0, 0, 0}, 1611 .hfc_prec_cfg_c2 = {0, 256, 0, 0, 0, 0, 0, 0}, 1612 /* PCIE 64 */ 1613 .wde_size0 = {RTW89_WDE_PG_64, 4095, 1,}, 1614 .wde_size0_v1 = {RTW89_WDE_PG_64, 3328, 0, 0,}, 1615 /* DLFW */ 1616 .wde_size4 = {RTW89_WDE_PG_64, 0, 4096,}, 1617 .wde_size4_v1 = {RTW89_WDE_PG_64, 0, 3328, 0,}, 1618 /* PCIE 64 */ 1619 .wde_size6 = {RTW89_WDE_PG_64, 512, 0,}, 1620 /* 8852B PCIE SCC */ 1621 .wde_size7 = {RTW89_WDE_PG_64, 510, 2,}, 1622 /* DLFW */ 1623 .wde_size9 = {RTW89_WDE_PG_64, 0, 1024,}, 1624 /* 8852C DLFW */ 1625 .wde_size18 = {RTW89_WDE_PG_64, 0, 2048,}, 1626 /* 8852C PCIE SCC */ 1627 .wde_size19 = {RTW89_WDE_PG_64, 3328, 0,}, 1628 .wde_size23 = {RTW89_WDE_PG_64, 1022, 2,}, 1629 /* PCIE */ 1630 .ple_size0 = {RTW89_PLE_PG_128, 1520, 16,}, 1631 .ple_size0_v1 = {RTW89_PLE_PG_128, 2688, 240, 212992,}, 1632 .ple_size3_v1 = {RTW89_PLE_PG_128, 2928, 0, 212992,}, 1633 /* DLFW */ 1634 .ple_size4 = {RTW89_PLE_PG_128, 64, 1472,}, 1635 /* PCIE 64 */ 1636 .ple_size6 = {RTW89_PLE_PG_128, 496, 16,}, 1637 /* DLFW */ 1638 .ple_size8 = {RTW89_PLE_PG_128, 64, 960,}, 1639 .ple_size9 = {RTW89_PLE_PG_128, 2288, 16,}, 1640 /* 8852C DLFW */ 1641 .ple_size18 = {RTW89_PLE_PG_128, 2544, 16,}, 1642 /* 8852C PCIE SCC */ 1643 .ple_size19 = {RTW89_PLE_PG_128, 1904, 16,}, 1644 /* PCIE 64 */ 1645 .wde_qt0 = {3792, 196, 0, 107,}, 1646 .wde_qt0_v1 = {3302, 6, 0, 20,}, 1647 /* DLFW */ 1648 .wde_qt4 = {0, 0, 0, 0,}, 1649 /* PCIE 64 */ 1650 .wde_qt6 = {448, 48, 0, 16,}, 1651 /* 8852B PCIE SCC */ 1652 .wde_qt7 = {446, 48, 0, 16,}, 1653 /* 8852C DLFW */ 1654 .wde_qt17 = {0, 0, 0, 0,}, 1655 /* 8852C PCIE SCC */ 1656 .wde_qt18 = {3228, 60, 0, 40,}, 1657 .wde_qt23 = {958, 48, 0, 16,}, 1658 .ple_qt0 = {320, 320, 32, 16, 13, 13, 292, 292, 64, 18, 1, 4, 0,}, 1659 .ple_qt1 = {320, 320, 32, 16, 1316, 1316, 1595, 1595, 1367, 1321, 1, 1307, 0,}, 1660 /* PCIE SCC */ 1661 .ple_qt4 = {264, 0, 16, 20, 26, 13, 356, 0, 32, 40, 8,}, 1662 /* PCIE SCC */ 1663 .ple_qt5 = {264, 0, 32, 20, 64, 13, 1101, 0, 64, 128, 120,}, 1664 .ple_qt9 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 1, 0, 0,}, 1665 /* DLFW */ 1666 .ple_qt13 = {0, 0, 16, 48, 0, 0, 0, 0, 0, 0, 0,}, 1667 /* PCIE 64 */ 1668 .ple_qt18 = {147, 0, 16, 20, 17, 13, 89, 0, 32, 14, 8, 0,}, 1669 /* DLFW 52C */ 1670 .ple_qt44 = {0, 0, 16, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1671 /* DLFW 52C */ 1672 .ple_qt45 = {0, 0, 32, 256, 0, 0, 0, 0, 0, 0, 0, 0,}, 1673 /* 8852C PCIE SCC */ 1674 .ple_qt46 = {525, 0, 16, 20, 13, 13, 178, 0, 32, 62, 8, 16,}, 1675 /* 8852C PCIE SCC */ 1676 .ple_qt47 = {525, 0, 32, 20, 1034, 13, 1199, 0, 1053, 62, 160, 1037,}, 1677 .ple_qt57 = {147, 0, 16, 20, 13, 13, 178, 0, 32, 14, 8, 0,}, 1678 /* PCIE 64 */ 1679 .ple_qt58 = {147, 0, 16, 20, 157, 13, 229, 0, 172, 14, 24, 0,}, 1680 .ple_qt59 = {147, 0, 32, 20, 1860, 13, 2025, 0, 1879, 14, 24, 0,}, 1681 /* 8852A PCIE WOW */ 1682 .ple_qt_52a_wow = {264, 0, 32, 20, 64, 13, 1005, 0, 64, 128, 120,}, 1683 /* 8852B PCIE WOW */ 1684 .ple_qt_52b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1685 /* 8852BT PCIE WOW */ 1686 .ple_qt_52bt_wow = {147, 0, 32, 20, 1860, 13, 1929, 0, 1879, 14, 24, 0,}, 1687 /* 8851B PCIE WOW */ 1688 .ple_qt_51b_wow = {147, 0, 16, 20, 157, 13, 133, 0, 172, 14, 24, 0,}, 1689 .ple_rsvd_qt0 = {2, 107, 107, 6, 6, 6, 6, 0, 0, 0,}, 1690 .ple_rsvd_qt1 = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,}, 1691 .rsvd0_size0 = {212992, 0,}, 1692 .rsvd1_size0 = {587776, 2048,}, 1693 }; 1694 EXPORT_SYMBOL(rtw89_mac_size); 1695 get_dle_mem_cfg(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1696 static const struct rtw89_dle_mem *get_dle_mem_cfg(struct rtw89_dev *rtwdev, 1697 enum rtw89_qta_mode mode) 1698 { 1699 struct rtw89_mac_info *mac = &rtwdev->mac; 1700 const struct rtw89_dle_mem *cfg; 1701 1702 cfg = &rtwdev->chip->dle_mem[mode]; 1703 if (!cfg) 1704 return NULL; 1705 1706 if (cfg->mode != mode) { 1707 rtw89_warn(rtwdev, "qta mode unmatch!\n"); 1708 return NULL; 1709 } 1710 1711 mac->dle_info.rsvd_qt = cfg->rsvd_qt; 1712 mac->dle_info.ple_pg_size = cfg->ple_size->pge_size; 1713 mac->dle_info.ple_free_pg = cfg->ple_size->lnk_pge_num; 1714 mac->dle_info.qta_mode = mode; 1715 mac->dle_info.c0_rx_qta = cfg->ple_min_qt->cma0_dma; 1716 mac->dle_info.c1_rx_qta = cfg->ple_min_qt->cma1_dma; 1717 1718 return cfg; 1719 } 1720 rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev * rtwdev,enum rtw89_mac_dle_rsvd_qt_type type,struct rtw89_mac_dle_rsvd_qt_cfg * cfg)1721 int rtw89_mac_get_dle_rsvd_qt_cfg(struct rtw89_dev *rtwdev, 1722 enum rtw89_mac_dle_rsvd_qt_type type, 1723 struct rtw89_mac_dle_rsvd_qt_cfg *cfg) 1724 { 1725 struct rtw89_dle_info *dle_info = &rtwdev->mac.dle_info; 1726 const struct rtw89_rsvd_quota *rsvd_qt = dle_info->rsvd_qt; 1727 1728 switch (type) { 1729 case DLE_RSVD_QT_MPDU_INFO: 1730 cfg->pktid = dle_info->ple_free_pg; 1731 cfg->pg_num = rsvd_qt->mpdu_info_tbl; 1732 break; 1733 case DLE_RSVD_QT_B0_CSI: 1734 cfg->pktid = dle_info->ple_free_pg + rsvd_qt->mpdu_info_tbl; 1735 cfg->pg_num = rsvd_qt->b0_csi; 1736 break; 1737 case DLE_RSVD_QT_B1_CSI: 1738 cfg->pktid = dle_info->ple_free_pg + 1739 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi; 1740 cfg->pg_num = rsvd_qt->b1_csi; 1741 break; 1742 case DLE_RSVD_QT_B0_LMR: 1743 cfg->pktid = dle_info->ple_free_pg + 1744 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi; 1745 cfg->pg_num = rsvd_qt->b0_lmr; 1746 break; 1747 case DLE_RSVD_QT_B1_LMR: 1748 cfg->pktid = dle_info->ple_free_pg + 1749 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1750 rsvd_qt->b0_lmr; 1751 cfg->pg_num = rsvd_qt->b1_lmr; 1752 break; 1753 case DLE_RSVD_QT_B0_FTM: 1754 cfg->pktid = dle_info->ple_free_pg + 1755 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1756 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr; 1757 cfg->pg_num = rsvd_qt->b0_ftm; 1758 break; 1759 case DLE_RSVD_QT_B1_FTM: 1760 cfg->pktid = dle_info->ple_free_pg + 1761 rsvd_qt->mpdu_info_tbl + rsvd_qt->b0_csi + rsvd_qt->b1_csi + 1762 rsvd_qt->b0_lmr + rsvd_qt->b1_lmr + rsvd_qt->b0_ftm; 1763 cfg->pg_num = rsvd_qt->b1_ftm; 1764 break; 1765 default: 1766 return -EINVAL; 1767 } 1768 1769 cfg->size = (u32)cfg->pg_num * dle_info->ple_pg_size; 1770 1771 return 0; 1772 } 1773 mac_is_txq_empty_ax(struct rtw89_dev * rtwdev)1774 static bool mac_is_txq_empty_ax(struct rtw89_dev *rtwdev) 1775 { 1776 struct rtw89_mac_dle_dfi_qempty qempty; 1777 u32 grpnum, qtmp, val32, msk32; 1778 int i, j, ret; 1779 1780 grpnum = rtwdev->chip->wde_qempty_acq_grpnum; 1781 qempty.dle_type = DLE_CTRL_TYPE_WDE; 1782 1783 for (i = 0; i < grpnum; i++) { 1784 qempty.grpsel = i; 1785 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1786 if (ret) { 1787 rtw89_warn(rtwdev, "dle dfi acq empty %d\n", ret); 1788 return false; 1789 } 1790 qtmp = qempty.qempty; 1791 for (j = 0 ; j < QEMP_ACQ_GRP_MACID_NUM; j++) { 1792 val32 = u32_get_bits(qtmp, QEMP_ACQ_GRP_QSEL_MASK); 1793 if (val32 != QEMP_ACQ_GRP_QSEL_MASK) 1794 return false; 1795 qtmp >>= QEMP_ACQ_GRP_QSEL_SH; 1796 } 1797 } 1798 1799 qempty.grpsel = rtwdev->chip->wde_qempty_mgq_grpsel; 1800 ret = rtw89_mac_dle_dfi_qempty_cfg(rtwdev, &qempty); 1801 if (ret) { 1802 rtw89_warn(rtwdev, "dle dfi mgq empty %d\n", ret); 1803 return false; 1804 } 1805 msk32 = B_CMAC0_MGQ_NORMAL | B_CMAC0_MGQ_NO_PWRSAV | B_CMAC0_CPUMGQ; 1806 if ((qempty.qempty & msk32) != msk32) 1807 return false; 1808 1809 if (rtwdev->dbcc_en) { 1810 msk32 |= B_CMAC1_MGQ_NORMAL | B_CMAC1_MGQ_NO_PWRSAV | B_CMAC1_CPUMGQ; 1811 if ((qempty.qempty & msk32) != msk32) 1812 return false; 1813 } 1814 1815 msk32 = B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 1816 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 1817 B_AX_WDE_EMPTY_QUE_OTHERS | B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | 1818 B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 1819 B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_HIF | 1820 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | 1821 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 1822 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX; 1823 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 1824 1825 return (val32 & msk32) == msk32; 1826 } 1827 dle_used_size(const struct rtw89_dle_mem * cfg)1828 static inline u32 dle_used_size(const struct rtw89_dle_mem *cfg) 1829 { 1830 const struct rtw89_dle_size *wde = cfg->wde_size; 1831 const struct rtw89_dle_size *ple = cfg->ple_size; 1832 u32 used; 1833 1834 used = wde->pge_size * (wde->lnk_pge_num + wde->unlnk_pge_num) + 1835 ple->pge_size * (ple->lnk_pge_num + ple->unlnk_pge_num); 1836 1837 if (cfg->rsvd0_size && cfg->rsvd1_size) { 1838 used += cfg->rsvd0_size->size; 1839 used += cfg->rsvd1_size->size; 1840 } 1841 1842 return used; 1843 } 1844 dle_expected_used_size(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)1845 static u32 dle_expected_used_size(struct rtw89_dev *rtwdev, 1846 enum rtw89_qta_mode mode) 1847 { 1848 u32 size = rtwdev->chip->fifo_size; 1849 1850 if (mode == RTW89_QTA_SCC) 1851 size -= rtwdev->chip->dle_scc_rsvd_size; 1852 1853 return size; 1854 } 1855 dle_func_en_ax(struct rtw89_dev * rtwdev,bool enable)1856 static void dle_func_en_ax(struct rtw89_dev *rtwdev, bool enable) 1857 { 1858 if (enable) 1859 rtw89_write32_set(rtwdev, R_AX_DMAC_FUNC_EN, 1860 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1861 else 1862 rtw89_write32_clr(rtwdev, R_AX_DMAC_FUNC_EN, 1863 B_AX_DLE_WDE_EN | B_AX_DLE_PLE_EN); 1864 } 1865 dle_clk_en_ax(struct rtw89_dev * rtwdev,bool enable)1866 static void dle_clk_en_ax(struct rtw89_dev *rtwdev, bool enable) 1867 { 1868 u32 val = B_AX_DLE_WDE_CLK_EN | B_AX_DLE_PLE_CLK_EN; 1869 1870 if (enable) { 1871 if (rtwdev->chip->chip_id == RTL8851B) 1872 val |= B_AX_AXIDMA_CLK_EN; 1873 rtw89_write32_set(rtwdev, R_AX_DMAC_CLK_EN, val); 1874 } else { 1875 rtw89_write32_clr(rtwdev, R_AX_DMAC_CLK_EN, val); 1876 } 1877 } 1878 dle_mix_cfg_ax(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg)1879 static int dle_mix_cfg_ax(struct rtw89_dev *rtwdev, const struct rtw89_dle_mem *cfg) 1880 { 1881 const struct rtw89_dle_size *size_cfg; 1882 u32 val; 1883 u8 bound = 0; 1884 1885 val = rtw89_read32(rtwdev, R_AX_WDE_PKTBUF_CFG); 1886 size_cfg = cfg->wde_size; 1887 1888 switch (size_cfg->pge_size) { 1889 default: 1890 case RTW89_WDE_PG_64: 1891 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_64, 1892 B_AX_WDE_PAGE_SEL_MASK); 1893 break; 1894 case RTW89_WDE_PG_128: 1895 val = u32_replace_bits(val, S_AX_WDE_PAGE_SEL_128, 1896 B_AX_WDE_PAGE_SEL_MASK); 1897 break; 1898 case RTW89_WDE_PG_256: 1899 rtw89_err(rtwdev, "[ERR]WDE DLE doesn't support 256 byte!\n"); 1900 return -EINVAL; 1901 } 1902 1903 val = u32_replace_bits(val, bound, B_AX_WDE_START_BOUND_MASK); 1904 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1905 B_AX_WDE_FREE_PAGE_NUM_MASK); 1906 rtw89_write32(rtwdev, R_AX_WDE_PKTBUF_CFG, val); 1907 1908 val = rtw89_read32(rtwdev, R_AX_PLE_PKTBUF_CFG); 1909 bound = (size_cfg->lnk_pge_num + size_cfg->unlnk_pge_num) 1910 * size_cfg->pge_size / DLE_BOUND_UNIT; 1911 size_cfg = cfg->ple_size; 1912 1913 switch (size_cfg->pge_size) { 1914 default: 1915 case RTW89_PLE_PG_64: 1916 rtw89_err(rtwdev, "[ERR]PLE DLE doesn't support 64 byte!\n"); 1917 return -EINVAL; 1918 case RTW89_PLE_PG_128: 1919 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_128, 1920 B_AX_PLE_PAGE_SEL_MASK); 1921 break; 1922 case RTW89_PLE_PG_256: 1923 val = u32_replace_bits(val, S_AX_PLE_PAGE_SEL_256, 1924 B_AX_PLE_PAGE_SEL_MASK); 1925 break; 1926 } 1927 1928 val = u32_replace_bits(val, bound, B_AX_PLE_START_BOUND_MASK); 1929 val = u32_replace_bits(val, size_cfg->lnk_pge_num, 1930 B_AX_PLE_FREE_PAGE_NUM_MASK); 1931 rtw89_write32(rtwdev, R_AX_PLE_PKTBUF_CFG, val); 1932 1933 return 0; 1934 } 1935 chk_dle_rdy_ax(struct rtw89_dev * rtwdev,bool wde_or_ple)1936 static int chk_dle_rdy_ax(struct rtw89_dev *rtwdev, bool wde_or_ple) 1937 { 1938 u32 reg, mask; 1939 u32 ini; 1940 1941 if (wde_or_ple) { 1942 reg = R_AX_WDE_INI_STATUS; 1943 mask = WDE_MGN_INI_RDY; 1944 } else { 1945 reg = R_AX_PLE_INI_STATUS; 1946 mask = PLE_MGN_INI_RDY; 1947 } 1948 1949 return read_poll_timeout(rtw89_read32, ini, (ini & mask) == mask, 1, 1950 2000, false, rtwdev, reg); 1951 } 1952 1953 #define INVALID_QT_WCPU U16_MAX 1954 #define SET_QUOTA_VAL(_min_x, _max_x, _module, _idx) \ 1955 do { \ 1956 val = u32_encode_bits(_min_x, B_AX_ ## _module ## _MIN_SIZE_MASK) | \ 1957 u32_encode_bits(_max_x, B_AX_ ## _module ## _MAX_SIZE_MASK); \ 1958 rtw89_write32(rtwdev, \ 1959 R_AX_ ## _module ## _QTA ## _idx ## _CFG, \ 1960 val); \ 1961 } while (0) 1962 #define SET_QUOTA(_x, _module, _idx) \ 1963 SET_QUOTA_VAL(min_cfg->_x, max_cfg->_x, _module, _idx) 1964 wde_quota_cfg_ax(struct rtw89_dev * rtwdev,const struct rtw89_wde_quota * min_cfg,const struct rtw89_wde_quota * max_cfg,u16 ext_wde_min_qt_wcpu)1965 static void wde_quota_cfg_ax(struct rtw89_dev *rtwdev, 1966 const struct rtw89_wde_quota *min_cfg, 1967 const struct rtw89_wde_quota *max_cfg, 1968 u16 ext_wde_min_qt_wcpu) 1969 { 1970 u16 min_qt_wcpu = ext_wde_min_qt_wcpu != INVALID_QT_WCPU ? 1971 ext_wde_min_qt_wcpu : min_cfg->wcpu; 1972 u32 val; 1973 1974 SET_QUOTA(hif, WDE, 0); 1975 SET_QUOTA_VAL(min_qt_wcpu, max_cfg->wcpu, WDE, 1); 1976 SET_QUOTA(pkt_in, WDE, 3); 1977 SET_QUOTA(cpu_io, WDE, 4); 1978 } 1979 ple_quota_cfg_ax(struct rtw89_dev * rtwdev,const struct rtw89_ple_quota * min_cfg,const struct rtw89_ple_quota * max_cfg)1980 static void ple_quota_cfg_ax(struct rtw89_dev *rtwdev, 1981 const struct rtw89_ple_quota *min_cfg, 1982 const struct rtw89_ple_quota *max_cfg) 1983 { 1984 u32 val; 1985 1986 SET_QUOTA(cma0_tx, PLE, 0); 1987 SET_QUOTA(cma1_tx, PLE, 1); 1988 SET_QUOTA(c2h, PLE, 2); 1989 SET_QUOTA(h2c, PLE, 3); 1990 SET_QUOTA(wcpu, PLE, 4); 1991 SET_QUOTA(mpdu_proc, PLE, 5); 1992 SET_QUOTA(cma0_dma, PLE, 6); 1993 SET_QUOTA(cma1_dma, PLE, 7); 1994 SET_QUOTA(bb_rpt, PLE, 8); 1995 SET_QUOTA(wd_rel, PLE, 9); 1996 SET_QUOTA(cpu_io, PLE, 10); 1997 if (rtwdev->chip->chip_id == RTL8852C) 1998 SET_QUOTA(tx_rpt, PLE, 11); 1999 } 2000 rtw89_mac_resize_ple_rx_quota(struct rtw89_dev * rtwdev,bool wow)2001 int rtw89_mac_resize_ple_rx_quota(struct rtw89_dev *rtwdev, bool wow) 2002 { 2003 const struct rtw89_ple_quota *min_cfg, *max_cfg; 2004 const struct rtw89_dle_mem *cfg; 2005 u32 val; 2006 2007 if (rtwdev->chip->chip_id == RTL8852C) 2008 return 0; 2009 2010 if (rtwdev->mac.qta_mode != RTW89_QTA_SCC) { 2011 rtw89_err(rtwdev, "[ERR]support SCC mode only\n"); 2012 return -EINVAL; 2013 } 2014 2015 if (wow) 2016 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_WOW); 2017 else 2018 cfg = get_dle_mem_cfg(rtwdev, RTW89_QTA_SCC); 2019 if (!cfg) { 2020 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2021 return -EINVAL; 2022 } 2023 2024 min_cfg = cfg->ple_min_qt; 2025 max_cfg = cfg->ple_max_qt; 2026 SET_QUOTA(cma0_dma, PLE, 6); 2027 SET_QUOTA(cma1_dma, PLE, 7); 2028 2029 return 0; 2030 } 2031 #undef SET_QUOTA 2032 rtw89_mac_hw_mgnt_sec(struct rtw89_dev * rtwdev,bool enable)2033 void rtw89_mac_hw_mgnt_sec(struct rtw89_dev *rtwdev, bool enable) 2034 { 2035 const struct rtw89_chip_info *chip = rtwdev->chip; 2036 u32 msk32 = B_AX_UC_MGNT_DEC | B_AX_BMC_MGNT_DEC; 2037 2038 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 2039 return; 2040 2041 /* 8852C enable B_AX_UC_MGNT_DEC by default */ 2042 if (chip->chip_id == RTL8852C) 2043 msk32 = B_AX_BMC_MGNT_DEC; 2044 2045 if (enable) 2046 rtw89_write32_set(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2047 else 2048 rtw89_write32_clr(rtwdev, R_AX_SEC_ENG_CTRL, msk32); 2049 } 2050 dle_quota_cfg(struct rtw89_dev * rtwdev,const struct rtw89_dle_mem * cfg,u16 ext_wde_min_qt_wcpu)2051 static void dle_quota_cfg(struct rtw89_dev *rtwdev, 2052 const struct rtw89_dle_mem *cfg, 2053 u16 ext_wde_min_qt_wcpu) 2054 { 2055 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2056 2057 mac->wde_quota_cfg(rtwdev, cfg->wde_min_qt, cfg->wde_max_qt, ext_wde_min_qt_wcpu); 2058 mac->ple_quota_cfg(rtwdev, cfg->ple_min_qt, cfg->ple_max_qt); 2059 } 2060 rtw89_mac_dle_init(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode,enum rtw89_qta_mode ext_mode)2061 int rtw89_mac_dle_init(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 2062 enum rtw89_qta_mode ext_mode) 2063 { 2064 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2065 const struct rtw89_dle_mem *cfg, *ext_cfg; 2066 u16 ext_wde_min_qt_wcpu = INVALID_QT_WCPU; 2067 int ret; 2068 2069 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2070 if (ret) 2071 return ret; 2072 2073 cfg = get_dle_mem_cfg(rtwdev, mode); 2074 if (!cfg) { 2075 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2076 ret = -EINVAL; 2077 goto error; 2078 } 2079 2080 if (mode == RTW89_QTA_DLFW) { 2081 ext_cfg = get_dle_mem_cfg(rtwdev, ext_mode); 2082 if (!ext_cfg) { 2083 rtw89_err(rtwdev, "[ERR]get_dle_ext_mem_cfg %d\n", 2084 ext_mode); 2085 ret = -EINVAL; 2086 goto error; 2087 } 2088 ext_wde_min_qt_wcpu = ext_cfg->wde_min_qt->wcpu; 2089 } 2090 2091 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 2092 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 2093 ret = -EINVAL; 2094 goto error; 2095 } 2096 2097 mac->dle_func_en(rtwdev, false); 2098 mac->dle_clk_en(rtwdev, true); 2099 2100 ret = mac->dle_mix_cfg(rtwdev, cfg); 2101 if (ret) { 2102 rtw89_err(rtwdev, "[ERR] dle mix cfg\n"); 2103 goto error; 2104 } 2105 dle_quota_cfg(rtwdev, cfg, ext_wde_min_qt_wcpu); 2106 2107 mac->dle_func_en(rtwdev, true); 2108 2109 ret = mac->chk_dle_rdy(rtwdev, true); 2110 if (ret) { 2111 rtw89_err(rtwdev, "[ERR]WDE cfg ready\n"); 2112 return ret; 2113 } 2114 2115 ret = mac->chk_dle_rdy(rtwdev, false); 2116 if (ret) { 2117 rtw89_err(rtwdev, "[ERR]PLE cfg ready\n"); 2118 return ret; 2119 } 2120 2121 return 0; 2122 error: 2123 mac->dle_func_en(rtwdev, false); 2124 rtw89_err(rtwdev, "[ERR]trxcfg wde 0x8900 = %x\n", 2125 rtw89_read32(rtwdev, R_AX_WDE_INI_STATUS)); 2126 rtw89_err(rtwdev, "[ERR]trxcfg ple 0x8D00 = %x\n", 2127 rtw89_read32(rtwdev, R_AX_PLE_INI_STATUS)); 2128 2129 return ret; 2130 } 2131 preload_init_set(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)2132 static int preload_init_set(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2133 enum rtw89_qta_mode mode) 2134 { 2135 u32 reg, max_preld_size, min_rsvd_size; 2136 2137 max_preld_size = (mac_idx == RTW89_MAC_0 ? 2138 PRELD_B0_ENT_NUM : PRELD_B1_ENT_NUM) * PRELD_AMSDU_SIZE; 2139 reg = mac_idx == RTW89_MAC_0 ? 2140 R_AX_TXPKTCTL_B0_PRELD_CFG0 : R_AX_TXPKTCTL_B1_PRELD_CFG0; 2141 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_USEMAXSZ_MASK, max_preld_size); 2142 rtw89_write32_set(rtwdev, reg, B_AX_B0_PRELD_FEN); 2143 2144 min_rsvd_size = PRELD_AMSDU_SIZE; 2145 reg = mac_idx == RTW89_MAC_0 ? 2146 R_AX_TXPKTCTL_B0_PRELD_CFG1 : R_AX_TXPKTCTL_B1_PRELD_CFG1; 2147 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_TXENDWIN_MASK, PRELD_NEXT_WND); 2148 rtw89_write32_mask(rtwdev, reg, B_AX_B0_PRELD_NXT_RSVMINSZ_MASK, min_rsvd_size); 2149 2150 return 0; 2151 } 2152 is_qta_poh(struct rtw89_dev * rtwdev)2153 static bool is_qta_poh(struct rtw89_dev *rtwdev) 2154 { 2155 return rtwdev->hci.type == RTW89_HCI_TYPE_PCIE; 2156 } 2157 rtw89_mac_preload_init(struct rtw89_dev * rtwdev,enum rtw89_mac_idx mac_idx,enum rtw89_qta_mode mode)2158 int rtw89_mac_preload_init(struct rtw89_dev *rtwdev, enum rtw89_mac_idx mac_idx, 2159 enum rtw89_qta_mode mode) 2160 { 2161 const struct rtw89_chip_info *chip = rtwdev->chip; 2162 2163 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev) || 2164 !is_qta_poh(rtwdev)) 2165 return 0; 2166 2167 return preload_init_set(rtwdev, mac_idx, mode); 2168 } 2169 dle_is_txq_empty(struct rtw89_dev * rtwdev)2170 static bool dle_is_txq_empty(struct rtw89_dev *rtwdev) 2171 { 2172 u32 msk32; 2173 u32 val32; 2174 2175 msk32 = B_AX_WDE_EMPTY_QUE_CMAC0_ALL_AC | B_AX_WDE_EMPTY_QUE_CMAC0_MBH | 2176 B_AX_WDE_EMPTY_QUE_CMAC1_MBH | B_AX_WDE_EMPTY_QUE_CMAC0_WMM0 | 2177 B_AX_WDE_EMPTY_QUE_CMAC0_WMM1 | B_AX_WDE_EMPTY_QUE_OTHERS | 2178 B_AX_PLE_EMPTY_QUE_DMAC_MPDU_TX | B_AX_PLE_EMPTY_QTA_DMAC_H2C | 2179 B_AX_PLE_EMPTY_QUE_DMAC_SEC_TX | B_AX_WDE_EMPTY_QUE_DMAC_PKTIN | 2180 B_AX_WDE_EMPTY_QTA_DMAC_HIF | B_AX_WDE_EMPTY_QTA_DMAC_WLAN_CPU | 2181 B_AX_WDE_EMPTY_QTA_DMAC_PKTIN | B_AX_WDE_EMPTY_QTA_DMAC_CPUIO | 2182 B_AX_PLE_EMPTY_QTA_DMAC_B0_TXPL | 2183 B_AX_PLE_EMPTY_QTA_DMAC_B1_TXPL | 2184 B_AX_PLE_EMPTY_QTA_DMAC_MPDU_TX | 2185 B_AX_PLE_EMPTY_QTA_DMAC_CPUIO | 2186 B_AX_WDE_EMPTY_QTA_DMAC_DATA_CPU | 2187 B_AX_PLE_EMPTY_QTA_DMAC_WLAN_CPU; 2188 val32 = rtw89_read32(rtwdev, R_AX_DLE_EMPTY0); 2189 2190 if ((val32 & msk32) == msk32) 2191 return true; 2192 2193 return false; 2194 } 2195 _patch_ss2f_path(struct rtw89_dev * rtwdev)2196 static void _patch_ss2f_path(struct rtw89_dev *rtwdev) 2197 { 2198 const struct rtw89_chip_info *chip = rtwdev->chip; 2199 2200 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 2201 return; 2202 2203 rtw89_write32_mask(rtwdev, R_AX_SS2FINFO_PATH, B_AX_SS_DEST_QUEUE_MASK, 2204 SS2F_PATH_WLCPU); 2205 } 2206 sta_sch_init_ax(struct rtw89_dev * rtwdev)2207 static int sta_sch_init_ax(struct rtw89_dev *rtwdev) 2208 { 2209 u32 p_val; 2210 u8 val; 2211 int ret; 2212 2213 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2214 if (ret) 2215 return ret; 2216 2217 val = rtw89_read8(rtwdev, R_AX_SS_CTRL); 2218 val |= B_AX_SS_EN; 2219 rtw89_write8(rtwdev, R_AX_SS_CTRL, val); 2220 2221 ret = read_poll_timeout(rtw89_read32, p_val, p_val & B_AX_SS_INIT_DONE_1, 2222 1, TRXCFG_WAIT_CNT, false, rtwdev, R_AX_SS_CTRL); 2223 if (ret) { 2224 rtw89_err(rtwdev, "[ERR]STA scheduler init\n"); 2225 return ret; 2226 } 2227 2228 rtw89_write32_set(rtwdev, R_AX_SS_CTRL, B_AX_SS_WARM_INIT_FLG); 2229 rtw89_write32_clr(rtwdev, R_AX_SS_CTRL, B_AX_SS_NONEMPTY_SS2FINFO_EN); 2230 2231 _patch_ss2f_path(rtwdev); 2232 2233 return 0; 2234 } 2235 mpdu_proc_init_ax(struct rtw89_dev * rtwdev)2236 static int mpdu_proc_init_ax(struct rtw89_dev *rtwdev) 2237 { 2238 int ret; 2239 2240 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2241 if (ret) 2242 return ret; 2243 2244 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 2245 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 2246 rtw89_write32_set(rtwdev, R_AX_MPDU_PROC, 2247 B_AX_APPEND_FCS | B_AX_A_ICV_ERR); 2248 rtw89_write32(rtwdev, R_AX_CUT_AMSDU_CTRL, TRXCFG_MPDU_PROC_CUT_CTRL); 2249 2250 return 0; 2251 } 2252 sec_eng_init_ax(struct rtw89_dev * rtwdev)2253 static int sec_eng_init_ax(struct rtw89_dev *rtwdev) 2254 { 2255 const struct rtw89_chip_info *chip = rtwdev->chip; 2256 u32 val = 0; 2257 int ret; 2258 2259 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 2260 if (ret) 2261 return ret; 2262 2263 val = rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL); 2264 /* init clock */ 2265 val |= (B_AX_CLK_EN_CGCMP | B_AX_CLK_EN_WAPI | B_AX_CLK_EN_WEP_TKIP); 2266 /* init TX encryption */ 2267 val |= (B_AX_SEC_TX_ENC | B_AX_SEC_RX_DEC); 2268 val |= (B_AX_MC_DEC | B_AX_BC_DEC); 2269 if (chip->chip_id == RTL8852C) 2270 val |= B_AX_UC_MGNT_DEC; 2271 if (chip->chip_id == RTL8852A || chip->chip_id == RTL8852B || 2272 chip->chip_id == RTL8851B) 2273 val &= ~B_AX_TX_PARTIAL_MODE; 2274 rtw89_write32(rtwdev, R_AX_SEC_ENG_CTRL, val); 2275 2276 /* init MIC ICV append */ 2277 val = rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC); 2278 val |= (B_AX_APPEND_ICV | B_AX_APPEND_MIC); 2279 2280 /* option init */ 2281 rtw89_write32(rtwdev, R_AX_SEC_MPDU_PROC, val); 2282 2283 if (chip->chip_id == RTL8852C) 2284 rtw89_write32_mask(rtwdev, R_AX_SEC_DEBUG1, 2285 B_AX_TX_TIMEOUT_SEL_MASK, AX_TX_TO_VAL); 2286 2287 return 0; 2288 } 2289 dmac_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2290 static int dmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2291 { 2292 int ret; 2293 2294 ret = rtw89_mac_dle_init(rtwdev, rtwdev->mac.qta_mode, RTW89_QTA_INVALID); 2295 if (ret) { 2296 rtw89_err(rtwdev, "[ERR]DLE init %d\n", ret); 2297 return ret; 2298 } 2299 2300 ret = rtw89_mac_preload_init(rtwdev, RTW89_MAC_0, rtwdev->mac.qta_mode); 2301 if (ret) { 2302 rtw89_err(rtwdev, "[ERR]preload init %d\n", ret); 2303 return ret; 2304 } 2305 2306 ret = rtw89_mac_hfc_init(rtwdev, true, true, true); 2307 if (ret) { 2308 rtw89_err(rtwdev, "[ERR]HCI FC init %d\n", ret); 2309 return ret; 2310 } 2311 2312 ret = sta_sch_init_ax(rtwdev); 2313 if (ret) { 2314 rtw89_err(rtwdev, "[ERR]STA SCH init %d\n", ret); 2315 return ret; 2316 } 2317 2318 ret = mpdu_proc_init_ax(rtwdev); 2319 if (ret) { 2320 rtw89_err(rtwdev, "[ERR]MPDU Proc init %d\n", ret); 2321 return ret; 2322 } 2323 2324 ret = sec_eng_init_ax(rtwdev); 2325 if (ret) { 2326 rtw89_err(rtwdev, "[ERR]Security Engine init %d\n", ret); 2327 return ret; 2328 } 2329 2330 return ret; 2331 } 2332 addr_cam_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2333 static int addr_cam_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2334 { 2335 u32 val, reg; 2336 u16 p_val; 2337 int ret; 2338 2339 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2340 if (ret) 2341 return ret; 2342 2343 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_ADDR_CAM_CTRL, mac_idx); 2344 2345 val = rtw89_read32(rtwdev, reg); 2346 val |= u32_encode_bits(0x7f, B_AX_ADDR_CAM_RANGE_MASK) | 2347 B_AX_ADDR_CAM_CLR | B_AX_ADDR_CAM_EN; 2348 rtw89_write32(rtwdev, reg, val); 2349 2350 ret = read_poll_timeout(rtw89_read16, p_val, !(p_val & B_AX_ADDR_CAM_CLR), 2351 1, TRXCFG_WAIT_CNT, false, rtwdev, reg); 2352 if (ret) { 2353 rtw89_err(rtwdev, "[ERR]ADDR_CAM reset\n"); 2354 return ret; 2355 } 2356 2357 return 0; 2358 } 2359 scheduler_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2360 static int scheduler_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2361 { 2362 u32 ret; 2363 u32 reg; 2364 u32 val; 2365 2366 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2367 if (ret) 2368 return ret; 2369 2370 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_1, mac_idx); 2371 if (rtwdev->chip->chip_id == RTL8852C) 2372 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2373 SIFS_MACTXEN_T1_V1); 2374 else 2375 rtw89_write32_mask(rtwdev, reg, B_AX_SIFS_MACTXEN_T1_MASK, 2376 SIFS_MACTXEN_T1); 2377 2378 if (rtw89_is_rtl885xb(rtwdev)) { 2379 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCH_EXT_CTRL, mac_idx); 2380 rtw89_write32_set(rtwdev, reg, B_AX_PORT_RST_TSF_ADV); 2381 } 2382 2383 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CFG_0, mac_idx); 2384 rtw89_write32_clr(rtwdev, reg, B_AX_BTCCA_EN); 2385 2386 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PREBKF_CFG_0, mac_idx); 2387 if (rtwdev->chip->chip_id == RTL8852C) { 2388 val = rtw89_read32_mask(rtwdev, R_AX_SEC_ENG_CTRL, 2389 B_AX_TX_PARTIAL_MODE); 2390 if (!val) 2391 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2392 SCH_PREBKF_24US); 2393 } else { 2394 rtw89_write32_mask(rtwdev, reg, B_AX_PREBKF_TIME_MASK, 2395 SCH_PREBKF_24US); 2396 } 2397 2398 return 0; 2399 } 2400 rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev * rtwdev,enum rtw89_machdr_frame_type type,enum rtw89_mac_fwd_target fwd_target,u8 mac_idx)2401 static int rtw89_mac_typ_fltr_opt_ax(struct rtw89_dev *rtwdev, 2402 enum rtw89_machdr_frame_type type, 2403 enum rtw89_mac_fwd_target fwd_target, 2404 u8 mac_idx) 2405 { 2406 u32 reg; 2407 u32 val; 2408 2409 switch (fwd_target) { 2410 case RTW89_FWD_DONT_CARE: 2411 val = RX_FLTR_FRAME_DROP; 2412 break; 2413 case RTW89_FWD_TO_HOST: 2414 val = RX_FLTR_FRAME_TO_HOST; 2415 break; 2416 case RTW89_FWD_TO_WLAN_CPU: 2417 val = RX_FLTR_FRAME_TO_WLCPU; 2418 break; 2419 default: 2420 rtw89_err(rtwdev, "[ERR]set rx filter fwd target err\n"); 2421 return -EINVAL; 2422 } 2423 2424 switch (type) { 2425 case RTW89_MGNT: 2426 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MGNT_FLTR, mac_idx); 2427 break; 2428 case RTW89_CTRL: 2429 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTRL_FLTR, mac_idx); 2430 break; 2431 case RTW89_DATA: 2432 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DATA_FLTR, mac_idx); 2433 break; 2434 default: 2435 rtw89_err(rtwdev, "[ERR]set rx filter type err\n"); 2436 return -EINVAL; 2437 } 2438 rtw89_write32(rtwdev, reg, val); 2439 2440 return 0; 2441 } 2442 rx_fltr_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2443 static int rx_fltr_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2444 { 2445 int ret, i; 2446 u32 mac_ftlr, plcp_ftlr; 2447 2448 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2449 if (ret) 2450 return ret; 2451 2452 for (i = RTW89_MGNT; i <= RTW89_DATA; i++) { 2453 ret = rtw89_mac_typ_fltr_opt_ax(rtwdev, i, RTW89_FWD_TO_HOST, 2454 mac_idx); 2455 if (ret) 2456 return ret; 2457 } 2458 mac_ftlr = rtwdev->hal.rx_fltr; 2459 plcp_ftlr = B_AX_CCK_CRC_CHK | B_AX_CCK_SIG_CHK | 2460 B_AX_LSIG_PARITY_CHK_EN | B_AX_SIGA_CRC_CHK | 2461 B_AX_VHT_SU_SIGB_CRC_CHK | B_AX_VHT_MU_SIGB_CRC_CHK | 2462 B_AX_HE_SIGB_CRC_CHK; 2463 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx), 2464 mac_ftlr); 2465 rtw89_write16(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx), 2466 plcp_ftlr); 2467 2468 return 0; 2469 } 2470 _patch_dis_resp_chk(struct rtw89_dev * rtwdev,u8 mac_idx)2471 static void _patch_dis_resp_chk(struct rtw89_dev *rtwdev, u8 mac_idx) 2472 { 2473 u32 reg, val32; 2474 u32 b_rsp_chk_nav, b_rsp_chk_cca; 2475 2476 b_rsp_chk_nav = B_AX_RSP_CHK_TXNAV | B_AX_RSP_CHK_INTRA_NAV | 2477 B_AX_RSP_CHK_BASIC_NAV; 2478 b_rsp_chk_cca = B_AX_RSP_CHK_SEC_CCA_80 | B_AX_RSP_CHK_SEC_CCA_40 | 2479 B_AX_RSP_CHK_SEC_CCA_20 | B_AX_RSP_CHK_BTCCA | 2480 B_AX_RSP_CHK_EDCCA | B_AX_RSP_CHK_CCA; 2481 2482 switch (rtwdev->chip->chip_id) { 2483 case RTL8852A: 2484 case RTL8852B: 2485 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2486 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_nav; 2487 rtw89_write32(rtwdev, reg, val32); 2488 2489 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2490 val32 = rtw89_read32(rtwdev, reg) & ~b_rsp_chk_cca; 2491 rtw89_write32(rtwdev, reg, val32); 2492 break; 2493 default: 2494 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RSP_CHK_SIG, mac_idx); 2495 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_nav; 2496 rtw89_write32(rtwdev, reg, val32); 2497 2498 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2499 val32 = rtw89_read32(rtwdev, reg) | b_rsp_chk_cca; 2500 rtw89_write32(rtwdev, reg, val32); 2501 break; 2502 } 2503 } 2504 cca_ctrl_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2505 static int cca_ctrl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2506 { 2507 u32 val, reg; 2508 int ret; 2509 2510 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2511 if (ret) 2512 return ret; 2513 2514 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CCA_CONTROL, mac_idx); 2515 val = rtw89_read32(rtwdev, reg); 2516 val |= (B_AX_TB_CHK_BASIC_NAV | B_AX_TB_CHK_BTCCA | 2517 B_AX_TB_CHK_EDCCA | B_AX_TB_CHK_CCA_P20 | 2518 B_AX_SIFS_CHK_BTCCA | B_AX_SIFS_CHK_CCA_P20 | 2519 B_AX_CTN_CHK_INTRA_NAV | 2520 B_AX_CTN_CHK_BASIC_NAV | B_AX_CTN_CHK_BTCCA | 2521 B_AX_CTN_CHK_EDCCA | B_AX_CTN_CHK_CCA_S80 | 2522 B_AX_CTN_CHK_CCA_S40 | B_AX_CTN_CHK_CCA_S20 | 2523 B_AX_CTN_CHK_CCA_P20); 2524 val &= ~(B_AX_TB_CHK_TX_NAV | B_AX_TB_CHK_CCA_S80 | 2525 B_AX_TB_CHK_CCA_S40 | B_AX_TB_CHK_CCA_S20 | 2526 B_AX_SIFS_CHK_CCA_S80 | B_AX_SIFS_CHK_CCA_S40 | 2527 B_AX_SIFS_CHK_CCA_S20 | B_AX_CTN_CHK_TXNAV | 2528 B_AX_SIFS_CHK_EDCCA); 2529 2530 rtw89_write32(rtwdev, reg, val); 2531 2532 _patch_dis_resp_chk(rtwdev, mac_idx); 2533 2534 return 0; 2535 } 2536 nav_ctrl_init_ax(struct rtw89_dev * rtwdev)2537 static int nav_ctrl_init_ax(struct rtw89_dev *rtwdev) 2538 { 2539 rtw89_write32_set(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_PLCP_UP_NAV_EN | 2540 B_AX_WMAC_TF_UP_NAV_EN | 2541 B_AX_WMAC_NAV_UPPER_EN); 2542 rtw89_write32_mask(rtwdev, R_AX_WMAC_NAV_CTL, B_AX_WMAC_NAV_UPPER_MASK, NAV_25MS); 2543 2544 return 0; 2545 } 2546 spatial_reuse_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2547 static int spatial_reuse_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2548 { 2549 u32 reg; 2550 int ret; 2551 2552 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2553 if (ret) 2554 return ret; 2555 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_SR_CTRL, mac_idx); 2556 rtw89_write8_clr(rtwdev, reg, B_AX_SR_EN); 2557 2558 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BSSID_SRC_CTRL, mac_idx); 2559 rtw89_write8_set(rtwdev, reg, B_AX_PLCP_SRC_EN); 2560 2561 return 0; 2562 } 2563 tmac_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2564 static int tmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2565 { 2566 u32 reg; 2567 int ret; 2568 2569 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2570 if (ret) 2571 return ret; 2572 2573 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MAC_LOOPBACK, mac_idx); 2574 rtw89_write32_clr(rtwdev, reg, B_AX_MACLBK_EN); 2575 2576 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TCR0, mac_idx); 2577 rtw89_write32_mask(rtwdev, reg, B_AX_TCR_UDF_THSD_MASK, TCR_UDF_THSD); 2578 2579 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXD_FIFO_CTRL, mac_idx); 2580 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_HIGH_MCS_THRE_MASK, TXDFIFO_HIGH_MCS_THRE); 2581 rtw89_write32_mask(rtwdev, reg, B_AX_TXDFIFO_LOW_MCS_THRE_MASK, TXDFIFO_LOW_MCS_THRE); 2582 2583 return 0; 2584 } 2585 trxptcl_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2586 static int trxptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2587 { 2588 const struct rtw89_chip_info *chip = rtwdev->chip; 2589 const struct rtw89_rrsr_cfgs *rrsr = chip->rrsr_cfgs; 2590 u32 reg, val, sifs; 2591 int ret; 2592 2593 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2594 if (ret) 2595 return ret; 2596 2597 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_0, mac_idx); 2598 val = rtw89_read32(rtwdev, reg); 2599 val &= ~B_AX_WMAC_SPEC_SIFS_CCK_MASK; 2600 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_CCK_MASK, WMAC_SPEC_SIFS_CCK); 2601 2602 switch (rtwdev->chip->chip_id) { 2603 case RTL8852A: 2604 sifs = WMAC_SPEC_SIFS_OFDM_52A; 2605 break; 2606 case RTL8851B: 2607 case RTL8852B: 2608 case RTL8852BT: 2609 sifs = WMAC_SPEC_SIFS_OFDM_52B; 2610 break; 2611 default: 2612 sifs = WMAC_SPEC_SIFS_OFDM_52C; 2613 break; 2614 } 2615 val &= ~B_AX_WMAC_SPEC_SIFS_OFDM_MASK; 2616 val |= FIELD_PREP(B_AX_WMAC_SPEC_SIFS_OFDM_MASK, sifs); 2617 rtw89_write32(rtwdev, reg, val); 2618 2619 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXTRIG_TEST_USER_2, mac_idx); 2620 rtw89_write32_set(rtwdev, reg, B_AX_RXTRIG_FCSCHK_EN); 2621 2622 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->ref_rate.addr, mac_idx); 2623 rtw89_write32_mask(rtwdev, reg, rrsr->ref_rate.mask, rrsr->ref_rate.data); 2624 reg = rtw89_mac_reg_by_idx(rtwdev, rrsr->rsc.addr, mac_idx); 2625 rtw89_write32_mask(rtwdev, reg, rrsr->rsc.mask, rrsr->rsc.data); 2626 2627 return 0; 2628 } 2629 rst_bacam(struct rtw89_dev * rtwdev)2630 static void rst_bacam(struct rtw89_dev *rtwdev) 2631 { 2632 u32 val32; 2633 int ret; 2634 2635 rtw89_write32_mask(rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK, 2636 S_AX_BACAM_RST_ALL); 2637 2638 ret = read_poll_timeout_atomic(rtw89_read32_mask, val32, val32 == 0, 2639 1, 1000, false, 2640 rtwdev, R_AX_RESPBA_CAM_CTRL, B_AX_BACAM_RST_MASK); 2641 if (ret) 2642 rtw89_warn(rtwdev, "failed to reset BA CAM\n"); 2643 } 2644 rmac_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2645 static int rmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2646 { 2647 #define TRXCFG_RMAC_CCA_TO 32 2648 #define TRXCFG_RMAC_DATA_TO 15 2649 #define RX_MAX_LEN_UNIT 512 2650 #define PLD_RLS_MAX_PG 127 2651 #define RX_SPEC_MAX_LEN (11454 + RX_MAX_LEN_UNIT) 2652 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2653 int ret; 2654 u32 reg, rx_max_len, rx_qta; 2655 u16 val; 2656 2657 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2658 if (ret) 2659 return ret; 2660 2661 if (mac_idx == RTW89_MAC_0) 2662 rst_bacam(rtwdev); 2663 2664 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RESPBA_CAM_CTRL, mac_idx); 2665 rtw89_write8_set(rtwdev, reg, B_AX_SSN_SEL); 2666 2667 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx); 2668 val = rtw89_read16(rtwdev, reg); 2669 val = u16_replace_bits(val, TRXCFG_RMAC_DATA_TO, 2670 B_AX_RX_DLK_DATA_TIME_MASK); 2671 val = u16_replace_bits(val, TRXCFG_RMAC_CCA_TO, 2672 B_AX_RX_DLK_CCA_TIME_MASK); 2673 if (chip_id == RTL8852BT) 2674 val |= B_AX_RX_DLK_RST_EN; 2675 rtw89_write16(rtwdev, reg, val); 2676 2677 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx); 2678 rtw89_write8_mask(rtwdev, reg, B_AX_CH_EN_MASK, 0x1); 2679 2680 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RX_FLTR_OPT, mac_idx); 2681 if (mac_idx == RTW89_MAC_0) 2682 rx_qta = rtwdev->mac.dle_info.c0_rx_qta; 2683 else 2684 rx_qta = rtwdev->mac.dle_info.c1_rx_qta; 2685 rx_qta = min_t(u32, rx_qta, PLD_RLS_MAX_PG); 2686 rx_max_len = rx_qta * rtwdev->mac.dle_info.ple_pg_size; 2687 rx_max_len = min_t(u32, rx_max_len, RX_SPEC_MAX_LEN); 2688 rx_max_len /= RX_MAX_LEN_UNIT; 2689 rtw89_write32_mask(rtwdev, reg, B_AX_RX_MPDU_MAX_LEN_MASK, rx_max_len); 2690 2691 if (chip_id == RTL8852A && rtwdev->hal.cv == CHIP_CBV) { 2692 rtw89_write16_mask(rtwdev, 2693 rtw89_mac_reg_by_idx(rtwdev, R_AX_DLK_PROTECT_CTL, mac_idx), 2694 B_AX_RX_DLK_CCA_TIME_MASK, 0); 2695 rtw89_write16_set(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_RCR, mac_idx), 2696 BIT(12)); 2697 } 2698 2699 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PLCP_HDR_FLTR, mac_idx); 2700 rtw89_write8_clr(rtwdev, reg, B_AX_VHT_SU_SIGB_CRC_CHK); 2701 2702 return ret; 2703 } 2704 cmac_com_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2705 static int cmac_com_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2706 { 2707 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2708 u32 val, reg; 2709 int ret; 2710 2711 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2712 if (ret) 2713 return ret; 2714 2715 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TX_SUB_CARRIER_VALUE, mac_idx); 2716 val = rtw89_read32(rtwdev, reg); 2717 val = u32_replace_bits(val, 0, B_AX_TXSC_20M_MASK); 2718 val = u32_replace_bits(val, 0, B_AX_TXSC_40M_MASK); 2719 val = u32_replace_bits(val, 0, B_AX_TXSC_80M_MASK); 2720 rtw89_write32(rtwdev, reg, val); 2721 2722 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2723 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_RRSR1, mac_idx); 2724 rtw89_write32_mask(rtwdev, reg, B_AX_RRSR_RATE_EN_MASK, RRSR_OFDM_CCK_EN); 2725 } 2726 2727 return 0; 2728 } 2729 rtw89_mac_is_qta_dbcc(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode)2730 bool rtw89_mac_is_qta_dbcc(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode) 2731 { 2732 const struct rtw89_dle_mem *cfg; 2733 2734 cfg = get_dle_mem_cfg(rtwdev, mode); 2735 if (!cfg) { 2736 rtw89_err(rtwdev, "[ERR]get_dle_mem_cfg\n"); 2737 return false; 2738 } 2739 2740 return (cfg->ple_min_qt->cma1_dma && cfg->ple_max_qt->cma1_dma); 2741 } 2742 ptcl_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2743 static int ptcl_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2744 { 2745 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 2746 u32 val, reg; 2747 int ret; 2748 2749 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2750 if (ret) 2751 return ret; 2752 2753 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 2754 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SIFS_SETTING, mac_idx); 2755 val = rtw89_read32(rtwdev, reg); 2756 val = u32_replace_bits(val, S_AX_CTS2S_TH_1K, 2757 B_AX_HW_CTS2SELF_PKT_LEN_TH_MASK); 2758 val = u32_replace_bits(val, S_AX_CTS2S_TH_SEC_256B, 2759 B_AX_HW_CTS2SELF_PKT_LEN_TH_TWW_MASK); 2760 val |= B_AX_HW_CTS2SELF_EN; 2761 rtw89_write32(rtwdev, reg, val); 2762 2763 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_FSM_MON, mac_idx); 2764 val = rtw89_read32(rtwdev, reg); 2765 val = u32_replace_bits(val, S_AX_PTCL_TO_2MS, B_AX_PTCL_TX_ARB_TO_THR_MASK); 2766 val &= ~B_AX_PTCL_TX_ARB_TO_MODE; 2767 rtw89_write32(rtwdev, reg, val); 2768 } 2769 2770 if (mac_idx == RTW89_MAC_0) { 2771 rtw89_write8_set(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2772 B_AX_CMAC_TX_MODE_0 | B_AX_CMAC_TX_MODE_1); 2773 rtw89_write8_clr(rtwdev, R_AX_PTCL_COMMON_SETTING_0, 2774 B_AX_PTCL_TRIGGER_SS_EN_0 | 2775 B_AX_PTCL_TRIGGER_SS_EN_1 | 2776 B_AX_PTCL_TRIGGER_SS_EN_UL); 2777 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL, 2778 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2779 } else if (mac_idx == RTW89_MAC_1) { 2780 rtw89_write8_mask(rtwdev, R_AX_PTCLRPT_FULL_HDL_C1, 2781 B_AX_SPE_RPT_PATH_MASK, FWD_TO_WLCPU); 2782 } 2783 2784 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) { 2785 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AGG_LEN_VHT_0, mac_idx); 2786 rtw89_write32_mask(rtwdev, reg, 2787 B_AX_AMPDU_MAX_LEN_VHT_MASK, 0x3FF80); 2788 } 2789 2790 return 0; 2791 } 2792 cmac_dma_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2793 static int cmac_dma_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2794 { 2795 u32 reg; 2796 int ret; 2797 2798 if (!rtw89_is_rtl885xb(rtwdev)) 2799 return 0; 2800 2801 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 2802 if (ret) 2803 return ret; 2804 2805 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_RXDMA_CTRL_0, mac_idx); 2806 rtw89_write8_clr(rtwdev, reg, RX_FULL_MODE); 2807 2808 return 0; 2809 } 2810 cmac_init_ax(struct rtw89_dev * rtwdev,u8 mac_idx)2811 static int cmac_init_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 2812 { 2813 int ret; 2814 2815 ret = scheduler_init_ax(rtwdev, mac_idx); 2816 if (ret) { 2817 rtw89_err(rtwdev, "[ERR]CMAC%d SCH init %d\n", mac_idx, ret); 2818 return ret; 2819 } 2820 2821 ret = addr_cam_init_ax(rtwdev, mac_idx); 2822 if (ret) { 2823 rtw89_err(rtwdev, "[ERR]CMAC%d ADDR_CAM reset %d\n", mac_idx, 2824 ret); 2825 return ret; 2826 } 2827 2828 ret = rx_fltr_init_ax(rtwdev, mac_idx); 2829 if (ret) { 2830 rtw89_err(rtwdev, "[ERR]CMAC%d RX filter init %d\n", mac_idx, 2831 ret); 2832 return ret; 2833 } 2834 2835 ret = cca_ctrl_init_ax(rtwdev, mac_idx); 2836 if (ret) { 2837 rtw89_err(rtwdev, "[ERR]CMAC%d CCA CTRL init %d\n", mac_idx, 2838 ret); 2839 return ret; 2840 } 2841 2842 ret = nav_ctrl_init_ax(rtwdev); 2843 if (ret) { 2844 rtw89_err(rtwdev, "[ERR]CMAC%d NAV CTRL init %d\n", mac_idx, 2845 ret); 2846 return ret; 2847 } 2848 2849 ret = spatial_reuse_init_ax(rtwdev, mac_idx); 2850 if (ret) { 2851 rtw89_err(rtwdev, "[ERR]CMAC%d Spatial Reuse init %d\n", 2852 mac_idx, ret); 2853 return ret; 2854 } 2855 2856 ret = tmac_init_ax(rtwdev, mac_idx); 2857 if (ret) { 2858 rtw89_err(rtwdev, "[ERR]CMAC%d TMAC init %d\n", mac_idx, ret); 2859 return ret; 2860 } 2861 2862 ret = trxptcl_init_ax(rtwdev, mac_idx); 2863 if (ret) { 2864 rtw89_err(rtwdev, "[ERR]CMAC%d TRXPTCL init %d\n", mac_idx, ret); 2865 return ret; 2866 } 2867 2868 ret = rmac_init_ax(rtwdev, mac_idx); 2869 if (ret) { 2870 rtw89_err(rtwdev, "[ERR]CMAC%d RMAC init %d\n", mac_idx, ret); 2871 return ret; 2872 } 2873 2874 ret = cmac_com_init_ax(rtwdev, mac_idx); 2875 if (ret) { 2876 rtw89_err(rtwdev, "[ERR]CMAC%d Com init %d\n", mac_idx, ret); 2877 return ret; 2878 } 2879 2880 ret = ptcl_init_ax(rtwdev, mac_idx); 2881 if (ret) { 2882 rtw89_err(rtwdev, "[ERR]CMAC%d PTCL init %d\n", mac_idx, ret); 2883 return ret; 2884 } 2885 2886 ret = cmac_dma_init_ax(rtwdev, mac_idx); 2887 if (ret) { 2888 rtw89_err(rtwdev, "[ERR]CMAC%d DMA init %d\n", mac_idx, ret); 2889 return ret; 2890 } 2891 2892 return ret; 2893 } 2894 rtw89_mac_read_phycap(struct rtw89_dev * rtwdev,struct rtw89_mac_c2h_info * c2h_info)2895 static int rtw89_mac_read_phycap(struct rtw89_dev *rtwdev, 2896 struct rtw89_mac_c2h_info *c2h_info) 2897 { 2898 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 2899 struct rtw89_mac_h2c_info h2c_info = {0}; 2900 u32 ret; 2901 2902 mac->cnv_efuse_state(rtwdev, false); 2903 2904 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_GET_FEATURE; 2905 h2c_info.content_len = 0; 2906 2907 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, c2h_info); 2908 if (ret) 2909 goto out; 2910 2911 if (c2h_info->id != RTW89_FWCMD_C2HREG_FUNC_PHY_CAP) 2912 ret = -EINVAL; 2913 2914 out: 2915 mac->cnv_efuse_state(rtwdev, true); 2916 2917 return ret; 2918 } 2919 rtw89_mac_setup_phycap(struct rtw89_dev * rtwdev)2920 int rtw89_mac_setup_phycap(struct rtw89_dev *rtwdev) 2921 { 2922 struct rtw89_efuse *efuse = &rtwdev->efuse; 2923 struct rtw89_hal *hal = &rtwdev->hal; 2924 const struct rtw89_chip_info *chip = rtwdev->chip; 2925 struct rtw89_mac_c2h_info c2h_info = {0}; 2926 const struct rtw89_c2hreg_phycap *phycap; 2927 u8 tx_nss; 2928 u8 rx_nss; 2929 u8 tx_ant; 2930 u8 rx_ant; 2931 u32 ret; 2932 2933 ret = rtw89_mac_read_phycap(rtwdev, &c2h_info); 2934 if (ret) 2935 return ret; 2936 2937 phycap = &c2h_info.u.phycap; 2938 2939 tx_nss = u32_get_bits(phycap->w1, RTW89_C2HREG_PHYCAP_W1_TX_NSS); 2940 rx_nss = u32_get_bits(phycap->w0, RTW89_C2HREG_PHYCAP_W0_RX_NSS); 2941 tx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_TX_NUM); 2942 rx_ant = u32_get_bits(phycap->w3, RTW89_C2HREG_PHYCAP_W3_ANT_RX_NUM); 2943 2944 hal->tx_nss = tx_nss ? min_t(u8, tx_nss, chip->tx_nss) : chip->tx_nss; 2945 hal->rx_nss = rx_nss ? min_t(u8, rx_nss, chip->rx_nss) : chip->rx_nss; 2946 2947 if (tx_ant == 1) 2948 hal->antenna_tx = RF_B; 2949 if (rx_ant == 1) 2950 hal->antenna_rx = RF_B; 2951 2952 if (tx_nss == 1 && tx_ant == 2 && rx_ant == 2) { 2953 hal->antenna_tx = RF_B; 2954 hal->tx_path_diversity = true; 2955 } 2956 2957 if (chip->rf_path_num == 1) { 2958 hal->antenna_tx = RF_A; 2959 hal->antenna_rx = RF_A; 2960 if ((efuse->rfe_type % 3) == 2) 2961 hal->ant_diversity = true; 2962 } 2963 2964 rtw89_debug(rtwdev, RTW89_DBG_FW, 2965 "phycap hal/phy/chip: tx_nss=0x%x/0x%x/0x%x rx_nss=0x%x/0x%x/0x%x\n", 2966 hal->tx_nss, tx_nss, chip->tx_nss, 2967 hal->rx_nss, rx_nss, chip->rx_nss); 2968 rtw89_debug(rtwdev, RTW89_DBG_FW, 2969 "ant num/bitmap: tx=%d/0x%x rx=%d/0x%x\n", 2970 tx_ant, hal->antenna_tx, rx_ant, hal->antenna_rx); 2971 rtw89_debug(rtwdev, RTW89_DBG_FW, "TX path diversity=%d\n", hal->tx_path_diversity); 2972 rtw89_debug(rtwdev, RTW89_DBG_FW, "Antenna diversity=%d\n", hal->ant_diversity); 2973 2974 return 0; 2975 } 2976 rtw89_hw_sch_tx_en_h2c(struct rtw89_dev * rtwdev,u8 band,u16 tx_en_u16,u16 mask_u16)2977 static int rtw89_hw_sch_tx_en_h2c(struct rtw89_dev *rtwdev, u8 band, 2978 u16 tx_en_u16, u16 mask_u16) 2979 { 2980 u32 ret; 2981 struct rtw89_mac_c2h_info c2h_info = {0}; 2982 struct rtw89_mac_h2c_info h2c_info = {0}; 2983 struct rtw89_h2creg_sch_tx_en *sch_tx_en = &h2c_info.u.sch_tx_en; 2984 2985 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_SCH_TX_EN; 2986 h2c_info.content_len = sizeof(*sch_tx_en) - RTW89_H2CREG_HDR_LEN; 2987 2988 u32p_replace_bits(&sch_tx_en->w0, tx_en_u16, RTW89_H2CREG_SCH_TX_EN_W0_EN); 2989 u32p_replace_bits(&sch_tx_en->w1, mask_u16, RTW89_H2CREG_SCH_TX_EN_W1_MASK); 2990 u32p_replace_bits(&sch_tx_en->w1, band, RTW89_H2CREG_SCH_TX_EN_W1_BAND); 2991 2992 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 2993 if (ret) 2994 return ret; 2995 2996 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_TX_PAUSE_RPT) 2997 return -EINVAL; 2998 2999 return 0; 3000 } 3001 rtw89_set_hw_sch_tx_en(struct rtw89_dev * rtwdev,u8 mac_idx,u16 tx_en,u16 tx_en_mask)3002 static int rtw89_set_hw_sch_tx_en(struct rtw89_dev *rtwdev, u8 mac_idx, 3003 u16 tx_en, u16 tx_en_mask) 3004 { 3005 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx); 3006 u16 val; 3007 int ret; 3008 3009 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3010 if (ret) 3011 return ret; 3012 3013 if (test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags)) 3014 return rtw89_hw_sch_tx_en_h2c(rtwdev, mac_idx, 3015 tx_en, tx_en_mask); 3016 3017 val = rtw89_read16(rtwdev, reg); 3018 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3019 rtw89_write16(rtwdev, reg, val); 3020 3021 return 0; 3022 } 3023 rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en,u32 tx_en_mask)3024 static int rtw89_set_hw_sch_tx_en_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3025 u32 tx_en, u32 tx_en_mask) 3026 { 3027 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx); 3028 u32 val; 3029 int ret; 3030 3031 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3032 if (ret) 3033 return ret; 3034 3035 val = rtw89_read32(rtwdev, reg); 3036 val = (val & ~tx_en_mask) | (tx_en & tx_en_mask); 3037 rtw89_write32(rtwdev, reg, val); 3038 3039 return 0; 3040 } 3041 rtw89_mac_stop_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)3042 int rtw89_mac_stop_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, 3043 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3044 { 3045 int ret; 3046 3047 *tx_en = rtw89_read16(rtwdev, 3048 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_TXEN, mac_idx)); 3049 3050 switch (sel) { 3051 case RTW89_SCH_TX_SEL_ALL: 3052 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3053 B_AX_CTN_TXEN_ALL_MASK); 3054 if (ret) 3055 return ret; 3056 break; 3057 case RTW89_SCH_TX_SEL_HIQ: 3058 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3059 0, B_AX_CTN_TXEN_HGQ); 3060 if (ret) 3061 return ret; 3062 break; 3063 case RTW89_SCH_TX_SEL_MG0: 3064 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 3065 0, B_AX_CTN_TXEN_MGQ); 3066 if (ret) 3067 return ret; 3068 break; 3069 case RTW89_SCH_TX_SEL_MACID: 3070 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, 0, 3071 B_AX_CTN_TXEN_ALL_MASK); 3072 if (ret) 3073 return ret; 3074 break; 3075 default: 3076 return 0; 3077 } 3078 3079 return 0; 3080 } 3081 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx); 3082 rtw89_mac_stop_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 * tx_en,enum rtw89_sch_tx_sel sel)3083 int rtw89_mac_stop_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, 3084 u32 *tx_en, enum rtw89_sch_tx_sel sel) 3085 { 3086 int ret; 3087 3088 *tx_en = rtw89_read32(rtwdev, 3089 rtw89_mac_reg_by_idx(rtwdev, R_AX_CTN_DRV_TXEN, mac_idx)); 3090 3091 switch (sel) { 3092 case RTW89_SCH_TX_SEL_ALL: 3093 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3094 B_AX_CTN_TXEN_ALL_MASK_V1); 3095 if (ret) 3096 return ret; 3097 break; 3098 case RTW89_SCH_TX_SEL_HIQ: 3099 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3100 0, B_AX_CTN_TXEN_HGQ); 3101 if (ret) 3102 return ret; 3103 break; 3104 case RTW89_SCH_TX_SEL_MG0: 3105 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 3106 0, B_AX_CTN_TXEN_MGQ); 3107 if (ret) 3108 return ret; 3109 break; 3110 case RTW89_SCH_TX_SEL_MACID: 3111 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, 0, 3112 B_AX_CTN_TXEN_ALL_MASK_V1); 3113 if (ret) 3114 return ret; 3115 break; 3116 default: 3117 return 0; 3118 } 3119 3120 return 0; 3121 } 3122 EXPORT_SYMBOL(rtw89_mac_stop_sch_tx_v1); 3123 rtw89_mac_resume_sch_tx(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)3124 int rtw89_mac_resume_sch_tx(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3125 { 3126 int ret; 3127 3128 ret = rtw89_set_hw_sch_tx_en(rtwdev, mac_idx, tx_en, B_AX_CTN_TXEN_ALL_MASK); 3129 if (ret) 3130 return ret; 3131 3132 return 0; 3133 } 3134 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx); 3135 rtw89_mac_resume_sch_tx_v1(struct rtw89_dev * rtwdev,u8 mac_idx,u32 tx_en)3136 int rtw89_mac_resume_sch_tx_v1(struct rtw89_dev *rtwdev, u8 mac_idx, u32 tx_en) 3137 { 3138 int ret; 3139 3140 ret = rtw89_set_hw_sch_tx_en_v1(rtwdev, mac_idx, tx_en, 3141 B_AX_CTN_TXEN_ALL_MASK_V1); 3142 if (ret) 3143 return ret; 3144 3145 return 0; 3146 } 3147 EXPORT_SYMBOL(rtw89_mac_resume_sch_tx_v1); 3148 dle_buf_req_ax(struct rtw89_dev * rtwdev,u16 buf_len,bool wd,u16 * pkt_id)3149 static int dle_buf_req_ax(struct rtw89_dev *rtwdev, u16 buf_len, bool wd, u16 *pkt_id) 3150 { 3151 u32 val, reg; 3152 int ret; 3153 3154 reg = wd ? R_AX_WD_BUF_REQ : R_AX_PL_BUF_REQ; 3155 val = buf_len; 3156 val |= B_AX_WD_BUF_REQ_EXEC; 3157 rtw89_write32(rtwdev, reg, val); 3158 3159 reg = wd ? R_AX_WD_BUF_STATUS : R_AX_PL_BUF_STATUS; 3160 3161 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_BUF_STAT_DONE, 3162 1, 2000, false, rtwdev, reg); 3163 if (ret) 3164 return ret; 3165 3166 *pkt_id = FIELD_GET(B_AX_WD_BUF_STAT_PKTID_MASK, val); 3167 if (*pkt_id == S_WD_BUF_STAT_PKTID_INVALID) 3168 return -ENOENT; 3169 3170 return 0; 3171 } 3172 set_cpuio_ax(struct rtw89_dev * rtwdev,struct rtw89_cpuio_ctrl * ctrl_para,bool wd)3173 static int set_cpuio_ax(struct rtw89_dev *rtwdev, 3174 struct rtw89_cpuio_ctrl *ctrl_para, bool wd) 3175 { 3176 u32 val, cmd_type, reg; 3177 int ret; 3178 3179 cmd_type = ctrl_para->cmd_type; 3180 3181 reg = wd ? R_AX_WD_CPUQ_OP_2 : R_AX_PL_CPUQ_OP_2; 3182 val = 0; 3183 val = u32_replace_bits(val, ctrl_para->start_pktid, 3184 B_AX_WD_CPUQ_OP_STRT_PKTID_MASK); 3185 val = u32_replace_bits(val, ctrl_para->end_pktid, 3186 B_AX_WD_CPUQ_OP_END_PKTID_MASK); 3187 rtw89_write32(rtwdev, reg, val); 3188 3189 reg = wd ? R_AX_WD_CPUQ_OP_1 : R_AX_PL_CPUQ_OP_1; 3190 val = 0; 3191 val = u32_replace_bits(val, ctrl_para->src_pid, 3192 B_AX_CPUQ_OP_SRC_PID_MASK); 3193 val = u32_replace_bits(val, ctrl_para->src_qid, 3194 B_AX_CPUQ_OP_SRC_QID_MASK); 3195 val = u32_replace_bits(val, ctrl_para->dst_pid, 3196 B_AX_CPUQ_OP_DST_PID_MASK); 3197 val = u32_replace_bits(val, ctrl_para->dst_qid, 3198 B_AX_CPUQ_OP_DST_QID_MASK); 3199 rtw89_write32(rtwdev, reg, val); 3200 3201 reg = wd ? R_AX_WD_CPUQ_OP_0 : R_AX_PL_CPUQ_OP_0; 3202 val = 0; 3203 val = u32_replace_bits(val, cmd_type, 3204 B_AX_CPUQ_OP_CMD_TYPE_MASK); 3205 val = u32_replace_bits(val, ctrl_para->macid, 3206 B_AX_CPUQ_OP_MACID_MASK); 3207 val = u32_replace_bits(val, ctrl_para->pkt_num, 3208 B_AX_CPUQ_OP_PKTNUM_MASK); 3209 val |= B_AX_WD_CPUQ_OP_EXEC; 3210 rtw89_write32(rtwdev, reg, val); 3211 3212 reg = wd ? R_AX_WD_CPUQ_OP_STATUS : R_AX_PL_CPUQ_OP_STATUS; 3213 3214 ret = read_poll_timeout(rtw89_read32, val, val & B_AX_WD_CPUQ_OP_STAT_DONE, 3215 1, 2000, false, rtwdev, reg); 3216 if (ret) 3217 return ret; 3218 3219 if (cmd_type == CPUIO_OP_CMD_GET_1ST_PID || 3220 cmd_type == CPUIO_OP_CMD_GET_NEXT_PID) 3221 ctrl_para->pktid = FIELD_GET(B_AX_WD_CPUQ_OP_PKTID_MASK, val); 3222 3223 return 0; 3224 } 3225 rtw89_mac_dle_quota_change(struct rtw89_dev * rtwdev,enum rtw89_qta_mode mode,bool band1_en)3226 int rtw89_mac_dle_quota_change(struct rtw89_dev *rtwdev, enum rtw89_qta_mode mode, 3227 bool band1_en) 3228 { 3229 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3230 const struct rtw89_dle_mem *cfg; 3231 3232 cfg = get_dle_mem_cfg(rtwdev, mode); 3233 if (!cfg) { 3234 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3235 return -EINVAL; 3236 } 3237 3238 if (dle_used_size(cfg) != dle_expected_used_size(rtwdev, mode)) { 3239 rtw89_err(rtwdev, "[ERR]wd/dle mem cfg\n"); 3240 return -EINVAL; 3241 } 3242 3243 dle_quota_cfg(rtwdev, cfg, INVALID_QT_WCPU); 3244 3245 return mac->dle_quota_change(rtwdev, band1_en); 3246 } 3247 dle_quota_change_ax(struct rtw89_dev * rtwdev,bool band1_en)3248 static int dle_quota_change_ax(struct rtw89_dev *rtwdev, bool band1_en) 3249 { 3250 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3251 struct rtw89_cpuio_ctrl ctrl_para = {0}; 3252 u16 pkt_id; 3253 int ret; 3254 3255 ret = mac->dle_buf_req(rtwdev, 0x20, true, &pkt_id); 3256 if (ret) { 3257 rtw89_err(rtwdev, "[ERR]WDE DLE buf req\n"); 3258 return ret; 3259 } 3260 3261 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3262 ctrl_para.start_pktid = pkt_id; 3263 ctrl_para.end_pktid = pkt_id; 3264 ctrl_para.pkt_num = 0; 3265 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS; 3266 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT; 3267 ret = mac->set_cpuio(rtwdev, &ctrl_para, true); 3268 if (ret) { 3269 rtw89_err(rtwdev, "[ERR]WDE DLE enqueue to head\n"); 3270 return -EFAULT; 3271 } 3272 3273 ret = mac->dle_buf_req(rtwdev, 0x20, false, &pkt_id); 3274 if (ret) { 3275 rtw89_err(rtwdev, "[ERR]PLE DLE buf req\n"); 3276 return ret; 3277 } 3278 3279 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD; 3280 ctrl_para.start_pktid = pkt_id; 3281 ctrl_para.end_pktid = pkt_id; 3282 ctrl_para.pkt_num = 0; 3283 ctrl_para.dst_pid = PLE_DLE_PORT_ID_PLRLS; 3284 ctrl_para.dst_qid = PLE_DLE_QUEID_NO_REPORT; 3285 ret = mac->set_cpuio(rtwdev, &ctrl_para, false); 3286 if (ret) { 3287 rtw89_err(rtwdev, "[ERR]PLE DLE enqueue to head\n"); 3288 return -EFAULT; 3289 } 3290 3291 return 0; 3292 } 3293 band_idle_ck_b(struct rtw89_dev * rtwdev,u8 mac_idx)3294 static int band_idle_ck_b(struct rtw89_dev *rtwdev, u8 mac_idx) 3295 { 3296 int ret; 3297 u32 reg; 3298 u8 val; 3299 3300 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 3301 if (ret) 3302 return ret; 3303 3304 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_TX_CTN_SEL, mac_idx); 3305 3306 ret = read_poll_timeout(rtw89_read8, val, 3307 (val & B_AX_PTCL_TX_ON_STAT) == 0, 3308 SW_CVR_DUR_US, 3309 SW_CVR_DUR_US * PTCL_IDLE_POLL_CNT, 3310 false, rtwdev, reg); 3311 if (ret) 3312 return ret; 3313 3314 return 0; 3315 } 3316 band1_enable_ax(struct rtw89_dev * rtwdev)3317 static int band1_enable_ax(struct rtw89_dev *rtwdev) 3318 { 3319 int ret, i; 3320 u32 sleep_bak[4] = {0}; 3321 u32 pause_bak[4] = {0}; 3322 u32 tx_en; 3323 3324 ret = rtw89_chip_stop_sch_tx(rtwdev, 0, &tx_en, RTW89_SCH_TX_SEL_ALL); 3325 if (ret) { 3326 rtw89_err(rtwdev, "[ERR]stop sch tx %d\n", ret); 3327 return ret; 3328 } 3329 3330 for (i = 0; i < 4; i++) { 3331 sleep_bak[i] = rtw89_read32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4); 3332 pause_bak[i] = rtw89_read32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4); 3333 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, U32_MAX); 3334 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, U32_MAX); 3335 } 3336 3337 ret = band_idle_ck_b(rtwdev, 0); 3338 if (ret) { 3339 rtw89_err(rtwdev, "[ERR]tx idle poll %d\n", ret); 3340 return ret; 3341 } 3342 3343 ret = rtw89_mac_dle_quota_change(rtwdev, rtwdev->mac.qta_mode, true); 3344 if (ret) { 3345 rtw89_err(rtwdev, "[ERR]DLE quota change %d\n", ret); 3346 return ret; 3347 } 3348 3349 for (i = 0; i < 4; i++) { 3350 rtw89_write32(rtwdev, R_AX_MACID_SLEEP_0 + i * 4, sleep_bak[i]); 3351 rtw89_write32(rtwdev, R_AX_SS_MACID_PAUSE_0 + i * 4, pause_bak[i]); 3352 } 3353 3354 ret = rtw89_chip_resume_sch_tx(rtwdev, 0, tx_en); 3355 if (ret) { 3356 rtw89_err(rtwdev, "[ERR]CMAC1 resume sch tx %d\n", ret); 3357 return ret; 3358 } 3359 3360 ret = cmac_func_en_ax(rtwdev, 1, true); 3361 if (ret) { 3362 rtw89_err(rtwdev, "[ERR]CMAC1 func en %d\n", ret); 3363 return ret; 3364 } 3365 3366 ret = cmac_init_ax(rtwdev, 1); 3367 if (ret) { 3368 rtw89_err(rtwdev, "[ERR]CMAC1 init %d\n", ret); 3369 return ret; 3370 } 3371 3372 rtw89_write32_set(rtwdev, R_AX_SYS_ISO_CTRL_EXTEND, 3373 B_AX_R_SYM_FEN_WLBBFUN_1 | B_AX_R_SYM_FEN_WLBBGLB_1); 3374 3375 return 0; 3376 } 3377 rtw89_wdrls_imr_enable(struct rtw89_dev * rtwdev)3378 static void rtw89_wdrls_imr_enable(struct rtw89_dev *rtwdev) 3379 { 3380 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3381 3382 rtw89_write32_clr(rtwdev, R_AX_WDRLS_ERR_IMR, B_AX_WDRLS_IMR_EN_CLR); 3383 rtw89_write32_set(rtwdev, R_AX_WDRLS_ERR_IMR, imr->wdrls_imr_set); 3384 } 3385 rtw89_wsec_imr_enable(struct rtw89_dev * rtwdev)3386 static void rtw89_wsec_imr_enable(struct rtw89_dev *rtwdev) 3387 { 3388 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3389 3390 rtw89_write32_set(rtwdev, imr->wsec_imr_reg, imr->wsec_imr_set); 3391 } 3392 rtw89_mpdu_trx_imr_enable(struct rtw89_dev * rtwdev)3393 static void rtw89_mpdu_trx_imr_enable(struct rtw89_dev *rtwdev) 3394 { 3395 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3396 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3397 3398 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3399 B_AX_TX_GET_ERRPKTID_INT_EN | 3400 B_AX_TX_NXT_ERRPKTID_INT_EN | 3401 B_AX_TX_MPDU_SIZE_ZERO_INT_EN | 3402 B_AX_TX_OFFSET_ERR_INT_EN | 3403 B_AX_TX_HDR3_SIZE_ERR_INT_EN); 3404 if (chip_id == RTL8852C) 3405 rtw89_write32_clr(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3406 B_AX_TX_ETH_TYPE_ERR_EN | 3407 B_AX_TX_LLC_PRE_ERR_EN | 3408 B_AX_TX_NW_TYPE_ERR_EN | 3409 B_AX_TX_KSRCH_ERR_EN); 3410 rtw89_write32_set(rtwdev, R_AX_MPDU_TX_ERR_IMR, 3411 imr->mpdu_tx_imr_set); 3412 3413 rtw89_write32_clr(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3414 B_AX_GETPKTID_ERR_INT_EN | 3415 B_AX_MHDRLEN_ERR_INT_EN | 3416 B_AX_RPT_ERR_INT_EN); 3417 rtw89_write32_set(rtwdev, R_AX_MPDU_RX_ERR_IMR, 3418 imr->mpdu_rx_imr_set); 3419 } 3420 rtw89_sta_sch_imr_enable(struct rtw89_dev * rtwdev)3421 static void rtw89_sta_sch_imr_enable(struct rtw89_dev *rtwdev) 3422 { 3423 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3424 3425 rtw89_write32_clr(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3426 B_AX_SEARCH_HANG_TIMEOUT_INT_EN | 3427 B_AX_RPT_HANG_TIMEOUT_INT_EN | 3428 B_AX_PLE_B_PKTID_ERR_INT_EN); 3429 rtw89_write32_set(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR, 3430 imr->sta_sch_imr_set); 3431 } 3432 rtw89_txpktctl_imr_enable(struct rtw89_dev * rtwdev)3433 static void rtw89_txpktctl_imr_enable(struct rtw89_dev *rtwdev) 3434 { 3435 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3436 3437 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b0_reg, 3438 imr->txpktctl_imr_b0_clr); 3439 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b0_reg, 3440 imr->txpktctl_imr_b0_set); 3441 rtw89_write32_clr(rtwdev, imr->txpktctl_imr_b1_reg, 3442 imr->txpktctl_imr_b1_clr); 3443 rtw89_write32_set(rtwdev, imr->txpktctl_imr_b1_reg, 3444 imr->txpktctl_imr_b1_set); 3445 } 3446 rtw89_wde_imr_enable(struct rtw89_dev * rtwdev)3447 static void rtw89_wde_imr_enable(struct rtw89_dev *rtwdev) 3448 { 3449 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3450 3451 rtw89_write32_clr(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_clr); 3452 rtw89_write32_set(rtwdev, R_AX_WDE_ERR_IMR, imr->wde_imr_set); 3453 } 3454 rtw89_ple_imr_enable(struct rtw89_dev * rtwdev)3455 static void rtw89_ple_imr_enable(struct rtw89_dev *rtwdev) 3456 { 3457 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3458 3459 rtw89_write32_clr(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_clr); 3460 rtw89_write32_set(rtwdev, R_AX_PLE_ERR_IMR, imr->ple_imr_set); 3461 } 3462 rtw89_pktin_imr_enable(struct rtw89_dev * rtwdev)3463 static void rtw89_pktin_imr_enable(struct rtw89_dev *rtwdev) 3464 { 3465 rtw89_write32_set(rtwdev, R_AX_PKTIN_ERR_IMR, 3466 B_AX_PKTIN_GETPKTID_ERR_INT_EN); 3467 } 3468 rtw89_dispatcher_imr_enable(struct rtw89_dev * rtwdev)3469 static void rtw89_dispatcher_imr_enable(struct rtw89_dev *rtwdev) 3470 { 3471 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3472 3473 rtw89_write32_clr(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3474 imr->host_disp_imr_clr); 3475 rtw89_write32_set(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR, 3476 imr->host_disp_imr_set); 3477 rtw89_write32_clr(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3478 imr->cpu_disp_imr_clr); 3479 rtw89_write32_set(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR, 3480 imr->cpu_disp_imr_set); 3481 rtw89_write32_clr(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3482 imr->other_disp_imr_clr); 3483 rtw89_write32_set(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR, 3484 imr->other_disp_imr_set); 3485 } 3486 rtw89_cpuio_imr_enable(struct rtw89_dev * rtwdev)3487 static void rtw89_cpuio_imr_enable(struct rtw89_dev *rtwdev) 3488 { 3489 rtw89_write32_clr(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_CLR); 3490 rtw89_write32_set(rtwdev, R_AX_CPUIO_ERR_IMR, B_AX_CPUIO_IMR_SET); 3491 } 3492 rtw89_bbrpt_imr_enable(struct rtw89_dev * rtwdev)3493 static void rtw89_bbrpt_imr_enable(struct rtw89_dev *rtwdev) 3494 { 3495 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3496 3497 rtw89_write32_set(rtwdev, imr->bbrpt_com_err_imr_reg, 3498 B_AX_BBRPT_COM_NULL_PLPKTID_ERR_INT_EN); 3499 rtw89_write32_clr(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3500 B_AX_BBRPT_CHINFO_IMR_CLR); 3501 rtw89_write32_set(rtwdev, imr->bbrpt_chinfo_err_imr_reg, 3502 imr->bbrpt_err_imr_set); 3503 rtw89_write32_set(rtwdev, imr->bbrpt_dfs_err_imr_reg, 3504 B_AX_BBRPT_DFS_TO_ERR_INT_EN); 3505 rtw89_write32_set(rtwdev, R_AX_LA_ERRFLAG, B_AX_LA_IMR_DATA_LOSS_ERR); 3506 } 3507 rtw89_scheduler_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3508 static void rtw89_scheduler_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3509 { 3510 u32 reg; 3511 3512 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_SCHEDULE_ERR_IMR, mac_idx); 3513 rtw89_write32_clr(rtwdev, reg, B_AX_SORT_NON_IDLE_ERR_INT_EN | 3514 B_AX_FSM_TIMEOUT_ERR_INT_EN); 3515 rtw89_write32_set(rtwdev, reg, B_AX_FSM_TIMEOUT_ERR_INT_EN); 3516 } 3517 rtw89_ptcl_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3518 static void rtw89_ptcl_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3519 { 3520 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3521 u32 reg; 3522 3523 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PTCL_IMR0, mac_idx); 3524 rtw89_write32_clr(rtwdev, reg, imr->ptcl_imr_clr); 3525 rtw89_write32_set(rtwdev, reg, imr->ptcl_imr_set); 3526 } 3527 rtw89_cdma_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3528 static void rtw89_cdma_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3529 { 3530 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3531 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3532 u32 reg; 3533 3534 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_0_reg, mac_idx); 3535 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_0_clr); 3536 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_0_set); 3537 3538 if (chip_id == RTL8852C) { 3539 reg = rtw89_mac_reg_by_idx(rtwdev, imr->cdma_imr_1_reg, mac_idx); 3540 rtw89_write32_clr(rtwdev, reg, imr->cdma_imr_1_clr); 3541 rtw89_write32_set(rtwdev, reg, imr->cdma_imr_1_set); 3542 } 3543 } 3544 rtw89_phy_intf_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3545 static void rtw89_phy_intf_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3546 { 3547 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3548 u32 reg; 3549 3550 reg = rtw89_mac_reg_by_idx(rtwdev, imr->phy_intf_imr_reg, mac_idx); 3551 rtw89_write32_clr(rtwdev, reg, imr->phy_intf_imr_clr); 3552 rtw89_write32_set(rtwdev, reg, imr->phy_intf_imr_set); 3553 } 3554 rtw89_rmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3555 static void rtw89_rmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3556 { 3557 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3558 u32 reg; 3559 3560 reg = rtw89_mac_reg_by_idx(rtwdev, imr->rmac_imr_reg, mac_idx); 3561 rtw89_write32_clr(rtwdev, reg, imr->rmac_imr_clr); 3562 rtw89_write32_set(rtwdev, reg, imr->rmac_imr_set); 3563 } 3564 rtw89_tmac_imr_enable(struct rtw89_dev * rtwdev,u8 mac_idx)3565 static void rtw89_tmac_imr_enable(struct rtw89_dev *rtwdev, u8 mac_idx) 3566 { 3567 const struct rtw89_imr_info *imr = rtwdev->chip->imr_info; 3568 u32 reg; 3569 3570 reg = rtw89_mac_reg_by_idx(rtwdev, imr->tmac_imr_reg, mac_idx); 3571 rtw89_write32_clr(rtwdev, reg, imr->tmac_imr_clr); 3572 rtw89_write32_set(rtwdev, reg, imr->tmac_imr_set); 3573 } 3574 enable_imr_ax(struct rtw89_dev * rtwdev,u8 mac_idx,enum rtw89_mac_hwmod_sel sel)3575 static int enable_imr_ax(struct rtw89_dev *rtwdev, u8 mac_idx, 3576 enum rtw89_mac_hwmod_sel sel) 3577 { 3578 int ret; 3579 3580 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, sel); 3581 if (ret) { 3582 rtw89_err(rtwdev, "MAC%d mac_idx%d is not ready\n", 3583 sel, mac_idx); 3584 return ret; 3585 } 3586 3587 if (sel == RTW89_DMAC_SEL) { 3588 rtw89_wdrls_imr_enable(rtwdev); 3589 rtw89_wsec_imr_enable(rtwdev); 3590 rtw89_mpdu_trx_imr_enable(rtwdev); 3591 rtw89_sta_sch_imr_enable(rtwdev); 3592 rtw89_txpktctl_imr_enable(rtwdev); 3593 rtw89_wde_imr_enable(rtwdev); 3594 rtw89_ple_imr_enable(rtwdev); 3595 rtw89_pktin_imr_enable(rtwdev); 3596 rtw89_dispatcher_imr_enable(rtwdev); 3597 rtw89_cpuio_imr_enable(rtwdev); 3598 rtw89_bbrpt_imr_enable(rtwdev); 3599 } else if (sel == RTW89_CMAC_SEL) { 3600 rtw89_scheduler_imr_enable(rtwdev, mac_idx); 3601 rtw89_ptcl_imr_enable(rtwdev, mac_idx); 3602 rtw89_cdma_imr_enable(rtwdev, mac_idx); 3603 rtw89_phy_intf_imr_enable(rtwdev, mac_idx); 3604 rtw89_rmac_imr_enable(rtwdev, mac_idx); 3605 rtw89_tmac_imr_enable(rtwdev, mac_idx); 3606 } else { 3607 return -EINVAL; 3608 } 3609 3610 return 0; 3611 } 3612 err_imr_ctrl_ax(struct rtw89_dev * rtwdev,bool en)3613 static void err_imr_ctrl_ax(struct rtw89_dev *rtwdev, bool en) 3614 { 3615 rtw89_write32(rtwdev, R_AX_DMAC_ERR_IMR, 3616 en ? DMAC_ERR_IMR_EN : DMAC_ERR_IMR_DIS); 3617 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR, 3618 en ? CMAC0_ERR_IMR_EN : CMAC0_ERR_IMR_DIS); 3619 if (!rtw89_is_rtl885xb(rtwdev) && rtwdev->mac.dle_info.c1_rx_qta) 3620 rtw89_write32(rtwdev, R_AX_CMAC_ERR_IMR_C1, 3621 en ? CMAC1_ERR_IMR_EN : CMAC1_ERR_IMR_DIS); 3622 } 3623 dbcc_enable_ax(struct rtw89_dev * rtwdev,bool enable)3624 static int dbcc_enable_ax(struct rtw89_dev *rtwdev, bool enable) 3625 { 3626 int ret = 0; 3627 3628 if (enable) { 3629 ret = band1_enable_ax(rtwdev); 3630 if (ret) { 3631 rtw89_err(rtwdev, "[ERR] band1_enable %d\n", ret); 3632 return ret; 3633 } 3634 3635 ret = enable_imr_ax(rtwdev, RTW89_MAC_1, RTW89_CMAC_SEL); 3636 if (ret) { 3637 rtw89_err(rtwdev, "[ERR] enable CMAC1 IMR %d\n", ret); 3638 return ret; 3639 } 3640 } else { 3641 rtw89_err(rtwdev, "[ERR] disable dbcc is not implemented not\n"); 3642 return -EINVAL; 3643 } 3644 3645 return 0; 3646 } 3647 set_host_rpr_ax(struct rtw89_dev * rtwdev)3648 static int set_host_rpr_ax(struct rtw89_dev *rtwdev) 3649 { 3650 if (rtwdev->hci.type == RTW89_HCI_TYPE_PCIE) { 3651 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3652 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_POH); 3653 rtw89_write32_set(rtwdev, R_AX_RLSRPT0_CFG0, 3654 B_AX_RLSRPT0_FLTR_MAP_MASK); 3655 } else { 3656 rtw89_write32_mask(rtwdev, R_AX_WDRLS_CFG, 3657 B_AX_WDRLS_MODE_MASK, RTW89_RPR_MODE_STF); 3658 rtw89_write32_clr(rtwdev, R_AX_RLSRPT0_CFG0, 3659 B_AX_RLSRPT0_FLTR_MAP_MASK); 3660 } 3661 3662 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_AGGNUM_MASK, 30); 3663 rtw89_write32_mask(rtwdev, R_AX_RLSRPT0_CFG1, B_AX_RLSRPT0_TO_MASK, 255); 3664 3665 return 0; 3666 } 3667 trx_init_ax(struct rtw89_dev * rtwdev)3668 static int trx_init_ax(struct rtw89_dev *rtwdev) 3669 { 3670 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3671 enum rtw89_qta_mode qta_mode = rtwdev->mac.qta_mode; 3672 int ret; 3673 3674 ret = dmac_init_ax(rtwdev, 0); 3675 if (ret) { 3676 rtw89_err(rtwdev, "[ERR]DMAC init %d\n", ret); 3677 return ret; 3678 } 3679 3680 ret = cmac_init_ax(rtwdev, 0); 3681 if (ret) { 3682 rtw89_err(rtwdev, "[ERR]CMAC%d init %d\n", 0, ret); 3683 return ret; 3684 } 3685 3686 if (rtw89_mac_is_qta_dbcc(rtwdev, qta_mode)) { 3687 ret = dbcc_enable_ax(rtwdev, true); 3688 if (ret) { 3689 rtw89_err(rtwdev, "[ERR]dbcc_enable init %d\n", ret); 3690 return ret; 3691 } 3692 } 3693 3694 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_DMAC_SEL); 3695 if (ret) { 3696 rtw89_err(rtwdev, "[ERR] enable DMAC IMR %d\n", ret); 3697 return ret; 3698 } 3699 3700 ret = enable_imr_ax(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 3701 if (ret) { 3702 rtw89_err(rtwdev, "[ERR] to enable CMAC0 IMR %d\n", ret); 3703 return ret; 3704 } 3705 3706 err_imr_ctrl_ax(rtwdev, true); 3707 3708 ret = set_host_rpr_ax(rtwdev); 3709 if (ret) { 3710 rtw89_err(rtwdev, "[ERR] set host rpr %d\n", ret); 3711 return ret; 3712 } 3713 3714 if (chip_id == RTL8852C) 3715 rtw89_write32_clr(rtwdev, R_AX_RSP_CHK_SIG, 3716 B_AX_RSP_STATIC_RTS_CHK_SERV_BW_EN); 3717 3718 return 0; 3719 } 3720 rtw89_mac_feat_init(struct rtw89_dev * rtwdev)3721 static int rtw89_mac_feat_init(struct rtw89_dev *rtwdev) 3722 { 3723 #define BACAM_1024BMP_OCC_ENTRY 4 3724 #define BACAM_MAX_RU_SUPPORT_B0_STA 1 3725 #define BACAM_MAX_RU_SUPPORT_B1_STA 1 3726 const struct rtw89_chip_info *chip = rtwdev->chip; 3727 u8 users, offset; 3728 3729 if (chip->bacam_ver != RTW89_BACAM_V1) 3730 return 0; 3731 3732 offset = 0; 3733 users = BACAM_MAX_RU_SUPPORT_B0_STA; 3734 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_0); 3735 3736 offset += users * BACAM_1024BMP_OCC_ENTRY; 3737 users = BACAM_MAX_RU_SUPPORT_B1_STA; 3738 rtw89_fw_h2c_init_ba_cam_users(rtwdev, users, offset, RTW89_MAC_1); 3739 3740 return 0; 3741 } 3742 rtw89_disable_fw_watchdog(struct rtw89_dev * rtwdev)3743 static void rtw89_disable_fw_watchdog(struct rtw89_dev *rtwdev) 3744 { 3745 u32 val32; 3746 3747 if (rtw89_is_rtl885xb(rtwdev)) { 3748 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3749 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_APB_WRAP_EN); 3750 return; 3751 } 3752 3753 rtw89_mac_mem_write(rtwdev, R_AX_WDT_CTRL, 3754 WDT_CTRL_ALL_DIS, RTW89_MAC_MEM_CPU_LOCAL); 3755 3756 val32 = rtw89_mac_mem_read(rtwdev, R_AX_WDT_STATUS, RTW89_MAC_MEM_CPU_LOCAL); 3757 val32 |= B_AX_FS_WDT_INT; 3758 val32 &= ~B_AX_FS_WDT_INT_MSK; 3759 rtw89_mac_mem_write(rtwdev, R_AX_WDT_STATUS, val32, RTW89_MAC_MEM_CPU_LOCAL); 3760 } 3761 rtw89_mac_disable_cpu_ax(struct rtw89_dev * rtwdev)3762 static void rtw89_mac_disable_cpu_ax(struct rtw89_dev *rtwdev) 3763 { 3764 clear_bit(RTW89_FLAG_FW_RDY, rtwdev->flags); 3765 3766 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3767 rtw89_write32_clr(rtwdev, R_AX_WCPU_FW_CTRL, B_AX_WCPU_FWDL_EN | 3768 B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3769 rtw89_write32_clr(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3770 3771 rtw89_disable_fw_watchdog(rtwdev); 3772 3773 rtw89_write32_clr(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3774 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_PLATFORM_EN); 3775 } 3776 rtw89_mac_enable_cpu_ax(struct rtw89_dev * rtwdev,u8 boot_reason,bool dlfw,bool include_bb)3777 static int rtw89_mac_enable_cpu_ax(struct rtw89_dev *rtwdev, u8 boot_reason, 3778 bool dlfw, bool include_bb) 3779 { 3780 u32 val; 3781 int ret; 3782 3783 if (rtw89_read32(rtwdev, R_AX_PLATFORM_ENABLE) & B_AX_WCPU_EN) 3784 return -EFAULT; 3785 3786 rtw89_write32(rtwdev, R_AX_UDM1, 0); 3787 rtw89_write32(rtwdev, R_AX_UDM2, 0); 3788 rtw89_write32(rtwdev, R_AX_HALT_H2C_CTRL, 0); 3789 rtw89_write32(rtwdev, R_AX_HALT_C2H_CTRL, 0); 3790 rtw89_write32(rtwdev, R_AX_HALT_H2C, 0); 3791 rtw89_write32(rtwdev, R_AX_HALT_C2H, 0); 3792 3793 rtw89_write32_set(rtwdev, R_AX_SYS_CLK_CTRL, B_AX_CPU_CLK_EN); 3794 3795 val = rtw89_read32(rtwdev, R_AX_WCPU_FW_CTRL); 3796 val &= ~(B_AX_WCPU_FWDL_EN | B_AX_H2C_PATH_RDY | B_AX_FWDL_PATH_RDY); 3797 val = u32_replace_bits(val, RTW89_FWDL_INITIAL_STATE, 3798 B_AX_WCPU_FWDL_STS_MASK); 3799 3800 if (dlfw) 3801 val |= B_AX_WCPU_FWDL_EN; 3802 3803 rtw89_write32(rtwdev, R_AX_WCPU_FW_CTRL, val); 3804 3805 if (rtw89_is_rtl885xb(rtwdev)) 3806 rtw89_write32_mask(rtwdev, R_AX_SEC_CTRL, 3807 B_AX_SEC_IDMEM_SIZE_CONFIG_MASK, 0x2); 3808 3809 rtw89_write16_mask(rtwdev, R_AX_BOOT_REASON, B_AX_BOOT_REASON_MASK, 3810 boot_reason); 3811 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_WCPU_EN); 3812 3813 if (!dlfw) { 3814 mdelay(5); 3815 3816 ret = rtw89_fw_check_rdy(rtwdev, RTW89_FWDL_CHECK_FREERTOS_DONE); 3817 if (ret) 3818 return ret; 3819 } 3820 3821 return 0; 3822 } 3823 rtw89_mac_hci_func_en_ax(struct rtw89_dev * rtwdev)3824 static void rtw89_mac_hci_func_en_ax(struct rtw89_dev *rtwdev) 3825 { 3826 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3827 u32 val; 3828 3829 if (chip_id == RTL8852C) 3830 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3831 B_AX_PKT_BUF_EN | B_AX_H_AXIDMA_EN; 3832 else 3833 val = B_AX_MAC_FUNC_EN | B_AX_DMAC_FUNC_EN | B_AX_DISPATCHER_EN | 3834 B_AX_PKT_BUF_EN; 3835 rtw89_write32(rtwdev, R_AX_DMAC_FUNC_EN, val); 3836 } 3837 rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev * rtwdev)3838 static void rtw89_mac_dmac_func_pre_en_ax(struct rtw89_dev *rtwdev) 3839 { 3840 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 3841 u32 val; 3842 3843 if (chip_id == RTL8851B || chip_id == RTL8852BT) 3844 val = B_AX_DISPATCHER_CLK_EN | B_AX_AXIDMA_CLK_EN; 3845 else 3846 val = B_AX_DISPATCHER_CLK_EN; 3847 rtw89_write32(rtwdev, R_AX_DMAC_CLK_EN, val); 3848 3849 if (chip_id != RTL8852C) 3850 return; 3851 3852 val = rtw89_read32(rtwdev, R_AX_HAXI_INIT_CFG1); 3853 val &= ~(B_AX_DMA_MODE_MASK | B_AX_STOP_AXI_MST); 3854 val |= FIELD_PREP(B_AX_DMA_MODE_MASK, DMA_MOD_PCIE_1B) | 3855 B_AX_TXHCI_EN_V1 | B_AX_RXHCI_EN_V1; 3856 rtw89_write32(rtwdev, R_AX_HAXI_INIT_CFG1, val); 3857 3858 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP1, 3859 B_AX_STOP_ACH0 | B_AX_STOP_ACH1 | B_AX_STOP_ACH3 | 3860 B_AX_STOP_ACH4 | B_AX_STOP_ACH5 | B_AX_STOP_ACH6 | 3861 B_AX_STOP_ACH7 | B_AX_STOP_CH8 | B_AX_STOP_CH9 | 3862 B_AX_STOP_CH12 | B_AX_STOP_ACH2); 3863 rtw89_write32_clr(rtwdev, R_AX_HAXI_DMA_STOP2, B_AX_STOP_CH10 | B_AX_STOP_CH11); 3864 rtw89_write32_set(rtwdev, R_AX_PLATFORM_ENABLE, B_AX_AXIDMA_EN); 3865 } 3866 rtw89_mac_dmac_pre_init(struct rtw89_dev * rtwdev)3867 static int rtw89_mac_dmac_pre_init(struct rtw89_dev *rtwdev) 3868 { 3869 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3870 int ret; 3871 3872 mac->hci_func_en(rtwdev); 3873 mac->dmac_func_pre_en(rtwdev); 3874 3875 ret = rtw89_mac_dle_init(rtwdev, RTW89_QTA_DLFW, rtwdev->mac.qta_mode); 3876 if (ret) { 3877 rtw89_err(rtwdev, "[ERR]DLE pre init %d\n", ret); 3878 return ret; 3879 } 3880 3881 ret = rtw89_mac_hfc_init(rtwdev, true, false, true); 3882 if (ret) { 3883 rtw89_err(rtwdev, "[ERR]HCI FC pre init %d\n", ret); 3884 return ret; 3885 } 3886 3887 return ret; 3888 } 3889 rtw89_mac_enable_bb_rf(struct rtw89_dev * rtwdev)3890 int rtw89_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 3891 { 3892 rtw89_write8_set(rtwdev, R_AX_SYS_FUNC_EN, 3893 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3894 rtw89_write32_set(rtwdev, R_AX_WLRF_CTRL, 3895 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3896 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3897 rtw89_write8_set(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3898 3899 return 0; 3900 } 3901 EXPORT_SYMBOL(rtw89_mac_enable_bb_rf); 3902 rtw89_mac_disable_bb_rf(struct rtw89_dev * rtwdev)3903 int rtw89_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 3904 { 3905 rtw89_write8_clr(rtwdev, R_AX_SYS_FUNC_EN, 3906 B_AX_FEN_BBRSTB | B_AX_FEN_BB_GLB_RSTN); 3907 rtw89_write32_clr(rtwdev, R_AX_WLRF_CTRL, 3908 B_AX_WLRF1_CTRL_7 | B_AX_WLRF1_CTRL_1 | 3909 B_AX_WLRF_CTRL_7 | B_AX_WLRF_CTRL_1); 3910 rtw89_write8_clr(rtwdev, R_AX_PHYREG_SET, PHYREG_SET_ALL_CYCLE); 3911 3912 return 0; 3913 } 3914 EXPORT_SYMBOL(rtw89_mac_disable_bb_rf); 3915 rtw89_mac_partial_init(struct rtw89_dev * rtwdev,bool include_bb)3916 int rtw89_mac_partial_init(struct rtw89_dev *rtwdev, bool include_bb) 3917 { 3918 int ret; 3919 3920 ret = rtw89_mac_power_switch(rtwdev, true); 3921 if (ret) { 3922 rtw89_mac_power_switch(rtwdev, false); 3923 ret = rtw89_mac_power_switch(rtwdev, true); 3924 if (ret) 3925 return ret; 3926 } 3927 3928 rtw89_mac_ctrl_hci_dma_trx(rtwdev, true); 3929 3930 if (include_bb) { 3931 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_0); 3932 if (rtwdev->dbcc_en) 3933 rtw89_chip_bb_preinit(rtwdev, RTW89_PHY_1); 3934 } 3935 3936 ret = rtw89_mac_dmac_pre_init(rtwdev); 3937 if (ret) 3938 return ret; 3939 3940 if (rtwdev->hci.ops->mac_pre_init) { 3941 ret = rtwdev->hci.ops->mac_pre_init(rtwdev); 3942 if (ret) 3943 return ret; 3944 } 3945 3946 ret = rtw89_fw_download(rtwdev, RTW89_FW_NORMAL, include_bb); 3947 if (ret) 3948 return ret; 3949 3950 return 0; 3951 } 3952 rtw89_mac_init(struct rtw89_dev * rtwdev)3953 int rtw89_mac_init(struct rtw89_dev *rtwdev) 3954 { 3955 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 3956 const struct rtw89_chip_info *chip = rtwdev->chip; 3957 bool include_bb = !!chip->bbmcu_nr; 3958 int ret; 3959 3960 ret = rtw89_mac_partial_init(rtwdev, include_bb); 3961 if (ret) 3962 goto fail; 3963 3964 ret = rtw89_chip_enable_bb_rf(rtwdev); 3965 if (ret) 3966 goto fail; 3967 3968 ret = mac->sys_init(rtwdev); 3969 if (ret) 3970 goto fail; 3971 3972 ret = mac->trx_init(rtwdev); 3973 if (ret) 3974 goto fail; 3975 3976 ret = rtw89_mac_feat_init(rtwdev); 3977 if (ret) 3978 goto fail; 3979 3980 if (rtwdev->hci.ops->mac_post_init) { 3981 ret = rtwdev->hci.ops->mac_post_init(rtwdev); 3982 if (ret) 3983 goto fail; 3984 } 3985 3986 rtw89_fw_send_all_early_h2c(rtwdev); 3987 rtw89_fw_h2c_set_ofld_cfg(rtwdev); 3988 3989 return ret; 3990 fail: 3991 rtw89_mac_power_switch(rtwdev, false); 3992 3993 return ret; 3994 } 3995 rtw89_mac_dmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)3996 static void rtw89_mac_dmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 3997 { 3998 u8 i; 3999 4000 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 4001 return; 4002 4003 for (i = 0; i < 4; i++) { 4004 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4005 DMAC_TBL_BASE_ADDR + (macid << 4) + (i << 2)); 4006 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0); 4007 } 4008 } 4009 rtw89_mac_cmac_tbl_init(struct rtw89_dev * rtwdev,u8 macid)4010 static void rtw89_mac_cmac_tbl_init(struct rtw89_dev *rtwdev, u8 macid) 4011 { 4012 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 4013 return; 4014 4015 rtw89_write32(rtwdev, R_AX_FILTER_MODEL_ADDR, 4016 CMAC_TBL_BASE_ADDR + macid * CCTL_INFO_SIZE); 4017 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY, 0x4); 4018 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 4, 0x400A0004); 4019 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 8, 0); 4020 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 12, 0); 4021 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 16, 0); 4022 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 20, 0xE43000B); 4023 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 24, 0); 4024 rtw89_write32(rtwdev, R_AX_INDIR_ACCESS_ENTRY + 28, 0xB8109); 4025 } 4026 rtw89_mac_set_macid_pause(struct rtw89_dev * rtwdev,u8 macid,bool pause)4027 int rtw89_mac_set_macid_pause(struct rtw89_dev *rtwdev, u8 macid, bool pause) 4028 { 4029 u8 sh = FIELD_GET(GENMASK(4, 0), macid); 4030 u8 grp = macid >> 5; 4031 int ret; 4032 4033 /* If this is called by change_interface() in the case of P2P, it could 4034 * be power-off, so ignore this operation. 4035 */ 4036 if (test_bit(RTW89_FLAG_CHANGING_INTERFACE, rtwdev->flags) && 4037 !test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 4038 return 0; 4039 4040 ret = rtw89_mac_check_mac_en(rtwdev, RTW89_MAC_0, RTW89_CMAC_SEL); 4041 if (ret) 4042 return ret; 4043 4044 rtw89_fw_h2c_macid_pause(rtwdev, sh, grp, pause); 4045 4046 return 0; 4047 } 4048 4049 static const struct rtw89_port_reg rtw89_port_base_ax = { 4050 .port_cfg = R_AX_PORT_CFG_P0, 4051 .tbtt_prohib = R_AX_TBTT_PROHIB_P0, 4052 .bcn_area = R_AX_BCN_AREA_P0, 4053 .bcn_early = R_AX_BCNERLYINT_CFG_P0, 4054 .tbtt_early = R_AX_TBTTERLYINT_CFG_P0, 4055 .tbtt_agg = R_AX_TBTT_AGG_P0, 4056 .bcn_space = R_AX_BCN_SPACE_CFG_P0, 4057 .bcn_forcetx = R_AX_BCN_FORCETX_P0, 4058 .bcn_err_cnt = R_AX_BCN_ERR_CNT_P0, 4059 .bcn_err_flag = R_AX_BCN_ERR_FLAG_P0, 4060 .dtim_ctrl = R_AX_DTIM_CTRL_P0, 4061 .tbtt_shift = R_AX_TBTT_SHIFT_P0, 4062 .bcn_cnt_tmr = R_AX_BCN_CNT_TMR_P0, 4063 .tsftr_l = R_AX_TSFTR_LOW_P0, 4064 .tsftr_h = R_AX_TSFTR_HIGH_P0, 4065 .md_tsft = R_AX_MD_TSFT_STMP_CTL, 4066 .bss_color = R_AX_PTCL_BSS_COLOR_0, 4067 .mbssid = R_AX_MBSSID_CTRL, 4068 .mbssid_drop = R_AX_MBSSID_DROP_0, 4069 .tsf_sync = R_AX_PORT0_TSF_SYNC, 4070 .ptcl_dbg = R_AX_PTCL_DBG, 4071 .ptcl_dbg_info = R_AX_PTCL_DBG_INFO, 4072 .bcn_drop_all = R_AX_BCN_DROP_ALL0, 4073 .hiq_win = {R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG, 4074 R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2, 4075 R_AX_PORT_HGQ_WINDOW_CFG + 3}, 4076 }; 4077 rtw89_mac_check_packet_ctrl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 type)4078 static void rtw89_mac_check_packet_ctrl(struct rtw89_dev *rtwdev, 4079 struct rtw89_vif *rtwvif, u8 type) 4080 { 4081 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4082 const struct rtw89_port_reg *p = mac->port_base; 4083 u8 mask = B_AX_PTCL_DBG_INFO_MASK_BY_PORT(rtwvif->port); 4084 u32 reg_info, reg_ctrl; 4085 u32 val; 4086 int ret; 4087 4088 reg_info = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg_info, rtwvif->mac_idx); 4089 reg_ctrl = rtw89_mac_reg_by_idx(rtwdev, p->ptcl_dbg, rtwvif->mac_idx); 4090 4091 rtw89_write32_mask(rtwdev, reg_ctrl, B_AX_PTCL_DBG_SEL_MASK, type); 4092 rtw89_write32_set(rtwdev, reg_ctrl, B_AX_PTCL_DBG_EN); 4093 fsleep(100); 4094 4095 ret = read_poll_timeout(rtw89_read32_mask, val, val == 0, 1000, 100000, 4096 true, rtwdev, reg_info, mask); 4097 if (ret) 4098 rtw89_warn(rtwdev, "Polling beacon packet empty fail\n"); 4099 } 4100 rtw89_mac_bcn_drop(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4101 static void rtw89_mac_bcn_drop(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4102 { 4103 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4104 const struct rtw89_port_reg *p = mac->port_base; 4105 4106 rtw89_write32_set(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4107 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK, 1); 4108 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, B_AX_BCN_MSK_AREA_MASK, 0); 4109 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 0); 4110 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 2); 4111 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK, 1); 4112 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 1); 4113 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4114 4115 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM0); 4116 if (rtwvif->port == RTW89_PORT_0) 4117 rtw89_mac_check_packet_ctrl(rtwdev, rtwvif, AX_PTCL_DBG_BCNQ_NUM1); 4118 4119 rtw89_write32_clr(rtwdev, p->bcn_drop_all, BIT(rtwvif->port)); 4120 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TBTT_PROHIB_EN); 4121 fsleep(2000); 4122 } 4123 4124 #define BCN_INTERVAL 100 4125 #define BCN_ERLY_DEF 160 4126 #define BCN_SETUP_DEF 2 4127 #define BCN_HOLD_DEF 200 4128 #define BCN_MASK_DEF 0 4129 #define TBTT_ERLY_DEF 5 4130 #define BCN_SET_UNIT 32 4131 #define BCN_ERLY_SET_DLY (10 * 2) 4132 rtw89_mac_port_cfg_func_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4133 static void rtw89_mac_port_cfg_func_sw(struct rtw89_dev *rtwdev, 4134 struct rtw89_vif *rtwvif) 4135 { 4136 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4137 const struct rtw89_port_reg *p = mac->port_base; 4138 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4139 const struct rtw89_chip_info *chip = rtwdev->chip; 4140 bool need_backup = false; 4141 u32 backup_val; 4142 4143 if (!rtw89_read32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN)) 4144 return; 4145 4146 if (chip->chip_id == RTL8852A && rtwvif->port != RTW89_PORT_0) { 4147 need_backup = true; 4148 backup_val = rtw89_read32_port(rtwdev, rtwvif, p->tbtt_prohib); 4149 } 4150 4151 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4152 rtw89_mac_bcn_drop(rtwdev, rtwvif); 4153 4154 if (chip->chip_id == RTL8852A) { 4155 rtw89_write32_port_clr(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_SETUP_MASK); 4156 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, B_AX_TBTT_HOLD_MASK, 1); 4157 rtw89_write16_port_clr(rtwdev, rtwvif, p->tbtt_early, B_AX_TBTTERLY_MASK); 4158 rtw89_write16_port_clr(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK); 4159 } 4160 4161 msleep(vif->bss_conf.beacon_int + 1); 4162 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_PORT_FUNC_EN | 4163 B_AX_BRK_SETUP); 4164 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSFTR_RST); 4165 rtw89_write32_port(rtwdev, rtwvif, p->bcn_cnt_tmr, 0); 4166 4167 if (need_backup) 4168 rtw89_write32_port(rtwdev, rtwvif, p->tbtt_prohib, backup_val); 4169 } 4170 rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4171 static void rtw89_mac_port_cfg_tx_rpt(struct rtw89_dev *rtwdev, 4172 struct rtw89_vif *rtwvif, bool en) 4173 { 4174 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4175 const struct rtw89_port_reg *p = mac->port_base; 4176 4177 if (en) 4178 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4179 else 4180 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TXBCN_RPT_EN); 4181 } 4182 rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4183 static void rtw89_mac_port_cfg_rx_rpt(struct rtw89_dev *rtwdev, 4184 struct rtw89_vif *rtwvif, bool en) 4185 { 4186 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4187 const struct rtw89_port_reg *p = mac->port_base; 4188 4189 if (en) 4190 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4191 else 4192 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_RXBCN_RPT_EN); 4193 } 4194 rtw89_mac_port_cfg_net_type(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4195 static void rtw89_mac_port_cfg_net_type(struct rtw89_dev *rtwdev, 4196 struct rtw89_vif *rtwvif) 4197 { 4198 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4199 const struct rtw89_port_reg *p = mac->port_base; 4200 4201 rtw89_write32_port_mask(rtwdev, rtwvif, p->port_cfg, B_AX_NET_TYPE_MASK, 4202 rtwvif->net_type); 4203 } 4204 rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4205 static void rtw89_mac_port_cfg_bcn_prct(struct rtw89_dev *rtwdev, 4206 struct rtw89_vif *rtwvif) 4207 { 4208 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4209 const struct rtw89_port_reg *p = mac->port_base; 4210 bool en = rtwvif->net_type != RTW89_NET_TYPE_NO_LINK; 4211 u32 bits = B_AX_TBTT_PROHIB_EN | B_AX_BRK_SETUP; 4212 4213 if (en) 4214 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bits); 4215 else 4216 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bits); 4217 } 4218 rtw89_mac_port_cfg_rx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4219 static void rtw89_mac_port_cfg_rx_sw(struct rtw89_dev *rtwdev, 4220 struct rtw89_vif *rtwvif) 4221 { 4222 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4223 const struct rtw89_port_reg *p = mac->port_base; 4224 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4225 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4226 u32 bit = B_AX_RX_BSSID_FIT_EN; 4227 4228 if (en) 4229 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, bit); 4230 else 4231 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, bit); 4232 } 4233 rtw89_mac_port_cfg_rx_sync(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4234 void rtw89_mac_port_cfg_rx_sync(struct rtw89_dev *rtwdev, 4235 struct rtw89_vif *rtwvif, bool en) 4236 { 4237 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4238 const struct rtw89_port_reg *p = mac->port_base; 4239 4240 if (en) 4241 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4242 else 4243 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_TSF_UDT_EN); 4244 } 4245 rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4246 static void rtw89_mac_port_cfg_rx_sync_by_nettype(struct rtw89_dev *rtwdev, 4247 struct rtw89_vif *rtwvif) 4248 { 4249 bool en = rtwvif->net_type == RTW89_NET_TYPE_INFRA || 4250 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4251 4252 rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif, en); 4253 } 4254 rtw89_mac_port_cfg_tx_sw(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)4255 static void rtw89_mac_port_cfg_tx_sw(struct rtw89_dev *rtwdev, 4256 struct rtw89_vif *rtwvif, bool en) 4257 { 4258 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4259 const struct rtw89_port_reg *p = mac->port_base; 4260 4261 if (en) 4262 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4263 else 4264 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, B_AX_BCNTX_EN); 4265 } 4266 rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4267 static void rtw89_mac_port_cfg_tx_sw_by_nettype(struct rtw89_dev *rtwdev, 4268 struct rtw89_vif *rtwvif) 4269 { 4270 bool en = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE || 4271 rtwvif->net_type == RTW89_NET_TYPE_AD_HOC; 4272 4273 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4274 } 4275 rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev * rtwdev,bool en)4276 void rtw89_mac_enable_beacon_for_ap_vifs(struct rtw89_dev *rtwdev, bool en) 4277 { 4278 struct rtw89_vif *rtwvif; 4279 4280 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4281 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4282 rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif, en); 4283 } 4284 rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4285 static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev, 4286 struct rtw89_vif *rtwvif) 4287 { 4288 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4289 const struct rtw89_port_reg *p = mac->port_base; 4290 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4291 u16 bcn_int = vif->bss_conf.beacon_int ? vif->bss_conf.beacon_int : BCN_INTERVAL; 4292 4293 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_space, B_AX_BCN_SPACE_MASK, 4294 bcn_int); 4295 } 4296 rtw89_mac_port_cfg_hiq_win(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4297 static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev, 4298 struct rtw89_vif *rtwvif) 4299 { 4300 u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0; 4301 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4302 const struct rtw89_port_reg *p = mac->port_base; 4303 u8 port = rtwvif->port; 4304 u32 reg; 4305 4306 reg = rtw89_mac_reg_by_idx(rtwdev, p->hiq_win[port], rtwvif->mac_idx); 4307 rtw89_write8(rtwdev, reg, win); 4308 } 4309 rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4310 static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev, 4311 struct rtw89_vif *rtwvif) 4312 { 4313 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4314 const struct rtw89_port_reg *p = mac->port_base; 4315 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4316 u32 addr; 4317 4318 addr = rtw89_mac_reg_by_idx(rtwdev, p->md_tsft, rtwvif->mac_idx); 4319 rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE); 4320 4321 rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK, 4322 vif->bss_conf.dtim_period); 4323 } 4324 rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4325 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev, 4326 struct rtw89_vif *rtwvif) 4327 { 4328 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4329 const struct rtw89_port_reg *p = mac->port_base; 4330 4331 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4332 B_AX_TBTT_SETUP_MASK, BCN_SETUP_DEF); 4333 } 4334 rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4335 static void rtw89_mac_port_cfg_bcn_hold_time(struct rtw89_dev *rtwdev, 4336 struct rtw89_vif *rtwvif) 4337 { 4338 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4339 const struct rtw89_port_reg *p = mac->port_base; 4340 4341 rtw89_write32_port_mask(rtwdev, rtwvif, p->tbtt_prohib, 4342 B_AX_TBTT_HOLD_MASK, BCN_HOLD_DEF); 4343 } 4344 rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4345 static void rtw89_mac_port_cfg_bcn_mask_area(struct rtw89_dev *rtwdev, 4346 struct rtw89_vif *rtwvif) 4347 { 4348 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4349 const struct rtw89_port_reg *p = mac->port_base; 4350 4351 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_area, 4352 B_AX_BCN_MSK_AREA_MASK, BCN_MASK_DEF); 4353 } 4354 rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4355 static void rtw89_mac_port_cfg_tbtt_early(struct rtw89_dev *rtwdev, 4356 struct rtw89_vif *rtwvif) 4357 { 4358 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4359 const struct rtw89_port_reg *p = mac->port_base; 4360 4361 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_early, 4362 B_AX_TBTTERLY_MASK, TBTT_ERLY_DEF); 4363 } 4364 rtw89_mac_port_cfg_bss_color(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4365 static void rtw89_mac_port_cfg_bss_color(struct rtw89_dev *rtwdev, 4366 struct rtw89_vif *rtwvif) 4367 { 4368 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4369 const struct rtw89_port_reg *p = mac->port_base; 4370 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif); 4371 static const u32 masks[RTW89_PORT_NUM] = { 4372 B_AX_BSS_COLOB_AX_PORT_0_MASK, B_AX_BSS_COLOB_AX_PORT_1_MASK, 4373 B_AX_BSS_COLOB_AX_PORT_2_MASK, B_AX_BSS_COLOB_AX_PORT_3_MASK, 4374 B_AX_BSS_COLOB_AX_PORT_4_MASK, 4375 }; 4376 u8 port = rtwvif->port; 4377 u32 reg_base; 4378 u32 reg; 4379 u8 bss_color; 4380 4381 bss_color = vif->bss_conf.he_bss_color.color; 4382 reg_base = port >= 4 ? p->bss_color + 4 : p->bss_color; 4383 reg = rtw89_mac_reg_by_idx(rtwdev, reg_base, rtwvif->mac_idx); 4384 rtw89_write32_mask(rtwdev, reg, masks[port], bss_color); 4385 } 4386 rtw89_mac_port_cfg_mbssid(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4387 static void rtw89_mac_port_cfg_mbssid(struct rtw89_dev *rtwdev, 4388 struct rtw89_vif *rtwvif) 4389 { 4390 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4391 const struct rtw89_port_reg *p = mac->port_base; 4392 u8 port = rtwvif->port; 4393 u32 reg; 4394 4395 if (rtwvif->net_type == RTW89_NET_TYPE_AP_MODE) 4396 return; 4397 4398 if (port == 0) { 4399 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid, rtwvif->mac_idx); 4400 rtw89_write32_clr(rtwdev, reg, B_AX_P0MB_ALL_MASK); 4401 } 4402 } 4403 rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4404 static void rtw89_mac_port_cfg_hiq_drop(struct rtw89_dev *rtwdev, 4405 struct rtw89_vif *rtwvif) 4406 { 4407 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4408 const struct rtw89_port_reg *p = mac->port_base; 4409 u8 port = rtwvif->port; 4410 u32 reg; 4411 u32 val; 4412 4413 reg = rtw89_mac_reg_by_idx(rtwdev, p->mbssid_drop, rtwvif->mac_idx); 4414 val = rtw89_read32(rtwdev, reg); 4415 val &= ~FIELD_PREP(B_AX_PORT_DROP_4_0_MASK, BIT(port)); 4416 if (port == 0) 4417 val &= ~BIT(0); 4418 rtw89_write32(rtwdev, reg, val); 4419 } 4420 rtw89_mac_port_cfg_func_en(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool enable)4421 static void rtw89_mac_port_cfg_func_en(struct rtw89_dev *rtwdev, 4422 struct rtw89_vif *rtwvif, bool enable) 4423 { 4424 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4425 const struct rtw89_port_reg *p = mac->port_base; 4426 4427 if (enable) 4428 rtw89_write32_port_set(rtwdev, rtwvif, p->port_cfg, 4429 B_AX_PORT_FUNC_EN); 4430 else 4431 rtw89_write32_port_clr(rtwdev, rtwvif, p->port_cfg, 4432 B_AX_PORT_FUNC_EN); 4433 } 4434 rtw89_mac_port_cfg_bcn_early(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4435 static void rtw89_mac_port_cfg_bcn_early(struct rtw89_dev *rtwdev, 4436 struct rtw89_vif *rtwvif) 4437 { 4438 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4439 const struct rtw89_port_reg *p = mac->port_base; 4440 4441 rtw89_write32_port_mask(rtwdev, rtwvif, p->bcn_early, B_AX_BCNERLY_MASK, 4442 BCN_ERLY_DEF); 4443 } 4444 rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4445 static void rtw89_mac_port_cfg_tbtt_shift(struct rtw89_dev *rtwdev, 4446 struct rtw89_vif *rtwvif) 4447 { 4448 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4449 const struct rtw89_port_reg *p = mac->port_base; 4450 u16 val; 4451 4452 if (rtwdev->chip->chip_id != RTL8852C) 4453 return; 4454 4455 if (rtwvif->wifi_role != RTW89_WIFI_ROLE_P2P_CLIENT && 4456 rtwvif->wifi_role != RTW89_WIFI_ROLE_STATION) 4457 return; 4458 4459 val = FIELD_PREP(B_AX_TBTT_SHIFT_OFST_MAG, 1) | 4460 B_AX_TBTT_SHIFT_OFST_SIGN; 4461 4462 rtw89_write16_port_mask(rtwdev, rtwvif, p->tbtt_shift, 4463 B_AX_TBTT_SHIFT_OFST_MASK, val); 4464 } 4465 rtw89_mac_port_tsf_sync(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_vif * rtwvif_src,u16 offset_tu)4466 void rtw89_mac_port_tsf_sync(struct rtw89_dev *rtwdev, 4467 struct rtw89_vif *rtwvif, 4468 struct rtw89_vif *rtwvif_src, 4469 u16 offset_tu) 4470 { 4471 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4472 const struct rtw89_port_reg *p = mac->port_base; 4473 u32 val, reg; 4474 4475 val = RTW89_PORT_OFFSET_TU_TO_32US(offset_tu); 4476 reg = rtw89_mac_reg_by_idx(rtwdev, p->tsf_sync + rtwvif->port * 4, 4477 rtwvif->mac_idx); 4478 4479 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_SRC, rtwvif_src->port); 4480 rtw89_write32_mask(rtwdev, reg, B_AX_SYNC_PORT_OFFSET_VAL, val); 4481 rtw89_write32_set(rtwdev, reg, B_AX_SYNC_NOW); 4482 } 4483 rtw89_mac_port_tsf_sync_rand(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_vif * rtwvif_src,u8 offset,int * n_offset)4484 static void rtw89_mac_port_tsf_sync_rand(struct rtw89_dev *rtwdev, 4485 struct rtw89_vif *rtwvif, 4486 struct rtw89_vif *rtwvif_src, 4487 u8 offset, int *n_offset) 4488 { 4489 if (rtwvif->net_type != RTW89_NET_TYPE_AP_MODE || rtwvif == rtwvif_src) 4490 return; 4491 4492 /* adjust offset randomly to avoid beacon conflict */ 4493 offset = offset - offset / 4 + get_random_u32() % (offset / 2); 4494 rtw89_mac_port_tsf_sync(rtwdev, rtwvif, rtwvif_src, 4495 (*n_offset) * offset); 4496 4497 (*n_offset)++; 4498 } 4499 rtw89_mac_port_tsf_resync_all(struct rtw89_dev * rtwdev)4500 static void rtw89_mac_port_tsf_resync_all(struct rtw89_dev *rtwdev) 4501 { 4502 struct rtw89_vif *src = NULL, *tmp; 4503 u8 offset = 100, vif_aps = 0; 4504 int n_offset = 1; 4505 4506 rtw89_for_each_rtwvif(rtwdev, tmp) { 4507 if (!src || tmp->net_type == RTW89_NET_TYPE_INFRA) 4508 src = tmp; 4509 if (tmp->net_type == RTW89_NET_TYPE_AP_MODE) 4510 vif_aps++; 4511 } 4512 4513 if (vif_aps == 0) 4514 return; 4515 4516 offset /= (vif_aps + 1); 4517 4518 rtw89_for_each_rtwvif(rtwdev, tmp) 4519 rtw89_mac_port_tsf_sync_rand(rtwdev, tmp, src, offset, &n_offset); 4520 } 4521 rtw89_mac_vif_init(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4522 int rtw89_mac_vif_init(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4523 { 4524 int ret; 4525 4526 ret = rtw89_mac_port_update(rtwdev, rtwvif); 4527 if (ret) 4528 return ret; 4529 4530 rtw89_mac_dmac_tbl_init(rtwdev, rtwvif->mac_id); 4531 rtw89_mac_cmac_tbl_init(rtwdev, rtwvif->mac_id); 4532 4533 ret = rtw89_mac_set_macid_pause(rtwdev, rtwvif->mac_id, false); 4534 if (ret) 4535 return ret; 4536 4537 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_CREATE); 4538 if (ret) 4539 return ret; 4540 4541 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif, NULL, true); 4542 if (ret) 4543 return ret; 4544 4545 ret = rtw89_cam_init(rtwdev, rtwvif); 4546 if (ret) 4547 return ret; 4548 4549 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4550 if (ret) 4551 return ret; 4552 4553 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif, NULL); 4554 if (ret) 4555 return ret; 4556 4557 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif, NULL); 4558 if (ret) 4559 return ret; 4560 4561 return 0; 4562 } 4563 rtw89_mac_vif_deinit(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4564 int rtw89_mac_vif_deinit(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4565 { 4566 int ret; 4567 4568 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif, NULL, RTW89_ROLE_REMOVE); 4569 if (ret) 4570 return ret; 4571 4572 rtw89_cam_deinit(rtwdev, rtwvif); 4573 4574 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif, NULL, NULL); 4575 if (ret) 4576 return ret; 4577 4578 return 0; 4579 } 4580 rtw89_mac_port_update(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4581 int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4582 { 4583 u8 port = rtwvif->port; 4584 4585 if (port >= RTW89_PORT_NUM) 4586 return -EINVAL; 4587 4588 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4589 rtw89_mac_port_cfg_tx_rpt(rtwdev, rtwvif, false); 4590 rtw89_mac_port_cfg_rx_rpt(rtwdev, rtwvif, false); 4591 rtw89_mac_port_cfg_net_type(rtwdev, rtwvif); 4592 rtw89_mac_port_cfg_bcn_prct(rtwdev, rtwvif); 4593 rtw89_mac_port_cfg_rx_sw(rtwdev, rtwvif); 4594 rtw89_mac_port_cfg_rx_sync_by_nettype(rtwdev, rtwvif); 4595 rtw89_mac_port_cfg_tx_sw_by_nettype(rtwdev, rtwvif); 4596 rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif); 4597 rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif); 4598 rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif); 4599 rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif); 4600 rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif); 4601 rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif); 4602 rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif); 4603 rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif); 4604 rtw89_mac_port_cfg_tbtt_shift(rtwdev, rtwvif); 4605 rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif); 4606 rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif); 4607 rtw89_mac_port_cfg_func_en(rtwdev, rtwvif, true); 4608 rtw89_mac_port_tsf_resync_all(rtwdev); 4609 fsleep(BCN_ERLY_SET_DLY); 4610 rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif); 4611 4612 return 0; 4613 } 4614 rtw89_mac_port_get_tsf(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u64 * tsf)4615 int rtw89_mac_port_get_tsf(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4616 u64 *tsf) 4617 { 4618 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4619 const struct rtw89_port_reg *p = mac->port_base; 4620 u32 tsf_low, tsf_high; 4621 int ret; 4622 4623 ret = rtw89_mac_check_mac_en(rtwdev, rtwvif->mac_idx, RTW89_CMAC_SEL); 4624 if (ret) 4625 return ret; 4626 4627 tsf_low = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_l); 4628 tsf_high = rtw89_read32_port(rtwdev, rtwvif, p->tsftr_h); 4629 *tsf = (u64)tsf_high << 32 | tsf_low; 4630 4631 return 0; 4632 } 4633 rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy * wiphy,struct cfg80211_bss * bss,void * data)4634 static void rtw89_mac_check_he_obss_narrow_bw_ru_iter(struct wiphy *wiphy, 4635 struct cfg80211_bss *bss, 4636 void *data) 4637 { 4638 const struct cfg80211_bss_ies *ies; 4639 const struct element *elem; 4640 bool *tolerated = data; 4641 4642 rcu_read_lock(); 4643 ies = rcu_dereference(bss->ies); 4644 elem = cfg80211_find_elem(WLAN_EID_EXT_CAPABILITY, ies->data, 4645 ies->len); 4646 4647 if (!elem || elem->datalen < 10 || 4648 !(elem->data[10] & WLAN_EXT_CAPA10_OBSS_NARROW_BW_RU_TOLERANCE_SUPPORT)) 4649 *tolerated = false; 4650 rcu_read_unlock(); 4651 } 4652 rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif)4653 void rtw89_mac_set_he_obss_narrow_bw_ru(struct rtw89_dev *rtwdev, 4654 struct ieee80211_vif *vif) 4655 { 4656 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 4657 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 4658 struct ieee80211_hw *hw = rtwdev->hw; 4659 bool tolerated = true; 4660 u32 reg; 4661 4662 if (!vif->bss_conf.he_support || vif->type != NL80211_IFTYPE_STATION) 4663 return; 4664 4665 if (!(vif->bss_conf.chanreq.oper.chan->flags & IEEE80211_CHAN_RADAR)) 4666 return; 4667 4668 cfg80211_bss_iter(hw->wiphy, &vif->bss_conf.chanreq.oper, 4669 rtw89_mac_check_he_obss_narrow_bw_ru_iter, 4670 &tolerated); 4671 4672 reg = rtw89_mac_reg_by_idx(rtwdev, mac->narrow_bw_ru_dis.addr, 4673 rtwvif->mac_idx); 4674 if (tolerated) 4675 rtw89_write32_clr(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4676 else 4677 rtw89_write32_set(rtwdev, reg, mac->narrow_bw_ru_dis.mask); 4678 } 4679 rtw89_mac_stop_ap(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4680 void rtw89_mac_stop_ap(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4681 { 4682 rtw89_mac_port_cfg_func_sw(rtwdev, rtwvif); 4683 } 4684 rtw89_mac_add_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4685 int rtw89_mac_add_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4686 { 4687 int ret; 4688 4689 rtwvif->mac_id = rtw89_acquire_mac_id(rtwdev); 4690 if (rtwvif->mac_id == RTW89_MAX_MAC_ID_NUM) 4691 return -ENOSPC; 4692 4693 ret = rtw89_mac_vif_init(rtwdev, rtwvif); 4694 if (ret) 4695 goto release_mac_id; 4696 4697 return 0; 4698 4699 release_mac_id: 4700 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4701 4702 return ret; 4703 } 4704 rtw89_mac_remove_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4705 int rtw89_mac_remove_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 4706 { 4707 int ret; 4708 4709 ret = rtw89_mac_vif_deinit(rtwdev, rtwvif); 4710 rtw89_release_mac_id(rtwdev, rtwvif->mac_id); 4711 4712 return ret; 4713 } 4714 4715 static void rtw89_mac_c2h_macid_pause(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4716 rtw89_mac_c2h_macid_pause(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4717 { 4718 } 4719 rtw89_is_op_chan(struct rtw89_dev * rtwdev,u8 band,u8 channel)4720 static bool rtw89_is_op_chan(struct rtw89_dev *rtwdev, u8 band, u8 channel) 4721 { 4722 const struct rtw89_chan *op = &rtwdev->scan_info.op_chan; 4723 4724 return band == op->band_type && channel == op->primary_channel; 4725 } 4726 4727 static void rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len)4728 rtw89_mac_c2h_scanofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb, 4729 u32 len) 4730 { 4731 const struct rtw89_c2h_scanofld *c2h = 4732 (const struct rtw89_c2h_scanofld *)skb->data; 4733 struct ieee80211_vif *vif = rtwdev->scan_info.scanning_vif; 4734 struct rtw89_vif *rtwvif = vif_to_rtwvif_safe(vif); 4735 struct rtw89_chan new; 4736 u8 reason, status, tx_fail, band, actual_period, expect_period; 4737 u32 last_chan = rtwdev->scan_info.last_chan_idx, report_tsf; 4738 u8 mac_idx, sw_def, fw_def; 4739 u16 chan; 4740 int ret; 4741 4742 if (!rtwvif) 4743 return; 4744 4745 tx_fail = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_TX_FAIL); 4746 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 4747 chan = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PRI_CH); 4748 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 4749 band = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_BAND); 4750 actual_period = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_PERIOD); 4751 mac_idx = le32_get_bits(c2h->w5, RTW89_C2H_SCANOFLD_W5_MAC_IDX); 4752 4753 4754 if (!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ))) 4755 band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G; 4756 4757 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4758 "mac_idx[%d] band: %d, chan: %d, reason: %d, status: %d, tx_fail: %d, actual: %d\n", 4759 mac_idx, band, chan, reason, status, tx_fail, actual_period); 4760 4761 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) { 4762 sw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_SW_DEF); 4763 expect_period = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_EXPECT_PERIOD); 4764 fw_def = le32_get_bits(c2h->w6, RTW89_C2H_SCANOFLD_W6_FW_DEF); 4765 report_tsf = le32_get_bits(c2h->w7, RTW89_C2H_SCANOFLD_W7_REPORT_TSF); 4766 4767 rtw89_debug(rtwdev, RTW89_DBG_HW_SCAN, 4768 "sw_def: %d, fw_def: %d, tsf: %x, expect: %d\n", 4769 sw_def, fw_def, report_tsf, expect_period); 4770 } 4771 4772 switch (reason) { 4773 case RTW89_SCAN_LEAVE_OP_NOTIFY: 4774 case RTW89_SCAN_LEAVE_CH_NOTIFY: 4775 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4776 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, false); 4777 ieee80211_stop_queues(rtwdev->hw); 4778 } 4779 return; 4780 case RTW89_SCAN_END_SCAN_NOTIFY: 4781 if (rtwdev->scan_info.abort) 4782 return; 4783 4784 if (rtwvif && rtwvif->scan_req && 4785 last_chan < rtwvif->scan_req->n_channels) { 4786 ret = rtw89_hw_scan_offload(rtwdev, vif, true); 4787 if (ret) { 4788 rtw89_hw_scan_abort(rtwdev, vif); 4789 rtw89_warn(rtwdev, "HW scan failed: %d\n", ret); 4790 } 4791 } else { 4792 rtw89_hw_scan_complete(rtwdev, vif, false); 4793 } 4794 break; 4795 case RTW89_SCAN_ENTER_OP_NOTIFY: 4796 case RTW89_SCAN_ENTER_CH_NOTIFY: 4797 if (rtw89_is_op_chan(rtwdev, band, chan)) { 4798 rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4799 &rtwdev->scan_info.op_chan); 4800 rtw89_mac_enable_beacon_for_ap_vifs(rtwdev, true); 4801 ieee80211_wake_queues(rtwdev->hw); 4802 } else { 4803 rtw89_chan_create(&new, chan, chan, band, 4804 RTW89_CHANNEL_WIDTH_20); 4805 rtw89_assign_entity_chan(rtwdev, rtwvif->chanctx_idx, 4806 &new); 4807 } 4808 break; 4809 default: 4810 return; 4811 } 4812 } 4813 4814 static void rtw89_mac_bcn_fltr_rpt(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct sk_buff * skb)4815 rtw89_mac_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif, 4816 struct sk_buff *skb) 4817 { 4818 struct ieee80211_vif *vif = rtwvif_to_vif_safe(rtwvif); 4819 enum nl80211_cqm_rssi_threshold_event nl_event; 4820 const struct rtw89_c2h_mac_bcnfltr_rpt *c2h = 4821 (const struct rtw89_c2h_mac_bcnfltr_rpt *)skb->data; 4822 u8 type, event, mac_id; 4823 s8 sig; 4824 4825 type = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_TYPE); 4826 sig = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MA) - MAX_RSSI; 4827 event = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_EVENT); 4828 mac_id = le32_get_bits(c2h->w2, RTW89_C2H_MAC_BCNFLTR_RPT_W2_MACID); 4829 4830 if (mac_id != rtwvif->mac_id) 4831 return; 4832 4833 rtw89_debug(rtwdev, RTW89_DBG_FW, 4834 "C2H bcnfltr rpt macid: %d, type: %d, ma: %d, event: %d\n", 4835 mac_id, type, sig, event); 4836 4837 switch (type) { 4838 case RTW89_BCN_FLTR_BEACON_LOSS: 4839 if (!rtwdev->scanning && !rtwvif->offchan) 4840 ieee80211_connection_loss(vif); 4841 else 4842 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, vif, true); 4843 return; 4844 case RTW89_BCN_FLTR_NOTIFY: 4845 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4846 break; 4847 case RTW89_BCN_FLTR_RSSI: 4848 if (event == RTW89_BCN_FLTR_RSSI_LOW) 4849 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_LOW; 4850 else if (event == RTW89_BCN_FLTR_RSSI_HIGH) 4851 nl_event = NL80211_CQM_RSSI_THRESHOLD_EVENT_HIGH; 4852 else 4853 return; 4854 break; 4855 default: 4856 return; 4857 } 4858 4859 ieee80211_cqm_rssi_notify(vif, nl_event, sig, GFP_KERNEL); 4860 } 4861 4862 static void rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4863 rtw89_mac_c2h_bcn_fltr_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4864 u32 len) 4865 { 4866 struct rtw89_vif *rtwvif; 4867 4868 rtw89_for_each_rtwvif(rtwdev, rtwvif) 4869 rtw89_mac_bcn_fltr_rpt(rtwdev, rtwvif, c2h); 4870 } 4871 4872 static void rtw89_mac_c2h_rec_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4873 rtw89_mac_c2h_rec_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4874 { 4875 /* N.B. This will run in interrupt context. */ 4876 4877 rtw89_debug(rtwdev, RTW89_DBG_FW, 4878 "C2H rev ack recv, cat: %d, class: %d, func: %d, seq : %d\n", 4879 RTW89_GET_MAC_C2H_REV_ACK_CAT(c2h->data), 4880 RTW89_GET_MAC_C2H_REV_ACK_CLASS(c2h->data), 4881 RTW89_GET_MAC_C2H_REV_ACK_FUNC(c2h->data), 4882 RTW89_GET_MAC_C2H_REV_ACK_H2C_SEQ(c2h->data)); 4883 } 4884 4885 static void rtw89_mac_c2h_done_ack(struct rtw89_dev * rtwdev,struct sk_buff * skb_c2h,u32 len)4886 rtw89_mac_c2h_done_ack(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, u32 len) 4887 { 4888 /* N.B. This will run in interrupt context. */ 4889 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 4890 struct rtw89_wait_info *ps_wait = &rtwdev->mac.ps_wait; 4891 const struct rtw89_c2h_done_ack *c2h = 4892 (const struct rtw89_c2h_done_ack *)skb_c2h->data; 4893 u8 h2c_cat = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CAT); 4894 u8 h2c_class = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_CLASS); 4895 u8 h2c_func = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_FUNC); 4896 u8 h2c_return = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_RETURN); 4897 u8 h2c_seq = le32_get_bits(c2h->w2, RTW89_C2H_DONE_ACK_W2_H2C_SEQ); 4898 struct rtw89_completion_data data = {}; 4899 unsigned int cond; 4900 4901 rtw89_debug(rtwdev, RTW89_DBG_FW, 4902 "C2H done ack recv, cat: %d, class: %d, func: %d, ret: %d, seq : %d\n", 4903 h2c_cat, h2c_class, h2c_func, h2c_return, h2c_seq); 4904 4905 if (h2c_cat != H2C_CAT_MAC) 4906 return; 4907 4908 switch (h2c_class) { 4909 default: 4910 return; 4911 case H2C_CL_MAC_PS: 4912 switch (h2c_func) { 4913 default: 4914 return; 4915 case H2C_FUNC_IPS_CFG: 4916 cond = RTW89_PS_WAIT_COND_IPS_CFG; 4917 break; 4918 } 4919 4920 data.err = !!h2c_return; 4921 rtw89_complete_cond(ps_wait, cond, &data); 4922 return; 4923 case H2C_CL_MAC_FW_OFLD: 4924 switch (h2c_func) { 4925 default: 4926 return; 4927 case H2C_FUNC_ADD_SCANOFLD_CH: 4928 cond = RTW89_SCANOFLD_WAIT_COND_ADD_CH; 4929 break; 4930 case H2C_FUNC_SCANOFLD: 4931 cond = RTW89_SCANOFLD_WAIT_COND_START; 4932 break; 4933 case H2C_FUNC_SCANOFLD_BE: 4934 cond = RTW89_SCANOFLD_BE_WAIT_COND_START; 4935 break; 4936 } 4937 4938 data.err = !!h2c_return; 4939 rtw89_complete_cond(fw_ofld_wait, cond, &data); 4940 return; 4941 } 4942 } 4943 4944 static void rtw89_mac_c2h_log(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4945 rtw89_mac_c2h_log(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4946 { 4947 rtw89_fw_log_dump(rtwdev, c2h->data, len); 4948 } 4949 4950 static void rtw89_mac_c2h_bcn_cnt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4951 rtw89_mac_c2h_bcn_cnt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4952 { 4953 } 4954 4955 static void rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev * rtwdev,struct sk_buff * skb_c2h,u32 len)4956 rtw89_mac_c2h_pkt_ofld_rsp(struct rtw89_dev *rtwdev, struct sk_buff *skb_c2h, 4957 u32 len) 4958 { 4959 struct rtw89_wait_info *wait = &rtwdev->mac.fw_ofld_wait; 4960 const struct rtw89_c2h_pkt_ofld_rsp *c2h = 4961 (const struct rtw89_c2h_pkt_ofld_rsp *)skb_c2h->data; 4962 u16 pkt_len = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_LEN); 4963 u8 pkt_id = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_ID); 4964 u8 pkt_op = le32_get_bits(c2h->w2, RTW89_C2H_PKT_OFLD_RSP_W2_PTK_OP); 4965 struct rtw89_completion_data data = {}; 4966 unsigned int cond; 4967 4968 rtw89_debug(rtwdev, RTW89_DBG_FW, "pkt ofld rsp: id %d op %d len %d\n", 4969 pkt_id, pkt_op, pkt_len); 4970 4971 data.err = !pkt_len; 4972 cond = RTW89_FW_OFLD_WAIT_COND_PKT_OFLD(pkt_id, pkt_op); 4973 4974 rtw89_complete_cond(wait, cond, &data); 4975 } 4976 4977 static void rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4978 rtw89_mac_c2h_tsf32_toggle_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 4979 u32 len) 4980 { 4981 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_TSF32_TOGGLE_CHANGE); 4982 } 4983 4984 static void rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)4985 rtw89_mac_c2h_mcc_rcv_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 4986 { 4987 u8 group = RTW89_GET_MAC_C2H_MCC_RCV_ACK_GROUP(c2h->data); 4988 u8 func = RTW89_GET_MAC_C2H_MCC_RCV_ACK_H2C_FUNC(c2h->data); 4989 4990 switch (func) { 4991 case H2C_FUNC_ADD_MCC: 4992 case H2C_FUNC_START_MCC: 4993 case H2C_FUNC_STOP_MCC: 4994 case H2C_FUNC_DEL_MCC_GROUP: 4995 case H2C_FUNC_RESET_MCC_GROUP: 4996 case H2C_FUNC_MCC_REQ_TSF: 4997 case H2C_FUNC_MCC_MACID_BITMAP: 4998 case H2C_FUNC_MCC_SYNC: 4999 case H2C_FUNC_MCC_SET_DURATION: 5000 break; 5001 default: 5002 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5003 "invalid MCC C2H RCV ACK: func %d\n", func); 5004 return; 5005 } 5006 5007 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5008 "MCC C2H RCV ACK: group %d, func %d\n", group, func); 5009 } 5010 5011 static void rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)5012 rtw89_mac_c2h_mcc_req_ack(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5013 { 5014 u8 group = RTW89_GET_MAC_C2H_MCC_REQ_ACK_GROUP(c2h->data); 5015 u8 func = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_FUNC(c2h->data); 5016 u8 retcode = RTW89_GET_MAC_C2H_MCC_REQ_ACK_H2C_RETURN(c2h->data); 5017 struct rtw89_completion_data data = {}; 5018 unsigned int cond; 5019 bool next = false; 5020 5021 switch (func) { 5022 case H2C_FUNC_MCC_REQ_TSF: 5023 next = true; 5024 break; 5025 case H2C_FUNC_MCC_MACID_BITMAP: 5026 case H2C_FUNC_MCC_SYNC: 5027 case H2C_FUNC_MCC_SET_DURATION: 5028 break; 5029 case H2C_FUNC_ADD_MCC: 5030 case H2C_FUNC_START_MCC: 5031 case H2C_FUNC_STOP_MCC: 5032 case H2C_FUNC_DEL_MCC_GROUP: 5033 case H2C_FUNC_RESET_MCC_GROUP: 5034 default: 5035 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5036 "invalid MCC C2H REQ ACK: func %d\n", func); 5037 return; 5038 } 5039 5040 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5041 "MCC C2H REQ ACK: group %d, func %d, return code %d\n", 5042 group, func, retcode); 5043 5044 if (!retcode && next) 5045 return; 5046 5047 data.err = !!retcode; 5048 cond = RTW89_MCC_WAIT_COND(group, func); 5049 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5050 } 5051 5052 static void rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)5053 rtw89_mac_c2h_mcc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5054 { 5055 u8 group = RTW89_GET_MAC_C2H_MCC_TSF_RPT_GROUP(c2h->data); 5056 struct rtw89_completion_data data = {}; 5057 struct rtw89_mac_mcc_tsf_rpt *rpt; 5058 unsigned int cond; 5059 5060 rpt = (struct rtw89_mac_mcc_tsf_rpt *)data.buf; 5061 rpt->macid_x = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_X(c2h->data); 5062 rpt->macid_y = RTW89_GET_MAC_C2H_MCC_TSF_RPT_MACID_Y(c2h->data); 5063 rpt->tsf_x_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_X(c2h->data); 5064 rpt->tsf_x_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_X(c2h->data); 5065 rpt->tsf_y_low = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_LOW_Y(c2h->data); 5066 rpt->tsf_y_high = RTW89_GET_MAC_C2H_MCC_TSF_RPT_TSF_HIGH_Y(c2h->data); 5067 5068 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5069 "MCC C2H TSF RPT: macid %d> %llu, macid %d> %llu\n", 5070 rpt->macid_x, (u64)rpt->tsf_x_high << 32 | rpt->tsf_x_low, 5071 rpt->macid_y, (u64)rpt->tsf_y_high << 32 | rpt->tsf_y_low); 5072 5073 cond = RTW89_MCC_WAIT_COND(group, H2C_FUNC_MCC_REQ_TSF); 5074 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5075 } 5076 5077 static void rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)5078 rtw89_mac_c2h_mcc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5079 { 5080 u8 group = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_GROUP(c2h->data); 5081 u8 macid = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_MACID(c2h->data); 5082 u8 status = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_STATUS(c2h->data); 5083 u32 tsf_low = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_LOW(c2h->data); 5084 u32 tsf_high = RTW89_GET_MAC_C2H_MCC_STATUS_RPT_TSF_HIGH(c2h->data); 5085 struct rtw89_completion_data data = {}; 5086 unsigned int cond; 5087 bool rsp = true; 5088 bool err; 5089 u8 func; 5090 5091 switch (status) { 5092 case RTW89_MAC_MCC_ADD_ROLE_OK: 5093 case RTW89_MAC_MCC_ADD_ROLE_FAIL: 5094 func = H2C_FUNC_ADD_MCC; 5095 err = status == RTW89_MAC_MCC_ADD_ROLE_FAIL; 5096 break; 5097 case RTW89_MAC_MCC_START_GROUP_OK: 5098 case RTW89_MAC_MCC_START_GROUP_FAIL: 5099 func = H2C_FUNC_START_MCC; 5100 err = status == RTW89_MAC_MCC_START_GROUP_FAIL; 5101 break; 5102 case RTW89_MAC_MCC_STOP_GROUP_OK: 5103 case RTW89_MAC_MCC_STOP_GROUP_FAIL: 5104 func = H2C_FUNC_STOP_MCC; 5105 err = status == RTW89_MAC_MCC_STOP_GROUP_FAIL; 5106 break; 5107 case RTW89_MAC_MCC_DEL_GROUP_OK: 5108 case RTW89_MAC_MCC_DEL_GROUP_FAIL: 5109 func = H2C_FUNC_DEL_MCC_GROUP; 5110 err = status == RTW89_MAC_MCC_DEL_GROUP_FAIL; 5111 break; 5112 case RTW89_MAC_MCC_RESET_GROUP_OK: 5113 case RTW89_MAC_MCC_RESET_GROUP_FAIL: 5114 func = H2C_FUNC_RESET_MCC_GROUP; 5115 err = status == RTW89_MAC_MCC_RESET_GROUP_FAIL; 5116 break; 5117 case RTW89_MAC_MCC_SWITCH_CH_OK: 5118 case RTW89_MAC_MCC_SWITCH_CH_FAIL: 5119 case RTW89_MAC_MCC_TXNULL0_OK: 5120 case RTW89_MAC_MCC_TXNULL0_FAIL: 5121 case RTW89_MAC_MCC_TXNULL1_OK: 5122 case RTW89_MAC_MCC_TXNULL1_FAIL: 5123 case RTW89_MAC_MCC_SWITCH_EARLY: 5124 case RTW89_MAC_MCC_TBTT: 5125 case RTW89_MAC_MCC_DURATION_START: 5126 case RTW89_MAC_MCC_DURATION_END: 5127 rsp = false; 5128 break; 5129 default: 5130 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5131 "invalid MCC C2H STS RPT: status %d\n", status); 5132 return; 5133 } 5134 5135 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5136 "MCC C2H STS RPT: group %d, macid %d, status %d, tsf %llu\n", 5137 group, macid, status, (u64)tsf_high << 32 | tsf_low); 5138 5139 if (!rsp) 5140 return; 5141 5142 data.err = err; 5143 cond = RTW89_MCC_WAIT_COND(group, func); 5144 rtw89_complete_cond(&rtwdev->mcc.wait, cond, &data); 5145 } 5146 5147 static void rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)5148 rtw89_mac_c2h_mrc_tsf_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5149 { 5150 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5151 const struct rtw89_c2h_mrc_tsf_rpt *c2h_rpt; 5152 struct rtw89_completion_data data = {}; 5153 struct rtw89_mac_mrc_tsf_rpt *rpt; 5154 unsigned int i; 5155 5156 c2h_rpt = (const struct rtw89_c2h_mrc_tsf_rpt *)c2h->data; 5157 rpt = (struct rtw89_mac_mrc_tsf_rpt *)data.buf; 5158 rpt->num = min_t(u8, RTW89_MAC_MRC_MAX_REQ_TSF_NUM, 5159 le32_get_bits(c2h_rpt->w2, 5160 RTW89_C2H_MRC_TSF_RPT_W2_REQ_TSF_NUM)); 5161 5162 for (i = 0; i < rpt->num; i++) { 5163 u32 tsf_high = le32_to_cpu(c2h_rpt->infos[i].tsf_high); 5164 u32 tsf_low = le32_to_cpu(c2h_rpt->infos[i].tsf_low); 5165 5166 rpt->tsfs[i] = (u64)tsf_high << 32 | tsf_low; 5167 5168 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5169 "MRC C2H TSF RPT: index %u> %llu\n", 5170 i, rpt->tsfs[i]); 5171 } 5172 5173 rtw89_complete_cond(wait, RTW89_MRC_WAIT_COND_REQ_TSF, &data); 5174 } 5175 5176 static void rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len)5177 rtw89_mac_c2h_wow_aoac_rpt(struct rtw89_dev *rtwdev, struct sk_buff *skb, u32 len) 5178 { 5179 struct rtw89_wow_param *rtw_wow = &rtwdev->wow; 5180 struct rtw89_wow_aoac_report *aoac_rpt = &rtw_wow->aoac_rpt; 5181 struct rtw89_wait_info *wait = &rtw_wow->wait; 5182 const struct rtw89_c2h_wow_aoac_report *c2h = 5183 (const struct rtw89_c2h_wow_aoac_report *)skb->data; 5184 struct rtw89_completion_data data = {}; 5185 5186 aoac_rpt->rpt_ver = c2h->rpt_ver; 5187 aoac_rpt->sec_type = c2h->sec_type; 5188 aoac_rpt->key_idx = c2h->key_idx; 5189 aoac_rpt->pattern_idx = c2h->pattern_idx; 5190 aoac_rpt->rekey_ok = u8_get_bits(c2h->rekey_ok, 5191 RTW89_C2H_WOW_AOAC_RPT_REKEY_IDX); 5192 memcpy(aoac_rpt->ptk_tx_iv, c2h->ptk_tx_iv, sizeof(aoac_rpt->ptk_tx_iv)); 5193 memcpy(aoac_rpt->eapol_key_replay_count, c2h->eapol_key_replay_count, 5194 sizeof(aoac_rpt->eapol_key_replay_count)); 5195 memcpy(aoac_rpt->gtk, c2h->gtk, sizeof(aoac_rpt->gtk)); 5196 memcpy(aoac_rpt->ptk_rx_iv, c2h->ptk_rx_iv, sizeof(aoac_rpt->ptk_rx_iv)); 5197 memcpy(aoac_rpt->gtk_rx_iv, c2h->gtk_rx_iv, sizeof(aoac_rpt->gtk_rx_iv)); 5198 aoac_rpt->igtk_key_id = le64_to_cpu(c2h->igtk_key_id); 5199 aoac_rpt->igtk_ipn = le64_to_cpu(c2h->igtk_ipn); 5200 memcpy(aoac_rpt->igtk, c2h->igtk, sizeof(aoac_rpt->igtk)); 5201 5202 rtw89_complete_cond(wait, RTW89_WOW_WAIT_COND_AOAC, &data); 5203 } 5204 5205 static void rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u32 len)5206 rtw89_mac_c2h_mrc_status_rpt(struct rtw89_dev *rtwdev, struct sk_buff *c2h, u32 len) 5207 { 5208 struct rtw89_wait_info *wait = &rtwdev->mcc.wait; 5209 const struct rtw89_c2h_mrc_status_rpt *c2h_rpt; 5210 struct rtw89_completion_data data = {}; 5211 enum rtw89_mac_mrc_status status; 5212 unsigned int cond; 5213 bool next = false; 5214 u32 tsf_high; 5215 u32 tsf_low; 5216 u8 sch_idx; 5217 u8 func; 5218 5219 c2h_rpt = (const struct rtw89_c2h_mrc_status_rpt *)c2h->data; 5220 sch_idx = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_SCH_IDX); 5221 status = le32_get_bits(c2h_rpt->w2, RTW89_C2H_MRC_STATUS_RPT_W2_STATUS); 5222 tsf_high = le32_to_cpu(c2h_rpt->tsf_high); 5223 tsf_low = le32_to_cpu(c2h_rpt->tsf_low); 5224 5225 switch (status) { 5226 case RTW89_MAC_MRC_START_SCH_OK: 5227 func = H2C_FUNC_START_MRC; 5228 break; 5229 case RTW89_MAC_MRC_STOP_SCH_OK: 5230 /* H2C_FUNC_DEL_MRC without STOP_ONLY, so wait for DEL_SCH_OK */ 5231 func = H2C_FUNC_DEL_MRC; 5232 next = true; 5233 break; 5234 case RTW89_MAC_MRC_DEL_SCH_OK: 5235 func = H2C_FUNC_DEL_MRC; 5236 break; 5237 case RTW89_MAC_MRC_EMPTY_SCH_FAIL: 5238 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5239 "MRC C2H STS RPT: empty sch fail\n"); 5240 return; 5241 case RTW89_MAC_MRC_ROLE_NOT_EXIST_FAIL: 5242 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5243 "MRC C2H STS RPT: role not exist fail\n"); 5244 return; 5245 case RTW89_MAC_MRC_DATA_NOT_FOUND_FAIL: 5246 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5247 "MRC C2H STS RPT: data not found fail\n"); 5248 return; 5249 case RTW89_MAC_MRC_GET_NEXT_SLOT_FAIL: 5250 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5251 "MRC C2H STS RPT: get next slot fail\n"); 5252 return; 5253 case RTW89_MAC_MRC_ALT_ROLE_FAIL: 5254 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5255 "MRC C2H STS RPT: alt role fail\n"); 5256 return; 5257 case RTW89_MAC_MRC_ADD_PSTIMER_FAIL: 5258 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5259 "MRC C2H STS RPT: add ps timer fail\n"); 5260 return; 5261 case RTW89_MAC_MRC_MALLOC_FAIL: 5262 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5263 "MRC C2H STS RPT: malloc fail\n"); 5264 return; 5265 case RTW89_MAC_MRC_SWITCH_CH_FAIL: 5266 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5267 "MRC C2H STS RPT: switch ch fail\n"); 5268 return; 5269 case RTW89_MAC_MRC_TXNULL0_FAIL: 5270 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5271 "MRC C2H STS RPT: tx null-0 fail\n"); 5272 return; 5273 case RTW89_MAC_MRC_PORT_FUNC_EN_FAIL: 5274 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5275 "MRC C2H STS RPT: port func en fail\n"); 5276 return; 5277 default: 5278 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5279 "invalid MRC C2H STS RPT: status %d\n", status); 5280 return; 5281 } 5282 5283 rtw89_debug(rtwdev, RTW89_DBG_CHAN, 5284 "MRC C2H STS RPT: sch_idx %d, status %d, tsf %llu\n", 5285 sch_idx, status, (u64)tsf_high << 32 | tsf_low); 5286 5287 if (next) 5288 return; 5289 5290 cond = RTW89_MRC_WAIT_COND(sch_idx, func); 5291 rtw89_complete_cond(wait, cond, &data); 5292 } 5293 5294 static 5295 void (* const rtw89_mac_c2h_ofld_handler[])(struct rtw89_dev *rtwdev, 5296 struct sk_buff *c2h, u32 len) = { 5297 [RTW89_MAC_C2H_FUNC_EFUSE_DUMP] = NULL, 5298 [RTW89_MAC_C2H_FUNC_READ_RSP] = NULL, 5299 [RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP] = rtw89_mac_c2h_pkt_ofld_rsp, 5300 [RTW89_MAC_C2H_FUNC_BCN_RESEND] = NULL, 5301 [RTW89_MAC_C2H_FUNC_MACID_PAUSE] = rtw89_mac_c2h_macid_pause, 5302 [RTW89_MAC_C2H_FUNC_SCANOFLD_RSP] = rtw89_mac_c2h_scanofld_rsp, 5303 [RTW89_MAC_C2H_FUNC_TSF32_TOGL_RPT] = rtw89_mac_c2h_tsf32_toggle_rpt, 5304 [RTW89_MAC_C2H_FUNC_BCNFLTR_RPT] = rtw89_mac_c2h_bcn_fltr_rpt, 5305 }; 5306 5307 static 5308 void (* const rtw89_mac_c2h_info_handler[])(struct rtw89_dev *rtwdev, 5309 struct sk_buff *c2h, u32 len) = { 5310 [RTW89_MAC_C2H_FUNC_REC_ACK] = rtw89_mac_c2h_rec_ack, 5311 [RTW89_MAC_C2H_FUNC_DONE_ACK] = rtw89_mac_c2h_done_ack, 5312 [RTW89_MAC_C2H_FUNC_C2H_LOG] = rtw89_mac_c2h_log, 5313 [RTW89_MAC_C2H_FUNC_BCN_CNT] = rtw89_mac_c2h_bcn_cnt, 5314 }; 5315 5316 static 5317 void (* const rtw89_mac_c2h_mcc_handler[])(struct rtw89_dev *rtwdev, 5318 struct sk_buff *c2h, u32 len) = { 5319 [RTW89_MAC_C2H_FUNC_MCC_RCV_ACK] = rtw89_mac_c2h_mcc_rcv_ack, 5320 [RTW89_MAC_C2H_FUNC_MCC_REQ_ACK] = rtw89_mac_c2h_mcc_req_ack, 5321 [RTW89_MAC_C2H_FUNC_MCC_TSF_RPT] = rtw89_mac_c2h_mcc_tsf_rpt, 5322 [RTW89_MAC_C2H_FUNC_MCC_STATUS_RPT] = rtw89_mac_c2h_mcc_status_rpt, 5323 }; 5324 5325 static 5326 void (* const rtw89_mac_c2h_mrc_handler[])(struct rtw89_dev *rtwdev, 5327 struct sk_buff *c2h, u32 len) = { 5328 [RTW89_MAC_C2H_FUNC_MRC_TSF_RPT] = rtw89_mac_c2h_mrc_tsf_rpt, 5329 [RTW89_MAC_C2H_FUNC_MRC_STATUS_RPT] = rtw89_mac_c2h_mrc_status_rpt, 5330 }; 5331 5332 static 5333 void (* const rtw89_mac_c2h_wow_handler[])(struct rtw89_dev *rtwdev, 5334 struct sk_buff *c2h, u32 len) = { 5335 [RTW89_MAC_C2H_FUNC_AOAC_REPORT] = rtw89_mac_c2h_wow_aoac_rpt, 5336 }; 5337 rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev * rtwdev,struct sk_buff * skb)5338 static void rtw89_mac_c2h_scanofld_rsp_atomic(struct rtw89_dev *rtwdev, 5339 struct sk_buff *skb) 5340 { 5341 const struct rtw89_c2h_scanofld *c2h = 5342 (const struct rtw89_c2h_scanofld *)skb->data; 5343 struct rtw89_wait_info *fw_ofld_wait = &rtwdev->mac.fw_ofld_wait; 5344 struct rtw89_completion_data data = {}; 5345 unsigned int cond; 5346 u8 status, reason; 5347 5348 status = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_STATUS); 5349 reason = le32_get_bits(c2h->w2, RTW89_C2H_SCANOFLD_W2_RSN); 5350 data.err = status != RTW89_SCAN_STATUS_SUCCESS; 5351 5352 if (reason == RTW89_SCAN_END_SCAN_NOTIFY) { 5353 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) 5354 cond = RTW89_SCANOFLD_BE_WAIT_COND_STOP; 5355 else 5356 cond = RTW89_SCANOFLD_WAIT_COND_STOP; 5357 5358 rtw89_complete_cond(fw_ofld_wait, cond, &data); 5359 } 5360 } 5361 rtw89_mac_c2h_chk_atomic(struct rtw89_dev * rtwdev,struct sk_buff * c2h,u8 class,u8 func)5362 bool rtw89_mac_c2h_chk_atomic(struct rtw89_dev *rtwdev, struct sk_buff *c2h, 5363 u8 class, u8 func) 5364 { 5365 switch (class) { 5366 default: 5367 return false; 5368 case RTW89_MAC_C2H_CLASS_INFO: 5369 switch (func) { 5370 default: 5371 return false; 5372 case RTW89_MAC_C2H_FUNC_REC_ACK: 5373 case RTW89_MAC_C2H_FUNC_DONE_ACK: 5374 return true; 5375 } 5376 case RTW89_MAC_C2H_CLASS_OFLD: 5377 switch (func) { 5378 default: 5379 return false; 5380 case RTW89_MAC_C2H_FUNC_SCANOFLD_RSP: 5381 rtw89_mac_c2h_scanofld_rsp_atomic(rtwdev, c2h); 5382 return false; 5383 case RTW89_MAC_C2H_FUNC_PKT_OFLD_RSP: 5384 return true; 5385 } 5386 case RTW89_MAC_C2H_CLASS_MCC: 5387 return true; 5388 case RTW89_MAC_C2H_CLASS_MRC: 5389 return true; 5390 case RTW89_MAC_C2H_CLASS_WOW: 5391 return true; 5392 } 5393 } 5394 rtw89_mac_c2h_handle(struct rtw89_dev * rtwdev,struct sk_buff * skb,u32 len,u8 class,u8 func)5395 void rtw89_mac_c2h_handle(struct rtw89_dev *rtwdev, struct sk_buff *skb, 5396 u32 len, u8 class, u8 func) 5397 { 5398 void (*handler)(struct rtw89_dev *rtwdev, 5399 struct sk_buff *c2h, u32 len) = NULL; 5400 5401 switch (class) { 5402 case RTW89_MAC_C2H_CLASS_INFO: 5403 if (func < RTW89_MAC_C2H_FUNC_INFO_MAX) 5404 handler = rtw89_mac_c2h_info_handler[func]; 5405 break; 5406 case RTW89_MAC_C2H_CLASS_OFLD: 5407 if (func < RTW89_MAC_C2H_FUNC_OFLD_MAX) 5408 handler = rtw89_mac_c2h_ofld_handler[func]; 5409 break; 5410 case RTW89_MAC_C2H_CLASS_MCC: 5411 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MCC) 5412 handler = rtw89_mac_c2h_mcc_handler[func]; 5413 break; 5414 case RTW89_MAC_C2H_CLASS_MRC: 5415 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_MRC) 5416 handler = rtw89_mac_c2h_mrc_handler[func]; 5417 break; 5418 case RTW89_MAC_C2H_CLASS_WOW: 5419 if (func < NUM_OF_RTW89_MAC_C2H_FUNC_WOW) 5420 handler = rtw89_mac_c2h_wow_handler[func]; 5421 break; 5422 case RTW89_MAC_C2H_CLASS_FWDBG: 5423 return; 5424 default: 5425 rtw89_info(rtwdev, "c2h class %d not support\n", class); 5426 return; 5427 } 5428 if (!handler) { 5429 rtw89_info(rtwdev, "c2h class %d func %d not support\n", class, 5430 func); 5431 return; 5432 } 5433 handler(rtwdev, skb, len); 5434 } 5435 5436 static rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx,u32 reg_base,u32 * cr)5437 bool rtw89_mac_get_txpwr_cr_ax(struct rtw89_dev *rtwdev, 5438 enum rtw89_phy_idx phy_idx, 5439 u32 reg_base, u32 *cr) 5440 { 5441 enum rtw89_qta_mode mode = rtwdev->mac.qta_mode; 5442 u32 addr = rtw89_mac_reg_by_idx(rtwdev, reg_base, phy_idx); 5443 5444 if (addr < R_AX_PWR_RATE_CTRL || addr > CMAC1_END_ADDR_AX) { 5445 rtw89_err(rtwdev, "[TXPWR] addr=0x%x exceed txpwr cr\n", 5446 addr); 5447 goto error; 5448 } 5449 5450 if (addr >= CMAC1_START_ADDR_AX && addr <= CMAC1_END_ADDR_AX) 5451 if (mode == RTW89_QTA_SCC) { 5452 rtw89_err(rtwdev, 5453 "[TXPWR] addr=0x%x but hw not enable\n", 5454 addr); 5455 goto error; 5456 } 5457 5458 *cr = addr; 5459 return true; 5460 5461 error: 5462 rtw89_err(rtwdev, "[TXPWR] check txpwr cr 0x%x(phy%d) fail\n", 5463 addr, phy_idx); 5464 5465 return false; 5466 } 5467 5468 static rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev * rtwdev,u8 mac_idx,bool enable)5469 int rtw89_mac_cfg_ppdu_status_ax(struct rtw89_dev *rtwdev, u8 mac_idx, bool enable) 5470 { 5471 u32 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_PPDU_STAT, mac_idx); 5472 int ret; 5473 5474 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5475 if (ret) 5476 return ret; 5477 5478 if (!enable) { 5479 rtw89_write32_clr(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN); 5480 return 0; 5481 } 5482 5483 rtw89_write32(rtwdev, reg, B_AX_PPDU_STAT_RPT_EN | 5484 B_AX_APP_MAC_INFO_RPT | 5485 B_AX_APP_RX_CNT_RPT | B_AX_APP_PLCP_HDR_RPT | 5486 B_AX_PPDU_STAT_RPT_CRC32); 5487 rtw89_write32_mask(rtwdev, R_AX_HW_RPT_FWD, B_AX_FWD_PPDU_STAT_MASK, 5488 RTW89_PRPT_DEST_HOST); 5489 5490 return 0; 5491 } 5492 rtw89_mac_update_rts_threshold(struct rtw89_dev * rtwdev,u8 mac_idx)5493 void rtw89_mac_update_rts_threshold(struct rtw89_dev *rtwdev, u8 mac_idx) 5494 { 5495 #define MAC_AX_TIME_TH_SH 5 5496 #define MAC_AX_LEN_TH_SH 4 5497 #define MAC_AX_TIME_TH_MAX 255 5498 #define MAC_AX_LEN_TH_MAX 255 5499 #define MAC_AX_TIME_TH_DEF 88 5500 #define MAC_AX_LEN_TH_DEF 4080 5501 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5502 struct ieee80211_hw *hw = rtwdev->hw; 5503 u32 rts_threshold = hw->wiphy->rts_threshold; 5504 u32 time_th, len_th; 5505 u32 reg; 5506 5507 if (rts_threshold == (u32)-1) { 5508 time_th = MAC_AX_TIME_TH_DEF; 5509 len_th = MAC_AX_LEN_TH_DEF; 5510 } else { 5511 time_th = MAC_AX_TIME_TH_MAX << MAC_AX_TIME_TH_SH; 5512 len_th = rts_threshold; 5513 } 5514 5515 time_th = min_t(u32, time_th >> MAC_AX_TIME_TH_SH, MAC_AX_TIME_TH_MAX); 5516 len_th = min_t(u32, len_th >> MAC_AX_LEN_TH_SH, MAC_AX_LEN_TH_MAX); 5517 5518 reg = rtw89_mac_reg_by_idx(rtwdev, mac->agg_len_ht, mac_idx); 5519 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_TXTIME_TH_MASK, time_th); 5520 rtw89_write16_mask(rtwdev, reg, B_AX_RTS_LEN_TH_MASK, len_th); 5521 } 5522 rtw89_mac_flush_txq(struct rtw89_dev * rtwdev,u32 queues,bool drop)5523 void rtw89_mac_flush_txq(struct rtw89_dev *rtwdev, u32 queues, bool drop) 5524 { 5525 bool empty; 5526 int ret; 5527 5528 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5529 return; 5530 5531 ret = read_poll_timeout(dle_is_txq_empty, empty, empty, 5532 10000, 200000, false, rtwdev); 5533 if (ret && !drop && (rtwdev->total_sta_assoc || rtwdev->scanning)) 5534 rtw89_info(rtwdev, "timed out to flush queues\n"); 5535 } 5536 rtw89_mac_coex_init(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)5537 int rtw89_mac_coex_init(struct rtw89_dev *rtwdev, const struct rtw89_mac_ax_coex *coex) 5538 { 5539 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id; 5540 u8 val; 5541 u16 val16; 5542 u32 val32; 5543 int ret; 5544 5545 rtw89_write8_set(rtwdev, R_AX_GPIO_MUXCFG, B_AX_ENBT); 5546 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5547 rtw89_write8_set(rtwdev, R_AX_BTC_FUNC_EN, B_AX_PTA_WL_TX_EN); 5548 rtw89_write8_set(rtwdev, R_AX_BT_COEX_CFG_2 + 1, B_AX_GNT_BT_POLARITY >> 8); 5549 rtw89_write8_set(rtwdev, R_AX_CSR_MODE, B_AX_STATIS_BT_EN | B_AX_WL_ACT_MSK); 5550 rtw89_write8_set(rtwdev, R_AX_CSR_MODE + 2, B_AX_BT_CNT_RST >> 16); 5551 if (chip_id != RTL8851B && chip_id != RTL8852BT) 5552 rtw89_write8_clr(rtwdev, R_AX_TRXPTCL_RESP_0 + 3, B_AX_RSP_CHK_BTCCA >> 24); 5553 5554 val16 = rtw89_read16(rtwdev, R_AX_CCA_CFG_0); 5555 val16 = (val16 | B_AX_BTCCA_EN) & ~B_AX_BTCCA_BRK_TXOP_EN; 5556 rtw89_write16(rtwdev, R_AX_CCA_CFG_0, val16); 5557 5558 ret = rtw89_mac_read_lte(rtwdev, R_AX_LTE_SW_CFG_2, &val32); 5559 if (ret) { 5560 rtw89_err(rtwdev, "Read R_AX_LTE_SW_CFG_2 fail!\n"); 5561 return ret; 5562 } 5563 val32 = val32 & B_AX_WL_RX_CTRL; 5564 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_2, val32); 5565 if (ret) { 5566 rtw89_err(rtwdev, "Write R_AX_LTE_SW_CFG_2 fail!\n"); 5567 return ret; 5568 } 5569 5570 switch (coex->pta_mode) { 5571 case RTW89_MAC_AX_COEX_RTK_MODE: 5572 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5573 val &= ~B_AX_BTMODE_MASK; 5574 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_0_3); 5575 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5576 5577 val = rtw89_read8(rtwdev, R_AX_TDMA_MODE); 5578 rtw89_write8(rtwdev, R_AX_TDMA_MODE, val | B_AX_RTK_BT_ENABLE); 5579 5580 val = rtw89_read8(rtwdev, R_AX_BT_COEX_CFG_5); 5581 val &= ~B_AX_BT_RPT_SAMPLE_RATE_MASK; 5582 val |= FIELD_PREP(B_AX_BT_RPT_SAMPLE_RATE_MASK, MAC_AX_RTK_RATE); 5583 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_5, val); 5584 break; 5585 case RTW89_MAC_AX_COEX_CSR_MODE: 5586 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG); 5587 val &= ~B_AX_BTMODE_MASK; 5588 val |= FIELD_PREP(B_AX_BTMODE_MASK, MAC_AX_BT_MODE_2); 5589 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG, val); 5590 5591 val16 = rtw89_read16(rtwdev, R_AX_CSR_MODE); 5592 val16 &= ~B_AX_BT_PRI_DETECT_TO_MASK; 5593 val16 |= FIELD_PREP(B_AX_BT_PRI_DETECT_TO_MASK, MAC_AX_CSR_PRI_TO); 5594 val16 &= ~B_AX_BT_TRX_INIT_DETECT_MASK; 5595 val16 |= FIELD_PREP(B_AX_BT_TRX_INIT_DETECT_MASK, MAC_AX_CSR_TRX_TO); 5596 val16 &= ~B_AX_BT_STAT_DELAY_MASK; 5597 val16 |= FIELD_PREP(B_AX_BT_STAT_DELAY_MASK, MAC_AX_CSR_DELAY); 5598 val16 |= B_AX_ENHANCED_BT; 5599 rtw89_write16(rtwdev, R_AX_CSR_MODE, val16); 5600 5601 rtw89_write8(rtwdev, R_AX_BT_COEX_CFG_2, MAC_AX_CSR_RATE); 5602 break; 5603 default: 5604 return -EINVAL; 5605 } 5606 5607 switch (coex->direction) { 5608 case RTW89_MAC_AX_COEX_INNER: 5609 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5610 val = (val & ~BIT(2)) | BIT(1); 5611 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5612 break; 5613 case RTW89_MAC_AX_COEX_OUTPUT: 5614 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5615 val = val | BIT(1) | BIT(0); 5616 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5617 break; 5618 case RTW89_MAC_AX_COEX_INPUT: 5619 val = rtw89_read8(rtwdev, R_AX_GPIO_MUXCFG + 1); 5620 val = val & ~(BIT(2) | BIT(1)); 5621 rtw89_write8(rtwdev, R_AX_GPIO_MUXCFG + 1, val); 5622 break; 5623 default: 5624 return -EINVAL; 5625 } 5626 5627 return 0; 5628 } 5629 EXPORT_SYMBOL(rtw89_mac_coex_init); 5630 rtw89_mac_coex_init_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex * coex)5631 int rtw89_mac_coex_init_v1(struct rtw89_dev *rtwdev, 5632 const struct rtw89_mac_ax_coex *coex) 5633 { 5634 rtw89_write32_set(rtwdev, R_AX_BTC_CFG, 5635 B_AX_BTC_EN | B_AX_BTG_LNA1_GAIN_SEL); 5636 rtw89_write32_set(rtwdev, R_AX_BT_CNT_CFG, B_AX_BT_CNT_EN); 5637 rtw89_write16_set(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_EN); 5638 rtw89_write16_clr(rtwdev, R_AX_CCA_CFG_0, B_AX_BTCCA_BRK_TXOP_EN); 5639 5640 switch (coex->pta_mode) { 5641 case RTW89_MAC_AX_COEX_RTK_MODE: 5642 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5643 MAC_AX_RTK_MODE); 5644 rtw89_write32_mask(rtwdev, R_AX_RTK_MODE_CFG_V1, 5645 B_AX_SAMPLE_CLK_MASK, MAC_AX_RTK_RATE); 5646 break; 5647 case RTW89_MAC_AX_COEX_CSR_MODE: 5648 rtw89_write32_mask(rtwdev, R_AX_BTC_CFG, B_AX_BTC_MODE_MASK, 5649 MAC_AX_CSR_MODE); 5650 break; 5651 default: 5652 return -EINVAL; 5653 } 5654 5655 return 0; 5656 } 5657 EXPORT_SYMBOL(rtw89_mac_coex_init_v1); 5658 rtw89_mac_cfg_gnt(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)5659 int rtw89_mac_cfg_gnt(struct rtw89_dev *rtwdev, 5660 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5661 { 5662 u32 val = 0, ret; 5663 5664 if (gnt_cfg->band[0].gnt_bt) 5665 val |= B_AX_GNT_BT_RFC_S0_SW_VAL | B_AX_GNT_BT_BB_S0_SW_VAL; 5666 5667 if (gnt_cfg->band[0].gnt_bt_sw_en) 5668 val |= B_AX_GNT_BT_RFC_S0_SW_CTRL | B_AX_GNT_BT_BB_S0_SW_CTRL; 5669 5670 if (gnt_cfg->band[0].gnt_wl) 5671 val |= B_AX_GNT_WL_RFC_S0_SW_VAL | B_AX_GNT_WL_BB_S0_SW_VAL; 5672 5673 if (gnt_cfg->band[0].gnt_wl_sw_en) 5674 val |= B_AX_GNT_WL_RFC_S0_SW_CTRL | B_AX_GNT_WL_BB_S0_SW_CTRL; 5675 5676 if (gnt_cfg->band[1].gnt_bt) 5677 val |= B_AX_GNT_BT_RFC_S1_SW_VAL | B_AX_GNT_BT_BB_S1_SW_VAL; 5678 5679 if (gnt_cfg->band[1].gnt_bt_sw_en) 5680 val |= B_AX_GNT_BT_RFC_S1_SW_CTRL | B_AX_GNT_BT_BB_S1_SW_CTRL; 5681 5682 if (gnt_cfg->band[1].gnt_wl) 5683 val |= B_AX_GNT_WL_RFC_S1_SW_VAL | B_AX_GNT_WL_BB_S1_SW_VAL; 5684 5685 if (gnt_cfg->band[1].gnt_wl_sw_en) 5686 val |= B_AX_GNT_WL_RFC_S1_SW_CTRL | B_AX_GNT_WL_BB_S1_SW_CTRL; 5687 5688 ret = rtw89_mac_write_lte(rtwdev, R_AX_LTE_SW_CFG_1, val); 5689 if (ret) { 5690 rtw89_err(rtwdev, "Write LTE fail!\n"); 5691 return ret; 5692 } 5693 5694 return 0; 5695 } 5696 EXPORT_SYMBOL(rtw89_mac_cfg_gnt); 5697 rtw89_mac_cfg_gnt_v1(struct rtw89_dev * rtwdev,const struct rtw89_mac_ax_coex_gnt * gnt_cfg)5698 int rtw89_mac_cfg_gnt_v1(struct rtw89_dev *rtwdev, 5699 const struct rtw89_mac_ax_coex_gnt *gnt_cfg) 5700 { 5701 u32 val = 0; 5702 5703 if (gnt_cfg->band[0].gnt_bt) 5704 val |= B_AX_GNT_BT_RFC_S0_VAL | B_AX_GNT_BT_RX_VAL | 5705 B_AX_GNT_BT_TX_VAL; 5706 else 5707 val |= B_AX_WL_ACT_VAL; 5708 5709 if (gnt_cfg->band[0].gnt_bt_sw_en) 5710 val |= B_AX_GNT_BT_RFC_S0_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5711 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5712 5713 if (gnt_cfg->band[0].gnt_wl) 5714 val |= B_AX_GNT_WL_RFC_S0_VAL | B_AX_GNT_WL_RX_VAL | 5715 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5716 5717 if (gnt_cfg->band[0].gnt_wl_sw_en) 5718 val |= B_AX_GNT_WL_RFC_S0_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5719 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5720 5721 if (gnt_cfg->band[1].gnt_bt) 5722 val |= B_AX_GNT_BT_RFC_S1_VAL | B_AX_GNT_BT_RX_VAL | 5723 B_AX_GNT_BT_TX_VAL; 5724 else 5725 val |= B_AX_WL_ACT_VAL; 5726 5727 if (gnt_cfg->band[1].gnt_bt_sw_en) 5728 val |= B_AX_GNT_BT_RFC_S1_SWCTRL | B_AX_GNT_BT_RX_SWCTRL | 5729 B_AX_GNT_BT_TX_SWCTRL | B_AX_WL_ACT_SWCTRL; 5730 5731 if (gnt_cfg->band[1].gnt_wl) 5732 val |= B_AX_GNT_WL_RFC_S1_VAL | B_AX_GNT_WL_RX_VAL | 5733 B_AX_GNT_WL_TX_VAL | B_AX_GNT_WL_BB_VAL; 5734 5735 if (gnt_cfg->band[1].gnt_wl_sw_en) 5736 val |= B_AX_GNT_WL_RFC_S1_SWCTRL | B_AX_GNT_WL_RX_SWCTRL | 5737 B_AX_GNT_WL_TX_SWCTRL | B_AX_GNT_WL_BB_SWCTRL; 5738 5739 rtw89_write32(rtwdev, R_AX_GNT_SW_CTRL, val); 5740 5741 return 0; 5742 } 5743 EXPORT_SYMBOL(rtw89_mac_cfg_gnt_v1); 5744 5745 static rtw89_mac_cfg_plt_ax(struct rtw89_dev * rtwdev,struct rtw89_mac_ax_plt * plt)5746 int rtw89_mac_cfg_plt_ax(struct rtw89_dev *rtwdev, struct rtw89_mac_ax_plt *plt) 5747 { 5748 u32 reg; 5749 u16 val; 5750 int ret; 5751 5752 ret = rtw89_mac_check_mac_en(rtwdev, plt->band, RTW89_CMAC_SEL); 5753 if (ret) 5754 return ret; 5755 5756 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, plt->band); 5757 val = (plt->tx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_TX_PLT_GNT_LTE_RX : 0) | 5758 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_TX_PLT_GNT_BT_TX : 0) | 5759 (plt->tx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_TX_PLT_GNT_BT_RX : 0) | 5760 (plt->tx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_TX_PLT_GNT_WL : 0) | 5761 (plt->rx & RTW89_MAC_AX_PLT_LTE_RX ? B_AX_RX_PLT_GNT_LTE_RX : 0) | 5762 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_TX ? B_AX_RX_PLT_GNT_BT_TX : 0) | 5763 (plt->rx & RTW89_MAC_AX_PLT_GNT_BT_RX ? B_AX_RX_PLT_GNT_BT_RX : 0) | 5764 (plt->rx & RTW89_MAC_AX_PLT_GNT_WL ? B_AX_RX_PLT_GNT_WL : 0) | 5765 B_AX_PLT_EN; 5766 rtw89_write16(rtwdev, reg, val); 5767 5768 return 0; 5769 } 5770 rtw89_mac_cfg_sb(struct rtw89_dev * rtwdev,u32 val)5771 void rtw89_mac_cfg_sb(struct rtw89_dev *rtwdev, u32 val) 5772 { 5773 u32 fw_sb; 5774 5775 fw_sb = rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5776 fw_sb = FIELD_GET(B_MAC_AX_SB_FW_MASK, fw_sb); 5777 fw_sb = fw_sb & ~B_MAC_AX_BTGS1_NOTIFY; 5778 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) 5779 fw_sb = fw_sb | MAC_AX_NOTIFY_PWR_MAJOR; 5780 else 5781 fw_sb = fw_sb | MAC_AX_NOTIFY_TP_MAJOR; 5782 val = FIELD_GET(B_MAC_AX_SB_DRV_MASK, val); 5783 val = B_AX_TOGGLE | 5784 FIELD_PREP(B_MAC_AX_SB_DRV_MASK, val) | 5785 FIELD_PREP(B_MAC_AX_SB_FW_MASK, fw_sb); 5786 rtw89_write32(rtwdev, R_AX_SCOREBOARD, val); 5787 fsleep(1000); /* avoid BT FW loss information */ 5788 } 5789 rtw89_mac_get_sb(struct rtw89_dev * rtwdev)5790 u32 rtw89_mac_get_sb(struct rtw89_dev *rtwdev) 5791 { 5792 return rtw89_read32(rtwdev, R_AX_SCOREBOARD); 5793 } 5794 rtw89_mac_cfg_ctrl_path(struct rtw89_dev * rtwdev,bool wl)5795 int rtw89_mac_cfg_ctrl_path(struct rtw89_dev *rtwdev, bool wl) 5796 { 5797 u8 val = rtw89_read8(rtwdev, R_AX_SYS_SDIO_CTRL + 3); 5798 5799 val = wl ? val | BIT(2) : val & ~BIT(2); 5800 rtw89_write8(rtwdev, R_AX_SYS_SDIO_CTRL + 3, val); 5801 5802 return 0; 5803 } 5804 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path); 5805 rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev * rtwdev,bool wl)5806 int rtw89_mac_cfg_ctrl_path_v1(struct rtw89_dev *rtwdev, bool wl) 5807 { 5808 struct rtw89_btc *btc = &rtwdev->btc; 5809 struct rtw89_btc_dm *dm = &btc->dm; 5810 struct rtw89_mac_ax_gnt *g = dm->gnt.band; 5811 int i; 5812 5813 if (wl) 5814 return 0; 5815 5816 for (i = 0; i < RTW89_PHY_MAX; i++) { 5817 g[i].gnt_bt_sw_en = 1; 5818 g[i].gnt_bt = 1; 5819 g[i].gnt_wl_sw_en = 1; 5820 g[i].gnt_wl = 0; 5821 } 5822 5823 return rtw89_mac_cfg_gnt_v1(rtwdev, &dm->gnt); 5824 } 5825 EXPORT_SYMBOL(rtw89_mac_cfg_ctrl_path_v1); 5826 rtw89_mac_get_ctrl_path(struct rtw89_dev * rtwdev)5827 bool rtw89_mac_get_ctrl_path(struct rtw89_dev *rtwdev) 5828 { 5829 const struct rtw89_chip_info *chip = rtwdev->chip; 5830 u8 val = 0; 5831 5832 if (chip->chip_id == RTL8852C || chip->chip_id == RTL8922A) 5833 return false; 5834 else if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 5835 val = rtw89_read8_mask(rtwdev, R_AX_SYS_SDIO_CTRL + 3, 5836 B_AX_LTE_MUX_CTRL_PATH >> 24); 5837 5838 return !!val; 5839 } 5840 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev * rtwdev,u8 band)5841 static u16 rtw89_mac_get_plt_cnt_ax(struct rtw89_dev *rtwdev, u8 band) 5842 { 5843 u32 reg; 5844 u16 cnt; 5845 5846 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BT_PLT, band); 5847 cnt = rtw89_read32_mask(rtwdev, reg, B_AX_BT_PLT_PKT_CNT_MASK); 5848 rtw89_write16_set(rtwdev, reg, B_AX_BT_PLT_RST); 5849 5850 return cnt; 5851 } 5852 rtw89_mac_bfee_standby_timer(struct rtw89_dev * rtwdev,u8 mac_idx,bool keep)5853 static void rtw89_mac_bfee_standby_timer(struct rtw89_dev *rtwdev, u8 mac_idx, 5854 bool keep) 5855 { 5856 u32 reg; 5857 5858 if (rtwdev->chip->chip_gen != RTW89_CHIP_AX) 5859 return; 5860 5861 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee standby_timer to %d\n", keep); 5862 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5863 if (keep) { 5864 set_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5865 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5866 BFRP_RX_STANDBY_TIMER_KEEP); 5867 } else { 5868 clear_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 5869 rtw89_write32_mask(rtwdev, reg, B_AX_BFMEE_BFRP_RX_STANDBY_TIMER_MASK, 5870 BFRP_RX_STANDBY_TIMER_RELEASE); 5871 } 5872 } 5873 rtw89_mac_bfee_ctrl(struct rtw89_dev * rtwdev,u8 mac_idx,bool en)5874 void rtw89_mac_bfee_ctrl(struct rtw89_dev *rtwdev, u8 mac_idx, bool en) 5875 { 5876 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 5877 u32 reg; 5878 u32 mask = mac->bfee_ctrl.mask; 5879 5880 rtw89_debug(rtwdev, RTW89_DBG_BF, "set bfee ndpa_en to %d\n", en); 5881 reg = rtw89_mac_reg_by_idx(rtwdev, mac->bfee_ctrl.addr, mac_idx); 5882 if (en) { 5883 set_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5884 rtw89_write32_set(rtwdev, reg, mask); 5885 } else { 5886 clear_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 5887 rtw89_write32_clr(rtwdev, reg, mask); 5888 } 5889 } 5890 rtw89_mac_init_bfee_ax(struct rtw89_dev * rtwdev,u8 mac_idx)5891 static int rtw89_mac_init_bfee_ax(struct rtw89_dev *rtwdev, u8 mac_idx) 5892 { 5893 u32 reg; 5894 u32 val32; 5895 int ret; 5896 5897 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5898 if (ret) 5899 return ret; 5900 5901 /* AP mode set tx gid to 63 */ 5902 /* STA mode set tx gid to 0(default) */ 5903 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMER_CTRL_0, mac_idx); 5904 rtw89_write32_set(rtwdev, reg, B_AX_BFMER_NDP_BFEN); 5905 5906 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx); 5907 rtw89_write32(rtwdev, reg, CSI_RRSC_BMAP); 5908 5909 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_BFMEE_RESP_OPTION, mac_idx); 5910 val32 = FIELD_PREP(B_AX_BFMEE_NDP_RX_STANDBY_TIMER_MASK, NDP_RX_STANDBY_TIMER); 5911 rtw89_write32(rtwdev, reg, val32); 5912 rtw89_mac_bfee_standby_timer(rtwdev, mac_idx, true); 5913 rtw89_mac_bfee_ctrl(rtwdev, mac_idx, true); 5914 5915 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5916 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL | 5917 B_AX_BFMEE_USE_NSTS | 5918 B_AX_BFMEE_CSI_GID_SEL | 5919 B_AX_BFMEE_CSI_FORCE_RETE_EN); 5920 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RATE, mac_idx); 5921 rtw89_write32(rtwdev, reg, 5922 u32_encode_bits(CSI_INIT_RATE_HT, B_AX_BFMEE_HT_CSI_RATE_MASK) | 5923 u32_encode_bits(CSI_INIT_RATE_VHT, B_AX_BFMEE_VHT_CSI_RATE_MASK) | 5924 u32_encode_bits(CSI_INIT_RATE_HE, B_AX_BFMEE_HE_CSI_RATE_MASK)); 5925 5926 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_CSIRPT_OPTION, mac_idx); 5927 rtw89_write32_set(rtwdev, reg, 5928 B_AX_CSIPRT_VHTSU_AID_EN | B_AX_CSIPRT_HESU_AID_EN); 5929 5930 return 0; 5931 } 5932 rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)5933 static int rtw89_mac_set_csi_para_reg_ax(struct rtw89_dev *rtwdev, 5934 struct ieee80211_vif *vif, 5935 struct ieee80211_sta *sta) 5936 { 5937 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5938 u8 mac_idx = rtwvif->mac_idx; 5939 u8 nc = 1, nr = 3, ng = 0, cb = 1, cs = 1, ldpc_en = 1, stbc_en = 1; 5940 u8 port_sel = rtwvif->port; 5941 u8 sound_dim = 3, t; 5942 u8 *phy_cap = sta->deflink.he_cap.he_cap_elem.phy_cap_info; 5943 u32 reg; 5944 u16 val; 5945 int ret; 5946 5947 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 5948 if (ret) 5949 return ret; 5950 5951 if ((phy_cap[3] & IEEE80211_HE_PHY_CAP3_SU_BEAMFORMER) || 5952 (phy_cap[4] & IEEE80211_HE_PHY_CAP4_MU_BEAMFORMER)) { 5953 ldpc_en &= !!(phy_cap[1] & IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD); 5954 stbc_en &= !!(phy_cap[2] & IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ); 5955 t = FIELD_GET(IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_MASK, 5956 phy_cap[5]); 5957 sound_dim = min(sound_dim, t); 5958 } 5959 if ((sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_MU_BEAMFORMER_CAPABLE) || 5960 (sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_SU_BEAMFORMER_CAPABLE)) { 5961 ldpc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXLDPC); 5962 stbc_en &= !!(sta->deflink.vht_cap.cap & IEEE80211_VHT_CAP_RXSTBC_MASK); 5963 t = FIELD_GET(IEEE80211_VHT_CAP_SOUNDING_DIMENSIONS_MASK, 5964 sta->deflink.vht_cap.cap); 5965 sound_dim = min(sound_dim, t); 5966 } 5967 nc = min(nc, sound_dim); 5968 nr = min(nr, sound_dim); 5969 5970 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5971 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 5972 5973 val = FIELD_PREP(B_AX_BFMEE_CSIINFO0_NC_MASK, nc) | 5974 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NR_MASK, nr) | 5975 FIELD_PREP(B_AX_BFMEE_CSIINFO0_NG_MASK, ng) | 5976 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CB_MASK, cb) | 5977 FIELD_PREP(B_AX_BFMEE_CSIINFO0_CS_MASK, cs) | 5978 FIELD_PREP(B_AX_BFMEE_CSIINFO0_LDPC_EN, ldpc_en) | 5979 FIELD_PREP(B_AX_BFMEE_CSIINFO0_STBC_EN, stbc_en); 5980 5981 if (port_sel == 0) 5982 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 5983 else 5984 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_1, mac_idx); 5985 5986 rtw89_write16(rtwdev, reg, val); 5987 5988 return 0; 5989 } 5990 rtw89_mac_csi_rrsc_ax(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)5991 static int rtw89_mac_csi_rrsc_ax(struct rtw89_dev *rtwdev, 5992 struct ieee80211_vif *vif, 5993 struct ieee80211_sta *sta) 5994 { 5995 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 5996 u32 rrsc = BIT(RTW89_MAC_BF_RRSC_6M) | BIT(RTW89_MAC_BF_RRSC_24M); 5997 u32 reg; 5998 u8 mac_idx = rtwvif->mac_idx; 5999 int ret; 6000 6001 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6002 if (ret) 6003 return ret; 6004 6005 if (sta->deflink.he_cap.has_he) { 6006 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HE_MSC0) | 6007 BIT(RTW89_MAC_BF_RRSC_HE_MSC3) | 6008 BIT(RTW89_MAC_BF_RRSC_HE_MSC5)); 6009 } 6010 if (sta->deflink.vht_cap.vht_supported) { 6011 rrsc |= (BIT(RTW89_MAC_BF_RRSC_VHT_MSC0) | 6012 BIT(RTW89_MAC_BF_RRSC_VHT_MSC3) | 6013 BIT(RTW89_MAC_BF_RRSC_VHT_MSC5)); 6014 } 6015 if (sta->deflink.ht_cap.ht_supported) { 6016 rrsc |= (BIT(RTW89_MAC_BF_RRSC_HT_MSC0) | 6017 BIT(RTW89_MAC_BF_RRSC_HT_MSC3) | 6018 BIT(RTW89_MAC_BF_RRSC_HT_MSC5)); 6019 } 6020 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_CTRL_0, mac_idx); 6021 rtw89_write32_set(rtwdev, reg, B_AX_BFMEE_BFPARAM_SEL); 6022 rtw89_write32_clr(rtwdev, reg, B_AX_BFMEE_CSI_FORCE_RETE_EN); 6023 rtw89_write32(rtwdev, 6024 rtw89_mac_reg_by_idx(rtwdev, R_AX_TRXPTCL_RESP_CSI_RRSC, mac_idx), 6025 rrsc); 6026 6027 return 0; 6028 } 6029 rtw89_mac_bf_assoc_ax(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)6030 static void rtw89_mac_bf_assoc_ax(struct rtw89_dev *rtwdev, 6031 struct ieee80211_vif *vif, 6032 struct ieee80211_sta *sta) 6033 { 6034 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6035 6036 if (rtw89_sta_has_beamformer_cap(sta)) { 6037 rtw89_debug(rtwdev, RTW89_DBG_BF, 6038 "initialize bfee for new association\n"); 6039 rtw89_mac_init_bfee_ax(rtwdev, rtwvif->mac_idx); 6040 rtw89_mac_set_csi_para_reg_ax(rtwdev, vif, sta); 6041 rtw89_mac_csi_rrsc_ax(rtwdev, vif, sta); 6042 } 6043 } 6044 rtw89_mac_bf_disassoc(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta)6045 void rtw89_mac_bf_disassoc(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6046 struct ieee80211_sta *sta) 6047 { 6048 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6049 6050 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, false); 6051 } 6052 rtw89_mac_bf_set_gid_table(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_bss_conf * conf)6053 void rtw89_mac_bf_set_gid_table(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif, 6054 struct ieee80211_bss_conf *conf) 6055 { 6056 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv; 6057 u8 mac_idx = rtwvif->mac_idx; 6058 __le32 *p; 6059 6060 rtw89_debug(rtwdev, RTW89_DBG_BF, "update bf GID table\n"); 6061 6062 p = (__le32 *)conf->mu_group.membership; 6063 rtw89_write32(rtwdev, 6064 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN0, mac_idx), 6065 le32_to_cpu(p[0])); 6066 rtw89_write32(rtwdev, 6067 rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION_EN1, mac_idx), 6068 le32_to_cpu(p[1])); 6069 6070 p = (__le32 *)conf->mu_group.position; 6071 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION0, mac_idx), 6072 le32_to_cpu(p[0])); 6073 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION1, mac_idx), 6074 le32_to_cpu(p[1])); 6075 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION2, mac_idx), 6076 le32_to_cpu(p[2])); 6077 rtw89_write32(rtwdev, rtw89_mac_reg_by_idx(rtwdev, R_AX_GID_POSITION3, mac_idx), 6078 le32_to_cpu(p[3])); 6079 } 6080 6081 struct rtw89_mac_bf_monitor_iter_data { 6082 struct rtw89_dev *rtwdev; 6083 struct ieee80211_sta *down_sta; 6084 int count; 6085 }; 6086 6087 static rtw89_mac_bf_monitor_calc_iter(void * data,struct ieee80211_sta * sta)6088 void rtw89_mac_bf_monitor_calc_iter(void *data, struct ieee80211_sta *sta) 6089 { 6090 struct rtw89_mac_bf_monitor_iter_data *iter_data = 6091 (struct rtw89_mac_bf_monitor_iter_data *)data; 6092 struct ieee80211_sta *down_sta = iter_data->down_sta; 6093 int *count = &iter_data->count; 6094 6095 if (down_sta == sta) 6096 return; 6097 6098 if (rtw89_sta_has_beamformer_cap(sta)) 6099 (*count)++; 6100 } 6101 rtw89_mac_bf_monitor_calc(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,bool disconnect)6102 void rtw89_mac_bf_monitor_calc(struct rtw89_dev *rtwdev, 6103 struct ieee80211_sta *sta, bool disconnect) 6104 { 6105 struct rtw89_mac_bf_monitor_iter_data data; 6106 6107 data.rtwdev = rtwdev; 6108 data.down_sta = disconnect ? sta : NULL; 6109 data.count = 0; 6110 ieee80211_iterate_stations_atomic(rtwdev->hw, 6111 rtw89_mac_bf_monitor_calc_iter, 6112 &data); 6113 6114 rtw89_debug(rtwdev, RTW89_DBG_BF, "bfee STA count=%d\n", data.count); 6115 if (data.count) 6116 set_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6117 else 6118 clear_bit(RTW89_FLAG_BFEE_MON, rtwdev->flags); 6119 } 6120 _rtw89_mac_bf_monitor_track(struct rtw89_dev * rtwdev)6121 void _rtw89_mac_bf_monitor_track(struct rtw89_dev *rtwdev) 6122 { 6123 struct rtw89_traffic_stats *stats = &rtwdev->stats; 6124 struct rtw89_vif *rtwvif; 6125 bool en = stats->tx_tfc_lv <= stats->rx_tfc_lv; 6126 bool old = test_bit(RTW89_FLAG_BFEE_EN, rtwdev->flags); 6127 bool keep_timer = true; 6128 bool old_keep_timer; 6129 6130 old_keep_timer = test_bit(RTW89_FLAG_BFEE_TIMER_KEEP, rtwdev->flags); 6131 6132 if (stats->tx_tfc_lv <= RTW89_TFC_LOW && stats->rx_tfc_lv <= RTW89_TFC_LOW) 6133 keep_timer = false; 6134 6135 if (keep_timer != old_keep_timer) { 6136 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6137 rtw89_mac_bfee_standby_timer(rtwdev, rtwvif->mac_idx, 6138 keep_timer); 6139 } 6140 6141 if (en == old) 6142 return; 6143 6144 rtw89_for_each_rtwvif(rtwdev, rtwvif) 6145 rtw89_mac_bfee_ctrl(rtwdev, rtwvif->mac_idx, en); 6146 } 6147 6148 static int __rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 tx_time)6149 __rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6150 u32 tx_time) 6151 { 6152 #define MAC_AX_DFLT_TX_TIME 5280 6153 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6154 u32 max_tx_time = tx_time == 0 ? MAC_AX_DFLT_TX_TIME : tx_time; 6155 u32 reg; 6156 int ret = 0; 6157 6158 if (rtwsta->cctl_tx_time) { 6159 rtwsta->ampdu_max_time = (max_tx_time - 512) >> 9; 6160 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6161 } else { 6162 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6163 if (ret) { 6164 rtw89_warn(rtwdev, "failed to check cmac in set txtime\n"); 6165 return ret; 6166 } 6167 6168 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6169 rtw89_write32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK, 6170 max_tx_time >> 5); 6171 } 6172 6173 return ret; 6174 } 6175 rtw89_mac_set_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u32 tx_time)6176 int rtw89_mac_set_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6177 bool resume, u32 tx_time) 6178 { 6179 int ret = 0; 6180 6181 if (!resume) { 6182 rtwsta->cctl_tx_time = true; 6183 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6184 } else { 6185 ret = __rtw89_mac_set_tx_time(rtwdev, rtwsta, tx_time); 6186 rtwsta->cctl_tx_time = false; 6187 } 6188 6189 return ret; 6190 } 6191 rtw89_mac_get_tx_time(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u32 * tx_time)6192 int rtw89_mac_get_tx_time(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta, 6193 u32 *tx_time) 6194 { 6195 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6196 u32 reg; 6197 int ret = 0; 6198 6199 if (rtwsta->cctl_tx_time) { 6200 *tx_time = (rtwsta->ampdu_max_time + 1) << 9; 6201 } else { 6202 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6203 if (ret) { 6204 rtw89_warn(rtwdev, "failed to check cmac in tx_time\n"); 6205 return ret; 6206 } 6207 6208 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_AMPDU_AGG_LIMIT, mac_idx); 6209 *tx_time = rtw89_read32_mask(rtwdev, reg, B_AX_AMPDU_MAX_TIME_MASK) << 5; 6210 } 6211 6212 return ret; 6213 } 6214 rtw89_mac_set_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,bool resume,u8 tx_retry)6215 int rtw89_mac_set_tx_retry_limit(struct rtw89_dev *rtwdev, 6216 struct rtw89_sta *rtwsta, 6217 bool resume, u8 tx_retry) 6218 { 6219 int ret = 0; 6220 6221 rtwsta->data_tx_cnt_lmt = tx_retry; 6222 6223 if (!resume) { 6224 rtwsta->cctl_tx_retry_limit = true; 6225 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6226 } else { 6227 ret = rtw89_fw_h2c_txtime_cmac_tbl(rtwdev, rtwsta); 6228 rtwsta->cctl_tx_retry_limit = false; 6229 } 6230 6231 return ret; 6232 } 6233 rtw89_mac_get_tx_retry_limit(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta,u8 * tx_retry)6234 int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev, 6235 struct rtw89_sta *rtwsta, u8 *tx_retry) 6236 { 6237 u8 mac_idx = rtwsta->rtwvif->mac_idx; 6238 u32 reg; 6239 int ret = 0; 6240 6241 if (rtwsta->cctl_tx_retry_limit) { 6242 *tx_retry = rtwsta->data_tx_cnt_lmt; 6243 } else { 6244 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6245 if (ret) { 6246 rtw89_warn(rtwdev, "failed to check cmac in rty_lmt\n"); 6247 return ret; 6248 } 6249 6250 reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_TXCNT, mac_idx); 6251 *tx_retry = rtw89_read32_mask(rtwdev, reg, B_AX_L_TXCNT_LMT_MASK); 6252 } 6253 6254 return ret; 6255 } 6256 rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,bool en)6257 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev, 6258 struct rtw89_vif *rtwvif, bool en) 6259 { 6260 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6261 u8 mac_idx = rtwvif->mac_idx; 6262 u16 set = mac->muedca_ctrl.mask; 6263 u32 reg; 6264 u32 ret; 6265 6266 ret = rtw89_mac_check_mac_en(rtwdev, mac_idx, RTW89_CMAC_SEL); 6267 if (ret) 6268 return ret; 6269 6270 reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx); 6271 if (en) 6272 rtw89_write16_set(rtwdev, reg, set); 6273 else 6274 rtw89_write16_clr(rtwdev, reg, set); 6275 6276 return 0; 6277 } 6278 6279 static rtw89_mac_write_xtal_si_ax(struct rtw89_dev * rtwdev,u8 offset,u8 val,u8 mask)6280 int rtw89_mac_write_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 val, u8 mask) 6281 { 6282 u32 val32; 6283 int ret; 6284 6285 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6286 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, val) | 6287 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, mask) | 6288 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_WRITE) | 6289 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6290 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6291 6292 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6293 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6294 if (ret) { 6295 rtw89_warn(rtwdev, "xtal si not ready(W): offset=%x val=%x mask=%x\n", 6296 offset, val, mask); 6297 return ret; 6298 } 6299 6300 return 0; 6301 } 6302 6303 static rtw89_mac_read_xtal_si_ax(struct rtw89_dev * rtwdev,u8 offset,u8 * val)6304 int rtw89_mac_read_xtal_si_ax(struct rtw89_dev *rtwdev, u8 offset, u8 *val) 6305 { 6306 u32 val32; 6307 int ret; 6308 6309 val32 = FIELD_PREP(B_AX_WL_XTAL_SI_ADDR_MASK, offset) | 6310 FIELD_PREP(B_AX_WL_XTAL_SI_DATA_MASK, 0x00) | 6311 FIELD_PREP(B_AX_WL_XTAL_SI_BITMASK_MASK, 0x00) | 6312 FIELD_PREP(B_AX_WL_XTAL_SI_MODE_MASK, XTAL_SI_NORMAL_READ) | 6313 FIELD_PREP(B_AX_WL_XTAL_SI_CMD_POLL, 1); 6314 rtw89_write32(rtwdev, R_AX_WLAN_XTAL_SI_CTRL, val32); 6315 6316 ret = read_poll_timeout(rtw89_read32, val32, !(val32 & B_AX_WL_XTAL_SI_CMD_POLL), 6317 50, 50000, false, rtwdev, R_AX_WLAN_XTAL_SI_CTRL); 6318 if (ret) { 6319 rtw89_warn(rtwdev, "xtal si not ready(R): offset=%x\n", offset); 6320 return ret; 6321 } 6322 6323 *val = rtw89_read8(rtwdev, R_AX_WLAN_XTAL_SI_CTRL + 1); 6324 6325 return 0; 6326 } 6327 6328 static rtw89_mac_pkt_drop_sta(struct rtw89_dev * rtwdev,struct rtw89_sta * rtwsta)6329 void rtw89_mac_pkt_drop_sta(struct rtw89_dev *rtwdev, struct rtw89_sta *rtwsta) 6330 { 6331 static const enum rtw89_pkt_drop_sel sels[] = { 6332 RTW89_PKT_DROP_SEL_MACID_BE_ONCE, 6333 RTW89_PKT_DROP_SEL_MACID_BK_ONCE, 6334 RTW89_PKT_DROP_SEL_MACID_VI_ONCE, 6335 RTW89_PKT_DROP_SEL_MACID_VO_ONCE, 6336 }; 6337 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6338 struct rtw89_pkt_drop_params params = {0}; 6339 int i; 6340 6341 params.mac_band = RTW89_MAC_0; 6342 params.macid = rtwsta->mac_id; 6343 params.port = rtwvif->port; 6344 params.mbssid = 0; 6345 params.tf_trs = rtwvif->trigger; 6346 6347 for (i = 0; i < ARRAY_SIZE(sels); i++) { 6348 params.sel = sels[i]; 6349 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6350 } 6351 } 6352 rtw89_mac_pkt_drop_vif_iter(void * data,struct ieee80211_sta * sta)6353 static void rtw89_mac_pkt_drop_vif_iter(void *data, struct ieee80211_sta *sta) 6354 { 6355 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv; 6356 struct rtw89_vif *rtwvif = rtwsta->rtwvif; 6357 struct rtw89_dev *rtwdev = rtwvif->rtwdev; 6358 struct rtw89_vif *target = data; 6359 6360 if (rtwvif != target) 6361 return; 6362 6363 rtw89_mac_pkt_drop_sta(rtwdev, rtwsta); 6364 } 6365 rtw89_mac_pkt_drop_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)6366 void rtw89_mac_pkt_drop_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif) 6367 { 6368 ieee80211_iterate_stations_atomic(rtwdev->hw, 6369 rtw89_mac_pkt_drop_vif_iter, 6370 rtwvif); 6371 } 6372 rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev * rtwdev,enum rtw89_mac_idx band)6373 int rtw89_mac_ptk_drop_by_band_and_wait(struct rtw89_dev *rtwdev, 6374 enum rtw89_mac_idx band) 6375 { 6376 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6377 struct rtw89_pkt_drop_params params = {0}; 6378 bool empty; 6379 int i, ret = 0, try_cnt = 3; 6380 6381 params.mac_band = band; 6382 params.sel = RTW89_PKT_DROP_SEL_BAND_ONCE; 6383 6384 for (i = 0; i < try_cnt; i++) { 6385 ret = read_poll_timeout(mac->is_txq_empty, empty, empty, 50, 6386 50000, false, rtwdev); 6387 if (ret && !RTW89_CHK_FW_FEATURE(NO_PACKET_DROP, &rtwdev->fw)) 6388 rtw89_fw_h2c_pkt_drop(rtwdev, ¶ms); 6389 else 6390 return 0; 6391 } 6392 return ret; 6393 } 6394 rtw89_mac_cpu_io_rx(struct rtw89_dev * rtwdev,bool wow_enable)6395 int rtw89_mac_cpu_io_rx(struct rtw89_dev *rtwdev, bool wow_enable) 6396 { 6397 struct rtw89_mac_h2c_info h2c_info = {}; 6398 struct rtw89_mac_c2h_info c2h_info = {}; 6399 u32 ret; 6400 6401 h2c_info.id = RTW89_FWCMD_H2CREG_FUNC_WOW_CPUIO_RX_CTRL; 6402 h2c_info.content_len = sizeof(h2c_info.u.hdr); 6403 h2c_info.u.hdr.w0 = u32_encode_bits(wow_enable, RTW89_H2CREG_WOW_CPUIO_RX_CTRL_EN); 6404 6405 ret = rtw89_fw_msg_reg(rtwdev, &h2c_info, &c2h_info); 6406 if (ret) 6407 return ret; 6408 6409 if (c2h_info.id != RTW89_FWCMD_C2HREG_FUNC_WOW_CPUIO_RX_ACK) 6410 ret = -EINVAL; 6411 6412 return ret; 6413 } 6414 rtw89_wow_config_mac_ax(struct rtw89_dev * rtwdev,bool enable_wow)6415 static int rtw89_wow_config_mac_ax(struct rtw89_dev *rtwdev, bool enable_wow) 6416 { 6417 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def; 6418 const struct rtw89_chip_info *chip = rtwdev->chip; 6419 int ret; 6420 6421 if (enable_wow) { 6422 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, true); 6423 if (ret) { 6424 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6425 return ret; 6426 } 6427 6428 rtw89_write32_set(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6429 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6430 rtw89_write32_clr(rtwdev, mac->rx_fltr, B_AX_SNIFFER_MODE); 6431 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, false); 6432 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, 0); 6433 rtw89_write32(rtwdev, R_AX_ACTION_FWD1, 0); 6434 rtw89_write32(rtwdev, R_AX_TF_FWD, 0); 6435 rtw89_write32(rtwdev, R_AX_HW_RPT_FWD, 0); 6436 6437 if (chip->chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) 6438 rtw89_write8(rtwdev, R_BE_DBG_WOW_READY, WOWLAN_NOT_READY); 6439 else 6440 rtw89_write32_set(rtwdev, R_AX_DBG_WOW, 6441 B_AX_DBG_WOW_CPU_IO_RX_EN); 6442 } else { 6443 ret = rtw89_mac_resize_ple_rx_quota(rtwdev, false); 6444 if (ret) { 6445 rtw89_err(rtwdev, "[ERR]patch rx qta %d\n", ret); 6446 return ret; 6447 } 6448 6449 rtw89_mac_cpu_io_rx(rtwdev, enable_wow); 6450 rtw89_write32_clr(rtwdev, R_AX_RX_FUNCTION_STOP, B_AX_HDR_RX_STOP); 6451 rtw89_mac_cfg_ppdu_status(rtwdev, RTW89_MAC_0, true); 6452 rtw89_write32(rtwdev, R_AX_ACTION_FWD0, TRXCFG_MPDU_PROC_ACT_FRWD); 6453 rtw89_write32(rtwdev, R_AX_TF_FWD, TRXCFG_MPDU_PROC_TF_FRWD); 6454 } 6455 6456 return 0; 6457 } 6458 rtw89_fw_get_rdy_ax(struct rtw89_dev * rtwdev,enum rtw89_fwdl_check_type type)6459 static u8 rtw89_fw_get_rdy_ax(struct rtw89_dev *rtwdev, enum rtw89_fwdl_check_type type) 6460 { 6461 u8 val = rtw89_read8(rtwdev, R_AX_WCPU_FW_CTRL); 6462 6463 return FIELD_GET(B_AX_WCPU_FWDL_STS_MASK, val); 6464 } 6465 6466 static rtw89_fwdl_check_path_ready_ax(struct rtw89_dev * rtwdev,bool h2c_or_fwdl)6467 int rtw89_fwdl_check_path_ready_ax(struct rtw89_dev *rtwdev, 6468 bool h2c_or_fwdl) 6469 { 6470 u8 check = h2c_or_fwdl ? B_AX_H2C_PATH_RDY : B_AX_FWDL_PATH_RDY; 6471 u8 val; 6472 6473 return read_poll_timeout_atomic(rtw89_read8, val, val & check, 6474 1, FWDL_WAIT_CNT, false, 6475 rtwdev, R_AX_WCPU_FW_CTRL); 6476 } 6477 6478 const struct rtw89_mac_gen_def rtw89_mac_gen_ax = { 6479 .band1_offset = RTW89_MAC_AX_BAND_REG_OFFSET, 6480 .filter_model_addr = R_AX_FILTER_MODEL_ADDR, 6481 .indir_access_addr = R_AX_INDIR_ACCESS_ENTRY, 6482 .mem_base_addrs = rtw89_mac_mem_base_addrs_ax, 6483 .rx_fltr = R_AX_RX_FLTR_OPT, 6484 .port_base = &rtw89_port_base_ax, 6485 .agg_len_ht = R_AX_AGG_LEN_HT_0, 6486 .ps_status = R_AX_PPWRBIT_SETTING, 6487 6488 .muedca_ctrl = { 6489 .addr = R_AX_MUEDCA_EN, 6490 .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0, 6491 }, 6492 .bfee_ctrl = { 6493 .addr = R_AX_BFMEE_RESP_OPTION, 6494 .mask = B_AX_BFMEE_HT_NDPA_EN | B_AX_BFMEE_VHT_NDPA_EN | 6495 B_AX_BFMEE_HE_NDPA_EN, 6496 }, 6497 .narrow_bw_ru_dis = { 6498 .addr = R_AX_RXTRIG_TEST_USER_2, 6499 .mask = B_AX_RXTRIG_RU26_DIS, 6500 }, 6501 .wow_ctrl = {.addr = R_AX_WOW_CTRL, .mask = B_AX_WOW_WOWEN,}, 6502 6503 .check_mac_en = rtw89_mac_check_mac_en_ax, 6504 .sys_init = sys_init_ax, 6505 .trx_init = trx_init_ax, 6506 .hci_func_en = rtw89_mac_hci_func_en_ax, 6507 .dmac_func_pre_en = rtw89_mac_dmac_func_pre_en_ax, 6508 .dle_func_en = dle_func_en_ax, 6509 .dle_clk_en = dle_clk_en_ax, 6510 .bf_assoc = rtw89_mac_bf_assoc_ax, 6511 6512 .typ_fltr_opt = rtw89_mac_typ_fltr_opt_ax, 6513 .cfg_ppdu_status = rtw89_mac_cfg_ppdu_status_ax, 6514 6515 .dle_mix_cfg = dle_mix_cfg_ax, 6516 .chk_dle_rdy = chk_dle_rdy_ax, 6517 .dle_buf_req = dle_buf_req_ax, 6518 .hfc_func_en = hfc_func_en_ax, 6519 .hfc_h2c_cfg = hfc_h2c_cfg_ax, 6520 .hfc_mix_cfg = hfc_mix_cfg_ax, 6521 .hfc_get_mix_info = hfc_get_mix_info_ax, 6522 .wde_quota_cfg = wde_quota_cfg_ax, 6523 .ple_quota_cfg = ple_quota_cfg_ax, 6524 .set_cpuio = set_cpuio_ax, 6525 .dle_quota_change = dle_quota_change_ax, 6526 6527 .disable_cpu = rtw89_mac_disable_cpu_ax, 6528 .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax, 6529 .fwdl_get_status = rtw89_fw_get_rdy_ax, 6530 .fwdl_check_path_ready = rtw89_fwdl_check_path_ready_ax, 6531 .parse_efuse_map = rtw89_parse_efuse_map_ax, 6532 .parse_phycap_map = rtw89_parse_phycap_map_ax, 6533 .cnv_efuse_state = rtw89_cnv_efuse_state_ax, 6534 6535 .cfg_plt = rtw89_mac_cfg_plt_ax, 6536 .get_plt_cnt = rtw89_mac_get_plt_cnt_ax, 6537 6538 .get_txpwr_cr = rtw89_mac_get_txpwr_cr_ax, 6539 6540 .write_xtal_si = rtw89_mac_write_xtal_si_ax, 6541 .read_xtal_si = rtw89_mac_read_xtal_si_ax, 6542 6543 .dump_qta_lost = rtw89_mac_dump_qta_lost_ax, 6544 .dump_err_status = rtw89_mac_dump_err_status_ax, 6545 6546 .is_txq_empty = mac_is_txq_empty_ax, 6547 6548 .add_chan_list = rtw89_hw_scan_add_chan_list_ax, 6549 .add_chan_list_pno = rtw89_pno_scan_add_chan_list_ax, 6550 .scan_offload = rtw89_fw_h2c_scan_offload_ax, 6551 6552 .wow_config_mac = rtw89_wow_config_mac_ax, 6553 }; 6554 EXPORT_SYMBOL(rtw89_mac_gen_ax); 6555