1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2024 Realtek Corporation 3 */ 4 5 #ifndef __RTW89_8852BX_H__ 6 #define __RTW89_8852BX_H__ 7 8 #include "core.h" 9 10 #define RF_PATH_NUM_8852BX 2 11 #define BB_PATH_NUM_8852BX 2 12 13 enum rtw8852bx_pmac_mode { 14 NONE_TEST, 15 PKTS_TX, 16 PKTS_RX, 17 CONT_TX 18 }; 19 20 struct rtw8852bx_u_efuse { 21 u8 rsvd[0x88]; 22 u8 mac_addr[ETH_ALEN]; 23 }; 24 25 struct rtw8852bx_e_efuse { 26 u8 mac_addr[ETH_ALEN]; 27 }; 28 29 struct rtw8852bx_tssi_offset { 30 u8 cck_tssi[TSSI_CCK_CH_GROUP_NUM]; 31 u8 bw40_tssi[TSSI_MCS_2G_CH_GROUP_NUM]; 32 u8 rsvd[7]; 33 u8 bw40_1s_tssi_5g[TSSI_MCS_5G_CH_GROUP_NUM]; 34 } __packed; 35 36 struct rtw8852bx_efuse { 37 u8 rsvd[0x210]; 38 struct rtw8852bx_tssi_offset path_a_tssi; 39 u8 rsvd1[10]; 40 struct rtw8852bx_tssi_offset path_b_tssi; 41 u8 rsvd2[94]; 42 u8 channel_plan; 43 u8 xtal_k; 44 u8 rsvd3; 45 u8 iqk_lck; 46 u8 rsvd4[5]; 47 u8 reg_setting:2; 48 u8 tx_diversity:1; 49 u8 rx_diversity:2; 50 u8 ac_mode:1; 51 u8 module_type:2; 52 u8 rsvd5; 53 u8 shared_ant:1; 54 u8 coex_type:3; 55 u8 ant_iso:1; 56 u8 radio_on_off:1; 57 u8 rsvd6:2; 58 u8 eeprom_version; 59 u8 customer_id; 60 u8 tx_bb_swing_2g; 61 u8 tx_bb_swing_5g; 62 u8 tx_cali_pwr_trk_mode; 63 u8 trx_path_selection; 64 u8 rfe_type; 65 u8 country_code[2]; 66 u8 rsvd7[3]; 67 u8 path_a_therm; 68 u8 path_b_therm; 69 u8 rsvd8[2]; 70 u8 rx_gain_2g_ofdm; 71 u8 rsvd9; 72 u8 rx_gain_2g_cck; 73 u8 rsvd10; 74 u8 rx_gain_5g_low; 75 u8 rsvd11; 76 u8 rx_gain_5g_mid; 77 u8 rsvd12; 78 u8 rx_gain_5g_high; 79 u8 rsvd13[35]; 80 u8 path_a_cck_pwr_idx[6]; 81 u8 path_a_bw40_1tx_pwr_idx[5]; 82 u8 path_a_ofdm_1tx_pwr_idx_diff:4; 83 u8 path_a_bw20_1tx_pwr_idx_diff:4; 84 u8 path_a_bw20_2tx_pwr_idx_diff:4; 85 u8 path_a_bw40_2tx_pwr_idx_diff:4; 86 u8 path_a_cck_2tx_pwr_idx_diff:4; 87 u8 path_a_ofdm_2tx_pwr_idx_diff:4; 88 u8 rsvd14[0xf2]; 89 union { 90 struct rtw8852bx_u_efuse u; 91 struct rtw8852bx_e_efuse e; 92 }; 93 } __packed; 94 95 struct rtw8852bx_bb_pmac_info { 96 u8 en_pmac_tx:1; 97 u8 is_cck:1; 98 u8 mode:3; 99 u8 rsvd:3; 100 u16 tx_cnt; 101 u16 period; 102 u16 tx_time; 103 u8 duty_cycle; 104 }; 105 106 struct rtw8852bx_bb_tssi_bak { 107 u8 tx_path; 108 u8 rx_path; 109 u32 p0_rfmode; 110 u32 p0_rfmode_ftm; 111 u32 p1_rfmode; 112 u32 p1_rfmode_ftm; 113 s16 tx_pwr; /* S9 */ 114 }; 115 116 struct rtw8852bx_info { 117 int (*mac_enable_bb_rf)(struct rtw89_dev *rtwdev); 118 int (*mac_disable_bb_rf)(struct rtw89_dev *rtwdev); 119 void (*bb_sethw)(struct rtw89_dev *rtwdev); 120 void (*bb_reset_all)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 121 void (*bb_cfg_txrx_path)(struct rtw89_dev *rtwdev); 122 void (*bb_cfg_tx_path)(struct rtw89_dev *rtwdev, u8 tx_path); 123 void (*bb_ctrl_rx_path)(struct rtw89_dev *rtwdev, 124 enum rtw89_rf_path_bit rx_path, 125 const struct rtw89_chan *chan); 126 void (*bb_set_plcp_tx)(struct rtw89_dev *rtwdev); 127 void (*bb_set_power)(struct rtw89_dev *rtwdev, s16 pwr_dbm, 128 enum rtw89_phy_idx idx); 129 void (*bb_set_pmac_pkt_tx)(struct rtw89_dev *rtwdev, u8 enable, 130 u16 tx_cnt, u16 period, u16 tx_time, 131 enum rtw89_phy_idx idx, const struct rtw89_chan *chan); 132 void (*bb_backup_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 133 struct rtw8852bx_bb_tssi_bak *bak); 134 void (*bb_restore_tssi)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 135 const struct rtw8852bx_bb_tssi_bak *bak); 136 void (*bb_tx_mode_switch)(struct rtw89_dev *rtwdev, 137 enum rtw89_phy_idx idx, u8 mode); 138 void (*set_channel_mac)(struct rtw89_dev *rtwdev, 139 const struct rtw89_chan *chan, u8 mac_idx); 140 void (*set_channel_bb)(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 141 enum rtw89_phy_idx phy_idx); 142 void (*ctrl_nbtg_bt_tx)(struct rtw89_dev *rtwdev, bool en, 143 enum rtw89_phy_idx phy_idx); 144 void (*ctrl_btg_bt_rx)(struct rtw89_dev *rtwdev, bool en, 145 enum rtw89_phy_idx phy_idx); 146 void (*query_ppdu)(struct rtw89_dev *rtwdev, 147 struct rtw89_rx_phy_ppdu *phy_ppdu, 148 struct ieee80211_rx_status *status); 149 void (*convert_rpl_to_rssi)(struct rtw89_dev *rtwdev, 150 struct rtw89_rx_phy_ppdu *phy_ppdu); 151 int (*read_efuse)(struct rtw89_dev *rtwdev, u8 *log_map, 152 enum rtw89_efuse_block block); 153 int (*read_phycap)(struct rtw89_dev *rtwdev, u8 *phycap_map); 154 void (*power_trim)(struct rtw89_dev *rtwdev); 155 void (*set_txpwr)(struct rtw89_dev *rtwdev, 156 const struct rtw89_chan *chan, 157 enum rtw89_phy_idx phy_idx); 158 void (*set_txpwr_ctrl)(struct rtw89_dev *rtwdev, 159 enum rtw89_phy_idx phy_idx); 160 int (*init_txpwr_unit)(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx); 161 void (*set_txpwr_ul_tb_offset)(struct rtw89_dev *rtwdev, 162 s8 pw_ofst, enum rtw89_mac_idx mac_idx); 163 u8 (*get_thermal)(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path); 164 void (*adc_cfg)(struct rtw89_dev *rtwdev, u8 bw, u8 path); 165 void (*btc_init_cfg)(struct rtw89_dev *rtwdev); 166 void (*btc_set_wl_pri)(struct rtw89_dev *rtwdev, u8 map, bool state); 167 s8 (*btc_get_bt_rssi)(struct rtw89_dev *rtwdev, s8 val); 168 void (*btc_update_bt_cnt)(struct rtw89_dev *rtwdev); 169 void (*btc_wl_s1_standby)(struct rtw89_dev *rtwdev, bool state); 170 void (*btc_set_wl_rx_gain)(struct rtw89_dev *rtwdev, u32 level); 171 }; 172 173 extern const struct rtw8852bx_info rtw8852bx_info; 174 175 static inline rtw8852bx_mac_enable_bb_rf(struct rtw89_dev * rtwdev)176 int rtw8852bx_mac_enable_bb_rf(struct rtw89_dev *rtwdev) 177 { 178 return rtw8852bx_info.mac_enable_bb_rf(rtwdev); 179 } 180 181 static inline rtw8852bx_mac_disable_bb_rf(struct rtw89_dev * rtwdev)182 int rtw8852bx_mac_disable_bb_rf(struct rtw89_dev *rtwdev) 183 { 184 return rtw8852bx_info.mac_disable_bb_rf(rtwdev); 185 } 186 187 static inline rtw8852bx_bb_sethw(struct rtw89_dev * rtwdev)188 void rtw8852bx_bb_sethw(struct rtw89_dev *rtwdev) 189 { 190 rtw8852bx_info.bb_sethw(rtwdev); 191 } 192 193 static inline rtw8852bx_bb_reset_all(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)194 void rtw8852bx_bb_reset_all(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 195 { 196 rtw8852bx_info.bb_reset_all(rtwdev, phy_idx); 197 } 198 199 static inline rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev * rtwdev)200 void rtw8852bx_bb_cfg_txrx_path(struct rtw89_dev *rtwdev) 201 { 202 rtw8852bx_info.bb_cfg_txrx_path(rtwdev); 203 } 204 205 static inline rtw8852bx_bb_cfg_tx_path(struct rtw89_dev * rtwdev,u8 tx_path)206 void rtw8852bx_bb_cfg_tx_path(struct rtw89_dev *rtwdev, u8 tx_path) 207 { 208 rtw8852bx_info.bb_cfg_tx_path(rtwdev, tx_path); 209 } 210 211 static inline rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev * rtwdev,enum rtw89_rf_path_bit rx_path,const struct rtw89_chan * chan)212 void rtw8852bx_bb_ctrl_rx_path(struct rtw89_dev *rtwdev, 213 enum rtw89_rf_path_bit rx_path, 214 const struct rtw89_chan *chan) 215 { 216 rtw8852bx_info.bb_ctrl_rx_path(rtwdev, rx_path, chan); 217 } 218 219 static inline rtw8852bx_bb_set_plcp_tx(struct rtw89_dev * rtwdev)220 void rtw8852bx_bb_set_plcp_tx(struct rtw89_dev *rtwdev) 221 { 222 rtw8852bx_info.bb_set_plcp_tx(rtwdev); 223 } 224 225 static inline rtw8852bx_bb_set_power(struct rtw89_dev * rtwdev,s16 pwr_dbm,enum rtw89_phy_idx idx)226 void rtw8852bx_bb_set_power(struct rtw89_dev *rtwdev, s16 pwr_dbm, 227 enum rtw89_phy_idx idx) 228 { 229 rtw8852bx_info.bb_set_power(rtwdev, pwr_dbm, idx); 230 } 231 232 static inline rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev * rtwdev,u8 enable,u16 tx_cnt,u16 period,u16 tx_time,enum rtw89_phy_idx idx,const struct rtw89_chan * chan)233 void rtw8852bx_bb_set_pmac_pkt_tx(struct rtw89_dev *rtwdev, u8 enable, 234 u16 tx_cnt, u16 period, u16 tx_time, 235 enum rtw89_phy_idx idx, const struct rtw89_chan *chan) 236 { 237 rtw8852bx_info.bb_set_pmac_pkt_tx(rtwdev, enable, tx_cnt, period, tx_time, idx, 238 chan); 239 } 240 241 static inline rtw8852bx_bb_backup_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,struct rtw8852bx_bb_tssi_bak * bak)242 void rtw8852bx_bb_backup_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 243 struct rtw8852bx_bb_tssi_bak *bak) 244 { 245 rtw8852bx_info.bb_backup_tssi(rtwdev, idx, bak); 246 } 247 248 static inline rtw8852bx_bb_restore_tssi(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,const struct rtw8852bx_bb_tssi_bak * bak)249 void rtw8852bx_bb_restore_tssi(struct rtw89_dev *rtwdev, enum rtw89_phy_idx idx, 250 const struct rtw8852bx_bb_tssi_bak *bak) 251 { 252 rtw8852bx_info.bb_restore_tssi(rtwdev, idx, bak); 253 } 254 255 static inline rtw8852bx_bb_tx_mode_switch(struct rtw89_dev * rtwdev,enum rtw89_phy_idx idx,u8 mode)256 void rtw8852bx_bb_tx_mode_switch(struct rtw89_dev *rtwdev, 257 enum rtw89_phy_idx idx, u8 mode) 258 { 259 rtw8852bx_info.bb_tx_mode_switch(rtwdev, idx, mode); 260 } 261 262 static inline rtw8852bx_set_channel_mac(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,u8 mac_idx)263 void rtw8852bx_set_channel_mac(struct rtw89_dev *rtwdev, 264 const struct rtw89_chan *chan, u8 mac_idx) 265 { 266 rtw8852bx_info.set_channel_mac(rtwdev, chan, mac_idx); 267 } 268 269 static inline rtw8852bx_set_channel_bb(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)270 void rtw8852bx_set_channel_bb(struct rtw89_dev *rtwdev, const struct rtw89_chan *chan, 271 enum rtw89_phy_idx phy_idx) 272 { 273 rtw8852bx_info.set_channel_bb(rtwdev, chan, phy_idx); 274 } 275 276 static inline rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)277 void rtw8852bx_ctrl_nbtg_bt_tx(struct rtw89_dev *rtwdev, bool en, 278 enum rtw89_phy_idx phy_idx) 279 { 280 rtw8852bx_info.ctrl_nbtg_bt_tx(rtwdev, en, phy_idx); 281 } 282 283 static inline rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev * rtwdev,bool en,enum rtw89_phy_idx phy_idx)284 void rtw8852bx_ctrl_btg_bt_rx(struct rtw89_dev *rtwdev, bool en, 285 enum rtw89_phy_idx phy_idx) 286 { 287 rtw8852bx_info.ctrl_btg_bt_rx(rtwdev, en, phy_idx); 288 } 289 290 static inline rtw8852bx_query_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct ieee80211_rx_status * status)291 void rtw8852bx_query_ppdu(struct rtw89_dev *rtwdev, 292 struct rtw89_rx_phy_ppdu *phy_ppdu, 293 struct ieee80211_rx_status *status) 294 { 295 rtw8852bx_info.query_ppdu(rtwdev, phy_ppdu, status); 296 } 297 298 static inline rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)299 void rtw8852bx_convert_rpl_to_rssi(struct rtw89_dev *rtwdev, 300 struct rtw89_rx_phy_ppdu *phy_ppdu) 301 { 302 rtw8852bx_info.convert_rpl_to_rssi(rtwdev, phy_ppdu); 303 } 304 305 static inline rtw8852bx_read_efuse(struct rtw89_dev * rtwdev,u8 * log_map,enum rtw89_efuse_block block)306 int rtw8852bx_read_efuse(struct rtw89_dev *rtwdev, u8 *log_map, 307 enum rtw89_efuse_block block) 308 { 309 return rtw8852bx_info.read_efuse(rtwdev, log_map, block); 310 } 311 312 static inline rtw8852bx_read_phycap(struct rtw89_dev * rtwdev,u8 * phycap_map)313 int rtw8852bx_read_phycap(struct rtw89_dev *rtwdev, u8 *phycap_map) 314 { 315 return rtw8852bx_info.read_phycap(rtwdev, phycap_map); 316 } 317 318 static inline rtw8852bx_power_trim(struct rtw89_dev * rtwdev)319 void rtw8852bx_power_trim(struct rtw89_dev *rtwdev) 320 { 321 rtw8852bx_info.power_trim(rtwdev); 322 } 323 324 static inline rtw8852bx_set_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)325 void rtw8852bx_set_txpwr(struct rtw89_dev *rtwdev, 326 const struct rtw89_chan *chan, 327 enum rtw89_phy_idx phy_idx) 328 { 329 rtw8852bx_info.set_txpwr(rtwdev, chan, phy_idx); 330 } 331 332 static inline rtw8852bx_set_txpwr_ctrl(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)333 void rtw8852bx_set_txpwr_ctrl(struct rtw89_dev *rtwdev, 334 enum rtw89_phy_idx phy_idx) 335 { 336 rtw8852bx_info.set_txpwr_ctrl(rtwdev, phy_idx); 337 } 338 339 static inline rtw8852bx_init_txpwr_unit(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)340 int rtw8852bx_init_txpwr_unit(struct rtw89_dev *rtwdev, enum rtw89_phy_idx phy_idx) 341 { 342 return rtw8852bx_info.init_txpwr_unit(rtwdev, phy_idx); 343 } 344 345 static inline rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,s8 pw_ofst,enum rtw89_mac_idx mac_idx)346 void rtw8852bx_set_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev, 347 s8 pw_ofst, enum rtw89_mac_idx mac_idx) 348 { 349 rtw8852bx_info.set_txpwr_ul_tb_offset(rtwdev, pw_ofst, mac_idx); 350 } 351 352 static inline rtw8852bx_get_thermal(struct rtw89_dev * rtwdev,enum rtw89_rf_path rf_path)353 u8 rtw8852bx_get_thermal(struct rtw89_dev *rtwdev, enum rtw89_rf_path rf_path) 354 { 355 return rtw8852bx_info.get_thermal(rtwdev, rf_path); 356 } 357 358 static inline rtw8852bx_adc_cfg(struct rtw89_dev * rtwdev,u8 bw,u8 path)359 void rtw8852bx_adc_cfg(struct rtw89_dev *rtwdev, u8 bw, u8 path) 360 { 361 rtw8852bx_info.adc_cfg(rtwdev, bw, path); 362 } 363 364 static inline rtw8852bx_btc_init_cfg(struct rtw89_dev * rtwdev)365 void rtw8852bx_btc_init_cfg(struct rtw89_dev *rtwdev) 366 { 367 rtw8852bx_info.btc_init_cfg(rtwdev); 368 } 369 370 static inline rtw8852bx_btc_set_wl_pri(struct rtw89_dev * rtwdev,u8 map,bool state)371 void rtw8852bx_btc_set_wl_pri(struct rtw89_dev *rtwdev, u8 map, bool state) 372 { 373 rtw8852bx_info.btc_set_wl_pri(rtwdev, map, state); 374 } 375 376 static inline rtw8852bx_btc_get_bt_rssi(struct rtw89_dev * rtwdev,s8 val)377 s8 rtw8852bx_btc_get_bt_rssi(struct rtw89_dev *rtwdev, s8 val) 378 { 379 return rtw8852bx_info.btc_get_bt_rssi(rtwdev, val); 380 } 381 382 static inline rtw8852bx_btc_update_bt_cnt(struct rtw89_dev * rtwdev)383 void rtw8852bx_btc_update_bt_cnt(struct rtw89_dev *rtwdev) 384 { 385 rtw8852bx_info.btc_update_bt_cnt(rtwdev); 386 } 387 388 static inline rtw8852bx_btc_wl_s1_standby(struct rtw89_dev * rtwdev,bool state)389 void rtw8852bx_btc_wl_s1_standby(struct rtw89_dev *rtwdev, bool state) 390 { 391 rtw8852bx_info.btc_wl_s1_standby(rtwdev, state); 392 } 393 394 static inline rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev * rtwdev,u32 level)395 void rtw8852bx_btc_set_wl_rx_gain(struct rtw89_dev *rtwdev, u32 level) 396 { 397 rtw8852bx_info.btc_set_wl_rx_gain(rtwdev, level); 398 } 399 400 #endif 401