1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 2009-2012 Realtek Corporation.*/
3
4 #include "../wifi.h"
5 #include "../efuse.h"
6 #include "../base.h"
7 #include "../regd.h"
8 #include "../cam.h"
9 #include "../ps.h"
10 #include "../pci.h"
11 #include "reg.h"
12 #include "def.h"
13 #include "phy.h"
14 #include "../rtl8723com/phy_common.h"
15 #include "dm.h"
16 #include "../rtl8723com/dm_common.h"
17 #include "fw.h"
18 #include "../rtl8723com/fw_common.h"
19 #include "led.h"
20 #include "hw.h"
21 #include "../pwrseqcmd.h"
22 #include "pwrseq.h"
23 #include "btc.h"
24
25 #define LLT_CONFIG 5
26
_rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw * hw,u8 set_bits,u8 clear_bits)27 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw *hw,
28 u8 set_bits, u8 clear_bits)
29 {
30 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
31 struct rtl_priv *rtlpriv = rtl_priv(hw);
32
33 rtlpci->reg_bcn_ctrl_val |= set_bits;
34 rtlpci->reg_bcn_ctrl_val &= ~clear_bits;
35
36 rtl_write_byte(rtlpriv, REG_BCN_CTRL, (u8) rtlpci->reg_bcn_ctrl_val);
37 }
38
_rtl8723e_stop_tx_beacon(struct ieee80211_hw * hw)39 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw *hw)
40 {
41 struct rtl_priv *rtlpriv = rtl_priv(hw);
42 u8 tmp1byte;
43
44 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
45 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte & (~BIT(6)));
46 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0x64);
47 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
48 tmp1byte &= ~(BIT(0));
49 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
50 }
51
_rtl8723e_resume_tx_beacon(struct ieee80211_hw * hw)52 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw *hw)
53 {
54 struct rtl_priv *rtlpriv = rtl_priv(hw);
55 u8 tmp1byte;
56
57 tmp1byte = rtl_read_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2);
58 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2, tmp1byte | BIT(6));
59 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
60 tmp1byte = rtl_read_byte(rtlpriv, REG_TBTT_PROHIBIT + 2);
61 tmp1byte |= BIT(1);
62 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 2, tmp1byte);
63 }
64
_rtl8723e_enable_bcn_sub_func(struct ieee80211_hw * hw)65 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw *hw)
66 {
67 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(1));
68 }
69
_rtl8723e_disable_bcn_sub_func(struct ieee80211_hw * hw)70 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw *hw)
71 {
72 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(1), 0);
73 }
74
rtl8723e_get_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)75 void rtl8723e_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
76 {
77 struct rtl_priv *rtlpriv = rtl_priv(hw);
78 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
79 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
80
81 switch (variable) {
82 case HW_VAR_RCR:
83 *((u32 *)(val)) = rtlpci->receive_config;
84 break;
85 case HW_VAR_RF_STATE:
86 *((enum rf_pwrstate *)(val)) = ppsc->rfpwr_state;
87 break;
88 case HW_VAR_FWLPS_RF_ON:{
89 enum rf_pwrstate rfstate;
90 u32 val_rcr;
91
92 rtlpriv->cfg->ops->get_hw_reg(hw,
93 HW_VAR_RF_STATE,
94 (u8 *)(&rfstate));
95 if (rfstate == ERFOFF) {
96 *((bool *)(val)) = true;
97 } else {
98 val_rcr = rtl_read_dword(rtlpriv, REG_RCR);
99 val_rcr &= 0x00070000;
100 if (val_rcr)
101 *((bool *)(val)) = false;
102 else
103 *((bool *)(val)) = true;
104 }
105 break;
106 }
107 case HW_VAR_FW_PSMODE_STATUS:
108 *((bool *)(val)) = ppsc->fw_current_inpsmode;
109 break;
110 case HW_VAR_CORRECT_TSF:{
111 u64 tsf;
112 u32 *ptsf_low = (u32 *)&tsf;
113 u32 *ptsf_high = ((u32 *)&tsf) + 1;
114
115 *ptsf_high = rtl_read_dword(rtlpriv, (REG_TSFTR + 4));
116 *ptsf_low = rtl_read_dword(rtlpriv, REG_TSFTR);
117
118 *((u64 *)(val)) = tsf;
119
120 break;
121 }
122 case HAL_DEF_WOWLAN:
123 break;
124 default:
125 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
126 "switch case %#x not processed\n", variable);
127 break;
128 }
129 }
130
rtl8723e_set_hw_reg(struct ieee80211_hw * hw,u8 variable,u8 * val)131 void rtl8723e_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
132 {
133 struct rtl_priv *rtlpriv = rtl_priv(hw);
134 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
135 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
136 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
137 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
138 u8 idx;
139
140 switch (variable) {
141 case HW_VAR_ETHER_ADDR:{
142 for (idx = 0; idx < ETH_ALEN; idx++) {
143 rtl_write_byte(rtlpriv, (REG_MACID + idx),
144 val[idx]);
145 }
146 break;
147 }
148 case HW_VAR_BASIC_RATE:{
149 u16 b_rate_cfg = ((u16 *)val)[0];
150 u8 rate_index = 0;
151
152 b_rate_cfg = b_rate_cfg & 0x15f;
153 b_rate_cfg |= 0x01;
154 rtl_write_byte(rtlpriv, REG_RRSR, b_rate_cfg & 0xff);
155 rtl_write_byte(rtlpriv, REG_RRSR + 1,
156 (b_rate_cfg >> 8) & 0xff);
157 while (b_rate_cfg > 0x1) {
158 b_rate_cfg = (b_rate_cfg >> 1);
159 rate_index++;
160 }
161 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL,
162 rate_index);
163 break;
164 }
165 case HW_VAR_BSSID:{
166 for (idx = 0; idx < ETH_ALEN; idx++) {
167 rtl_write_byte(rtlpriv, (REG_BSSID + idx),
168 val[idx]);
169 }
170 break;
171 }
172 case HW_VAR_SIFS:{
173 rtl_write_byte(rtlpriv, REG_SIFS_CTX + 1, val[0]);
174 rtl_write_byte(rtlpriv, REG_SIFS_TRX + 1, val[1]);
175
176 rtl_write_byte(rtlpriv, REG_SPEC_SIFS + 1, val[0]);
177 rtl_write_byte(rtlpriv, REG_MAC_SPEC_SIFS + 1, val[0]);
178
179 if (!mac->ht_enable)
180 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
181 0x0e0e);
182 else
183 rtl_write_word(rtlpriv, REG_RESP_SIFS_OFDM,
184 *((u16 *)val));
185 break;
186 }
187 case HW_VAR_SLOT_TIME:{
188 u8 e_aci;
189
190 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
191 "HW_VAR_SLOT_TIME %x\n", val[0]);
192
193 rtl_write_byte(rtlpriv, REG_SLOT, val[0]);
194
195 for (e_aci = 0; e_aci < AC_MAX; e_aci++) {
196 rtlpriv->cfg->ops->set_hw_reg(hw,
197 HW_VAR_AC_PARAM,
198 (u8 *)(&e_aci));
199 }
200 break;
201 }
202 case HW_VAR_ACK_PREAMBLE:{
203 u8 reg_tmp;
204 u8 short_preamble = (bool)(*(u8 *)val);
205
206 reg_tmp = (mac->cur_40_prime_sc) << 5;
207 if (short_preamble)
208 reg_tmp |= 0x80;
209
210 rtl_write_byte(rtlpriv, REG_RRSR + 2, reg_tmp);
211 break;
212 }
213 case HW_VAR_AMPDU_MIN_SPACE:{
214 u8 min_spacing_to_set;
215
216 min_spacing_to_set = *((u8 *)val);
217 if (min_spacing_to_set <= 7) {
218
219 mac->min_space_cfg = ((mac->min_space_cfg &
220 0xf8) |
221 min_spacing_to_set);
222
223 *val = min_spacing_to_set;
224
225 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
226 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
227 mac->min_space_cfg);
228
229 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
230 mac->min_space_cfg);
231 }
232 break;
233 }
234 case HW_VAR_SHORTGI_DENSITY:{
235 u8 density_to_set;
236
237 density_to_set = *((u8 *)val);
238 mac->min_space_cfg |= (density_to_set << 3);
239
240 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
241 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
242 mac->min_space_cfg);
243
244 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE,
245 mac->min_space_cfg);
246
247 break;
248 }
249 case HW_VAR_AMPDU_FACTOR:{
250 u8 regtoset_normal[4] = { 0x41, 0xa8, 0x72, 0xb9 };
251 u8 regtoset_bt[4] = {0x31, 0x74, 0x42, 0x97};
252 u8 factor_toset;
253 u8 *p_regtoset = NULL;
254 u8 index = 0;
255
256 if ((rtlpriv->btcoexist.bt_coexistence) &&
257 (rtlpriv->btcoexist.bt_coexist_type ==
258 BT_CSR_BC4))
259 p_regtoset = regtoset_bt;
260 else
261 p_regtoset = regtoset_normal;
262
263 factor_toset = *((u8 *)val);
264 if (factor_toset <= 3) {
265 factor_toset = (1 << (factor_toset + 2));
266 if (factor_toset > 0xf)
267 factor_toset = 0xf;
268
269 for (index = 0; index < 4; index++) {
270 if ((p_regtoset[index] & 0xf0) >
271 (factor_toset << 4))
272 p_regtoset[index] =
273 (p_regtoset[index] & 0x0f) |
274 (factor_toset << 4);
275
276 if ((p_regtoset[index] & 0x0f) >
277 factor_toset)
278 p_regtoset[index] =
279 (p_regtoset[index] & 0xf0) |
280 (factor_toset);
281
282 rtl_write_byte(rtlpriv,
283 (REG_AGGLEN_LMT + index),
284 p_regtoset[index]);
285 }
286
287 rtl_dbg(rtlpriv, COMP_MLME, DBG_LOUD,
288 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
289 factor_toset);
290 }
291 break;
292 }
293 case HW_VAR_AC_PARAM:{
294 u8 e_aci = *((u8 *)val);
295
296 rtl8723_dm_init_edca_turbo(hw);
297
298 if (rtlpci->acm_method != EACMWAY2_SW)
299 rtlpriv->cfg->ops->set_hw_reg(hw,
300 HW_VAR_ACM_CTRL,
301 (u8 *)(&e_aci));
302 break;
303 }
304 case HW_VAR_ACM_CTRL:{
305 u8 e_aci = *((u8 *)val);
306 union aci_aifsn *p_aci_aifsn =
307 (union aci_aifsn *)(&mac->ac[0].aifs);
308 u8 acm = p_aci_aifsn->f.acm;
309 u8 acm_ctrl = rtl_read_byte(rtlpriv, REG_ACMHWCTRL);
310
311 acm_ctrl =
312 acm_ctrl | ((rtlpci->acm_method == 2) ? 0x0 : 0x1);
313
314 if (acm) {
315 switch (e_aci) {
316 case AC0_BE:
317 acm_ctrl |= ACMHW_BEQEN;
318 break;
319 case AC2_VI:
320 acm_ctrl |= ACMHW_VIQEN;
321 break;
322 case AC3_VO:
323 acm_ctrl |= ACMHW_VOQEN;
324 break;
325 default:
326 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
327 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
328 acm);
329 break;
330 }
331 } else {
332 switch (e_aci) {
333 case AC0_BE:
334 acm_ctrl &= (~ACMHW_BEQEN);
335 break;
336 case AC2_VI:
337 acm_ctrl &= (~ACMHW_VIQEN);
338 break;
339 case AC3_VO:
340 acm_ctrl &= (~ACMHW_VOQEN);
341 break;
342 default:
343 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
344 "switch case %#x not processed\n",
345 e_aci);
346 break;
347 }
348 }
349
350 rtl_dbg(rtlpriv, COMP_QOS, DBG_TRACE,
351 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
352 acm_ctrl);
353 rtl_write_byte(rtlpriv, REG_ACMHWCTRL, acm_ctrl);
354 break;
355 }
356 case HW_VAR_RCR:{
357 rtl_write_dword(rtlpriv, REG_RCR, ((u32 *)(val))[0]);
358 rtlpci->receive_config = ((u32 *)(val))[0];
359 break;
360 }
361 case HW_VAR_RETRY_LIMIT:{
362 u8 retry_limit = ((u8 *)(val))[0];
363
364 rtl_write_word(rtlpriv, REG_RL,
365 retry_limit << RETRY_LIMIT_SHORT_SHIFT |
366 retry_limit << RETRY_LIMIT_LONG_SHIFT);
367 break;
368 }
369 case HW_VAR_DUAL_TSF_RST:
370 rtl_write_byte(rtlpriv, REG_DUAL_TSF_RST, (BIT(0) | BIT(1)));
371 break;
372 case HW_VAR_EFUSE_BYTES:
373 rtlefuse->efuse_usedbytes = *((u16 *)val);
374 break;
375 case HW_VAR_EFUSE_USAGE:
376 rtlefuse->efuse_usedpercentage = *((u8 *)val);
377 break;
378 case HW_VAR_IO_CMD:
379 rtl8723e_phy_set_io_cmd(hw, (*(enum io_type *)val));
380 break;
381 case HW_VAR_WPA_CONFIG:
382 rtl_write_byte(rtlpriv, REG_SECCFG, *((u8 *)val));
383 break;
384 case HW_VAR_SET_RPWM:{
385 u8 rpwm_val;
386
387 rpwm_val = rtl_read_byte(rtlpriv, REG_PCIE_HRPWM);
388 udelay(1);
389
390 if (rpwm_val & BIT(7)) {
391 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
392 (*(u8 *)val));
393 } else {
394 rtl_write_byte(rtlpriv, REG_PCIE_HRPWM,
395 ((*(u8 *)val) | BIT(7)));
396 }
397
398 break;
399 }
400 case HW_VAR_H2C_FW_PWRMODE:{
401 u8 psmode = (*(u8 *)val);
402
403 if (psmode != FW_PS_ACTIVE_MODE)
404 rtl8723e_dm_rf_saving(hw, true);
405
406 rtl8723e_set_fw_pwrmode_cmd(hw, (*(u8 *)val));
407 break;
408 }
409 case HW_VAR_FW_PSMODE_STATUS:
410 ppsc->fw_current_inpsmode = *((bool *)val);
411 break;
412 case HW_VAR_H2C_FW_JOINBSSRPT:{
413 u8 mstatus = (*(u8 *)val);
414 u8 tmp_regcr, tmp_reg422;
415 bool b_recover = false;
416
417 if (mstatus == RT_MEDIA_CONNECT) {
418 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_AID,
419 NULL);
420
421 tmp_regcr = rtl_read_byte(rtlpriv, REG_CR + 1);
422 rtl_write_byte(rtlpriv, REG_CR + 1,
423 (tmp_regcr | BIT(0)));
424
425 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
426 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
427
428 tmp_reg422 =
429 rtl_read_byte(rtlpriv,
430 REG_FWHW_TXQ_CTRL + 2);
431 if (tmp_reg422 & BIT(6))
432 b_recover = true;
433 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 2,
434 tmp_reg422 & (~BIT(6)));
435
436 rtl8723e_set_fw_rsvdpagepkt(hw, 0);
437
438 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
439 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
440
441 if (b_recover) {
442 rtl_write_byte(rtlpriv,
443 REG_FWHW_TXQ_CTRL + 2,
444 tmp_reg422);
445 }
446
447 rtl_write_byte(rtlpriv, REG_CR + 1,
448 (tmp_regcr & ~(BIT(0))));
449 }
450 rtl8723e_set_fw_joinbss_report_cmd(hw, (*(u8 *)val));
451
452 break;
453 }
454 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD:{
455 rtl8723e_set_p2p_ps_offload_cmd(hw, (*(u8 *)val));
456 break;
457 }
458 case HW_VAR_AID:{
459 u16 u2btmp;
460
461 u2btmp = rtl_read_word(rtlpriv, REG_BCN_PSR_RPT);
462 u2btmp &= 0xC000;
463 rtl_write_word(rtlpriv, REG_BCN_PSR_RPT,
464 (u2btmp | mac->assoc_id));
465
466 break;
467 }
468 case HW_VAR_CORRECT_TSF:{
469 u8 btype_ibss = ((u8 *)(val))[0];
470
471 if (btype_ibss)
472 _rtl8723e_stop_tx_beacon(hw);
473
474 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(3));
475
476 rtl_write_dword(rtlpriv, REG_TSFTR,
477 (u32)(mac->tsf & 0xffffffff));
478 rtl_write_dword(rtlpriv, REG_TSFTR + 4,
479 (u32)((mac->tsf >> 32) & 0xffffffff));
480
481 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(3), 0);
482
483 if (btype_ibss)
484 _rtl8723e_resume_tx_beacon(hw);
485
486 break;
487 }
488 case HW_VAR_FW_LPS_ACTION:{
489 bool b_enter_fwlps = *((bool *)val);
490 u8 rpwm_val, fw_pwrmode;
491 bool fw_current_inps;
492
493 if (b_enter_fwlps) {
494 rpwm_val = 0x02; /* RF off */
495 fw_current_inps = true;
496 rtlpriv->cfg->ops->set_hw_reg(hw,
497 HW_VAR_FW_PSMODE_STATUS,
498 (u8 *)(&fw_current_inps));
499 rtlpriv->cfg->ops->set_hw_reg(hw,
500 HW_VAR_H2C_FW_PWRMODE,
501 (u8 *)(&ppsc->fwctrl_psmode));
502
503 rtlpriv->cfg->ops->set_hw_reg(hw,
504 HW_VAR_SET_RPWM,
505 (u8 *)(&rpwm_val));
506 } else {
507 rpwm_val = 0x0C; /* RF on */
508 fw_pwrmode = FW_PS_ACTIVE_MODE;
509 fw_current_inps = false;
510 rtlpriv->cfg->ops->set_hw_reg(hw,
511 HW_VAR_SET_RPWM,
512 (u8 *)(&rpwm_val));
513 rtlpriv->cfg->ops->set_hw_reg(hw,
514 HW_VAR_H2C_FW_PWRMODE,
515 (u8 *)(&fw_pwrmode));
516
517 rtlpriv->cfg->ops->set_hw_reg(hw,
518 HW_VAR_FW_PSMODE_STATUS,
519 (u8 *)(&fw_current_inps));
520 }
521 break;
522 }
523 default:
524 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
525 "switch case %#x not processed\n", variable);
526 break;
527 }
528 }
529
_rtl8723e_llt_write(struct ieee80211_hw * hw,u32 address,u32 data)530 static bool _rtl8723e_llt_write(struct ieee80211_hw *hw, u32 address, u32 data)
531 {
532 struct rtl_priv *rtlpriv = rtl_priv(hw);
533 bool status = true;
534 long count = 0;
535 u32 value = _LLT_INIT_ADDR(address) |
536 _LLT_INIT_DATA(data) | _LLT_OP(_LLT_WRITE_ACCESS);
537
538 rtl_write_dword(rtlpriv, REG_LLT_INIT, value);
539
540 do {
541 value = rtl_read_dword(rtlpriv, REG_LLT_INIT);
542 if (_LLT_NO_ACTIVE == _LLT_OP_VALUE(value))
543 break;
544
545 if (count > POLLING_LLT_THRESHOLD) {
546 pr_err("Failed to polling write LLT done at address %d!\n",
547 address);
548 status = false;
549 break;
550 }
551 } while (++count);
552
553 return status;
554 }
555
_rtl8723e_llt_table_init(struct ieee80211_hw * hw)556 static bool _rtl8723e_llt_table_init(struct ieee80211_hw *hw)
557 {
558 struct rtl_priv *rtlpriv = rtl_priv(hw);
559 unsigned short i;
560 u8 txpktbuf_bndy;
561 u8 maxpage;
562 bool status;
563 u8 ubyte;
564
565 #if LLT_CONFIG == 1
566 maxpage = 255;
567 txpktbuf_bndy = 252;
568 #elif LLT_CONFIG == 2
569 maxpage = 127;
570 txpktbuf_bndy = 124;
571 #elif LLT_CONFIG == 3
572 maxpage = 255;
573 txpktbuf_bndy = 174;
574 #elif LLT_CONFIG == 4
575 maxpage = 255;
576 txpktbuf_bndy = 246;
577 #elif LLT_CONFIG == 5
578 maxpage = 255;
579 txpktbuf_bndy = 246;
580 #endif
581
582 rtl_write_byte(rtlpriv, REG_CR, 0x8B);
583
584 #if LLT_CONFIG == 1
585 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x1c);
586 rtl_write_dword(rtlpriv, REG_RQPN, 0x80a71c1c);
587 #elif LLT_CONFIG == 2
588 rtl_write_dword(rtlpriv, REG_RQPN, 0x845B1010);
589 #elif LLT_CONFIG == 3
590 rtl_write_dword(rtlpriv, REG_RQPN, 0x84838484);
591 #elif LLT_CONFIG == 4
592 rtl_write_dword(rtlpriv, REG_RQPN, 0x80bd1c1c);
593 #elif LLT_CONFIG == 5
594 rtl_write_word(rtlpriv, REG_RQPN_NPQ, 0x0000);
595
596 rtl_write_dword(rtlpriv, REG_RQPN, 0x80ac1c29);
597 rtl_write_byte(rtlpriv, REG_RQPN_NPQ, 0x03);
598 #endif
599
600 rtl_write_dword(rtlpriv, REG_TRXFF_BNDY, (0x27FF0000 | txpktbuf_bndy));
601 rtl_write_byte(rtlpriv, REG_TDECTRL + 1, txpktbuf_bndy);
602
603 rtl_write_byte(rtlpriv, REG_TXPKTBUF_BCNQ_BDNY, txpktbuf_bndy);
604 rtl_write_byte(rtlpriv, REG_TXPKTBUF_MGQ_BDNY, txpktbuf_bndy);
605
606 rtl_write_byte(rtlpriv, 0x45D, txpktbuf_bndy);
607 rtl_write_byte(rtlpriv, REG_PBP, 0x11);
608 rtl_write_byte(rtlpriv, REG_RX_DRVINFO_SZ, 0x4);
609
610 for (i = 0; i < (txpktbuf_bndy - 1); i++) {
611 status = _rtl8723e_llt_write(hw, i, i + 1);
612 if (!status)
613 return status;
614 }
615
616 status = _rtl8723e_llt_write(hw, (txpktbuf_bndy - 1), 0xFF);
617 if (!status)
618 return status;
619
620 for (i = txpktbuf_bndy; i < maxpage; i++) {
621 status = _rtl8723e_llt_write(hw, i, (i + 1));
622 if (!status)
623 return status;
624 }
625
626 status = _rtl8723e_llt_write(hw, maxpage, txpktbuf_bndy);
627 if (!status)
628 return status;
629
630 rtl_write_byte(rtlpriv, REG_CR, 0xff);
631 ubyte = rtl_read_byte(rtlpriv, REG_RQPN + 3);
632 rtl_write_byte(rtlpriv, REG_RQPN + 3, ubyte | BIT(7));
633
634 return true;
635 }
636
_rtl8723e_gen_refresh_led_state(struct ieee80211_hw * hw)637 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw *hw)
638 {
639 struct rtl_priv *rtlpriv = rtl_priv(hw);
640 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
641 enum rtl_led_pin pin0 = rtlpriv->ledctl.sw_led0;
642
643 if (rtlpriv->rtlhal.up_first_time)
644 return;
645
646 if (ppsc->rfoff_reason == RF_CHANGE_BY_IPS)
647 rtl8723e_sw_led_on(hw, pin0);
648 else if (ppsc->rfoff_reason == RF_CHANGE_BY_INIT)
649 rtl8723e_sw_led_on(hw, pin0);
650 else
651 rtl8723e_sw_led_off(hw, pin0);
652 }
653
_rtl8712e_init_mac(struct ieee80211_hw * hw)654 static bool _rtl8712e_init_mac(struct ieee80211_hw *hw)
655 {
656 struct rtl_priv *rtlpriv = rtl_priv(hw);
657 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
658
659 unsigned char bytetmp;
660 unsigned short wordtmp;
661 u16 retry = 0;
662 u16 tmpu2b;
663 bool mac_func_enable;
664
665 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x00);
666 bytetmp = rtl_read_byte(rtlpriv, REG_CR);
667 if (bytetmp == 0xFF)
668 mac_func_enable = true;
669 else
670 mac_func_enable = false;
671
672 /* HW Power on sequence */
673 if (!rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
674 PWR_INTF_PCI_MSK, RTL8723_NIC_ENABLE_FLOW))
675 return false;
676
677 bytetmp = rtl_read_byte(rtlpriv, REG_PCIE_CTRL_REG+2);
678 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG+2, bytetmp | BIT(4));
679
680 /* eMAC time out function enable, 0x369[7]=1 */
681 bytetmp = rtl_read_byte(rtlpriv, 0x369);
682 rtl_write_byte(rtlpriv, 0x369, bytetmp | BIT(7));
683
684 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
685 * we should do this before Enabling ASPM backdoor.
686 */
687 do {
688 rtl_write_word(rtlpriv, 0x358, 0x5e);
689 udelay(100);
690 rtl_write_word(rtlpriv, 0x356, 0xc280);
691 rtl_write_word(rtlpriv, 0x354, 0xc290);
692 rtl_write_word(rtlpriv, 0x358, 0x3e);
693 udelay(100);
694 rtl_write_word(rtlpriv, 0x358, 0x5e);
695 udelay(100);
696 tmpu2b = rtl_read_word(rtlpriv, 0x356);
697 retry++;
698 } while (tmpu2b != 0xc290 && retry < 100);
699
700 if (retry >= 100) {
701 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD,
702 "InitMAC(): ePHY configure fail!!!\n");
703 return false;
704 }
705
706 rtl_write_word(rtlpriv, REG_CR, 0x2ff);
707 rtl_write_word(rtlpriv, REG_CR + 1, 0x06);
708
709 if (!mac_func_enable) {
710 if (!_rtl8723e_llt_table_init(hw))
711 return false;
712 }
713
714 rtl_write_dword(rtlpriv, REG_HISR, 0xffffffff);
715 rtl_write_byte(rtlpriv, REG_HISRE, 0xff);
716
717 rtl_write_word(rtlpriv, REG_TRXFF_BNDY + 2, 0x27ff);
718
719 wordtmp = rtl_read_word(rtlpriv, REG_TRXDMA_CTRL);
720 wordtmp &= 0xf;
721 wordtmp |= 0xF771;
722 rtl_write_word(rtlpriv, REG_TRXDMA_CTRL, wordtmp);
723
724 rtl_write_byte(rtlpriv, REG_FWHW_TXQ_CTRL + 1, 0x1F);
725 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
726 rtl_write_word(rtlpriv, REG_RXFLTMAP2, 0xFFFF);
727 rtl_write_dword(rtlpriv, REG_TCR, rtlpci->transmit_config);
728
729 rtl_write_byte(rtlpriv, 0x4d0, 0x0);
730
731 rtl_write_dword(rtlpriv, REG_BCNQ_DESA,
732 ((u64) rtlpci->tx_ring[BEACON_QUEUE].dma) &
733 DMA_BIT_MASK(32));
734 rtl_write_dword(rtlpriv, REG_MGQ_DESA,
735 (u64) rtlpci->tx_ring[MGNT_QUEUE].dma &
736 DMA_BIT_MASK(32));
737 rtl_write_dword(rtlpriv, REG_VOQ_DESA,
738 (u64) rtlpci->tx_ring[VO_QUEUE].dma & DMA_BIT_MASK(32));
739 rtl_write_dword(rtlpriv, REG_VIQ_DESA,
740 (u64) rtlpci->tx_ring[VI_QUEUE].dma & DMA_BIT_MASK(32));
741 rtl_write_dword(rtlpriv, REG_BEQ_DESA,
742 (u64) rtlpci->tx_ring[BE_QUEUE].dma & DMA_BIT_MASK(32));
743 rtl_write_dword(rtlpriv, REG_BKQ_DESA,
744 (u64) rtlpci->tx_ring[BK_QUEUE].dma & DMA_BIT_MASK(32));
745 rtl_write_dword(rtlpriv, REG_HQ_DESA,
746 (u64) rtlpci->tx_ring[HIGH_QUEUE].dma &
747 DMA_BIT_MASK(32));
748 rtl_write_dword(rtlpriv, REG_RX_DESA,
749 (u64) rtlpci->rx_ring[RX_MPDU_QUEUE].dma &
750 DMA_BIT_MASK(32));
751
752 rtl_write_byte(rtlpriv, REG_PCIE_CTRL_REG + 3, 0x74);
753
754 rtl_write_dword(rtlpriv, REG_INT_MIG, 0);
755
756 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
757 rtl_write_byte(rtlpriv, REG_APSD_CTRL, bytetmp & ~BIT(6));
758 do {
759 retry++;
760 bytetmp = rtl_read_byte(rtlpriv, REG_APSD_CTRL);
761 } while ((retry < 200) && (bytetmp & BIT(7)));
762
763 _rtl8723e_gen_refresh_led_state(hw);
764
765 rtl_write_dword(rtlpriv, REG_MCUTST_1, 0x0);
766
767 return true;
768 }
769
_rtl8723e_hw_configure(struct ieee80211_hw * hw)770 static void _rtl8723e_hw_configure(struct ieee80211_hw *hw)
771 {
772 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
773 struct rtl_priv *rtlpriv = rtl_priv(hw);
774 u8 reg_bw_opmode;
775 u32 reg_prsr;
776
777 reg_bw_opmode = BW_OPMODE_20MHZ;
778 reg_prsr = RATE_ALL_CCK | RATE_ALL_OFDM_AG;
779
780 rtl_write_byte(rtlpriv, REG_INIRTS_RATE_SEL, 0x8);
781
782 rtl_write_byte(rtlpriv, REG_BWOPMODE, reg_bw_opmode);
783
784 rtl_write_dword(rtlpriv, REG_RRSR, reg_prsr);
785
786 rtl_write_byte(rtlpriv, REG_SLOT, 0x09);
787
788 rtl_write_byte(rtlpriv, REG_AMPDU_MIN_SPACE, 0x0);
789
790 rtl_write_word(rtlpriv, REG_FWHW_TXQ_CTRL, 0x1F80);
791
792 rtl_write_word(rtlpriv, REG_RL, 0x0707);
793
794 rtl_write_dword(rtlpriv, REG_BAR_MODE_CTRL, 0x02012802);
795
796 rtl_write_byte(rtlpriv, REG_HWSEQ_CTRL, 0xFF);
797
798 rtl_write_dword(rtlpriv, REG_DARFRC, 0x01000000);
799 rtl_write_dword(rtlpriv, REG_DARFRC + 4, 0x07060504);
800 rtl_write_dword(rtlpriv, REG_RARFRC, 0x01000000);
801 rtl_write_dword(rtlpriv, REG_RARFRC + 4, 0x07060504);
802
803 if ((rtlpriv->btcoexist.bt_coexistence) &&
804 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
805 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0x97427431);
806 else
807 rtl_write_dword(rtlpriv, REG_AGGLEN_LMT, 0xb972a841);
808
809 rtl_write_byte(rtlpriv, REG_ATIMWND, 0x2);
810
811 rtl_write_byte(rtlpriv, REG_BCN_MAX_ERR, 0xff);
812
813 rtlpci->reg_bcn_ctrl_val = 0x1f;
814 rtl_write_byte(rtlpriv, REG_BCN_CTRL, rtlpci->reg_bcn_ctrl_val);
815
816 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
817
818 rtl_write_byte(rtlpriv, REG_TBTT_PROHIBIT + 1, 0xff);
819
820 rtl_write_byte(rtlpriv, REG_PIFS, 0x1C);
821 rtl_write_byte(rtlpriv, REG_AGGR_BREAK_TIME, 0x16);
822
823 if ((rtlpriv->btcoexist.bt_coexistence) &&
824 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4)) {
825 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
826 rtl_write_word(rtlpriv, REG_PROT_MODE_CTRL, 0x0402);
827 } else {
828 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
829 rtl_write_word(rtlpriv, REG_NAV_PROT_LEN, 0x0020);
830 }
831
832 if ((rtlpriv->btcoexist.bt_coexistence) &&
833 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4))
834 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x03086666);
835 else
836 rtl_write_dword(rtlpriv, REG_FAST_EDCA_CTRL, 0x086666);
837
838 rtl_write_byte(rtlpriv, REG_ACKTO, 0x40);
839
840 rtl_write_word(rtlpriv, REG_SPEC_SIFS, 0x1010);
841 rtl_write_word(rtlpriv, REG_MAC_SPEC_SIFS, 0x1010);
842
843 rtl_write_word(rtlpriv, REG_SIFS_CTX, 0x1010);
844
845 rtl_write_word(rtlpriv, REG_SIFS_TRX, 0x1010);
846
847 rtl_write_dword(rtlpriv, REG_MAR, 0xffffffff);
848 rtl_write_dword(rtlpriv, REG_MAR + 4, 0xffffffff);
849
850 rtl_write_dword(rtlpriv, 0x394, 0x1);
851 }
852
_rtl8723e_enable_aspm_back_door(struct ieee80211_hw * hw)853 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw *hw)
854 {
855 struct rtl_priv *rtlpriv = rtl_priv(hw);
856 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
857
858 rtl_write_byte(rtlpriv, 0x34b, 0x93);
859 rtl_write_word(rtlpriv, 0x350, 0x870c);
860 rtl_write_byte(rtlpriv, 0x352, 0x1);
861
862 if (ppsc->support_backdoor)
863 rtl_write_byte(rtlpriv, 0x349, 0x1b);
864 else
865 rtl_write_byte(rtlpriv, 0x349, 0x03);
866
867 rtl_write_word(rtlpriv, 0x350, 0x2718);
868 rtl_write_byte(rtlpriv, 0x352, 0x1);
869 }
870
rtl8723e_enable_hw_security_config(struct ieee80211_hw * hw)871 void rtl8723e_enable_hw_security_config(struct ieee80211_hw *hw)
872 {
873 struct rtl_priv *rtlpriv = rtl_priv(hw);
874 u8 sec_reg_value;
875
876 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
877 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
878 rtlpriv->sec.pairwise_enc_algorithm,
879 rtlpriv->sec.group_enc_algorithm);
880
881 if (rtlpriv->cfg->mod_params->sw_crypto || rtlpriv->sec.use_sw_sec) {
882 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
883 "not open hw encryption\n");
884 return;
885 }
886
887 sec_reg_value = SCR_TXENCENABLE | SCR_RXDECENABLE;
888
889 if (rtlpriv->sec.use_defaultkey) {
890 sec_reg_value |= SCR_TXUSEDK;
891 sec_reg_value |= SCR_RXUSEDK;
892 }
893
894 sec_reg_value |= (SCR_RXBCUSEDK | SCR_TXBCUSEDK);
895
896 rtl_write_byte(rtlpriv, REG_CR + 1, 0x02);
897
898 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
899 "The SECR-value %x\n", sec_reg_value);
900
901 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_WPA_CONFIG, &sec_reg_value);
902
903 }
904
rtl8723e_hw_init(struct ieee80211_hw * hw)905 int rtl8723e_hw_init(struct ieee80211_hw *hw)
906 {
907 struct rtl_priv *rtlpriv = rtl_priv(hw);
908 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
909 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
910 struct rtl_phy *rtlphy = &(rtlpriv->phy);
911 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
912 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
913 bool rtstatus;
914 int err;
915 u8 tmp_u1b;
916 unsigned long flags;
917
918 rtlpriv->rtlhal.being_init_adapter = true;
919 /* As this function can take a very long time (up to 350 ms)
920 * and can be called with irqs disabled, reenable the irqs
921 * to let the other devices continue being serviced.
922 *
923 * It is safe doing so since our own interrupts will only be enabled
924 * in a subsequent step.
925 */
926 local_save_flags(flags);
927 local_irq_enable();
928 rtlhal->fw_ready = false;
929
930 rtlpriv->intf_ops->disable_aspm(hw);
931 rtstatus = _rtl8712e_init_mac(hw);
932 if (!rtstatus) {
933 pr_err("Init MAC failed\n");
934 err = 1;
935 goto exit;
936 }
937
938 err = rtl8723_download_fw(hw, false, FW_8723A_POLLING_TIMEOUT_COUNT);
939 if (err) {
940 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
941 "Failed to download FW. Init HW without FW now..\n");
942 err = 1;
943 goto exit;
944 }
945 rtlhal->fw_ready = true;
946
947 rtlhal->last_hmeboxnum = 0;
948 rtl8723e_phy_mac_config(hw);
949 /* because last function modify RCR, so we update
950 * rcr var here, or TP will unstable for receive_config
951 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
952 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
953 */
954 rtlpci->receive_config = rtl_read_dword(rtlpriv, REG_RCR);
955 rtlpci->receive_config &= ~(RCR_ACRC32 | RCR_AICV);
956 rtl_write_dword(rtlpriv, REG_RCR, rtlpci->receive_config);
957
958 rtl8723e_phy_bb_config(hw);
959 rtlphy->rf_mode = RF_OP_BY_SW_3WIRE;
960 rtl8723e_phy_rf_config(hw);
961 if (IS_VENDOR_UMC_A_CUT(rtlhal->version)) {
962 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G1, MASKDWORD, 0x30255);
963 rtl_set_rfreg(hw, RF90_PATH_A, RF_RX_G2, MASKDWORD, 0x50a00);
964 } else if (IS_81XXC_VENDOR_UMC_B_CUT(rtlhal->version)) {
965 rtl_set_rfreg(hw, RF90_PATH_A, 0x0C, MASKDWORD, 0x894AE);
966 rtl_set_rfreg(hw, RF90_PATH_A, 0x0A, MASKDWORD, 0x1AF31);
967 rtl_set_rfreg(hw, RF90_PATH_A, RF_IPA, MASKDWORD, 0x8F425);
968 rtl_set_rfreg(hw, RF90_PATH_A, RF_SYN_G2, MASKDWORD, 0x4F200);
969 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK1, MASKDWORD, 0x44053);
970 rtl_set_rfreg(hw, RF90_PATH_A, RF_RCK2, MASKDWORD, 0x80201);
971 }
972 rtlphy->rfreg_chnlval[0] = rtl_get_rfreg(hw, (enum radio_path)0,
973 RF_CHNLBW, RFREG_OFFSET_MASK);
974 rtlphy->rfreg_chnlval[1] = rtl_get_rfreg(hw, (enum radio_path)1,
975 RF_CHNLBW, RFREG_OFFSET_MASK);
976 rtl_set_bbreg(hw, RFPGA0_RFMOD, BCCKEN, 0x1);
977 rtl_set_bbreg(hw, RFPGA0_RFMOD, BOFDMEN, 0x1);
978 rtl_set_bbreg(hw, RFPGA0_ANALOGPARAMETER2, BIT(10), 1);
979 _rtl8723e_hw_configure(hw);
980 rtl_cam_reset_all_entry(hw);
981 rtl8723e_enable_hw_security_config(hw);
982
983 ppsc->rfpwr_state = ERFON;
984
985 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_ETHER_ADDR, mac->mac_addr);
986 _rtl8723e_enable_aspm_back_door(hw);
987 rtlpriv->intf_ops->enable_aspm(hw);
988
989 rtl8723e_bt_hw_init(hw);
990
991 if (ppsc->rfpwr_state == ERFON) {
992 rtl8723e_phy_set_rfpath_switch(hw, 1);
993 if (rtlphy->iqk_initialized) {
994 rtl8723e_phy_iq_calibrate(hw, true);
995 } else {
996 rtl8723e_phy_iq_calibrate(hw, false);
997 rtlphy->iqk_initialized = true;
998 }
999
1000 rtl8723e_dm_check_txpower_tracking(hw);
1001 rtl8723e_phy_lc_calibrate(hw);
1002 }
1003
1004 tmp_u1b = efuse_read_1byte(hw, 0x1FA);
1005 if (!(tmp_u1b & BIT(0))) {
1006 rtl_set_rfreg(hw, RF90_PATH_A, 0x15, 0x0F, 0x05);
1007 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "PA BIAS path A\n");
1008 }
1009
1010 if (!(tmp_u1b & BIT(4))) {
1011 tmp_u1b = rtl_read_byte(rtlpriv, 0x16);
1012 tmp_u1b &= 0x0F;
1013 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x80);
1014 udelay(10);
1015 rtl_write_byte(rtlpriv, 0x16, tmp_u1b | 0x90);
1016 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE, "under 1.5V\n");
1017 }
1018 rtl8723e_dm_init(hw);
1019 exit:
1020 local_irq_restore(flags);
1021 rtlpriv->rtlhal.being_init_adapter = false;
1022 return err;
1023 }
1024
_rtl8723e_read_chip_version(struct ieee80211_hw * hw)1025 static enum version_8723e _rtl8723e_read_chip_version(struct ieee80211_hw *hw)
1026 {
1027 struct rtl_priv *rtlpriv = rtl_priv(hw);
1028 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1029 enum version_8723e version = 0x0000;
1030 u32 value32;
1031
1032 value32 = rtl_read_dword(rtlpriv, REG_SYS_CFG);
1033 if (value32 & TRP_VAUX_EN) {
1034 version = (enum version_8723e)(version |
1035 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1036 /* RTL8723 with BT function. */
1037 version = (enum version_8723e)(version |
1038 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1039
1040 } else {
1041 /* Normal mass production chip. */
1042 version = (enum version_8723e) NORMAL_CHIP;
1043 version = (enum version_8723e)(version |
1044 ((value32 & VENDOR_ID) ? CHIP_VENDOR_UMC : 0));
1045 /* RTL8723 with BT function. */
1046 version = (enum version_8723e)(version |
1047 ((value32 & BT_FUNC) ? CHIP_8723 : 0));
1048 if (IS_CHIP_VENDOR_UMC(version))
1049 version = (enum version_8723e)(version |
1050 ((value32 & CHIP_VER_RTL_MASK)));/* IC version (CUT) */
1051 if (IS_8723_SERIES(version)) {
1052 value32 = rtl_read_dword(rtlpriv, REG_GPIO_OUTSTS);
1053 /* ROM code version. */
1054 version = (enum version_8723e)(version |
1055 ((value32 & RF_RL_ID)>>20));
1056 }
1057 }
1058
1059 if (IS_8723_SERIES(version)) {
1060 value32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
1061 rtlphy->polarity_ctl = ((value32 & WL_HWPDN_SL) ?
1062 RT_POLARITY_HIGH_ACT :
1063 RT_POLARITY_LOW_ACT);
1064 }
1065 switch (version) {
1066 case VERSION_TEST_UMC_CHIP_8723:
1067 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1068 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1069 break;
1070 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT:
1071 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1072 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1073 break;
1074 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT:
1075 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1076 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1077 break;
1078 default:
1079 pr_err("Chip Version ID: Unknown. Bug?\n");
1080 break;
1081 }
1082
1083 if (IS_8723_SERIES(version))
1084 rtlphy->rf_type = RF_1T1R;
1085
1086 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Chip RF Type: %s\n",
1087 (rtlphy->rf_type == RF_2T2R) ? "RF_2T2R" : "RF_1T1R");
1088
1089 return version;
1090 }
1091
_rtl8723e_set_media_status(struct ieee80211_hw * hw,enum nl80211_iftype type)1092 static int _rtl8723e_set_media_status(struct ieee80211_hw *hw,
1093 enum nl80211_iftype type)
1094 {
1095 struct rtl_priv *rtlpriv = rtl_priv(hw);
1096 u8 bt_msr = rtl_read_byte(rtlpriv, MSR) & 0xfc;
1097 enum led_ctl_mode ledaction = LED_CTL_NO_LINK;
1098 u8 mode = MSR_NOLINK;
1099
1100 rtl_write_dword(rtlpriv, REG_BCN_CTRL, 0);
1101 rtl_dbg(rtlpriv, COMP_BEACON, DBG_LOUD,
1102 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1103
1104 switch (type) {
1105 case NL80211_IFTYPE_UNSPECIFIED:
1106 mode = MSR_NOLINK;
1107 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1108 "Set Network type to NO LINK!\n");
1109 break;
1110 case NL80211_IFTYPE_ADHOC:
1111 mode = MSR_ADHOC;
1112 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1113 "Set Network type to Ad Hoc!\n");
1114 break;
1115 case NL80211_IFTYPE_STATION:
1116 mode = MSR_INFRA;
1117 ledaction = LED_CTL_LINK;
1118 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1119 "Set Network type to STA!\n");
1120 break;
1121 case NL80211_IFTYPE_AP:
1122 mode = MSR_AP;
1123 ledaction = LED_CTL_LINK;
1124 rtl_dbg(rtlpriv, COMP_INIT, DBG_TRACE,
1125 "Set Network type to AP!\n");
1126 break;
1127 default:
1128 pr_err("Network type %d not support!\n", type);
1129 return 1;
1130 }
1131
1132 /* MSR_INFRA == Link in infrastructure network;
1133 * MSR_ADHOC == Link in ad hoc network;
1134 * Therefore, check link state is necessary.
1135 *
1136 * MSR_AP == AP mode; link state is not cared here.
1137 */
1138 if (mode != MSR_AP &&
1139 rtlpriv->mac80211.link_state < MAC80211_LINKED) {
1140 mode = MSR_NOLINK;
1141 ledaction = LED_CTL_NO_LINK;
1142 }
1143 if (mode == MSR_NOLINK || mode == MSR_INFRA) {
1144 _rtl8723e_stop_tx_beacon(hw);
1145 _rtl8723e_enable_bcn_sub_func(hw);
1146 } else if (mode == MSR_ADHOC || mode == MSR_AP) {
1147 _rtl8723e_resume_tx_beacon(hw);
1148 _rtl8723e_disable_bcn_sub_func(hw);
1149 } else {
1150 rtl_dbg(rtlpriv, COMP_ERR, DBG_WARNING,
1151 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1152 mode);
1153 }
1154
1155 rtl_write_byte(rtlpriv, MSR, bt_msr | mode);
1156 rtlpriv->cfg->ops->led_control(hw, ledaction);
1157 if (mode == MSR_AP)
1158 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x00);
1159 else
1160 rtl_write_byte(rtlpriv, REG_BCNTCFG + 1, 0x66);
1161 return 0;
1162 }
1163
rtl8723e_set_check_bssid(struct ieee80211_hw * hw,bool check_bssid)1164 void rtl8723e_set_check_bssid(struct ieee80211_hw *hw, bool check_bssid)
1165 {
1166 struct rtl_priv *rtlpriv = rtl_priv(hw);
1167 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1168 u32 reg_rcr = rtlpci->receive_config;
1169
1170 if (rtlpriv->psc.rfpwr_state != ERFON)
1171 return;
1172
1173 if (check_bssid) {
1174 reg_rcr |= (RCR_CBSSID_DATA | RCR_CBSSID_BCN);
1175 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RCR,
1176 (u8 *)(®_rcr));
1177 _rtl8723e_set_bcn_ctrl_reg(hw, 0, BIT(4));
1178 } else if (!check_bssid) {
1179 reg_rcr &= (~(RCR_CBSSID_DATA | RCR_CBSSID_BCN));
1180 _rtl8723e_set_bcn_ctrl_reg(hw, BIT(4), 0);
1181 rtlpriv->cfg->ops->set_hw_reg(hw,
1182 HW_VAR_RCR, (u8 *)(®_rcr));
1183 }
1184 }
1185
rtl8723e_set_network_type(struct ieee80211_hw * hw,enum nl80211_iftype type)1186 int rtl8723e_set_network_type(struct ieee80211_hw *hw,
1187 enum nl80211_iftype type)
1188 {
1189 struct rtl_priv *rtlpriv = rtl_priv(hw);
1190
1191 if (_rtl8723e_set_media_status(hw, type))
1192 return -EOPNOTSUPP;
1193
1194 if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
1195 if (type != NL80211_IFTYPE_AP)
1196 rtl8723e_set_check_bssid(hw, true);
1197 } else {
1198 rtl8723e_set_check_bssid(hw, false);
1199 }
1200
1201 return 0;
1202 }
1203
1204 /* don't set REG_EDCA_BE_PARAM here
1205 * because mac80211 will send pkt when scan
1206 */
rtl8723e_set_qos(struct ieee80211_hw * hw,int aci)1207 void rtl8723e_set_qos(struct ieee80211_hw *hw, int aci)
1208 {
1209 struct rtl_priv *rtlpriv = rtl_priv(hw);
1210
1211 rtl8723_dm_init_edca_turbo(hw);
1212 switch (aci) {
1213 case AC1_BK:
1214 rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f);
1215 break;
1216 case AC0_BE:
1217 break;
1218 case AC2_VI:
1219 rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322);
1220 break;
1221 case AC3_VO:
1222 rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222);
1223 break;
1224 default:
1225 WARN_ONCE(true, "rtl8723ae: invalid aci: %d !\n", aci);
1226 break;
1227 }
1228 }
1229
rtl8723e_enable_interrupt(struct ieee80211_hw * hw)1230 void rtl8723e_enable_interrupt(struct ieee80211_hw *hw)
1231 {
1232 struct rtl_priv *rtlpriv = rtl_priv(hw);
1233 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1234
1235 rtl_write_dword(rtlpriv, 0x3a8, rtlpci->irq_mask[0] & 0xFFFFFFFF);
1236 rtl_write_dword(rtlpriv, 0x3ac, rtlpci->irq_mask[1] & 0xFFFFFFFF);
1237 rtlpci->irq_enabled = true;
1238 }
1239
rtl8723e_disable_interrupt(struct ieee80211_hw * hw)1240 void rtl8723e_disable_interrupt(struct ieee80211_hw *hw)
1241 {
1242 struct rtl_priv *rtlpriv = rtl_priv(hw);
1243 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1244 rtl_write_dword(rtlpriv, 0x3a8, IMR8190_DISABLED);
1245 rtl_write_dword(rtlpriv, 0x3ac, IMR8190_DISABLED);
1246 rtlpci->irq_enabled = false;
1247 /*synchronize_irq(rtlpci->pdev->irq);*/
1248 }
1249
_rtl8723e_poweroff_adapter(struct ieee80211_hw * hw)1250 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw *hw)
1251 {
1252 struct rtl_priv *rtlpriv = rtl_priv(hw);
1253 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1254 u8 u1b_tmp;
1255
1256 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1257 /* 1. Run LPS WL RFOFF flow */
1258 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1259 PWR_INTF_PCI_MSK, RTL8723_NIC_LPS_ENTER_FLOW);
1260
1261 /* 2. 0x1F[7:0] = 0 */
1262 /* turn off RF */
1263 rtl_write_byte(rtlpriv, REG_RF_CTRL, 0x00);
1264 if ((rtl_read_byte(rtlpriv, REG_MCUFWDL) & BIT(7)) &&
1265 rtlhal->fw_ready) {
1266 rtl8723ae_firmware_selfreset(hw);
1267 }
1268
1269 /* Reset MCU. Suggested by Filen. */
1270 u1b_tmp = rtl_read_byte(rtlpriv, REG_SYS_FUNC_EN+1);
1271 rtl_write_byte(rtlpriv, REG_SYS_FUNC_EN+1, (u1b_tmp & (~BIT(2))));
1272
1273 /* g. MCUFWDL 0x80[1:0]=0 */
1274 /* reset MCU ready status */
1275 rtl_write_byte(rtlpriv, REG_MCUFWDL, 0x00);
1276
1277 /* HW card disable configuration. */
1278 rtl_hal_pwrseqcmdparsing(rtlpriv, PWR_CUT_ALL_MSK, PWR_FAB_ALL_MSK,
1279 PWR_INTF_PCI_MSK, RTL8723_NIC_DISABLE_FLOW);
1280
1281 /* Reset MCU IO Wrapper */
1282 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1283 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, (u1b_tmp & (~BIT(0))));
1284 u1b_tmp = rtl_read_byte(rtlpriv, REG_RSV_CTRL + 1);
1285 rtl_write_byte(rtlpriv, REG_RSV_CTRL + 1, u1b_tmp | BIT(0));
1286
1287 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1288 /* lock ISO/CLK/Power control register */
1289 rtl_write_byte(rtlpriv, REG_RSV_CTRL, 0x0e);
1290 }
1291
rtl8723e_card_disable(struct ieee80211_hw * hw)1292 void rtl8723e_card_disable(struct ieee80211_hw *hw)
1293 {
1294 struct rtl_priv *rtlpriv = rtl_priv(hw);
1295 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1296 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1297 enum nl80211_iftype opmode;
1298
1299 mac->link_state = MAC80211_NOLINK;
1300 opmode = NL80211_IFTYPE_UNSPECIFIED;
1301 _rtl8723e_set_media_status(hw, opmode);
1302 if (rtlpriv->rtlhal.driver_is_goingto_unload ||
1303 ppsc->rfoff_reason > RF_CHANGE_BY_PS)
1304 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1305 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1306 _rtl8723e_poweroff_adapter(hw);
1307
1308 /* after power off we should do iqk again */
1309 rtlpriv->phy.iqk_initialized = false;
1310 }
1311
rtl8723e_interrupt_recognized(struct ieee80211_hw * hw,struct rtl_int * intvec)1312 void rtl8723e_interrupt_recognized(struct ieee80211_hw *hw,
1313 struct rtl_int *intvec)
1314 {
1315 struct rtl_priv *rtlpriv = rtl_priv(hw);
1316 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1317
1318 intvec->inta = rtl_read_dword(rtlpriv, 0x3a0) & rtlpci->irq_mask[0];
1319 rtl_write_dword(rtlpriv, 0x3a0, intvec->inta);
1320 }
1321
rtl8723e_set_beacon_related_registers(struct ieee80211_hw * hw)1322 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw *hw)
1323 {
1324
1325 struct rtl_priv *rtlpriv = rtl_priv(hw);
1326 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1327 u16 bcn_interval, atim_window;
1328
1329 bcn_interval = mac->beacon_interval;
1330 atim_window = 2; /*FIX MERGE */
1331 rtl8723e_disable_interrupt(hw);
1332 rtl_write_word(rtlpriv, REG_ATIMWND, atim_window);
1333 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1334 rtl_write_word(rtlpriv, REG_BCNTCFG, 0x660f);
1335 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_CCK, 0x18);
1336 rtl_write_byte(rtlpriv, REG_RXTSF_OFFSET_OFDM, 0x18);
1337 rtl_write_byte(rtlpriv, 0x606, 0x30);
1338 rtl8723e_enable_interrupt(hw);
1339 }
1340
rtl8723e_set_beacon_interval(struct ieee80211_hw * hw)1341 void rtl8723e_set_beacon_interval(struct ieee80211_hw *hw)
1342 {
1343 struct rtl_priv *rtlpriv = rtl_priv(hw);
1344 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1345 u16 bcn_interval = mac->beacon_interval;
1346
1347 rtl_dbg(rtlpriv, COMP_BEACON, DBG_DMESG,
1348 "beacon_interval:%d\n", bcn_interval);
1349 rtl8723e_disable_interrupt(hw);
1350 rtl_write_word(rtlpriv, REG_BCN_INTERVAL, bcn_interval);
1351 rtl8723e_enable_interrupt(hw);
1352 }
1353
rtl8723e_update_interrupt_mask(struct ieee80211_hw * hw,u32 add_msr,u32 rm_msr)1354 void rtl8723e_update_interrupt_mask(struct ieee80211_hw *hw,
1355 u32 add_msr, u32 rm_msr)
1356 {
1357 struct rtl_priv *rtlpriv = rtl_priv(hw);
1358 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1359
1360 rtl_dbg(rtlpriv, COMP_INTR, DBG_LOUD,
1361 "add_msr:%x, rm_msr:%x\n", add_msr, rm_msr);
1362
1363 if (add_msr)
1364 rtlpci->irq_mask[0] |= add_msr;
1365 if (rm_msr)
1366 rtlpci->irq_mask[0] &= (~rm_msr);
1367 rtl8723e_disable_interrupt(hw);
1368 rtl8723e_enable_interrupt(hw);
1369 }
1370
_rtl8723e_get_chnl_group(u8 chnl)1371 static u8 _rtl8723e_get_chnl_group(u8 chnl)
1372 {
1373 u8 group;
1374
1375 if (chnl < 3)
1376 group = 0;
1377 else if (chnl < 9)
1378 group = 1;
1379 else
1380 group = 2;
1381 return group;
1382 }
1383
_rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw * hw,bool autoload_fail,u8 * hwinfo)1384 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw *hw,
1385 bool autoload_fail,
1386 u8 *hwinfo)
1387 {
1388 struct rtl_priv *rtlpriv = rtl_priv(hw);
1389 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1390 u8 rf_path, index, tempval;
1391 u16 i;
1392
1393 for (rf_path = 0; rf_path < 1; rf_path++) {
1394 for (i = 0; i < 3; i++) {
1395 if (!autoload_fail) {
1396 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1397 hwinfo[EEPROM_TXPOWERCCK + rf_path * 3 + i];
1398 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1399 hwinfo[EEPROM_TXPOWERHT40_1S + rf_path * 3 + i];
1400 } else {
1401 rtlefuse->eeprom_chnlarea_txpwr_cck[rf_path][i] =
1402 EEPROM_DEFAULT_TXPOWERLEVEL;
1403 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s[rf_path][i] =
1404 EEPROM_DEFAULT_TXPOWERLEVEL;
1405 }
1406 }
1407 }
1408
1409 for (i = 0; i < 3; i++) {
1410 if (!autoload_fail)
1411 tempval = hwinfo[EEPROM_TXPOWERHT40_2SDIFF + i];
1412 else
1413 tempval = EEPROM_DEFAULT_HT40_2SDIFF;
1414 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_A][i] =
1415 (tempval & 0xf);
1416 rtlefuse->eprom_chnl_txpwr_ht40_2sdf[RF90_PATH_B][i] =
1417 ((tempval & 0xf0) >> 4);
1418 }
1419
1420 for (rf_path = 0; rf_path < 2; rf_path++)
1421 for (i = 0; i < 3; i++)
1422 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1423 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path,
1424 i, rtlefuse->eeprom_chnlarea_txpwr_cck
1425 [rf_path][i]);
1426 for (rf_path = 0; rf_path < 2; rf_path++)
1427 for (i = 0; i < 3; i++)
1428 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1429 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1430 rf_path, i,
1431 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1432 [rf_path][i]);
1433 for (rf_path = 0; rf_path < 2; rf_path++)
1434 for (i = 0; i < 3; i++)
1435 RTPRINT(rtlpriv, FINIT, INIT_EEPROM,
1436 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1437 rf_path, i,
1438 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1439 [rf_path][i]);
1440
1441 for (rf_path = 0; rf_path < 2; rf_path++) {
1442 for (i = 0; i < 14; i++) {
1443 index = _rtl8723e_get_chnl_group((u8)i);
1444
1445 rtlefuse->txpwrlevel_cck[rf_path][i] =
1446 rtlefuse->eeprom_chnlarea_txpwr_cck
1447 [rf_path][index];
1448 rtlefuse->txpwrlevel_ht40_1s[rf_path][i] =
1449 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1450 [rf_path][index];
1451
1452 if ((rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1453 [rf_path][index] -
1454 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1455 [rf_path][index]) > 0) {
1456 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] =
1457 rtlefuse->eeprom_chnlarea_txpwr_ht40_1s
1458 [rf_path][index] -
1459 rtlefuse->eprom_chnl_txpwr_ht40_2sdf
1460 [rf_path][index];
1461 } else {
1462 rtlefuse->txpwrlevel_ht40_2s[rf_path][i] = 0;
1463 }
1464 }
1465
1466 for (i = 0; i < 14; i++) {
1467 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1468 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1469 rf_path, i,
1470 rtlefuse->txpwrlevel_cck[rf_path][i],
1471 rtlefuse->txpwrlevel_ht40_1s[rf_path][i],
1472 rtlefuse->txpwrlevel_ht40_2s[rf_path][i]);
1473 }
1474 }
1475
1476 for (i = 0; i < 3; i++) {
1477 if (!autoload_fail) {
1478 rtlefuse->eeprom_pwrlimit_ht40[i] =
1479 hwinfo[EEPROM_TXPWR_GROUP + i];
1480 rtlefuse->eeprom_pwrlimit_ht20[i] =
1481 hwinfo[EEPROM_TXPWR_GROUP + 3 + i];
1482 } else {
1483 rtlefuse->eeprom_pwrlimit_ht40[i] = 0;
1484 rtlefuse->eeprom_pwrlimit_ht20[i] = 0;
1485 }
1486 }
1487
1488 for (rf_path = 0; rf_path < 2; rf_path++) {
1489 for (i = 0; i < 14; i++) {
1490 index = _rtl8723e_get_chnl_group((u8)i);
1491
1492 if (rf_path == RF90_PATH_A) {
1493 rtlefuse->pwrgroup_ht20[rf_path][i] =
1494 (rtlefuse->eeprom_pwrlimit_ht20[index] & 0xf);
1495 rtlefuse->pwrgroup_ht40[rf_path][i] =
1496 (rtlefuse->eeprom_pwrlimit_ht40[index] & 0xf);
1497 } else if (rf_path == RF90_PATH_B) {
1498 rtlefuse->pwrgroup_ht20[rf_path][i] =
1499 ((rtlefuse->eeprom_pwrlimit_ht20[index] &
1500 0xf0) >> 4);
1501 rtlefuse->pwrgroup_ht40[rf_path][i] =
1502 ((rtlefuse->eeprom_pwrlimit_ht40[index] &
1503 0xf0) >> 4);
1504 }
1505
1506 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1507 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path, i,
1508 rtlefuse->pwrgroup_ht20[rf_path][i]);
1509 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1510 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path, i,
1511 rtlefuse->pwrgroup_ht40[rf_path][i]);
1512 }
1513 }
1514
1515 for (i = 0; i < 14; i++) {
1516 index = _rtl8723e_get_chnl_group((u8)i);
1517
1518 if (!autoload_fail)
1519 tempval = hwinfo[EEPROM_TXPOWERHT20DIFF + index];
1520 else
1521 tempval = EEPROM_DEFAULT_HT20_DIFF;
1522
1523 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] = (tempval & 0xF);
1524 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] =
1525 ((tempval >> 4) & 0xF);
1526
1527 if (rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] & BIT(3))
1528 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i] |= 0xF0;
1529
1530 if (rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] & BIT(3))
1531 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i] |= 0xF0;
1532
1533 index = _rtl8723e_get_chnl_group((u8)i);
1534
1535 if (!autoload_fail)
1536 tempval = hwinfo[EEPROM_TXPOWER_OFDMDIFF + index];
1537 else
1538 tempval = EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF;
1539
1540 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i] = (tempval & 0xF);
1541 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i] =
1542 ((tempval >> 4) & 0xF);
1543 }
1544
1545 rtlefuse->legacy_ht_txpowerdiff =
1546 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][7];
1547
1548 for (i = 0; i < 14; i++)
1549 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1550 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1551 rtlefuse->txpwr_ht20diff[RF90_PATH_A][i]);
1552 for (i = 0; i < 14; i++)
1553 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1554 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i,
1555 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_A][i]);
1556 for (i = 0; i < 14; i++)
1557 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1558 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i,
1559 rtlefuse->txpwr_ht20diff[RF90_PATH_B][i]);
1560 for (i = 0; i < 14; i++)
1561 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1562 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i,
1563 rtlefuse->txpwr_legacyhtdiff[RF90_PATH_B][i]);
1564
1565 if (!autoload_fail)
1566 rtlefuse->eeprom_regulatory = (hwinfo[RF_OPTION1] & 0x7);
1567 else
1568 rtlefuse->eeprom_regulatory = 0;
1569 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1570 "eeprom_regulatory = 0x%x\n", rtlefuse->eeprom_regulatory);
1571
1572 if (!autoload_fail)
1573 rtlefuse->eeprom_tssi[RF90_PATH_A] = hwinfo[EEPROM_TSSI_A];
1574 else
1575 rtlefuse->eeprom_tssi[RF90_PATH_A] = EEPROM_DEFAULT_TSSI;
1576
1577 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1578 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1579 rtlefuse->eeprom_tssi[RF90_PATH_A],
1580 rtlefuse->eeprom_tssi[RF90_PATH_B]);
1581
1582 if (!autoload_fail)
1583 tempval = hwinfo[EEPROM_THERMAL_METER];
1584 else
1585 tempval = EEPROM_DEFAULT_THERMALMETER;
1586 rtlefuse->eeprom_thermalmeter = (tempval & 0x1f);
1587
1588 if (rtlefuse->eeprom_thermalmeter == 0x1f || autoload_fail)
1589 rtlefuse->apk_thermalmeterignore = true;
1590
1591 rtlefuse->thermalmeter[0] = rtlefuse->eeprom_thermalmeter;
1592 RTPRINT(rtlpriv, FINIT, INIT_TXPOWER,
1593 "thermalmeter = 0x%x\n", rtlefuse->eeprom_thermalmeter);
1594 }
1595
_rtl8723e_read_adapter_info(struct ieee80211_hw * hw,bool b_pseudo_test)1596 static void _rtl8723e_read_adapter_info(struct ieee80211_hw *hw,
1597 bool b_pseudo_test)
1598 {
1599 struct rtl_priv *rtlpriv = rtl_priv(hw);
1600 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1601 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1602 int params[] = {RTL8190_EEPROM_ID, EEPROM_VID, EEPROM_DID,
1603 EEPROM_SVID, EEPROM_SMID, EEPROM_MAC_ADDR,
1604 EEPROM_CHANNELPLAN, EEPROM_VERSION, EEPROM_CUSTOMER_ID,
1605 COUNTRY_CODE_WORLD_WIDE_13};
1606 u8 *hwinfo;
1607
1608 if (b_pseudo_test) {
1609 /* need add */
1610 return;
1611 }
1612 hwinfo = kzalloc(HWSET_MAX_SIZE, GFP_KERNEL);
1613 if (!hwinfo)
1614 return;
1615
1616 if (rtl_get_hwinfo(hw, rtlpriv, HWSET_MAX_SIZE, hwinfo, params))
1617 goto exit;
1618
1619 _rtl8723e_read_txpower_info_from_hwpg(hw, rtlefuse->autoload_failflag,
1620 hwinfo);
1621
1622 rtl8723e_read_bt_coexist_info_from_hwpg(hw,
1623 rtlefuse->autoload_failflag, hwinfo);
1624
1625 if (rtlhal->oem_id != RT_CID_DEFAULT)
1626 goto exit;
1627
1628 switch (rtlefuse->eeprom_oemid) {
1629 case EEPROM_CID_DEFAULT:
1630 switch (rtlefuse->eeprom_did) {
1631 case 0x8176:
1632 switch (rtlefuse->eeprom_svid) {
1633 case 0x10EC:
1634 switch (rtlefuse->eeprom_smid) {
1635 case 0x6151 ... 0x6152:
1636 case 0x6154 ... 0x6155:
1637 case 0x6177 ... 0x6180:
1638 case 0x7151 ... 0x7152:
1639 case 0x7154 ... 0x7155:
1640 case 0x7177 ... 0x7180:
1641 case 0x8151 ... 0x8152:
1642 case 0x8154 ... 0x8155:
1643 case 0x8181 ... 0x8182:
1644 case 0x8184 ... 0x8185:
1645 case 0x9151 ... 0x9152:
1646 case 0x9154 ... 0x9155:
1647 case 0x9181 ... 0x9182:
1648 case 0x9184 ... 0x9185:
1649 rtlhal->oem_id = RT_CID_TOSHIBA;
1650 break;
1651 case 0x6191 ... 0x6193:
1652 case 0x7191 ... 0x7193:
1653 case 0x8191 ... 0x8193:
1654 case 0x9191 ... 0x9193:
1655 rtlhal->oem_id = RT_CID_819X_SAMSUNG;
1656 break;
1657 case 0x8197:
1658 case 0x9196:
1659 rtlhal->oem_id = RT_CID_819X_CLEVO;
1660 break;
1661 case 0x8203:
1662 rtlhal->oem_id = RT_CID_819X_PRONETS;
1663 break;
1664 case 0x8195:
1665 case 0x9195:
1666 case 0x7194:
1667 case 0x8200 ... 0x8202:
1668 case 0x9200:
1669 rtlhal->oem_id = RT_CID_819X_LENOVO;
1670 break;
1671 }
1672 break;
1673 case 0x1025:
1674 rtlhal->oem_id = RT_CID_819X_ACER;
1675 break;
1676 case 0x1028:
1677 switch (rtlefuse->eeprom_smid) {
1678 case 0x8194:
1679 case 0x8198:
1680 case 0x9197 ... 0x9198:
1681 rtlhal->oem_id = RT_CID_819X_DELL;
1682 break;
1683 }
1684 break;
1685 case 0x103C:
1686 switch (rtlefuse->eeprom_smid) {
1687 case 0x1629:
1688 rtlhal->oem_id = RT_CID_819X_HP;
1689 }
1690 break;
1691 case 0x1A32:
1692 switch (rtlefuse->eeprom_smid) {
1693 case 0x2315:
1694 rtlhal->oem_id = RT_CID_819X_QMI;
1695 break;
1696 }
1697 break;
1698 case 0x1043:
1699 switch (rtlefuse->eeprom_smid) {
1700 case 0x84B5:
1701 rtlhal->oem_id =
1702 RT_CID_819X_EDIMAX_ASUS;
1703 }
1704 break;
1705 }
1706 break;
1707 case 0x8178:
1708 switch (rtlefuse->eeprom_svid) {
1709 case 0x10ec:
1710 switch (rtlefuse->eeprom_smid) {
1711 case 0x6181 ... 0x6182:
1712 case 0x6184 ... 0x6185:
1713 case 0x7181 ... 0x7182:
1714 case 0x7184 ... 0x7185:
1715 case 0x8181 ... 0x8182:
1716 case 0x8184 ... 0x8185:
1717 case 0x9181 ... 0x9182:
1718 case 0x9184 ... 0x9185:
1719 rtlhal->oem_id = RT_CID_TOSHIBA;
1720 break;
1721 case 0x8186:
1722 rtlhal->oem_id =
1723 RT_CID_819X_PRONETS;
1724 break;
1725 }
1726 break;
1727 case 0x1025:
1728 rtlhal->oem_id = RT_CID_819X_ACER;
1729 break;
1730 case 0x1043:
1731 switch (rtlefuse->eeprom_smid) {
1732 case 0x8486:
1733 rtlhal->oem_id =
1734 RT_CID_819X_EDIMAX_ASUS;
1735 }
1736 break;
1737 }
1738 break;
1739 }
1740 break;
1741 case EEPROM_CID_TOSHIBA:
1742 rtlhal->oem_id = RT_CID_TOSHIBA;
1743 break;
1744 case EEPROM_CID_CCX:
1745 rtlhal->oem_id = RT_CID_CCX;
1746 break;
1747 case EEPROM_CID_QMI:
1748 rtlhal->oem_id = RT_CID_819X_QMI;
1749 break;
1750 case EEPROM_CID_WHQL:
1751 break;
1752 default:
1753 rtlhal->oem_id = RT_CID_DEFAULT;
1754 break;
1755 }
1756 exit:
1757 kfree(hwinfo);
1758 }
1759
_rtl8723e_hal_customized_behavior(struct ieee80211_hw * hw)1760 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw *hw)
1761 {
1762 struct rtl_priv *rtlpriv = rtl_priv(hw);
1763 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1764
1765 rtlpriv->ledctl.led_opendrain = true;
1766 switch (rtlhal->oem_id) {
1767 case RT_CID_819X_HP:
1768 rtlpriv->ledctl.led_opendrain = true;
1769 break;
1770 case RT_CID_819X_LENOVO:
1771 case RT_CID_DEFAULT:
1772 case RT_CID_TOSHIBA:
1773 case RT_CID_CCX:
1774 case RT_CID_819X_ACER:
1775 case RT_CID_WHQL:
1776 default:
1777 break;
1778 }
1779 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG,
1780 "RT Customized ID: 0x%02X\n", rtlhal->oem_id);
1781 }
1782
rtl8723e_read_eeprom_info(struct ieee80211_hw * hw)1783 void rtl8723e_read_eeprom_info(struct ieee80211_hw *hw)
1784 {
1785 struct rtl_priv *rtlpriv = rtl_priv(hw);
1786 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
1787 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1788 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1789 u8 tmp_u1b;
1790 u32 value32;
1791
1792 value32 = rtl_read_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST]);
1793 value32 = (value32 & ~EFUSE_SEL_MASK) | EFUSE_SEL(EFUSE_WIFI_SEL_0);
1794 rtl_write_dword(rtlpriv, rtlpriv->cfg->maps[EFUSE_TEST], value32);
1795
1796 rtlhal->version = _rtl8723e_read_chip_version(hw);
1797
1798 if (get_rf_type(rtlphy) == RF_1T1R)
1799 rtlpriv->dm.rfpath_rxenable[0] = true;
1800 else
1801 rtlpriv->dm.rfpath_rxenable[0] =
1802 rtlpriv->dm.rfpath_rxenable[1] = true;
1803 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "VersionID = 0x%4x\n",
1804 rtlhal->version);
1805
1806 tmp_u1b = rtl_read_byte(rtlpriv, REG_9346CR);
1807 if (tmp_u1b & BIT(4)) {
1808 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EEPROM\n");
1809 rtlefuse->epromtype = EEPROM_93C46;
1810 } else {
1811 rtl_dbg(rtlpriv, COMP_INIT, DBG_DMESG, "Boot from EFUSE\n");
1812 rtlefuse->epromtype = EEPROM_BOOT_EFUSE;
1813 }
1814 if (tmp_u1b & BIT(5)) {
1815 rtl_dbg(rtlpriv, COMP_INIT, DBG_LOUD, "Autoload OK\n");
1816 rtlefuse->autoload_failflag = false;
1817 _rtl8723e_read_adapter_info(hw, false);
1818 } else {
1819 rtlefuse->autoload_failflag = true;
1820 _rtl8723e_read_adapter_info(hw, false);
1821 pr_err("Autoload ERR!!\n");
1822 }
1823 _rtl8723e_hal_customized_behavior(hw);
1824 }
1825
rtl8723e_update_hal_rate_table(struct ieee80211_hw * hw,struct ieee80211_sta * sta)1826 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw *hw,
1827 struct ieee80211_sta *sta)
1828 {
1829 struct rtl_priv *rtlpriv = rtl_priv(hw);
1830 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1831 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1832 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1833 u32 ratr_value;
1834 u8 ratr_index = 0;
1835 u8 b_nmode = mac->ht_enable;
1836 u16 shortgi_rate;
1837 u32 tmp_ratr_value;
1838 u8 curtxbw_40mhz = mac->bw_40;
1839 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1840 1 : 0;
1841 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1842 1 : 0;
1843 enum wireless_mode wirelessmode = mac->mode;
1844 u32 ratr_mask;
1845
1846 if (rtlhal->current_bandtype == BAND_ON_5G)
1847 ratr_value = sta->deflink.supp_rates[1] << 4;
1848 else
1849 ratr_value = sta->deflink.supp_rates[0];
1850 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1851 ratr_value = 0xfff;
1852 ratr_value |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1853 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1854 switch (wirelessmode) {
1855 case WIRELESS_MODE_B:
1856 if (ratr_value & 0x0000000c)
1857 ratr_value &= 0x0000000d;
1858 else
1859 ratr_value &= 0x0000000f;
1860 break;
1861 case WIRELESS_MODE_G:
1862 ratr_value &= 0x00000FF5;
1863 break;
1864 case WIRELESS_MODE_N_24G:
1865 case WIRELESS_MODE_N_5G:
1866 b_nmode = 1;
1867 if (get_rf_type(rtlphy) == RF_1T2R ||
1868 get_rf_type(rtlphy) == RF_1T1R)
1869 ratr_mask = 0x000ff005;
1870 else
1871 ratr_mask = 0x0f0ff005;
1872
1873 ratr_value &= ratr_mask;
1874 break;
1875 default:
1876 if (rtlphy->rf_type == RF_1T2R)
1877 ratr_value &= 0x000ff0ff;
1878 else
1879 ratr_value &= 0x0f0ff0ff;
1880
1881 break;
1882 }
1883
1884 if ((rtlpriv->btcoexist.bt_coexistence) &&
1885 (rtlpriv->btcoexist.bt_coexist_type == BT_CSR_BC4) &&
1886 (rtlpriv->btcoexist.bt_cur_state) &&
1887 (rtlpriv->btcoexist.bt_ant_isolation) &&
1888 ((rtlpriv->btcoexist.bt_service == BT_SCO) ||
1889 (rtlpriv->btcoexist.bt_service == BT_BUSY)))
1890 ratr_value &= 0x0fffcfc0;
1891 else
1892 ratr_value &= 0x0FFFFFFF;
1893
1894 if (b_nmode &&
1895 ((curtxbw_40mhz && curshortgi_40mhz) ||
1896 (!curtxbw_40mhz && curshortgi_20mhz))) {
1897 ratr_value |= 0x10000000;
1898 tmp_ratr_value = (ratr_value >> 12);
1899
1900 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
1901 if ((1 << shortgi_rate) & tmp_ratr_value)
1902 break;
1903 }
1904
1905 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
1906 (shortgi_rate << 4) | (shortgi_rate);
1907 }
1908
1909 rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
1910
1911 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
1912 "%x\n", rtl_read_dword(rtlpriv, REG_ARFR0));
1913 }
1914
rtl8723e_update_hal_rate_mask(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)1915 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw *hw,
1916 struct ieee80211_sta *sta,
1917 u8 rssi_level, bool update_bw)
1918 {
1919 struct rtl_priv *rtlpriv = rtl_priv(hw);
1920 struct rtl_phy *rtlphy = &(rtlpriv->phy);
1921 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1922 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1923 struct rtl_sta_info *sta_entry = NULL;
1924 u32 ratr_bitmap;
1925 u8 ratr_index;
1926 u8 curtxbw_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SUP_WIDTH_20_40)
1927 ? 1 : 0;
1928 u8 curshortgi_40mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
1929 1 : 0;
1930 u8 curshortgi_20mhz = (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
1931 1 : 0;
1932 enum wireless_mode wirelessmode = 0;
1933 bool shortgi = false;
1934 u8 rate_mask[5];
1935 u8 macid = 0;
1936 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
1937
1938 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1939 wirelessmode = sta_entry->wireless_mode;
1940 if (mac->opmode == NL80211_IFTYPE_STATION)
1941 curtxbw_40mhz = mac->bw_40;
1942 else if (mac->opmode == NL80211_IFTYPE_AP ||
1943 mac->opmode == NL80211_IFTYPE_ADHOC)
1944 macid = sta->aid + 1;
1945
1946 if (rtlhal->current_bandtype == BAND_ON_5G)
1947 ratr_bitmap = sta->deflink.supp_rates[1] << 4;
1948 else
1949 ratr_bitmap = sta->deflink.supp_rates[0];
1950 if (mac->opmode == NL80211_IFTYPE_ADHOC)
1951 ratr_bitmap = 0xfff;
1952 ratr_bitmap |= (sta->deflink.ht_cap.mcs.rx_mask[1] << 20 |
1953 sta->deflink.ht_cap.mcs.rx_mask[0] << 12);
1954 switch (wirelessmode) {
1955 case WIRELESS_MODE_B:
1956 ratr_index = RATR_INX_WIRELESS_B;
1957 if (ratr_bitmap & 0x0000000c)
1958 ratr_bitmap &= 0x0000000d;
1959 else
1960 ratr_bitmap &= 0x0000000f;
1961 break;
1962 case WIRELESS_MODE_G:
1963 ratr_index = RATR_INX_WIRELESS_GB;
1964
1965 if (rssi_level == 1)
1966 ratr_bitmap &= 0x00000f00;
1967 else if (rssi_level == 2)
1968 ratr_bitmap &= 0x00000ff0;
1969 else
1970 ratr_bitmap &= 0x00000ff5;
1971 break;
1972 case WIRELESS_MODE_A:
1973 ratr_index = RATR_INX_WIRELESS_G;
1974 ratr_bitmap &= 0x00000ff0;
1975 break;
1976 case WIRELESS_MODE_N_24G:
1977 case WIRELESS_MODE_N_5G:
1978 ratr_index = RATR_INX_WIRELESS_NGB;
1979 if (rtlphy->rf_type == RF_1T2R ||
1980 rtlphy->rf_type == RF_1T1R) {
1981 if (curtxbw_40mhz) {
1982 if (rssi_level == 1)
1983 ratr_bitmap &= 0x000f0000;
1984 else if (rssi_level == 2)
1985 ratr_bitmap &= 0x000ff000;
1986 else
1987 ratr_bitmap &= 0x000ff015;
1988 } else {
1989 if (rssi_level == 1)
1990 ratr_bitmap &= 0x000f0000;
1991 else if (rssi_level == 2)
1992 ratr_bitmap &= 0x000ff000;
1993 else
1994 ratr_bitmap &= 0x000ff005;
1995 }
1996 } else {
1997 if (curtxbw_40mhz) {
1998 if (rssi_level == 1)
1999 ratr_bitmap &= 0x0f0f0000;
2000 else if (rssi_level == 2)
2001 ratr_bitmap &= 0x0f0ff000;
2002 else
2003 ratr_bitmap &= 0x0f0ff015;
2004 } else {
2005 if (rssi_level == 1)
2006 ratr_bitmap &= 0x0f0f0000;
2007 else if (rssi_level == 2)
2008 ratr_bitmap &= 0x0f0ff000;
2009 else
2010 ratr_bitmap &= 0x0f0ff005;
2011 }
2012 }
2013
2014 if ((curtxbw_40mhz && curshortgi_40mhz) ||
2015 (!curtxbw_40mhz && curshortgi_20mhz)) {
2016 if (macid == 0)
2017 shortgi = true;
2018 else if (macid == 1)
2019 shortgi = false;
2020 }
2021 break;
2022 default:
2023 ratr_index = RATR_INX_WIRELESS_NGB;
2024
2025 if (rtlphy->rf_type == RF_1T2R)
2026 ratr_bitmap &= 0x000ff0ff;
2027 else
2028 ratr_bitmap &= 0x0f0ff0ff;
2029 break;
2030 }
2031 sta_entry->ratr_index = ratr_index;
2032
2033 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2034 "ratr_bitmap :%x\n", ratr_bitmap);
2035 *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
2036 (ratr_index << 28);
2037 rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
2038 rtl_dbg(rtlpriv, COMP_RATR, DBG_DMESG,
2039 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2040 ratr_index, ratr_bitmap,
2041 rate_mask[0], rate_mask[1],
2042 rate_mask[2], rate_mask[3],
2043 rate_mask[4]);
2044 rtl8723e_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
2045 }
2046
rtl8723e_update_hal_rate_tbl(struct ieee80211_hw * hw,struct ieee80211_sta * sta,u8 rssi_level,bool update_bw)2047 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw *hw,
2048 struct ieee80211_sta *sta, u8 rssi_level,
2049 bool update_bw)
2050 {
2051 struct rtl_priv *rtlpriv = rtl_priv(hw);
2052
2053 if (rtlpriv->dm.useramask)
2054 rtl8723e_update_hal_rate_mask(hw, sta, rssi_level, update_bw);
2055 else
2056 rtl8723e_update_hal_rate_table(hw, sta);
2057 }
2058
rtl8723e_update_channel_access_setting(struct ieee80211_hw * hw)2059 void rtl8723e_update_channel_access_setting(struct ieee80211_hw *hw)
2060 {
2061 struct rtl_priv *rtlpriv = rtl_priv(hw);
2062 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2063 u16 sifs_timer;
2064
2065 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SLOT_TIME, &mac->slot_time);
2066 if (!mac->ht_enable)
2067 sifs_timer = 0x0a0a;
2068 else
2069 sifs_timer = 0x1010;
2070 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_SIFS, (u8 *)&sifs_timer);
2071 }
2072
rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw * hw,u8 * valid)2073 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 *valid)
2074 {
2075 struct rtl_priv *rtlpriv = rtl_priv(hw);
2076 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
2077 struct rtl_phy *rtlphy = &(rtlpriv->phy);
2078 enum rf_pwrstate e_rfpowerstate_toset;
2079 u8 u1tmp;
2080 bool b_actuallyset = false;
2081
2082 if (rtlpriv->rtlhal.being_init_adapter)
2083 return false;
2084
2085 if (ppsc->swrf_processing)
2086 return false;
2087
2088 spin_lock(&rtlpriv->locks.rf_ps_lock);
2089 if (ppsc->rfchange_inprogress) {
2090 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2091 return false;
2092 } else {
2093 ppsc->rfchange_inprogress = true;
2094 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2095 }
2096
2097 rtl_write_byte(rtlpriv, REG_GPIO_IO_SEL_2,
2098 rtl_read_byte(rtlpriv, REG_GPIO_IO_SEL_2)&~(BIT(1)));
2099
2100 u1tmp = rtl_read_byte(rtlpriv, REG_GPIO_PIN_CTRL_2);
2101
2102 if (rtlphy->polarity_ctl)
2103 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFOFF : ERFON;
2104 else
2105 e_rfpowerstate_toset = (u1tmp & BIT(1)) ? ERFON : ERFOFF;
2106
2107 if (ppsc->hwradiooff && (e_rfpowerstate_toset == ERFON)) {
2108 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2109 "GPIOChangeRF - HW Radio ON, RF ON\n");
2110
2111 e_rfpowerstate_toset = ERFON;
2112 ppsc->hwradiooff = false;
2113 b_actuallyset = true;
2114 } else if (!ppsc->hwradiooff && (e_rfpowerstate_toset == ERFOFF)) {
2115 rtl_dbg(rtlpriv, COMP_RF, DBG_DMESG,
2116 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2117
2118 e_rfpowerstate_toset = ERFOFF;
2119 ppsc->hwradiooff = true;
2120 b_actuallyset = true;
2121 }
2122
2123 if (b_actuallyset) {
2124 spin_lock(&rtlpriv->locks.rf_ps_lock);
2125 ppsc->rfchange_inprogress = false;
2126 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2127 } else {
2128 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_HALT_NIC)
2129 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
2130
2131 spin_lock(&rtlpriv->locks.rf_ps_lock);
2132 ppsc->rfchange_inprogress = false;
2133 spin_unlock(&rtlpriv->locks.rf_ps_lock);
2134 }
2135
2136 *valid = 1;
2137 return !ppsc->hwradiooff;
2138
2139 }
2140
rtl8723e_set_key(struct ieee80211_hw * hw,u32 key_index,u8 * p_macaddr,bool is_group,u8 enc_algo,bool is_wepkey,bool clear_all)2141 void rtl8723e_set_key(struct ieee80211_hw *hw, u32 key_index,
2142 u8 *p_macaddr, bool is_group, u8 enc_algo,
2143 bool is_wepkey, bool clear_all)
2144 {
2145 struct rtl_priv *rtlpriv = rtl_priv(hw);
2146 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
2147 struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
2148 u8 *macaddr = p_macaddr;
2149 u32 entry_id = 0;
2150 bool is_pairwise = false;
2151
2152 static u8 cam_const_addr[4][6] = {
2153 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2154 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2155 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2156 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2157 };
2158 static u8 cam_const_broad[] = {
2159 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2160 };
2161
2162 if (clear_all) {
2163 u8 idx = 0;
2164 u8 cam_offset = 0;
2165 u8 clear_number = 5;
2166
2167 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG, "clear_all\n");
2168
2169 for (idx = 0; idx < clear_number; idx++) {
2170 rtl_cam_mark_invalid(hw, cam_offset + idx);
2171 rtl_cam_empty_entry(hw, cam_offset + idx);
2172
2173 if (idx < 5) {
2174 memset(rtlpriv->sec.key_buf[idx], 0,
2175 MAX_KEY_LEN);
2176 rtlpriv->sec.key_len[idx] = 0;
2177 }
2178 }
2179
2180 } else {
2181 switch (enc_algo) {
2182 case WEP40_ENCRYPTION:
2183 enc_algo = CAM_WEP40;
2184 break;
2185 case WEP104_ENCRYPTION:
2186 enc_algo = CAM_WEP104;
2187 break;
2188 case TKIP_ENCRYPTION:
2189 enc_algo = CAM_TKIP;
2190 break;
2191 case AESCCMP_ENCRYPTION:
2192 enc_algo = CAM_AES;
2193 break;
2194 default:
2195 rtl_dbg(rtlpriv, COMP_ERR, DBG_LOUD,
2196 "switch case %#x not processed\n", enc_algo);
2197 enc_algo = CAM_TKIP;
2198 break;
2199 }
2200
2201 if (is_wepkey || rtlpriv->sec.use_defaultkey) {
2202 macaddr = cam_const_addr[key_index];
2203 entry_id = key_index;
2204 } else {
2205 if (is_group) {
2206 macaddr = cam_const_broad;
2207 entry_id = key_index;
2208 } else {
2209 if (mac->opmode == NL80211_IFTYPE_AP) {
2210 entry_id =
2211 rtl_cam_get_free_entry(hw, p_macaddr);
2212 if (entry_id >= TOTAL_CAM_ENTRY) {
2213 pr_err("Can not find free hw security cam entry\n");
2214 return;
2215 }
2216 } else {
2217 entry_id = CAM_PAIRWISE_KEY_POSITION;
2218 }
2219
2220 key_index = PAIRWISE_KEYIDX;
2221 is_pairwise = true;
2222 }
2223 }
2224
2225 if (rtlpriv->sec.key_len[key_index] == 0) {
2226 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2227 "delete one entry, entry_id is %d\n",
2228 entry_id);
2229 if (mac->opmode == NL80211_IFTYPE_AP)
2230 rtl_cam_del_entry(hw, p_macaddr);
2231 rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
2232 } else {
2233 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2234 "add one entry\n");
2235 if (is_pairwise) {
2236 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2237 "set Pairwise key\n");
2238
2239 rtl_cam_add_one_entry(hw, macaddr, key_index,
2240 entry_id, enc_algo,
2241 CAM_CONFIG_NO_USEDK,
2242 rtlpriv->sec.key_buf[key_index]);
2243 } else {
2244 rtl_dbg(rtlpriv, COMP_SEC, DBG_DMESG,
2245 "set group key\n");
2246
2247 if (mac->opmode == NL80211_IFTYPE_ADHOC) {
2248 rtl_cam_add_one_entry(hw,
2249 rtlefuse->dev_addr,
2250 PAIRWISE_KEYIDX,
2251 CAM_PAIRWISE_KEY_POSITION,
2252 enc_algo,
2253 CAM_CONFIG_NO_USEDK,
2254 rtlpriv->sec.key_buf
2255 [entry_id]);
2256 }
2257
2258 rtl_cam_add_one_entry(hw, macaddr, key_index,
2259 entry_id, enc_algo,
2260 CAM_CONFIG_NO_USEDK,
2261 rtlpriv->sec.key_buf[entry_id]);
2262 }
2263
2264 }
2265 }
2266 }
2267
rtl8723e_bt_var_init(struct ieee80211_hw * hw)2268 static void rtl8723e_bt_var_init(struct ieee80211_hw *hw)
2269 {
2270 struct rtl_priv *rtlpriv = rtl_priv(hw);
2271
2272 rtlpriv->btcoexist.bt_coexistence =
2273 rtlpriv->btcoexist.eeprom_bt_coexist;
2274 rtlpriv->btcoexist.bt_ant_num =
2275 rtlpriv->btcoexist.eeprom_bt_ant_num;
2276 rtlpriv->btcoexist.bt_coexist_type =
2277 rtlpriv->btcoexist.eeprom_bt_type;
2278
2279 rtlpriv->btcoexist.bt_ant_isolation =
2280 rtlpriv->btcoexist.eeprom_bt_ant_isol;
2281
2282 rtlpriv->btcoexist.bt_radio_shared_type =
2283 rtlpriv->btcoexist.eeprom_bt_radio_shared;
2284
2285 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2286 "BT Coexistence = 0x%x\n",
2287 rtlpriv->btcoexist.bt_coexistence);
2288
2289 if (rtlpriv->btcoexist.bt_coexistence) {
2290 rtlpriv->btcoexist.bt_busy_traffic = false;
2291 rtlpriv->btcoexist.bt_traffic_mode_set = false;
2292 rtlpriv->btcoexist.bt_non_traffic_mode_set = false;
2293
2294 rtlpriv->btcoexist.cstate = 0;
2295 rtlpriv->btcoexist.previous_state = 0;
2296
2297 if (rtlpriv->btcoexist.bt_ant_num == ANT_X2) {
2298 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2299 "BlueTooth BT_Ant_Num = Antx2\n");
2300 } else if (rtlpriv->btcoexist.bt_ant_num == ANT_X1) {
2301 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2302 "BlueTooth BT_Ant_Num = Antx1\n");
2303 }
2304 switch (rtlpriv->btcoexist.bt_coexist_type) {
2305 case BT_2WIRE:
2306 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2307 "BlueTooth BT_CoexistType = BT_2Wire\n");
2308 break;
2309 case BT_ISSC_3WIRE:
2310 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2311 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2312 break;
2313 case BT_ACCEL:
2314 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2315 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2316 break;
2317 case BT_CSR_BC4:
2318 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2319 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2320 break;
2321 case BT_CSR_BC8:
2322 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2323 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2324 break;
2325 case BT_RTL8756:
2326 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2327 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2328 break;
2329 default:
2330 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2331 "BlueTooth BT_CoexistType = Unknown\n");
2332 break;
2333 }
2334 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2335 "BlueTooth BT_Ant_isolation = %d\n",
2336 rtlpriv->btcoexist.bt_ant_isolation);
2337 rtl_dbg(rtlpriv, COMP_BT_COEXIST, DBG_TRACE,
2338 "BT_RadioSharedType = 0x%x\n",
2339 rtlpriv->btcoexist.bt_radio_shared_type);
2340 rtlpriv->btcoexist.bt_active_zero_cnt = 0;
2341 rtlpriv->btcoexist.cur_bt_disabled = false;
2342 rtlpriv->btcoexist.pre_bt_disabled = false;
2343 }
2344 }
2345
rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw * hw,bool auto_load_fail,u8 * hwinfo)2346 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw *hw,
2347 bool auto_load_fail, u8 *hwinfo)
2348 {
2349 struct rtl_priv *rtlpriv = rtl_priv(hw);
2350 u8 value;
2351 u32 tmpu_32;
2352
2353 if (!auto_load_fail) {
2354 tmpu_32 = rtl_read_dword(rtlpriv, REG_MULTI_FUNC_CTRL);
2355 if (tmpu_32 & BIT(18))
2356 rtlpriv->btcoexist.eeprom_bt_coexist = 1;
2357 else
2358 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2359 value = hwinfo[RF_OPTION4];
2360 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2361 rtlpriv->btcoexist.eeprom_bt_ant_num = (value & 0x1);
2362 rtlpriv->btcoexist.eeprom_bt_ant_isol = ((value & 0x10) >> 4);
2363 rtlpriv->btcoexist.eeprom_bt_radio_shared =
2364 ((value & 0x20) >> 5);
2365 } else {
2366 rtlpriv->btcoexist.eeprom_bt_coexist = 0;
2367 rtlpriv->btcoexist.eeprom_bt_type = BT_RTL8723A;
2368 rtlpriv->btcoexist.eeprom_bt_ant_num = ANT_X2;
2369 rtlpriv->btcoexist.eeprom_bt_ant_isol = 0;
2370 rtlpriv->btcoexist.eeprom_bt_radio_shared = BT_RADIO_SHARED;
2371 }
2372
2373 rtl8723e_bt_var_init(hw);
2374 }
2375
rtl8723e_bt_reg_init(struct ieee80211_hw * hw)2376 void rtl8723e_bt_reg_init(struct ieee80211_hw *hw)
2377 {
2378 struct rtl_priv *rtlpriv = rtl_priv(hw);
2379
2380 /* 0:Low, 1:High, 2:From Efuse. */
2381 rtlpriv->btcoexist.reg_bt_iso = 2;
2382 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2383 rtlpriv->btcoexist.reg_bt_sco = 3;
2384 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2385 rtlpriv->btcoexist.reg_bt_sco = 0;
2386 }
2387
rtl8723e_bt_hw_init(struct ieee80211_hw * hw)2388 void rtl8723e_bt_hw_init(struct ieee80211_hw *hw)
2389 {
2390 struct rtl_priv *rtlpriv = rtl_priv(hw);
2391
2392 if (rtlpriv->cfg->ops->get_btc_status())
2393 rtlpriv->btcoexist.btc_ops->btc_init_hw_config(rtlpriv);
2394 }
2395
rtl8723e_suspend(struct ieee80211_hw * hw)2396 void rtl8723e_suspend(struct ieee80211_hw *hw)
2397 {
2398 }
2399
rtl8723e_resume(struct ieee80211_hw * hw)2400 void rtl8723e_resume(struct ieee80211_hw *hw)
2401 {
2402 }
2403