1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc. 4 * Author: Joerg Roedel <jroedel@suse.de> 5 * Leo Duran <leo.duran@amd.com> 6 */ 7 8 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H 9 #define _ASM_X86_AMD_IOMMU_TYPES_H 10 11 #include <linux/bitfield.h> 12 #include <linux/iommu.h> 13 #include <linux/types.h> 14 #include <linux/mmu_notifier.h> 15 #include <linux/mutex.h> 16 #include <linux/msi.h> 17 #include <linux/list.h> 18 #include <linux/spinlock.h> 19 #include <linux/pci.h> 20 #include <linux/irqreturn.h> 21 #include <linux/io-pgtable.h> 22 23 /* 24 * Maximum number of IOMMUs supported 25 */ 26 #define MAX_IOMMUS 32 27 28 /* 29 * some size calculation constants 30 */ 31 #define DEV_TABLE_ENTRY_SIZE 32 32 #define ALIAS_TABLE_ENTRY_SIZE 2 33 #define RLOOKUP_TABLE_ENTRY_SIZE (sizeof(void *)) 34 35 /* Capability offsets used by the driver */ 36 #define MMIO_CAP_HDR_OFFSET 0x00 37 #define MMIO_RANGE_OFFSET 0x0c 38 #define MMIO_MISC_OFFSET 0x10 39 40 /* Masks, shifts and macros to parse the device range capability */ 41 #define MMIO_RANGE_LD_MASK 0xff000000 42 #define MMIO_RANGE_FD_MASK 0x00ff0000 43 #define MMIO_RANGE_BUS_MASK 0x0000ff00 44 #define MMIO_RANGE_LD_SHIFT 24 45 #define MMIO_RANGE_FD_SHIFT 16 46 #define MMIO_RANGE_BUS_SHIFT 8 47 #define MMIO_GET_LD(x) (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT) 48 #define MMIO_GET_FD(x) (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT) 49 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT) 50 #define MMIO_MSI_NUM(x) ((x) & 0x1f) 51 52 /* Flag masks for the AMD IOMMU exclusion range */ 53 #define MMIO_EXCL_ENABLE_MASK 0x01ULL 54 #define MMIO_EXCL_ALLOW_MASK 0x02ULL 55 56 /* Used offsets into the MMIO space */ 57 #define MMIO_DEV_TABLE_OFFSET 0x0000 58 #define MMIO_CMD_BUF_OFFSET 0x0008 59 #define MMIO_EVT_BUF_OFFSET 0x0010 60 #define MMIO_CONTROL_OFFSET 0x0018 61 #define MMIO_EXCL_BASE_OFFSET 0x0020 62 #define MMIO_EXCL_LIMIT_OFFSET 0x0028 63 #define MMIO_EXT_FEATURES 0x0030 64 #define MMIO_PPR_LOG_OFFSET 0x0038 65 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0 66 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8 67 #define MMIO_MSI_ADDR_LO_OFFSET 0x015C 68 #define MMIO_MSI_ADDR_HI_OFFSET 0x0160 69 #define MMIO_MSI_DATA_OFFSET 0x0164 70 #define MMIO_INTCAPXT_EVT_OFFSET 0x0170 71 #define MMIO_INTCAPXT_PPR_OFFSET 0x0178 72 #define MMIO_INTCAPXT_GALOG_OFFSET 0x0180 73 #define MMIO_EXT_FEATURES2 0x01A0 74 #define MMIO_CMD_HEAD_OFFSET 0x2000 75 #define MMIO_CMD_TAIL_OFFSET 0x2008 76 #define MMIO_EVT_HEAD_OFFSET 0x2010 77 #define MMIO_EVT_TAIL_OFFSET 0x2018 78 #define MMIO_STATUS_OFFSET 0x2020 79 #define MMIO_PPR_HEAD_OFFSET 0x2030 80 #define MMIO_PPR_TAIL_OFFSET 0x2038 81 #define MMIO_GA_HEAD_OFFSET 0x2040 82 #define MMIO_GA_TAIL_OFFSET 0x2048 83 #define MMIO_CNTR_CONF_OFFSET 0x4000 84 #define MMIO_CNTR_REG_OFFSET 0x40000 85 #define MMIO_REG_END_OFFSET 0x80000 86 87 88 89 /* Extended Feature Bits */ 90 #define FEATURE_PREFETCH BIT_ULL(0) 91 #define FEATURE_PPR BIT_ULL(1) 92 #define FEATURE_X2APIC BIT_ULL(2) 93 #define FEATURE_NX BIT_ULL(3) 94 #define FEATURE_GT BIT_ULL(4) 95 #define FEATURE_IA BIT_ULL(6) 96 #define FEATURE_GA BIT_ULL(7) 97 #define FEATURE_HE BIT_ULL(8) 98 #define FEATURE_PC BIT_ULL(9) 99 #define FEATURE_GATS GENMASK_ULL(13, 12) 100 #define FEATURE_GLX GENMASK_ULL(15, 14) 101 #define FEATURE_GAM_VAPIC BIT_ULL(21) 102 #define FEATURE_PASMAX GENMASK_ULL(36, 32) 103 #define FEATURE_GIOSUP BIT_ULL(48) 104 #define FEATURE_HASUP BIT_ULL(49) 105 #define FEATURE_EPHSUP BIT_ULL(50) 106 #define FEATURE_HDSUP BIT_ULL(52) 107 #define FEATURE_SNP BIT_ULL(63) 108 109 110 /* Extended Feature 2 Bits */ 111 #define FEATURE_SNPAVICSUP GENMASK_ULL(7, 5) 112 #define FEATURE_SNPAVICSUP_GAM(x) \ 113 (FIELD_GET(FEATURE_SNPAVICSUP, x) == 0x1) 114 115 /* Note: 116 * The current driver only support 16-bit PASID. 117 * Currently, hardware only implement upto 16-bit PASID 118 * even though the spec says it could have upto 20 bits. 119 */ 120 #define PASID_MASK 0x0000ffff 121 122 /* MMIO status bits */ 123 #define MMIO_STATUS_EVT_OVERFLOW_MASK BIT(0) 124 #define MMIO_STATUS_EVT_INT_MASK BIT(1) 125 #define MMIO_STATUS_COM_WAIT_INT_MASK BIT(2) 126 #define MMIO_STATUS_EVT_RUN_MASK BIT(3) 127 #define MMIO_STATUS_PPR_OVERFLOW_MASK BIT(5) 128 #define MMIO_STATUS_PPR_INT_MASK BIT(6) 129 #define MMIO_STATUS_PPR_RUN_MASK BIT(7) 130 #define MMIO_STATUS_GALOG_RUN_MASK BIT(8) 131 #define MMIO_STATUS_GALOG_OVERFLOW_MASK BIT(9) 132 #define MMIO_STATUS_GALOG_INT_MASK BIT(10) 133 134 /* event logging constants */ 135 #define EVENT_ENTRY_SIZE 0x10 136 #define EVENT_TYPE_SHIFT 28 137 #define EVENT_TYPE_MASK 0xf 138 #define EVENT_TYPE_ILL_DEV 0x1 139 #define EVENT_TYPE_IO_FAULT 0x2 140 #define EVENT_TYPE_DEV_TAB_ERR 0x3 141 #define EVENT_TYPE_PAGE_TAB_ERR 0x4 142 #define EVENT_TYPE_ILL_CMD 0x5 143 #define EVENT_TYPE_CMD_HARD_ERR 0x6 144 #define EVENT_TYPE_IOTLB_INV_TO 0x7 145 #define EVENT_TYPE_INV_DEV_REQ 0x8 146 #define EVENT_TYPE_INV_PPR_REQ 0x9 147 #define EVENT_TYPE_RMP_FAULT 0xd 148 #define EVENT_TYPE_RMP_HW_ERR 0xe 149 #define EVENT_DEVID_MASK 0xffff 150 #define EVENT_DEVID_SHIFT 0 151 #define EVENT_DOMID_MASK_LO 0xffff 152 #define EVENT_DOMID_MASK_HI 0xf0000 153 #define EVENT_FLAGS_MASK 0xfff 154 #define EVENT_FLAGS_SHIFT 0x10 155 #define EVENT_FLAG_RW 0x020 156 #define EVENT_FLAG_I 0x008 157 158 /* feature control bits */ 159 #define CONTROL_IOMMU_EN 0 160 #define CONTROL_HT_TUN_EN 1 161 #define CONTROL_EVT_LOG_EN 2 162 #define CONTROL_EVT_INT_EN 3 163 #define CONTROL_COMWAIT_EN 4 164 #define CONTROL_INV_TIMEOUT 5 165 #define CONTROL_PASSPW_EN 8 166 #define CONTROL_RESPASSPW_EN 9 167 #define CONTROL_COHERENT_EN 10 168 #define CONTROL_ISOC_EN 11 169 #define CONTROL_CMDBUF_EN 12 170 #define CONTROL_PPRLOG_EN 13 171 #define CONTROL_PPRINT_EN 14 172 #define CONTROL_PPR_EN 15 173 #define CONTROL_GT_EN 16 174 #define CONTROL_GA_EN 17 175 #define CONTROL_GAM_EN 25 176 #define CONTROL_GALOG_EN 28 177 #define CONTROL_GAINT_EN 29 178 #define CONTROL_XT_EN 50 179 #define CONTROL_INTCAPXT_EN 51 180 #define CONTROL_IRTCACHEDIS 59 181 #define CONTROL_SNPAVIC_EN 61 182 183 #define CTRL_INV_TO_MASK (7 << CONTROL_INV_TIMEOUT) 184 #define CTRL_INV_TO_NONE 0 185 #define CTRL_INV_TO_1MS 1 186 #define CTRL_INV_TO_10MS 2 187 #define CTRL_INV_TO_100MS 3 188 #define CTRL_INV_TO_1S 4 189 #define CTRL_INV_TO_10S 5 190 #define CTRL_INV_TO_100S 6 191 192 /* command specific defines */ 193 #define CMD_COMPL_WAIT 0x01 194 #define CMD_INV_DEV_ENTRY 0x02 195 #define CMD_INV_IOMMU_PAGES 0x03 196 #define CMD_INV_IOTLB_PAGES 0x04 197 #define CMD_INV_IRT 0x05 198 #define CMD_COMPLETE_PPR 0x07 199 #define CMD_INV_ALL 0x08 200 201 #define CMD_COMPL_WAIT_STORE_MASK 0x01 202 #define CMD_COMPL_WAIT_INT_MASK 0x02 203 #define CMD_INV_IOMMU_PAGES_SIZE_MASK 0x01 204 #define CMD_INV_IOMMU_PAGES_PDE_MASK 0x02 205 #define CMD_INV_IOMMU_PAGES_GN_MASK 0x04 206 207 #define PPR_STATUS_MASK 0xf 208 #define PPR_STATUS_SHIFT 12 209 210 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL 211 212 /* macros and definitions for device table entries */ 213 #define DEV_ENTRY_VALID 0x00 214 #define DEV_ENTRY_TRANSLATION 0x01 215 #define DEV_ENTRY_HAD 0x07 216 #define DEV_ENTRY_PPR 0x34 217 #define DEV_ENTRY_IR 0x3d 218 #define DEV_ENTRY_IW 0x3e 219 #define DEV_ENTRY_NO_PAGE_FAULT 0x62 220 #define DEV_ENTRY_EX 0x67 221 #define DEV_ENTRY_SYSMGT1 0x68 222 #define DEV_ENTRY_SYSMGT2 0x69 223 #define DEV_ENTRY_IRQ_TBL_EN 0x80 224 #define DEV_ENTRY_INIT_PASS 0xb8 225 #define DEV_ENTRY_EINT_PASS 0xb9 226 #define DEV_ENTRY_NMI_PASS 0xba 227 #define DEV_ENTRY_LINT0_PASS 0xbe 228 #define DEV_ENTRY_LINT1_PASS 0xbf 229 #define DEV_ENTRY_MODE_MASK 0x07 230 #define DEV_ENTRY_MODE_SHIFT 0x09 231 232 #define MAX_DEV_TABLE_ENTRIES 0xffff 233 234 /* constants to configure the command buffer */ 235 #define CMD_BUFFER_SIZE 8192 236 #define CMD_BUFFER_UNINITIALIZED 1 237 #define CMD_BUFFER_ENTRIES 512 238 #define MMIO_CMD_SIZE_SHIFT 56 239 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT) 240 241 /* constants for event buffer handling */ 242 #define EVT_BUFFER_SIZE 8192 /* 512 entries */ 243 #define EVT_LEN_MASK (0x9ULL << 56) 244 245 /* Constants for PPR Log handling */ 246 #define PPR_LOG_ENTRIES 512 247 #define PPR_LOG_SIZE_SHIFT 56 248 #define PPR_LOG_SIZE_512 (0x9ULL << PPR_LOG_SIZE_SHIFT) 249 #define PPR_ENTRY_SIZE 16 250 #define PPR_LOG_SIZE (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES) 251 252 /* PAGE_SERVICE_REQUEST PPR Log Buffer Entry flags */ 253 #define PPR_FLAG_EXEC 0x002 /* Execute permission requested */ 254 #define PPR_FLAG_READ 0x004 /* Read permission requested */ 255 #define PPR_FLAG_WRITE 0x020 /* Write permission requested */ 256 #define PPR_FLAG_US 0x040 /* 1: User, 0: Supervisor */ 257 #define PPR_FLAG_RVSD 0x080 /* Reserved bit not zero */ 258 #define PPR_FLAG_GN 0x100 /* GVA and PASID is valid */ 259 260 #define PPR_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 261 #define PPR_FLAGS(x) (((x) >> 48) & 0xfffULL) 262 #define PPR_DEVID(x) ((x) & 0xffffULL) 263 #define PPR_TAG(x) (((x) >> 32) & 0x3ffULL) 264 #define PPR_PASID1(x) (((x) >> 16) & 0xffffULL) 265 #define PPR_PASID2(x) (((x) >> 42) & 0xfULL) 266 #define PPR_PASID(x) ((PPR_PASID2(x) << 16) | PPR_PASID1(x)) 267 268 #define PPR_REQ_FAULT 0x01 269 270 /* Constants for GA Log handling */ 271 #define GA_LOG_ENTRIES 512 272 #define GA_LOG_SIZE_SHIFT 56 273 #define GA_LOG_SIZE_512 (0x8ULL << GA_LOG_SIZE_SHIFT) 274 #define GA_ENTRY_SIZE 8 275 #define GA_LOG_SIZE (GA_ENTRY_SIZE * GA_LOG_ENTRIES) 276 277 #define GA_TAG(x) (u32)(x & 0xffffffffULL) 278 #define GA_DEVID(x) (u16)(((x) >> 32) & 0xffffULL) 279 #define GA_REQ_TYPE(x) (((x) >> 60) & 0xfULL) 280 281 #define GA_GUEST_NR 0x1 282 283 #define IOMMU_IN_ADDR_BIT_SIZE 52 284 #define IOMMU_OUT_ADDR_BIT_SIZE 52 285 286 /* 287 * This bitmap is used to advertise the page sizes our hardware support 288 * to the IOMMU core, which will then use this information to split 289 * physically contiguous memory regions it is mapping into page sizes 290 * that we support. 291 * 292 * 512GB Pages are not supported due to a hardware bug 293 * Page sizes >= the 52 bit max physical address of the CPU are not supported. 294 */ 295 #define AMD_IOMMU_PGSIZES (GENMASK_ULL(51, 12) ^ SZ_512G) 296 297 /* Special mode where page-sizes are limited to 4 KiB */ 298 #define AMD_IOMMU_PGSIZES_4K (PAGE_SIZE) 299 300 /* 4K, 2MB, 1G page sizes are supported */ 301 #define AMD_IOMMU_PGSIZES_V2 (PAGE_SIZE | (1ULL << 21) | (1ULL << 30)) 302 303 /* Bit value definition for dte irq remapping fields*/ 304 #define DTE_IRQ_PHYS_ADDR_MASK GENMASK_ULL(51, 6) 305 #define DTE_IRQ_REMAP_INTCTL_MASK (0x3ULL << 60) 306 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60) 307 #define DTE_IRQ_REMAP_ENABLE 1ULL 308 309 /* 310 * AMD IOMMU hardware only support 512 IRTEs despite 311 * the architectural limitation of 2048 entries. 312 */ 313 #define DTE_INTTAB_ALIGNMENT 128 314 #define DTE_INTTABLEN_VALUE 9ULL 315 #define DTE_INTTABLEN (DTE_INTTABLEN_VALUE << 1) 316 #define DTE_INTTABLEN_MASK (0xfULL << 1) 317 #define MAX_IRQS_PER_TABLE (1 << DTE_INTTABLEN_VALUE) 318 319 #define PAGE_MODE_NONE 0x00 320 #define PAGE_MODE_1_LEVEL 0x01 321 #define PAGE_MODE_2_LEVEL 0x02 322 #define PAGE_MODE_3_LEVEL 0x03 323 #define PAGE_MODE_4_LEVEL 0x04 324 #define PAGE_MODE_5_LEVEL 0x05 325 #define PAGE_MODE_6_LEVEL 0x06 326 #define PAGE_MODE_7_LEVEL 0x07 327 328 #define GUEST_PGTABLE_4_LEVEL 0x00 329 #define GUEST_PGTABLE_5_LEVEL 0x01 330 331 #define PM_LEVEL_SHIFT(x) (12 + ((x) * 9)) 332 #define PM_LEVEL_SIZE(x) (((x) < 6) ? \ 333 ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \ 334 (0xffffffffffffffffULL)) 335 #define PM_LEVEL_INDEX(x, a) (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL) 336 #define PM_LEVEL_ENC(x) (((x) << 9) & 0xe00ULL) 337 #define PM_LEVEL_PDE(x, a) ((a) | PM_LEVEL_ENC((x)) | \ 338 IOMMU_PTE_PR | IOMMU_PTE_IR | IOMMU_PTE_IW) 339 #define PM_PTE_LEVEL(pte) (((pte) >> 9) & 0x7ULL) 340 341 #define PM_MAP_4k 0 342 #define PM_ADDR_MASK 0x000ffffffffff000ULL 343 #define PM_MAP_MASK(lvl) (PM_ADDR_MASK & \ 344 (~((1ULL << (12 + ((lvl) * 9))) - 1))) 345 #define PM_ALIGNED(lvl, addr) ((PM_MAP_MASK(lvl) & (addr)) == (addr)) 346 347 /* 348 * Returns the page table level to use for a given page size 349 * Pagesize is expected to be a power-of-two 350 */ 351 #define PAGE_SIZE_LEVEL(pagesize) \ 352 ((__ffs(pagesize) - 12) / 9) 353 /* 354 * Returns the number of ptes to use for a given page size 355 * Pagesize is expected to be a power-of-two 356 */ 357 #define PAGE_SIZE_PTE_COUNT(pagesize) \ 358 (1ULL << ((__ffs(pagesize) - 12) % 9)) 359 360 /* 361 * Aligns a given io-virtual address to a given page size 362 * Pagesize is expected to be a power-of-two 363 */ 364 #define PAGE_SIZE_ALIGN(address, pagesize) \ 365 ((address) & ~((pagesize) - 1)) 366 /* 367 * Creates an IOMMU PTE for an address and a given pagesize 368 * The PTE has no permission bits set 369 * Pagesize is expected to be a power-of-two larger than 4096 370 */ 371 #define PAGE_SIZE_PTE(address, pagesize) \ 372 (((address) | ((pagesize) - 1)) & \ 373 (~(pagesize >> 1)) & PM_ADDR_MASK) 374 375 /* 376 * Takes a PTE value with mode=0x07 and returns the page size it maps 377 */ 378 #define PTE_PAGE_SIZE(pte) \ 379 (1ULL << (1 + ffz(((pte) | 0xfffULL)))) 380 381 /* 382 * Takes a page-table level and returns the default page-size for this level 383 */ 384 #define PTE_LEVEL_PAGE_SIZE(level) \ 385 (1ULL << (12 + (9 * (level)))) 386 387 /* 388 * The IOPTE dirty bit 389 */ 390 #define IOMMU_PTE_HD_BIT (6) 391 392 /* 393 * Bit value definition for I/O PTE fields 394 */ 395 #define IOMMU_PTE_PR BIT_ULL(0) 396 #define IOMMU_PTE_HD BIT_ULL(IOMMU_PTE_HD_BIT) 397 #define IOMMU_PTE_U BIT_ULL(59) 398 #define IOMMU_PTE_FC BIT_ULL(60) 399 #define IOMMU_PTE_IR BIT_ULL(61) 400 #define IOMMU_PTE_IW BIT_ULL(62) 401 402 /* 403 * Bit value definition for DTE fields 404 */ 405 #define DTE_FLAG_V BIT_ULL(0) 406 #define DTE_FLAG_TV BIT_ULL(1) 407 #define DTE_FLAG_HAD (3ULL << 7) 408 #define DTE_FLAG_GIOV BIT_ULL(54) 409 #define DTE_FLAG_GV BIT_ULL(55) 410 #define DTE_GLX_SHIFT (56) 411 #define DTE_GLX_MASK (3) 412 #define DTE_FLAG_IR BIT_ULL(61) 413 #define DTE_FLAG_IW BIT_ULL(62) 414 415 #define DTE_FLAG_IOTLB BIT_ULL(32) 416 #define DTE_FLAG_MASK (0x3ffULL << 32) 417 #define DEV_DOMID_MASK 0xffffULL 418 419 #define DTE_GCR3_VAL_A(x) (((x) >> 12) & 0x00007ULL) 420 #define DTE_GCR3_VAL_B(x) (((x) >> 15) & 0x0ffffULL) 421 #define DTE_GCR3_VAL_C(x) (((x) >> 31) & 0x1fffffULL) 422 423 #define DTE_GCR3_SHIFT_A 58 424 #define DTE_GCR3_SHIFT_B 16 425 #define DTE_GCR3_SHIFT_C 43 426 427 #define DTE_GPT_LEVEL_SHIFT 54 428 429 #define GCR3_VALID 0x01ULL 430 431 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL) 432 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_PR) 433 #define IOMMU_PTE_DIRTY(pte) ((pte) & IOMMU_PTE_HD) 434 #define IOMMU_PTE_PAGE(pte) (iommu_phys_to_virt((pte) & IOMMU_PAGE_MASK)) 435 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07) 436 437 #define IOMMU_PROT_MASK 0x03 438 #define IOMMU_PROT_IR 0x01 439 #define IOMMU_PROT_IW 0x02 440 441 #define IOMMU_UNITY_MAP_FLAG_EXCL_RANGE (1 << 2) 442 443 /* IOMMU capabilities */ 444 #define IOMMU_CAP_IOTLB 24 445 #define IOMMU_CAP_NPCACHE 26 446 #define IOMMU_CAP_EFR 27 447 448 /* IOMMU IVINFO */ 449 #define IOMMU_IVINFO_OFFSET 36 450 #define IOMMU_IVINFO_EFRSUP BIT(0) 451 #define IOMMU_IVINFO_DMA_REMAP BIT(1) 452 453 /* IOMMU Feature Reporting Field (for IVHD type 10h */ 454 #define IOMMU_FEAT_GASUP_SHIFT 6 455 456 /* IOMMU Extended Feature Register (EFR) */ 457 #define IOMMU_EFR_XTSUP_SHIFT 2 458 #define IOMMU_EFR_GASUP_SHIFT 7 459 #define IOMMU_EFR_MSICAPMMIOSUP_SHIFT 46 460 461 #define MAX_DOMAIN_ID 65536 462 463 /* Timeout stuff */ 464 #define LOOP_TIMEOUT 100000 465 #define MMIO_STATUS_TIMEOUT 2000000 466 467 extern bool amd_iommu_dump; 468 #define DUMP_printk(format, arg...) \ 469 do { \ 470 if (amd_iommu_dump) \ 471 pr_info("AMD-Vi: " format, ## arg); \ 472 } while(0); 473 474 /* global flag if IOMMUs cache non-present entries */ 475 extern bool amd_iommu_np_cache; 476 /* Only true if all IOMMUs support device IOTLBs */ 477 extern bool amd_iommu_iotlb_sup; 478 479 struct irq_remap_table { 480 raw_spinlock_t lock; 481 unsigned min_index; 482 u32 *table; 483 }; 484 485 /* Interrupt remapping feature used? */ 486 extern bool amd_iommu_irq_remap; 487 488 extern const struct iommu_ops amd_iommu_ops; 489 490 /* IVRS indicates that pre-boot remapping was enabled */ 491 extern bool amdr_ivrs_remap_support; 492 493 /* kmem_cache to get tables with 128 byte alignement */ 494 extern struct kmem_cache *amd_iommu_irq_cache; 495 496 #define PCI_SBDF_TO_SEGID(sbdf) (((sbdf) >> 16) & 0xffff) 497 #define PCI_SBDF_TO_DEVID(sbdf) ((sbdf) & 0xffff) 498 #define PCI_SEG_DEVID_TO_SBDF(seg, devid) ((((u32)(seg) & 0xffff) << 16) | \ 499 ((devid) & 0xffff)) 500 501 /* Make iterating over all pci segment easier */ 502 #define for_each_pci_segment(pci_seg) \ 503 list_for_each_entry((pci_seg), &amd_iommu_pci_seg_list, list) 504 #define for_each_pci_segment_safe(pci_seg, next) \ 505 list_for_each_entry_safe((pci_seg), (next), &amd_iommu_pci_seg_list, list) 506 /* 507 * Make iterating over all IOMMUs easier 508 */ 509 #define for_each_iommu(iommu) \ 510 list_for_each_entry((iommu), &amd_iommu_list, list) 511 #define for_each_iommu_safe(iommu, next) \ 512 list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list) 513 /* Making iterating over protection_domain->dev_data_list easier */ 514 #define for_each_pdom_dev_data(pdom_dev_data, pdom) \ 515 list_for_each_entry(pdom_dev_data, &pdom->dev_data_list, list) 516 #define for_each_pdom_dev_data_safe(pdom_dev_data, next, pdom) \ 517 list_for_each_entry_safe((pdom_dev_data), (next), &pdom->dev_data_list, list) 518 519 struct amd_iommu; 520 struct iommu_domain; 521 struct irq_domain; 522 struct amd_irte_ops; 523 524 #define AMD_IOMMU_FLAG_TRANS_PRE_ENABLED (1 << 0) 525 526 #define io_pgtable_to_data(x) \ 527 container_of((x), struct amd_io_pgtable, pgtbl) 528 529 #define io_pgtable_ops_to_data(x) \ 530 io_pgtable_to_data(io_pgtable_ops_to_pgtable(x)) 531 532 #define io_pgtable_ops_to_domain(x) \ 533 container_of(io_pgtable_ops_to_data(x), \ 534 struct protection_domain, iop) 535 536 #define io_pgtable_cfg_to_data(x) \ 537 container_of((x), struct amd_io_pgtable, pgtbl.cfg) 538 539 struct gcr3_tbl_info { 540 u64 *gcr3_tbl; /* Guest CR3 table */ 541 int glx; /* Number of levels for GCR3 table */ 542 u32 pasid_cnt; /* Track attached PASIDs */ 543 u16 domid; /* Per device domain ID */ 544 }; 545 546 struct amd_io_pgtable { 547 struct io_pgtable pgtbl; 548 int mode; 549 u64 *root; 550 u64 *pgd; /* v2 pgtable pgd pointer */ 551 }; 552 553 enum protection_domain_mode { 554 PD_MODE_V1 = 1, 555 PD_MODE_V2, 556 }; 557 558 /* Track dev_data/PASID list for the protection domain */ 559 struct pdom_dev_data { 560 /* Points to attached device data */ 561 struct iommu_dev_data *dev_data; 562 /* PASID attached to the protection domain */ 563 ioasid_t pasid; 564 /* For protection_domain->dev_data_list */ 565 struct list_head list; 566 }; 567 568 /* 569 * This structure contains generic data for IOMMU protection domains 570 * independent of their use. 571 */ 572 struct protection_domain { 573 struct list_head dev_list; /* List of all devices in this domain */ 574 struct iommu_domain domain; /* generic domain handle used by 575 iommu core code */ 576 struct amd_io_pgtable iop; 577 spinlock_t lock; /* mostly used to lock the page table*/ 578 u16 id; /* the domain id written to the device table */ 579 enum protection_domain_mode pd_mode; /* Track page table type */ 580 bool dirty_tracking; /* dirty tracking is enabled in the domain */ 581 unsigned dev_cnt; /* devices assigned to this domain */ 582 unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */ 583 584 struct mmu_notifier mn; /* mmu notifier for the SVA domain */ 585 struct list_head dev_data_list; /* List of pdom_dev_data */ 586 }; 587 588 /* 589 * This structure contains information about one PCI segment in the system. 590 */ 591 struct amd_iommu_pci_seg { 592 /* List with all PCI segments in the system */ 593 struct list_head list; 594 595 /* List of all available dev_data structures */ 596 struct llist_head dev_data_list; 597 598 /* PCI segment number */ 599 u16 id; 600 601 /* Largest PCI device id we expect translation requests for */ 602 u16 last_bdf; 603 604 /* Size of the device table */ 605 u32 dev_table_size; 606 607 /* Size of the alias table */ 608 u32 alias_table_size; 609 610 /* Size of the rlookup table */ 611 u32 rlookup_table_size; 612 613 /* 614 * device table virtual address 615 * 616 * Pointer to the per PCI segment device table. 617 * It is indexed by the PCI device id or the HT unit id and contains 618 * information about the domain the device belongs to as well as the 619 * page table root pointer. 620 */ 621 struct dev_table_entry *dev_table; 622 623 /* 624 * The rlookup iommu table is used to find the IOMMU which is 625 * responsible for a specific device. It is indexed by the PCI 626 * device id. 627 */ 628 struct amd_iommu **rlookup_table; 629 630 /* 631 * This table is used to find the irq remapping table for a given 632 * device id quickly. 633 */ 634 struct irq_remap_table **irq_lookup_table; 635 636 /* 637 * Pointer to a device table which the content of old device table 638 * will be copied to. It's only be used in kdump kernel. 639 */ 640 struct dev_table_entry *old_dev_tbl_cpy; 641 642 /* 643 * The alias table is a driver specific data structure which contains the 644 * mappings of the PCI device ids to the actual requestor ids on the IOMMU. 645 * More than one device can share the same requestor id. 646 */ 647 u16 *alias_table; 648 649 /* 650 * A list of required unity mappings we find in ACPI. It is not locked 651 * because as runtime it is only read. It is created at ACPI table 652 * parsing time. 653 */ 654 struct list_head unity_map; 655 }; 656 657 /* 658 * Structure where we save information about one hardware AMD IOMMU in the 659 * system. 660 */ 661 struct amd_iommu { 662 struct list_head list; 663 664 /* Index within the IOMMU array */ 665 int index; 666 667 /* locks the accesses to the hardware */ 668 raw_spinlock_t lock; 669 670 /* Pointer to PCI device of this IOMMU */ 671 struct pci_dev *dev; 672 673 /* Cache pdev to root device for resume quirks */ 674 struct pci_dev *root_pdev; 675 676 /* physical address of MMIO space */ 677 u64 mmio_phys; 678 679 /* physical end address of MMIO space */ 680 u64 mmio_phys_end; 681 682 /* virtual address of MMIO space */ 683 u8 __iomem *mmio_base; 684 685 /* capabilities of that IOMMU read from ACPI */ 686 u32 cap; 687 688 /* flags read from acpi table */ 689 u8 acpi_flags; 690 691 /* Extended features */ 692 u64 features; 693 694 /* Extended features 2 */ 695 u64 features2; 696 697 /* PCI device id of the IOMMU device */ 698 u16 devid; 699 700 /* 701 * Capability pointer. There could be more than one IOMMU per PCI 702 * device function if there are more than one AMD IOMMU capability 703 * pointers. 704 */ 705 u16 cap_ptr; 706 707 /* pci domain of this IOMMU */ 708 struct amd_iommu_pci_seg *pci_seg; 709 710 /* start of exclusion range of that IOMMU */ 711 u64 exclusion_start; 712 /* length of exclusion range of that IOMMU */ 713 u64 exclusion_length; 714 715 /* command buffer virtual address */ 716 u8 *cmd_buf; 717 u32 cmd_buf_head; 718 u32 cmd_buf_tail; 719 720 /* event buffer virtual address */ 721 u8 *evt_buf; 722 723 /* Name for event log interrupt */ 724 unsigned char evt_irq_name[16]; 725 726 /* Base of the PPR log, if present */ 727 u8 *ppr_log; 728 729 /* Name for PPR log interrupt */ 730 unsigned char ppr_irq_name[16]; 731 732 /* Base of the GA log, if present */ 733 u8 *ga_log; 734 735 /* Name for GA log interrupt */ 736 unsigned char ga_irq_name[16]; 737 738 /* Tail of the GA log, if present */ 739 u8 *ga_log_tail; 740 741 /* true if interrupts for this IOMMU are already enabled */ 742 bool int_enabled; 743 744 /* if one, we need to send a completion wait command */ 745 bool need_sync; 746 747 /* true if disable irte caching */ 748 bool irtcachedis_enabled; 749 750 /* Handle for IOMMU core code */ 751 struct iommu_device iommu; 752 753 /* 754 * We can't rely on the BIOS to restore all values on reinit, so we 755 * need to stash them 756 */ 757 758 /* The iommu BAR */ 759 u32 stored_addr_lo; 760 u32 stored_addr_hi; 761 762 /* 763 * Each iommu has 6 l1s, each of which is documented as having 0x12 764 * registers 765 */ 766 u32 stored_l1[6][0x12]; 767 768 /* The l2 indirect registers */ 769 u32 stored_l2[0x83]; 770 771 /* The maximum PC banks and counters/bank (PCSup=1) */ 772 u8 max_banks; 773 u8 max_counters; 774 #ifdef CONFIG_IRQ_REMAP 775 struct irq_domain *ir_domain; 776 777 struct amd_irte_ops *irte_ops; 778 #endif 779 780 u32 flags; 781 volatile u64 *cmd_sem; 782 atomic64_t cmd_sem_val; 783 784 #ifdef CONFIG_AMD_IOMMU_DEBUGFS 785 /* DebugFS Info */ 786 struct dentry *debugfs; 787 #endif 788 789 /* IOPF support */ 790 struct iopf_queue *iopf_queue; 791 unsigned char iopfq_name[32]; 792 }; 793 dev_to_amd_iommu(struct device * dev)794 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev) 795 { 796 struct iommu_device *iommu = dev_to_iommu_device(dev); 797 798 return container_of(iommu, struct amd_iommu, iommu); 799 } 800 801 #define ACPIHID_UID_LEN 256 802 #define ACPIHID_HID_LEN 9 803 804 struct acpihid_map_entry { 805 struct list_head list; 806 u8 uid[ACPIHID_UID_LEN]; 807 u8 hid[ACPIHID_HID_LEN]; 808 u32 devid; 809 u32 root_devid; 810 bool cmd_line; 811 struct iommu_group *group; 812 }; 813 814 struct devid_map { 815 struct list_head list; 816 u8 id; 817 u32 devid; 818 bool cmd_line; 819 }; 820 821 #define AMD_IOMMU_DEVICE_FLAG_ATS_SUP 0x1 /* ATS feature supported */ 822 #define AMD_IOMMU_DEVICE_FLAG_PRI_SUP 0x2 /* PRI feature supported */ 823 #define AMD_IOMMU_DEVICE_FLAG_PASID_SUP 0x4 /* PASID context supported */ 824 /* Device may request execution on memory pages */ 825 #define AMD_IOMMU_DEVICE_FLAG_EXEC_SUP 0x8 826 /* Device may request super-user privileges */ 827 #define AMD_IOMMU_DEVICE_FLAG_PRIV_SUP 0x10 828 829 /* 830 * This struct contains device specific data for the IOMMU 831 */ 832 struct iommu_dev_data { 833 /*Protect against attach/detach races */ 834 spinlock_t lock; 835 836 struct list_head list; /* For domain->dev_list */ 837 struct llist_node dev_data_list; /* For global dev_data_list */ 838 struct protection_domain *domain; /* Domain the device is bound to */ 839 struct gcr3_tbl_info gcr3_info; /* Per-device GCR3 table */ 840 struct device *dev; 841 u16 devid; /* PCI Device ID */ 842 843 u32 max_pasids; /* Max supported PASIDs */ 844 u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */ 845 int ats_qdep; 846 u8 ats_enabled :1; /* ATS state */ 847 u8 pri_enabled :1; /* PRI state */ 848 u8 pasid_enabled:1; /* PASID state */ 849 u8 pri_tlp :1; /* PASID TLB required for 850 PPR completions */ 851 u8 ppr :1; /* Enable device PPR support */ 852 bool use_vapic; /* Enable device to use vapic mode */ 853 bool defer_attach; 854 855 struct ratelimit_state rs; /* Ratelimit IOPF messages */ 856 }; 857 858 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */ 859 extern struct list_head ioapic_map; 860 extern struct list_head hpet_map; 861 extern struct list_head acpihid_map; 862 863 /* 864 * List with all PCI segments in the system. This list is not locked because 865 * it is only written at driver initialization time 866 */ 867 extern struct list_head amd_iommu_pci_seg_list; 868 869 /* 870 * List with all IOMMUs in the system. This list is not locked because it is 871 * only written and read at driver initialization or suspend time 872 */ 873 extern struct list_head amd_iommu_list; 874 875 /* 876 * Array with pointers to each IOMMU struct 877 * The indices are referenced in the protection domains 878 */ 879 extern struct amd_iommu *amd_iommus[MAX_IOMMUS]; 880 881 /* 882 * Structure defining one entry in the device table 883 */ 884 struct dev_table_entry { 885 u64 data[4]; 886 }; 887 888 /* 889 * One entry for unity mappings parsed out of the ACPI table. 890 */ 891 struct unity_map_entry { 892 struct list_head list; 893 894 /* starting device id this entry is used for (including) */ 895 u16 devid_start; 896 /* end device id this entry is used for (including) */ 897 u16 devid_end; 898 899 /* start address to unity map (including) */ 900 u64 address_start; 901 /* end address to unity map (including) */ 902 u64 address_end; 903 904 /* required protection */ 905 int prot; 906 }; 907 908 /* 909 * Data structures for device handling 910 */ 911 912 /* size of the dma_ops aperture as power of 2 */ 913 extern unsigned amd_iommu_aperture_order; 914 915 /* allocation bitmap for domain ids */ 916 extern unsigned long *amd_iommu_pd_alloc_bitmap; 917 918 extern bool amd_iommu_force_isolation; 919 920 /* Max levels of glxval supported */ 921 extern int amd_iommu_max_glx_val; 922 923 /* Global EFR and EFR2 registers */ 924 extern u64 amd_iommu_efr; 925 extern u64 amd_iommu_efr2; 926 get_ioapic_devid(int id)927 static inline int get_ioapic_devid(int id) 928 { 929 struct devid_map *entry; 930 931 list_for_each_entry(entry, &ioapic_map, list) { 932 if (entry->id == id) 933 return entry->devid; 934 } 935 936 return -EINVAL; 937 } 938 get_hpet_devid(int id)939 static inline int get_hpet_devid(int id) 940 { 941 struct devid_map *entry; 942 943 list_for_each_entry(entry, &hpet_map, list) { 944 if (entry->id == id) 945 return entry->devid; 946 } 947 948 return -EINVAL; 949 } 950 951 enum amd_iommu_intr_mode_type { 952 AMD_IOMMU_GUEST_IR_LEGACY, 953 954 /* This mode is not visible to users. It is used when 955 * we cannot fully enable vAPIC and fallback to only support 956 * legacy interrupt remapping via 128-bit IRTE. 957 */ 958 AMD_IOMMU_GUEST_IR_LEGACY_GA, 959 AMD_IOMMU_GUEST_IR_VAPIC, 960 }; 961 962 #define AMD_IOMMU_GUEST_IR_GA(x) (x == AMD_IOMMU_GUEST_IR_VAPIC || \ 963 x == AMD_IOMMU_GUEST_IR_LEGACY_GA) 964 965 #define AMD_IOMMU_GUEST_IR_VAPIC(x) (x == AMD_IOMMU_GUEST_IR_VAPIC) 966 967 union irte { 968 u32 val; 969 struct { 970 u32 valid : 1, 971 no_fault : 1, 972 int_type : 3, 973 rq_eoi : 1, 974 dm : 1, 975 rsvd_1 : 1, 976 destination : 8, 977 vector : 8, 978 rsvd_2 : 8; 979 } fields; 980 }; 981 982 #define APICID_TO_IRTE_DEST_LO(x) (x & 0xffffff) 983 #define APICID_TO_IRTE_DEST_HI(x) ((x >> 24) & 0xff) 984 985 union irte_ga_lo { 986 u64 val; 987 988 /* For int remapping */ 989 struct { 990 u64 valid : 1, 991 no_fault : 1, 992 /* ------ */ 993 int_type : 3, 994 rq_eoi : 1, 995 dm : 1, 996 /* ------ */ 997 guest_mode : 1, 998 destination : 24, 999 ga_tag : 32; 1000 } fields_remap; 1001 1002 /* For guest vAPIC */ 1003 struct { 1004 u64 valid : 1, 1005 no_fault : 1, 1006 /* ------ */ 1007 ga_log_intr : 1, 1008 rsvd1 : 3, 1009 is_run : 1, 1010 /* ------ */ 1011 guest_mode : 1, 1012 destination : 24, 1013 ga_tag : 32; 1014 } fields_vapic; 1015 }; 1016 1017 union irte_ga_hi { 1018 u64 val; 1019 struct { 1020 u64 vector : 8, 1021 rsvd_1 : 4, 1022 ga_root_ptr : 40, 1023 rsvd_2 : 4, 1024 destination : 8; 1025 } fields; 1026 }; 1027 1028 struct irte_ga { 1029 union { 1030 struct { 1031 union irte_ga_lo lo; 1032 union irte_ga_hi hi; 1033 }; 1034 u128 irte; 1035 }; 1036 }; 1037 1038 struct irq_2_irte { 1039 u16 devid; /* Device ID for IRTE table */ 1040 u16 index; /* Index into IRTE table*/ 1041 }; 1042 1043 struct amd_ir_data { 1044 u32 cached_ga_tag; 1045 struct amd_iommu *iommu; 1046 struct irq_2_irte irq_2_irte; 1047 struct msi_msg msi_entry; 1048 void *entry; /* Pointer to union irte or struct irte_ga */ 1049 1050 /** 1051 * Store information for activate/de-activate 1052 * Guest virtual APIC mode during runtime. 1053 */ 1054 struct irq_cfg *cfg; 1055 int ga_vector; 1056 u64 ga_root_ptr; 1057 u32 ga_tag; 1058 }; 1059 1060 struct amd_irte_ops { 1061 void (*prepare)(void *, u32, bool, u8, u32, int); 1062 void (*activate)(struct amd_iommu *iommu, void *, u16, u16); 1063 void (*deactivate)(struct amd_iommu *iommu, void *, u16, u16); 1064 void (*set_affinity)(struct amd_iommu *iommu, void *, u16, u16, u8, u32); 1065 void *(*get)(struct irq_remap_table *, int); 1066 void (*set_allocated)(struct irq_remap_table *, int); 1067 bool (*is_allocated)(struct irq_remap_table *, int); 1068 void (*clear_allocated)(struct irq_remap_table *, int); 1069 }; 1070 1071 #ifdef CONFIG_IRQ_REMAP 1072 extern struct amd_irte_ops irte_32_ops; 1073 extern struct amd_irte_ops irte_128_ops; 1074 #endif 1075 1076 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */ 1077