1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include "amdgpu.h"
27 #include "amdgpu_smu.h"
28 #include "smu_v12_0_ppsmc.h"
29 #include "smu12_driver_if.h"
30 #include "smu_v12_0.h"
31 #include "renoir_ppt.h"
32 #include "smu_cmn.h"
33
34 /*
35 * DO NOT use these for err/warn/info/debug messages.
36 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
37 * They are more MGPU friendly.
38 */
39 #undef pr_err
40 #undef pr_warn
41 #undef pr_info
42 #undef pr_debug
43
44 #define mmMP1_SMN_C2PMSG_66 0x0282
45 #define mmMP1_SMN_C2PMSG_66_BASE_IDX 0
46
47 #define mmMP1_SMN_C2PMSG_82 0x0292
48 #define mmMP1_SMN_C2PMSG_82_BASE_IDX 0
49
50 #define mmMP1_SMN_C2PMSG_90 0x029a
51 #define mmMP1_SMN_C2PMSG_90_BASE_IDX 0
52
53 static struct cmn2asic_msg_mapping renoir_message_map[SMU_MSG_MAX_COUNT] = {
54 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
55 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
56 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
57 MSG_MAP(PowerUpGfx, PPSMC_MSG_PowerUpGfx, 1),
58 MSG_MAP(AllowGfxOff, PPSMC_MSG_EnableGfxOff, 1),
59 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisableGfxOff, 1),
60 MSG_MAP(PowerDownIspByTile, PPSMC_MSG_PowerDownIspByTile, 1),
61 MSG_MAP(PowerUpIspByTile, PPSMC_MSG_PowerUpIspByTile, 1),
62 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 1),
63 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 1),
64 MSG_MAP(PowerDownSdma, PPSMC_MSG_PowerDownSdma, 1),
65 MSG_MAP(PowerUpSdma, PPSMC_MSG_PowerUpSdma, 1),
66 MSG_MAP(SetHardMinIspclkByFreq, PPSMC_MSG_SetHardMinIspclkByFreq, 1),
67 MSG_MAP(SetHardMinVcn, PPSMC_MSG_SetHardMinVcn, 1),
68 MSG_MAP(SetAllowFclkSwitch, PPSMC_MSG_SetAllowFclkSwitch, 1),
69 MSG_MAP(SetMinVideoGfxclkFreq, PPSMC_MSG_SetMinVideoGfxclkFreq, 1),
70 MSG_MAP(ActiveProcessNotify, PPSMC_MSG_ActiveProcessNotify, 1),
71 MSG_MAP(SetCustomPolicy, PPSMC_MSG_SetCustomPolicy, 1),
72 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 1),
73 MSG_MAP(NumOfDisplays, PPSMC_MSG_SetDisplayCount, 1),
74 MSG_MAP(QueryPowerLimit, PPSMC_MSG_QueryPowerLimit, 1),
75 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
76 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
77 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
78 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 1),
79 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDeviceDriverReset, 1),
80 MSG_MAP(SetGfxclkOverdriveByFreqVid, PPSMC_MSG_SetGfxclkOverdriveByFreqVid, 1),
81 MSG_MAP(SetHardMinDcfclkByFreq, PPSMC_MSG_SetHardMinDcfclkByFreq, 1),
82 MSG_MAP(SetHardMinSocclkByFreq, PPSMC_MSG_SetHardMinSocclkByFreq, 1),
83 MSG_MAP(ControlIgpuATS, PPSMC_MSG_ControlIgpuATS, 1),
84 MSG_MAP(SetMinVideoFclkFreq, PPSMC_MSG_SetMinVideoFclkFreq, 1),
85 MSG_MAP(SetMinDeepSleepDcfclk, PPSMC_MSG_SetMinDeepSleepDcfclk, 1),
86 MSG_MAP(ForcePowerDownGfx, PPSMC_MSG_ForcePowerDownGfx, 1),
87 MSG_MAP(SetPhyclkVoltageByFreq, PPSMC_MSG_SetPhyclkVoltageByFreq, 1),
88 MSG_MAP(SetDppclkVoltageByFreq, PPSMC_MSG_SetDppclkVoltageByFreq, 1),
89 MSG_MAP(SetSoftMinVcn, PPSMC_MSG_SetSoftMinVcn, 1),
90 MSG_MAP(EnablePostCode, PPSMC_MSG_EnablePostCode, 1),
91 MSG_MAP(GetGfxclkFrequency, PPSMC_MSG_GetGfxclkFrequency, 1),
92 MSG_MAP(GetFclkFrequency, PPSMC_MSG_GetFclkFrequency, 1),
93 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxclkFrequency, 1),
94 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxclkFrequency, 1),
95 MSG_MAP(SoftReset, PPSMC_MSG_SoftReset, 1),
96 MSG_MAP(SetGfxCGPG, PPSMC_MSG_SetGfxCGPG, 1),
97 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
98 MSG_MAP(SetHardMinGfxClk, PPSMC_MSG_SetHardMinGfxClk, 1),
99 MSG_MAP(SetSoftMaxSocclkByFreq, PPSMC_MSG_SetSoftMaxSocclkByFreq, 1),
100 MSG_MAP(SetSoftMaxFclkByFreq, PPSMC_MSG_SetSoftMaxFclkByFreq, 1),
101 MSG_MAP(SetSoftMaxVcn, PPSMC_MSG_SetSoftMaxVcn, 1),
102 MSG_MAP(PowerGateMmHub, PPSMC_MSG_PowerGateMmHub, 1),
103 MSG_MAP(UpdatePmeRestore, PPSMC_MSG_UpdatePmeRestore, 1),
104 MSG_MAP(GpuChangeState, PPSMC_MSG_GpuChangeState, 1),
105 MSG_MAP(SetPowerLimitPercentage, PPSMC_MSG_SetPowerLimitPercentage, 1),
106 MSG_MAP(ForceGfxContentSave, PPSMC_MSG_ForceGfxContentSave, 1),
107 MSG_MAP(EnableTmdp48MHzRefclkPwrDown, PPSMC_MSG_EnableTmdp48MHzRefclkPwrDown, 1),
108 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 1),
109 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 1),
110 MSG_MAP(PowerGateAtHub, PPSMC_MSG_PowerGateAtHub, 1),
111 MSG_MAP(SetSoftMinJpeg, PPSMC_MSG_SetSoftMinJpeg, 1),
112 MSG_MAP(SetHardMinFclkByFreq, PPSMC_MSG_SetHardMinFclkByFreq, 1),
113 };
114
115 static struct cmn2asic_mapping renoir_clk_map[SMU_CLK_COUNT] = {
116 CLK_MAP(GFXCLK, CLOCK_GFXCLK),
117 CLK_MAP(SCLK, CLOCK_GFXCLK),
118 CLK_MAP(SOCCLK, CLOCK_SOCCLK),
119 CLK_MAP(UCLK, CLOCK_FCLK),
120 CLK_MAP(MCLK, CLOCK_FCLK),
121 CLK_MAP(VCLK, CLOCK_VCLK),
122 CLK_MAP(DCLK, CLOCK_DCLK),
123 };
124
125 static struct cmn2asic_mapping renoir_table_map[SMU_TABLE_COUNT] = {
126 TAB_MAP_VALID(WATERMARKS),
127 TAB_MAP_INVALID(CUSTOM_DPM),
128 TAB_MAP_VALID(DPMCLOCKS),
129 TAB_MAP_VALID(SMU_METRICS),
130 };
131
132 static struct cmn2asic_mapping renoir_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
133 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
134 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
135 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
136 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
137 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
138 };
139
140 static const uint8_t renoir_throttler_map[] = {
141 [THROTTLER_STATUS_BIT_SPL] = (SMU_THROTTLER_SPL_BIT),
142 [THROTTLER_STATUS_BIT_FPPT] = (SMU_THROTTLER_FPPT_BIT),
143 [THROTTLER_STATUS_BIT_SPPT] = (SMU_THROTTLER_SPPT_BIT),
144 [THROTTLER_STATUS_BIT_SPPT_APU] = (SMU_THROTTLER_SPPT_APU_BIT),
145 [THROTTLER_STATUS_BIT_THM_CORE] = (SMU_THROTTLER_TEMP_CORE_BIT),
146 [THROTTLER_STATUS_BIT_THM_GFX] = (SMU_THROTTLER_TEMP_GPU_BIT),
147 [THROTTLER_STATUS_BIT_THM_SOC] = (SMU_THROTTLER_TEMP_SOC_BIT),
148 [THROTTLER_STATUS_BIT_TDC_VDD] = (SMU_THROTTLER_TDC_VDD_BIT),
149 [THROTTLER_STATUS_BIT_TDC_SOC] = (SMU_THROTTLER_TDC_SOC_BIT),
150 [THROTTLER_STATUS_BIT_PROCHOT_CPU] = (SMU_THROTTLER_PROCHOT_CPU_BIT),
151 [THROTTLER_STATUS_BIT_PROCHOT_GFX] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
152 [THROTTLER_STATUS_BIT_EDC_CPU] = (SMU_THROTTLER_EDC_CPU_BIT),
153 [THROTTLER_STATUS_BIT_EDC_GFX] = (SMU_THROTTLER_EDC_GFX_BIT),
154 };
155
renoir_init_smc_tables(struct smu_context * smu)156 static int renoir_init_smc_tables(struct smu_context *smu)
157 {
158 struct smu_table_context *smu_table = &smu->smu_table;
159 struct smu_table *tables = smu_table->tables;
160
161 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
162 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
163 SMU_TABLE_INIT(tables, SMU_TABLE_DPMCLOCKS, sizeof(DpmClocks_t),
164 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
165 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_t),
166 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
167
168 smu_table->clocks_table = kzalloc(sizeof(DpmClocks_t), GFP_KERNEL);
169 if (!smu_table->clocks_table)
170 goto err0_out;
171
172 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_t), GFP_KERNEL);
173 if (!smu_table->metrics_table)
174 goto err1_out;
175 smu_table->metrics_time = 0;
176
177 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
178 if (!smu_table->watermarks_table)
179 goto err2_out;
180
181 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v2_2);
182 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
183 if (!smu_table->gpu_metrics_table)
184 goto err3_out;
185
186 return 0;
187
188 err3_out:
189 kfree(smu_table->watermarks_table);
190 err2_out:
191 kfree(smu_table->metrics_table);
192 err1_out:
193 kfree(smu_table->clocks_table);
194 err0_out:
195 return -ENOMEM;
196 }
197
198 /*
199 * This interface just for getting uclk ultimate freq and should't introduce
200 * other likewise function result in overmuch callback.
201 */
renoir_get_dpm_clk_limited(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t dpm_level,uint32_t * freq)202 static int renoir_get_dpm_clk_limited(struct smu_context *smu, enum smu_clk_type clk_type,
203 uint32_t dpm_level, uint32_t *freq)
204 {
205 DpmClocks_t *clk_table = smu->smu_table.clocks_table;
206
207 if (!clk_table || clk_type >= SMU_CLK_COUNT)
208 return -EINVAL;
209
210 switch (clk_type) {
211 case SMU_SOCCLK:
212 if (dpm_level >= NUM_SOCCLK_DPM_LEVELS)
213 return -EINVAL;
214 *freq = clk_table->SocClocks[dpm_level].Freq;
215 break;
216 case SMU_UCLK:
217 case SMU_MCLK:
218 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
219 return -EINVAL;
220 *freq = clk_table->FClocks[dpm_level].Freq;
221 break;
222 case SMU_DCEFCLK:
223 if (dpm_level >= NUM_DCFCLK_DPM_LEVELS)
224 return -EINVAL;
225 *freq = clk_table->DcfClocks[dpm_level].Freq;
226 break;
227 case SMU_FCLK:
228 if (dpm_level >= NUM_FCLK_DPM_LEVELS)
229 return -EINVAL;
230 *freq = clk_table->FClocks[dpm_level].Freq;
231 break;
232 case SMU_VCLK:
233 if (dpm_level >= NUM_VCN_DPM_LEVELS)
234 return -EINVAL;
235 *freq = clk_table->VClocks[dpm_level].Freq;
236 break;
237 case SMU_DCLK:
238 if (dpm_level >= NUM_VCN_DPM_LEVELS)
239 return -EINVAL;
240 *freq = clk_table->DClocks[dpm_level].Freq;
241 break;
242
243 default:
244 return -EINVAL;
245 }
246
247 return 0;
248 }
249
renoir_get_profiling_clk_mask(struct smu_context * smu,enum amd_dpm_forced_level level,uint32_t * sclk_mask,uint32_t * mclk_mask,uint32_t * soc_mask)250 static int renoir_get_profiling_clk_mask(struct smu_context *smu,
251 enum amd_dpm_forced_level level,
252 uint32_t *sclk_mask,
253 uint32_t *mclk_mask,
254 uint32_t *soc_mask)
255 {
256
257 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) {
258 if (sclk_mask)
259 *sclk_mask = 0;
260 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) {
261 if (mclk_mask)
262 /* mclk levels are in reverse order */
263 *mclk_mask = NUM_MEMCLK_DPM_LEVELS - 1;
264 } else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) {
265 if (sclk_mask)
266 /* The sclk as gfxclk and has three level about max/min/current */
267 *sclk_mask = 3 - 1;
268
269 if (mclk_mask)
270 /* mclk levels are in reverse order */
271 *mclk_mask = 0;
272
273 if (soc_mask)
274 *soc_mask = NUM_SOCCLK_DPM_LEVELS - 1;
275 }
276
277 return 0;
278 }
279
renoir_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)280 static int renoir_get_dpm_ultimate_freq(struct smu_context *smu,
281 enum smu_clk_type clk_type,
282 uint32_t *min,
283 uint32_t *max)
284 {
285 int ret = 0;
286 uint32_t mclk_mask, soc_mask;
287 uint32_t clock_limit;
288
289 if (!smu_cmn_clk_dpm_is_enabled(smu, clk_type)) {
290 switch (clk_type) {
291 case SMU_MCLK:
292 case SMU_UCLK:
293 clock_limit = smu->smu_table.boot_values.uclk;
294 break;
295 case SMU_GFXCLK:
296 case SMU_SCLK:
297 clock_limit = smu->smu_table.boot_values.gfxclk;
298 break;
299 case SMU_SOCCLK:
300 clock_limit = smu->smu_table.boot_values.socclk;
301 break;
302 default:
303 clock_limit = 0;
304 break;
305 }
306
307 /* clock in Mhz unit */
308 if (min)
309 *min = clock_limit / 100;
310 if (max)
311 *max = clock_limit / 100;
312
313 return 0;
314 }
315
316 if (max) {
317 ret = renoir_get_profiling_clk_mask(smu,
318 AMD_DPM_FORCED_LEVEL_PROFILE_PEAK,
319 NULL,
320 &mclk_mask,
321 &soc_mask);
322 if (ret)
323 goto failed;
324
325 switch (clk_type) {
326 case SMU_GFXCLK:
327 case SMU_SCLK:
328 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMaxGfxclkFrequency, max);
329 if (ret) {
330 dev_err(smu->adev->dev, "Attempt to get max GX frequency from SMC Failed !\n");
331 goto failed;
332 }
333 break;
334 case SMU_UCLK:
335 case SMU_FCLK:
336 case SMU_MCLK:
337 ret = renoir_get_dpm_clk_limited(smu, clk_type, mclk_mask, max);
338 if (ret)
339 goto failed;
340 break;
341 case SMU_SOCCLK:
342 ret = renoir_get_dpm_clk_limited(smu, clk_type, soc_mask, max);
343 if (ret)
344 goto failed;
345 break;
346 default:
347 ret = -EINVAL;
348 goto failed;
349 }
350 }
351
352 if (min) {
353 switch (clk_type) {
354 case SMU_GFXCLK:
355 case SMU_SCLK:
356 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMinGfxclkFrequency, min);
357 if (ret) {
358 dev_err(smu->adev->dev, "Attempt to get min GX frequency from SMC Failed !\n");
359 goto failed;
360 }
361 break;
362 case SMU_UCLK:
363 case SMU_FCLK:
364 case SMU_MCLK:
365 ret = renoir_get_dpm_clk_limited(smu, clk_type, NUM_MEMCLK_DPM_LEVELS - 1, min);
366 if (ret)
367 goto failed;
368 break;
369 case SMU_SOCCLK:
370 ret = renoir_get_dpm_clk_limited(smu, clk_type, 0, min);
371 if (ret)
372 goto failed;
373 break;
374 default:
375 ret = -EINVAL;
376 goto failed;
377 }
378 }
379 failed:
380 return ret;
381 }
382
renoir_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)383 static int renoir_od_edit_dpm_table(struct smu_context *smu,
384 enum PP_OD_DPM_TABLE_COMMAND type,
385 long input[], uint32_t size)
386 {
387 int ret = 0;
388 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
389
390 if (!(smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL)) {
391 dev_warn(smu->adev->dev,
392 "pp_od_clk_voltage is not accessible if power_dpm_force_performance_level is not in manual mode!\n");
393 return -EINVAL;
394 }
395
396 switch (type) {
397 case PP_OD_EDIT_SCLK_VDDC_TABLE:
398 if (size != 2) {
399 dev_err(smu->adev->dev, "Input parameter number not correct\n");
400 return -EINVAL;
401 }
402
403 if (input[0] == 0) {
404 if (input[1] < smu->gfx_default_hard_min_freq) {
405 dev_warn(smu->adev->dev,
406 "Fine grain setting minimum sclk (%ld) MHz is less than the minimum allowed (%d) MHz\n",
407 input[1], smu->gfx_default_hard_min_freq);
408 return -EINVAL;
409 }
410 smu->gfx_actual_hard_min_freq = input[1];
411 } else if (input[0] == 1) {
412 if (input[1] > smu->gfx_default_soft_max_freq) {
413 dev_warn(smu->adev->dev,
414 "Fine grain setting maximum sclk (%ld) MHz is greater than the maximum allowed (%d) MHz\n",
415 input[1], smu->gfx_default_soft_max_freq);
416 return -EINVAL;
417 }
418 smu->gfx_actual_soft_max_freq = input[1];
419 } else {
420 return -EINVAL;
421 }
422 break;
423 case PP_OD_RESTORE_DEFAULT_TABLE:
424 if (size != 0) {
425 dev_err(smu->adev->dev, "Input parameter number not correct\n");
426 return -EINVAL;
427 }
428 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
429 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
430 break;
431 case PP_OD_COMMIT_DPM_TABLE:
432 if (size != 0) {
433 dev_err(smu->adev->dev, "Input parameter number not correct\n");
434 return -EINVAL;
435 } else {
436 if (smu->gfx_actual_hard_min_freq > smu->gfx_actual_soft_max_freq) {
437 dev_err(smu->adev->dev,
438 "The setting minimum sclk (%d) MHz is greater than the setting maximum sclk (%d) MHz\n",
439 smu->gfx_actual_hard_min_freq,
440 smu->gfx_actual_soft_max_freq);
441 return -EINVAL;
442 }
443
444 ret = smu_cmn_send_smc_msg_with_param(smu,
445 SMU_MSG_SetHardMinGfxClk,
446 smu->gfx_actual_hard_min_freq,
447 NULL);
448 if (ret) {
449 dev_err(smu->adev->dev, "Set hard min sclk failed!");
450 return ret;
451 }
452
453 ret = smu_cmn_send_smc_msg_with_param(smu,
454 SMU_MSG_SetSoftMaxGfxClk,
455 smu->gfx_actual_soft_max_freq,
456 NULL);
457 if (ret) {
458 dev_err(smu->adev->dev, "Set soft max sclk failed!");
459 return ret;
460 }
461 }
462 break;
463 default:
464 return -ENOSYS;
465 }
466
467 return ret;
468 }
469
renoir_set_fine_grain_gfx_freq_parameters(struct smu_context * smu)470 static int renoir_set_fine_grain_gfx_freq_parameters(struct smu_context *smu)
471 {
472 uint32_t min = 0, max = 0;
473 uint32_t ret = 0;
474
475 ret = smu_cmn_send_smc_msg_with_param(smu,
476 SMU_MSG_GetMinGfxclkFrequency,
477 0, &min);
478 if (ret)
479 return ret;
480 ret = smu_cmn_send_smc_msg_with_param(smu,
481 SMU_MSG_GetMaxGfxclkFrequency,
482 0, &max);
483 if (ret)
484 return ret;
485
486 smu->gfx_default_hard_min_freq = min;
487 smu->gfx_default_soft_max_freq = max;
488 smu->gfx_actual_hard_min_freq = 0;
489 smu->gfx_actual_soft_max_freq = 0;
490
491 return 0;
492 }
493
renoir_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)494 static int renoir_print_clk_levels(struct smu_context *smu,
495 enum smu_clk_type clk_type, char *buf)
496 {
497 int i, idx, size = 0, ret = 0;
498 uint32_t cur_value = 0, value = 0, count = 0, min = 0, max = 0;
499 SmuMetrics_t metrics;
500 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
501 bool cur_value_match_level = false;
502
503 memset(&metrics, 0, sizeof(metrics));
504
505 ret = smu_cmn_get_metrics_table(smu, &metrics, false);
506 if (ret)
507 return ret;
508
509 smu_cmn_get_sysfs_buf(&buf, &size);
510
511 switch (clk_type) {
512 case SMU_OD_RANGE:
513 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
514 ret = smu_cmn_send_smc_msg_with_param(smu,
515 SMU_MSG_GetMinGfxclkFrequency,
516 0, &min);
517 if (ret)
518 return ret;
519 ret = smu_cmn_send_smc_msg_with_param(smu,
520 SMU_MSG_GetMaxGfxclkFrequency,
521 0, &max);
522 if (ret)
523 return ret;
524 size += sysfs_emit_at(buf, size, "OD_RANGE\nSCLK: %10uMhz %10uMhz\n", min, max);
525 }
526 break;
527 case SMU_OD_SCLK:
528 if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
529 min = (smu->gfx_actual_hard_min_freq > 0) ? smu->gfx_actual_hard_min_freq : smu->gfx_default_hard_min_freq;
530 max = (smu->gfx_actual_soft_max_freq > 0) ? smu->gfx_actual_soft_max_freq : smu->gfx_default_soft_max_freq;
531 size += sysfs_emit_at(buf, size, "OD_SCLK\n");
532 size += sysfs_emit_at(buf, size, "0:%10uMhz\n", min);
533 size += sysfs_emit_at(buf, size, "1:%10uMhz\n", max);
534 }
535 break;
536 case SMU_GFXCLK:
537 case SMU_SCLK:
538 /* retirve table returned paramters unit is MHz */
539 cur_value = metrics.ClockFrequency[CLOCK_GFXCLK];
540 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min, &max);
541 if (!ret) {
542 /* driver only know min/max gfx_clk, Add level 1 for all other gfx clks */
543 if (cur_value == max)
544 i = 2;
545 else if (cur_value == min)
546 i = 0;
547 else
548 i = 1;
549
550 size += sysfs_emit_at(buf, size, "0: %uMhz %s\n", min,
551 i == 0 ? "*" : "");
552 size += sysfs_emit_at(buf, size, "1: %uMhz %s\n",
553 i == 1 ? cur_value : RENOIR_UMD_PSTATE_GFXCLK,
554 i == 1 ? "*" : "");
555 size += sysfs_emit_at(buf, size, "2: %uMhz %s\n", max,
556 i == 2 ? "*" : "");
557 }
558 return size;
559 case SMU_SOCCLK:
560 count = NUM_SOCCLK_DPM_LEVELS;
561 cur_value = metrics.ClockFrequency[CLOCK_SOCCLK];
562 break;
563 case SMU_MCLK:
564 count = NUM_MEMCLK_DPM_LEVELS;
565 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
566 break;
567 case SMU_DCEFCLK:
568 count = NUM_DCFCLK_DPM_LEVELS;
569 cur_value = metrics.ClockFrequency[CLOCK_DCFCLK];
570 break;
571 case SMU_FCLK:
572 count = NUM_FCLK_DPM_LEVELS;
573 cur_value = metrics.ClockFrequency[CLOCK_FCLK];
574 break;
575 case SMU_VCLK:
576 count = NUM_VCN_DPM_LEVELS;
577 cur_value = metrics.ClockFrequency[CLOCK_VCLK];
578 break;
579 case SMU_DCLK:
580 count = NUM_VCN_DPM_LEVELS;
581 cur_value = metrics.ClockFrequency[CLOCK_DCLK];
582 break;
583 default:
584 break;
585 }
586
587 switch (clk_type) {
588 case SMU_SOCCLK:
589 case SMU_MCLK:
590 case SMU_DCEFCLK:
591 case SMU_FCLK:
592 case SMU_VCLK:
593 case SMU_DCLK:
594 for (i = 0; i < count; i++) {
595 idx = (clk_type == SMU_FCLK || clk_type == SMU_MCLK) ? (count - i - 1) : i;
596 ret = renoir_get_dpm_clk_limited(smu, clk_type, idx, &value);
597 if (ret)
598 return ret;
599 if (!value)
600 continue;
601 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
602 cur_value == value ? "*" : "");
603 if (cur_value == value)
604 cur_value_match_level = true;
605 }
606
607 if (!cur_value_match_level)
608 size += sysfs_emit_at(buf, size, " %uMhz *\n", cur_value);
609
610 break;
611 default:
612 break;
613 }
614
615 return size;
616 }
617
renoir_get_current_power_state(struct smu_context * smu)618 static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context *smu)
619 {
620 enum amd_pm_state_type pm_type;
621 struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
622
623 if (!smu_dpm_ctx->dpm_context ||
624 !smu_dpm_ctx->dpm_current_power_state)
625 return -EINVAL;
626
627 switch (smu_dpm_ctx->dpm_current_power_state->classification.ui_label) {
628 case SMU_STATE_UI_LABEL_BATTERY:
629 pm_type = POWER_STATE_TYPE_BATTERY;
630 break;
631 case SMU_STATE_UI_LABEL_BALLANCED:
632 pm_type = POWER_STATE_TYPE_BALANCED;
633 break;
634 case SMU_STATE_UI_LABEL_PERFORMANCE:
635 pm_type = POWER_STATE_TYPE_PERFORMANCE;
636 break;
637 default:
638 if (smu_dpm_ctx->dpm_current_power_state->classification.flags & SMU_STATE_CLASSIFICATION_FLAG_BOOT)
639 pm_type = POWER_STATE_TYPE_INTERNAL_BOOT;
640 else
641 pm_type = POWER_STATE_TYPE_DEFAULT;
642 break;
643 }
644
645 return pm_type;
646 }
647
renoir_dpm_set_vcn_enable(struct smu_context * smu,bool enable)648 static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
649 {
650 int ret = 0;
651
652 if (enable) {
653 /* vcn dpm on is a prerequisite for vcn power gate messages */
654 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
655 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 0, NULL);
656 if (ret)
657 return ret;
658 }
659 } else {
660 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
661 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
662 if (ret)
663 return ret;
664 }
665 }
666
667 return ret;
668 }
669
renoir_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)670 static int renoir_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
671 {
672 int ret = 0;
673
674 if (enable) {
675 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
676 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpJpeg, 0, NULL);
677 if (ret)
678 return ret;
679 }
680 } else {
681 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
682 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerDownJpeg, 0, NULL);
683 if (ret)
684 return ret;
685 }
686 }
687
688 return ret;
689 }
690
renoir_force_dpm_limit_value(struct smu_context * smu,bool highest)691 static int renoir_force_dpm_limit_value(struct smu_context *smu, bool highest)
692 {
693 int ret = 0, i = 0;
694 uint32_t min_freq, max_freq, force_freq;
695 enum smu_clk_type clk_type;
696
697 enum smu_clk_type clks[] = {
698 SMU_GFXCLK,
699 SMU_MCLK,
700 SMU_SOCCLK,
701 };
702
703 for (i = 0; i < ARRAY_SIZE(clks); i++) {
704 clk_type = clks[i];
705 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
706 if (ret)
707 return ret;
708
709 force_freq = highest ? max_freq : min_freq;
710 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, force_freq, force_freq);
711 if (ret)
712 return ret;
713 }
714
715 return ret;
716 }
717
renoir_unforce_dpm_levels(struct smu_context * smu)718 static int renoir_unforce_dpm_levels(struct smu_context *smu) {
719
720 int ret = 0, i = 0;
721 uint32_t min_freq, max_freq;
722 enum smu_clk_type clk_type;
723
724 struct clk_feature_map {
725 enum smu_clk_type clk_type;
726 uint32_t feature;
727 } clk_feature_map[] = {
728 {SMU_GFXCLK, SMU_FEATURE_DPM_GFXCLK_BIT},
729 {SMU_MCLK, SMU_FEATURE_DPM_UCLK_BIT},
730 {SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT},
731 };
732
733 for (i = 0; i < ARRAY_SIZE(clk_feature_map); i++) {
734 if (!smu_cmn_feature_is_enabled(smu, clk_feature_map[i].feature))
735 continue;
736
737 clk_type = clk_feature_map[i].clk_type;
738
739 ret = renoir_get_dpm_ultimate_freq(smu, clk_type, &min_freq, &max_freq);
740 if (ret)
741 return ret;
742
743 ret = smu_v12_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
744 if (ret)
745 return ret;
746 }
747
748 return ret;
749 }
750
751 /*
752 * This interface get dpm clock table for dc
753 */
renoir_get_dpm_clock_table(struct smu_context * smu,struct dpm_clocks * clock_table)754 static int renoir_get_dpm_clock_table(struct smu_context *smu, struct dpm_clocks *clock_table)
755 {
756 DpmClocks_t *table = smu->smu_table.clocks_table;
757 int i;
758
759 if (!clock_table || !table)
760 return -EINVAL;
761
762 for (i = 0; i < NUM_DCFCLK_DPM_LEVELS; i++) {
763 clock_table->DcfClocks[i].Freq = table->DcfClocks[i].Freq;
764 clock_table->DcfClocks[i].Vol = table->DcfClocks[i].Vol;
765 }
766
767 for (i = 0; i < NUM_SOCCLK_DPM_LEVELS; i++) {
768 clock_table->SocClocks[i].Freq = table->SocClocks[i].Freq;
769 clock_table->SocClocks[i].Vol = table->SocClocks[i].Vol;
770 }
771
772 for (i = 0; i < NUM_FCLK_DPM_LEVELS; i++) {
773 clock_table->FClocks[i].Freq = table->FClocks[i].Freq;
774 clock_table->FClocks[i].Vol = table->FClocks[i].Vol;
775 }
776
777 for (i = 0; i< NUM_MEMCLK_DPM_LEVELS; i++) {
778 clock_table->MemClocks[i].Freq = table->MemClocks[i].Freq;
779 clock_table->MemClocks[i].Vol = table->MemClocks[i].Vol;
780 }
781
782 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
783 clock_table->VClocks[i].Freq = table->VClocks[i].Freq;
784 clock_table->VClocks[i].Vol = table->VClocks[i].Vol;
785 }
786
787 for (i = 0; i < NUM_VCN_DPM_LEVELS; i++) {
788 clock_table->DClocks[i].Freq = table->DClocks[i].Freq;
789 clock_table->DClocks[i].Vol = table->DClocks[i].Vol;
790 }
791
792 return 0;
793 }
794
renoir_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)795 static int renoir_force_clk_levels(struct smu_context *smu,
796 enum smu_clk_type clk_type, uint32_t mask)
797 {
798
799 int ret = 0 ;
800 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
801
802 soft_min_level = mask ? (ffs(mask) - 1) : 0;
803 soft_max_level = mask ? (fls(mask) - 1) : 0;
804
805 switch (clk_type) {
806 case SMU_GFXCLK:
807 case SMU_SCLK:
808 if (soft_min_level > 2 || soft_max_level > 2) {
809 dev_info(smu->adev->dev, "Currently sclk only support 3 levels on APU\n");
810 return -EINVAL;
811 }
812
813 ret = renoir_get_dpm_ultimate_freq(smu, SMU_GFXCLK, &min_freq, &max_freq);
814 if (ret)
815 return ret;
816 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
817 soft_max_level == 0 ? min_freq :
818 soft_max_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : max_freq,
819 NULL);
820 if (ret)
821 return ret;
822 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinGfxClk,
823 soft_min_level == 2 ? max_freq :
824 soft_min_level == 1 ? RENOIR_UMD_PSTATE_GFXCLK : min_freq,
825 NULL);
826 if (ret)
827 return ret;
828 break;
829 case SMU_SOCCLK:
830 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
831 if (ret)
832 return ret;
833 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
834 if (ret)
835 return ret;
836 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxSocclkByFreq, max_freq, NULL);
837 if (ret)
838 return ret;
839 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinSocclkByFreq, min_freq, NULL);
840 if (ret)
841 return ret;
842 break;
843 case SMU_MCLK:
844 case SMU_FCLK:
845 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_min_level, &min_freq);
846 if (ret)
847 return ret;
848 ret = renoir_get_dpm_clk_limited(smu, clk_type, soft_max_level, &max_freq);
849 if (ret)
850 return ret;
851 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxFclkByFreq, max_freq, NULL);
852 if (ret)
853 return ret;
854 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetHardMinFclkByFreq, min_freq, NULL);
855 if (ret)
856 return ret;
857 break;
858 default:
859 break;
860 }
861
862 return ret;
863 }
864
renoir_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)865 static int renoir_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
866 {
867 int workload_type, ret;
868 uint32_t profile_mode = input[size];
869
870 if (profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
871 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", profile_mode);
872 return -EINVAL;
873 }
874
875 if (profile_mode == PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT ||
876 profile_mode == PP_SMC_POWER_PROFILE_POWERSAVING)
877 return 0;
878
879 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
880 workload_type = smu_cmn_to_asic_specific_index(smu,
881 CMN2ASIC_MAPPING_WORKLOAD,
882 profile_mode);
883 if (workload_type < 0) {
884 /*
885 * TODO: If some case need switch to powersave/default power mode
886 * then can consider enter WORKLOAD_COMPUTE/WORKLOAD_CUSTOM for power saving.
887 */
888 dev_dbg(smu->adev->dev, "Unsupported power profile mode %d on RENOIR\n", profile_mode);
889 return -EINVAL;
890 }
891
892 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ActiveProcessNotify,
893 1 << workload_type,
894 NULL);
895 if (ret) {
896 dev_err_once(smu->adev->dev, "Fail to set workload type %d\n", workload_type);
897 return ret;
898 }
899
900 smu->power_profile_mode = profile_mode;
901
902 return 0;
903 }
904
renoir_set_peak_clock_by_device(struct smu_context * smu)905 static int renoir_set_peak_clock_by_device(struct smu_context *smu)
906 {
907 int ret = 0;
908 uint32_t sclk_freq = 0, uclk_freq = 0;
909
910 ret = renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk_freq);
911 if (ret)
912 return ret;
913
914 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk_freq, sclk_freq);
915 if (ret)
916 return ret;
917
918 ret = renoir_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &uclk_freq);
919 if (ret)
920 return ret;
921
922 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_UCLK, uclk_freq, uclk_freq);
923 if (ret)
924 return ret;
925
926 return ret;
927 }
928
renior_set_dpm_profile_freq(struct smu_context * smu,enum amd_dpm_forced_level level,enum smu_clk_type clk_type)929 static int renior_set_dpm_profile_freq(struct smu_context *smu,
930 enum amd_dpm_forced_level level,
931 enum smu_clk_type clk_type)
932 {
933 int ret = 0;
934 uint32_t sclk = 0, socclk = 0, fclk = 0;
935
936 switch (clk_type) {
937 case SMU_GFXCLK:
938 case SMU_SCLK:
939 sclk = RENOIR_UMD_PSTATE_GFXCLK;
940 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
941 renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, NULL, &sclk);
942 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK)
943 renoir_get_dpm_ultimate_freq(smu, SMU_SCLK, &sclk, NULL);
944 break;
945 case SMU_SOCCLK:
946 socclk = RENOIR_UMD_PSTATE_SOCCLK;
947 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
948 renoir_get_dpm_ultimate_freq(smu, SMU_SOCCLK, NULL, &socclk);
949 break;
950 case SMU_FCLK:
951 case SMU_MCLK:
952 fclk = RENOIR_UMD_PSTATE_FCLK;
953 if (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
954 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, NULL, &fclk);
955 else if (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK)
956 renoir_get_dpm_ultimate_freq(smu, SMU_FCLK, &fclk, NULL);
957 break;
958 default:
959 ret = -EINVAL;
960 break;
961 }
962
963 if (sclk)
964 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SCLK, sclk, sclk);
965
966 if (socclk)
967 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_SOCCLK, socclk, socclk);
968
969 if (fclk)
970 ret = smu_v12_0_set_soft_freq_limited_range(smu, SMU_FCLK, fclk, fclk);
971
972 return ret;
973 }
974
renoir_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)975 static int renoir_set_performance_level(struct smu_context *smu,
976 enum amd_dpm_forced_level level)
977 {
978 int ret = 0;
979
980 switch (level) {
981 case AMD_DPM_FORCED_LEVEL_HIGH:
982 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
983 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
984
985 ret = renoir_force_dpm_limit_value(smu, true);
986 break;
987 case AMD_DPM_FORCED_LEVEL_LOW:
988 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
989 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
990
991 ret = renoir_force_dpm_limit_value(smu, false);
992 break;
993 case AMD_DPM_FORCED_LEVEL_AUTO:
994 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
995 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
996
997 ret = renoir_unforce_dpm_levels(smu);
998 break;
999 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
1000 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1001 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1002
1003 ret = smu_cmn_send_smc_msg_with_param(smu,
1004 SMU_MSG_SetHardMinGfxClk,
1005 RENOIR_UMD_PSTATE_GFXCLK,
1006 NULL);
1007 if (ret)
1008 return ret;
1009 ret = smu_cmn_send_smc_msg_with_param(smu,
1010 SMU_MSG_SetHardMinFclkByFreq,
1011 RENOIR_UMD_PSTATE_FCLK,
1012 NULL);
1013 if (ret)
1014 return ret;
1015 ret = smu_cmn_send_smc_msg_with_param(smu,
1016 SMU_MSG_SetHardMinSocclkByFreq,
1017 RENOIR_UMD_PSTATE_SOCCLK,
1018 NULL);
1019 if (ret)
1020 return ret;
1021 ret = smu_cmn_send_smc_msg_with_param(smu,
1022 SMU_MSG_SetHardMinVcn,
1023 RENOIR_UMD_PSTATE_VCNCLK,
1024 NULL);
1025 if (ret)
1026 return ret;
1027
1028 ret = smu_cmn_send_smc_msg_with_param(smu,
1029 SMU_MSG_SetSoftMaxGfxClk,
1030 RENOIR_UMD_PSTATE_GFXCLK,
1031 NULL);
1032 if (ret)
1033 return ret;
1034 ret = smu_cmn_send_smc_msg_with_param(smu,
1035 SMU_MSG_SetSoftMaxFclkByFreq,
1036 RENOIR_UMD_PSTATE_FCLK,
1037 NULL);
1038 if (ret)
1039 return ret;
1040 ret = smu_cmn_send_smc_msg_with_param(smu,
1041 SMU_MSG_SetSoftMaxSocclkByFreq,
1042 RENOIR_UMD_PSTATE_SOCCLK,
1043 NULL);
1044 if (ret)
1045 return ret;
1046 ret = smu_cmn_send_smc_msg_with_param(smu,
1047 SMU_MSG_SetSoftMaxVcn,
1048 RENOIR_UMD_PSTATE_VCNCLK,
1049 NULL);
1050 if (ret)
1051 return ret;
1052 break;
1053 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
1054 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
1055 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1056 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1057
1058 renior_set_dpm_profile_freq(smu, level, SMU_SCLK);
1059 renior_set_dpm_profile_freq(smu, level, SMU_MCLK);
1060 renior_set_dpm_profile_freq(smu, level, SMU_SOCCLK);
1061 break;
1062 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
1063 smu->gfx_actual_hard_min_freq = smu->gfx_default_hard_min_freq;
1064 smu->gfx_actual_soft_max_freq = smu->gfx_default_soft_max_freq;
1065
1066 ret = renoir_set_peak_clock_by_device(smu);
1067 break;
1068 case AMD_DPM_FORCED_LEVEL_MANUAL:
1069 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
1070 default:
1071 break;
1072 }
1073 return ret;
1074 }
1075
1076 /* save watermark settings into pplib smu structure,
1077 * also pass data to smu controller
1078 */
renoir_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)1079 static int renoir_set_watermarks_table(
1080 struct smu_context *smu,
1081 struct pp_smu_wm_range_sets *clock_ranges)
1082 {
1083 Watermarks_t *table = smu->smu_table.watermarks_table;
1084 int ret = 0;
1085 int i;
1086
1087 if (clock_ranges) {
1088 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
1089 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
1090 return -EINVAL;
1091
1092 /* save into smu->smu_table.tables[SMU_TABLE_WATERMARKS]->cpu_addr*/
1093 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
1094 table->WatermarkRow[WM_DCFCLK][i].MinClock =
1095 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
1096 table->WatermarkRow[WM_DCFCLK][i].MaxClock =
1097 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
1098 table->WatermarkRow[WM_DCFCLK][i].MinMclk =
1099 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
1100 table->WatermarkRow[WM_DCFCLK][i].MaxMclk =
1101 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
1102
1103 table->WatermarkRow[WM_DCFCLK][i].WmSetting =
1104 clock_ranges->reader_wm_sets[i].wm_inst;
1105 table->WatermarkRow[WM_DCFCLK][i].WmType =
1106 clock_ranges->reader_wm_sets[i].wm_type;
1107 }
1108
1109 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
1110 table->WatermarkRow[WM_SOCCLK][i].MinClock =
1111 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
1112 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
1113 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
1114 table->WatermarkRow[WM_SOCCLK][i].MinMclk =
1115 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
1116 table->WatermarkRow[WM_SOCCLK][i].MaxMclk =
1117 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
1118
1119 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
1120 clock_ranges->writer_wm_sets[i].wm_inst;
1121 table->WatermarkRow[WM_SOCCLK][i].WmType =
1122 clock_ranges->writer_wm_sets[i].wm_type;
1123 }
1124
1125 smu->watermarks_bitmap |= WATERMARKS_EXIST;
1126 }
1127
1128 /* pass data to smu controller */
1129 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1130 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
1131 ret = smu_cmn_write_watermarks_table(smu);
1132 if (ret) {
1133 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
1134 return ret;
1135 }
1136 smu->watermarks_bitmap |= WATERMARKS_LOADED;
1137 }
1138
1139 return 0;
1140 }
1141
renoir_get_power_profile_mode(struct smu_context * smu,char * buf)1142 static int renoir_get_power_profile_mode(struct smu_context *smu,
1143 char *buf)
1144 {
1145 uint32_t i, size = 0;
1146 int16_t workload_type = 0;
1147
1148 if (!buf)
1149 return -EINVAL;
1150
1151 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1152 /*
1153 * Conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT
1154 * Not all profile modes are supported on arcturus.
1155 */
1156 workload_type = smu_cmn_to_asic_specific_index(smu,
1157 CMN2ASIC_MAPPING_WORKLOAD,
1158 i);
1159 if (workload_type < 0)
1160 continue;
1161
1162 size += sysfs_emit_at(buf, size, "%2d %14s%s\n",
1163 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1164 }
1165
1166 return size;
1167 }
1168
renoir_get_ss_power_percent(SmuMetrics_t * metrics,uint32_t * apu_percent,uint32_t * dgpu_percent)1169 static void renoir_get_ss_power_percent(SmuMetrics_t *metrics,
1170 uint32_t *apu_percent, uint32_t *dgpu_percent)
1171 {
1172 uint32_t apu_boost = 0;
1173 uint32_t dgpu_boost = 0;
1174 uint16_t apu_limit = 0;
1175 uint16_t dgpu_limit = 0;
1176 uint16_t apu_power = 0;
1177 uint16_t dgpu_power = 0;
1178
1179 apu_power = metrics->ApuPower;
1180 apu_limit = metrics->StapmOriginalLimit;
1181 if (apu_power > apu_limit && apu_limit != 0)
1182 apu_boost = ((apu_power - apu_limit) * 100) / apu_limit;
1183 apu_boost = (apu_boost > 100) ? 100 : apu_boost;
1184
1185 dgpu_power = metrics->dGpuPower;
1186 if (metrics->StapmCurrentLimit > metrics->StapmOriginalLimit)
1187 dgpu_limit = metrics->StapmCurrentLimit - metrics->StapmOriginalLimit;
1188 if (dgpu_power > dgpu_limit && dgpu_limit != 0)
1189 dgpu_boost = ((dgpu_power - dgpu_limit) * 100) / dgpu_limit;
1190 dgpu_boost = (dgpu_boost > 100) ? 100 : dgpu_boost;
1191
1192 if (dgpu_boost >= apu_boost)
1193 apu_boost = 0;
1194 else
1195 dgpu_boost = 0;
1196
1197 *apu_percent = apu_boost;
1198 *dgpu_percent = dgpu_boost;
1199 }
1200
1201
renoir_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1202 static int renoir_get_smu_metrics_data(struct smu_context *smu,
1203 MetricsMember_t member,
1204 uint32_t *value)
1205 {
1206 struct smu_table_context *smu_table = &smu->smu_table;
1207
1208 SmuMetrics_t *metrics = (SmuMetrics_t *)smu_table->metrics_table;
1209 int ret = 0;
1210 uint32_t apu_percent = 0;
1211 uint32_t dgpu_percent = 0;
1212 struct amdgpu_device *adev = smu->adev;
1213
1214
1215 ret = smu_cmn_get_metrics_table(smu,
1216 NULL,
1217 false);
1218 if (ret)
1219 return ret;
1220
1221 switch (member) {
1222 case METRICS_AVERAGE_GFXCLK:
1223 *value = metrics->ClockFrequency[CLOCK_GFXCLK];
1224 break;
1225 case METRICS_AVERAGE_SOCCLK:
1226 *value = metrics->ClockFrequency[CLOCK_SOCCLK];
1227 break;
1228 case METRICS_AVERAGE_UCLK:
1229 *value = metrics->ClockFrequency[CLOCK_FCLK];
1230 break;
1231 case METRICS_AVERAGE_GFXACTIVITY:
1232 *value = metrics->AverageGfxActivity / 100;
1233 break;
1234 case METRICS_AVERAGE_VCNACTIVITY:
1235 *value = metrics->AverageUvdActivity / 100;
1236 break;
1237 case METRICS_CURR_SOCKETPOWER:
1238 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1239 IP_VERSION(12, 0, 1)) &&
1240 (adev->pm.fw_version >= 0x40000f)) ||
1241 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
1242 IP_VERSION(12, 0, 0)) &&
1243 (adev->pm.fw_version >= 0x373200)))
1244 *value = metrics->CurrentSocketPower << 8;
1245 else
1246 *value = (metrics->CurrentSocketPower << 8) / 1000;
1247 break;
1248 case METRICS_TEMPERATURE_EDGE:
1249 *value = (metrics->GfxTemperature / 100) *
1250 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1251 break;
1252 case METRICS_TEMPERATURE_HOTSPOT:
1253 *value = (metrics->SocTemperature / 100) *
1254 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1255 break;
1256 case METRICS_THROTTLER_STATUS:
1257 *value = metrics->ThrottlerStatus;
1258 break;
1259 case METRICS_VOLTAGE_VDDGFX:
1260 *value = metrics->Voltage[0];
1261 break;
1262 case METRICS_VOLTAGE_VDDSOC:
1263 *value = metrics->Voltage[1];
1264 break;
1265 case METRICS_SS_APU_SHARE:
1266 /* return the percentage of APU power boost
1267 * with respect to APU's power limit.
1268 */
1269 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1270 *value = apu_percent;
1271 break;
1272 case METRICS_SS_DGPU_SHARE:
1273 /* return the percentage of dGPU power boost
1274 * with respect to dGPU's power limit.
1275 */
1276 renoir_get_ss_power_percent(metrics, &apu_percent, &dgpu_percent);
1277 *value = dgpu_percent;
1278 break;
1279 default:
1280 *value = UINT_MAX;
1281 break;
1282 }
1283
1284 return ret;
1285 }
1286
renoir_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1287 static int renoir_read_sensor(struct smu_context *smu,
1288 enum amd_pp_sensors sensor,
1289 void *data, uint32_t *size)
1290 {
1291 int ret = 0;
1292
1293 if (!data || !size)
1294 return -EINVAL;
1295
1296 switch (sensor) {
1297 case AMDGPU_PP_SENSOR_GPU_LOAD:
1298 ret = renoir_get_smu_metrics_data(smu,
1299 METRICS_AVERAGE_GFXACTIVITY,
1300 (uint32_t *)data);
1301 *size = 4;
1302 break;
1303 case AMDGPU_PP_SENSOR_EDGE_TEMP:
1304 ret = renoir_get_smu_metrics_data(smu,
1305 METRICS_TEMPERATURE_EDGE,
1306 (uint32_t *)data);
1307 *size = 4;
1308 break;
1309 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1310 ret = renoir_get_smu_metrics_data(smu,
1311 METRICS_TEMPERATURE_HOTSPOT,
1312 (uint32_t *)data);
1313 *size = 4;
1314 break;
1315 case AMDGPU_PP_SENSOR_GFX_MCLK:
1316 ret = renoir_get_smu_metrics_data(smu,
1317 METRICS_AVERAGE_UCLK,
1318 (uint32_t *)data);
1319 *(uint32_t *)data *= 100;
1320 *size = 4;
1321 break;
1322 case AMDGPU_PP_SENSOR_GFX_SCLK:
1323 ret = renoir_get_smu_metrics_data(smu,
1324 METRICS_AVERAGE_GFXCLK,
1325 (uint32_t *)data);
1326 *(uint32_t *)data *= 100;
1327 *size = 4;
1328 break;
1329 case AMDGPU_PP_SENSOR_VDDGFX:
1330 ret = renoir_get_smu_metrics_data(smu,
1331 METRICS_VOLTAGE_VDDGFX,
1332 (uint32_t *)data);
1333 *size = 4;
1334 break;
1335 case AMDGPU_PP_SENSOR_VDDNB:
1336 ret = renoir_get_smu_metrics_data(smu,
1337 METRICS_VOLTAGE_VDDSOC,
1338 (uint32_t *)data);
1339 *size = 4;
1340 break;
1341 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1342 ret = renoir_get_smu_metrics_data(smu,
1343 METRICS_CURR_SOCKETPOWER,
1344 (uint32_t *)data);
1345 *size = 4;
1346 break;
1347 case AMDGPU_PP_SENSOR_SS_APU_SHARE:
1348 ret = renoir_get_smu_metrics_data(smu,
1349 METRICS_SS_APU_SHARE,
1350 (uint32_t *)data);
1351 *size = 4;
1352 break;
1353 case AMDGPU_PP_SENSOR_SS_DGPU_SHARE:
1354 ret = renoir_get_smu_metrics_data(smu,
1355 METRICS_SS_DGPU_SHARE,
1356 (uint32_t *)data);
1357 *size = 4;
1358 break;
1359 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1360 default:
1361 ret = -EOPNOTSUPP;
1362 break;
1363 }
1364
1365 return ret;
1366 }
1367
renoir_is_dpm_running(struct smu_context * smu)1368 static bool renoir_is_dpm_running(struct smu_context *smu)
1369 {
1370 struct amdgpu_device *adev = smu->adev;
1371
1372 /*
1373 * Until now, the pmfw hasn't exported the interface of SMU
1374 * feature mask to APU SKU so just force on all the feature
1375 * at early initial stage.
1376 */
1377 if (adev->in_suspend)
1378 return false;
1379 else
1380 return true;
1381
1382 }
1383
renoir_get_gpu_metrics(struct smu_context * smu,void ** table)1384 static ssize_t renoir_get_gpu_metrics(struct smu_context *smu,
1385 void **table)
1386 {
1387 struct smu_table_context *smu_table = &smu->smu_table;
1388 struct gpu_metrics_v2_2 *gpu_metrics =
1389 (struct gpu_metrics_v2_2 *)smu_table->gpu_metrics_table;
1390 SmuMetrics_t metrics;
1391 int ret = 0;
1392
1393 ret = smu_cmn_get_metrics_table(smu, &metrics, true);
1394 if (ret)
1395 return ret;
1396
1397 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 2, 2);
1398
1399 gpu_metrics->temperature_gfx = metrics.GfxTemperature;
1400 gpu_metrics->temperature_soc = metrics.SocTemperature;
1401 memcpy(&gpu_metrics->temperature_core[0],
1402 &metrics.CoreTemperature[0],
1403 sizeof(uint16_t) * 8);
1404 gpu_metrics->temperature_l3[0] = metrics.L3Temperature[0];
1405 gpu_metrics->temperature_l3[1] = metrics.L3Temperature[1];
1406
1407 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
1408 gpu_metrics->average_mm_activity = metrics.AverageUvdActivity;
1409
1410 gpu_metrics->average_socket_power = metrics.CurrentSocketPower;
1411 gpu_metrics->average_cpu_power = metrics.Power[0];
1412 gpu_metrics->average_soc_power = metrics.Power[1];
1413 memcpy(&gpu_metrics->average_core_power[0],
1414 &metrics.CorePower[0],
1415 sizeof(uint16_t) * 8);
1416
1417 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
1418 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
1419 gpu_metrics->average_fclk_frequency = metrics.AverageFclkFrequency;
1420 gpu_metrics->average_vclk_frequency = metrics.AverageVclkFrequency;
1421
1422 gpu_metrics->current_gfxclk = metrics.ClockFrequency[CLOCK_GFXCLK];
1423 gpu_metrics->current_socclk = metrics.ClockFrequency[CLOCK_SOCCLK];
1424 gpu_metrics->current_uclk = metrics.ClockFrequency[CLOCK_UMCCLK];
1425 gpu_metrics->current_fclk = metrics.ClockFrequency[CLOCK_FCLK];
1426 gpu_metrics->current_vclk = metrics.ClockFrequency[CLOCK_VCLK];
1427 gpu_metrics->current_dclk = metrics.ClockFrequency[CLOCK_DCLK];
1428 memcpy(&gpu_metrics->current_coreclk[0],
1429 &metrics.CoreFrequency[0],
1430 sizeof(uint16_t) * 8);
1431 gpu_metrics->current_l3clk[0] = metrics.L3Frequency[0];
1432 gpu_metrics->current_l3clk[1] = metrics.L3Frequency[1];
1433
1434 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
1435 gpu_metrics->indep_throttle_status =
1436 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
1437 renoir_throttler_map);
1438
1439 gpu_metrics->fan_pwm = metrics.FanPwm;
1440
1441 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
1442
1443 *table = (void *)gpu_metrics;
1444
1445 return sizeof(struct gpu_metrics_v2_2);
1446 }
1447
renoir_gfx_state_change_set(struct smu_context * smu,uint32_t state)1448 static int renoir_gfx_state_change_set(struct smu_context *smu, uint32_t state)
1449 {
1450
1451 return 0;
1452 }
1453
renoir_get_enabled_mask(struct smu_context * smu,uint64_t * feature_mask)1454 static int renoir_get_enabled_mask(struct smu_context *smu,
1455 uint64_t *feature_mask)
1456 {
1457 if (!feature_mask)
1458 return -EINVAL;
1459 memset(feature_mask, 0xff, sizeof(*feature_mask));
1460
1461 return 0;
1462 }
1463
1464 static const struct pptable_funcs renoir_ppt_funcs = {
1465 .set_power_state = NULL,
1466 .print_clk_levels = renoir_print_clk_levels,
1467 .get_current_power_state = renoir_get_current_power_state,
1468 .dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
1469 .dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
1470 .force_clk_levels = renoir_force_clk_levels,
1471 .set_power_profile_mode = renoir_set_power_profile_mode,
1472 .set_performance_level = renoir_set_performance_level,
1473 .get_dpm_clock_table = renoir_get_dpm_clock_table,
1474 .set_watermarks_table = renoir_set_watermarks_table,
1475 .get_power_profile_mode = renoir_get_power_profile_mode,
1476 .read_sensor = renoir_read_sensor,
1477 .check_fw_status = smu_v12_0_check_fw_status,
1478 .check_fw_version = smu_v12_0_check_fw_version,
1479 .powergate_sdma = smu_v12_0_powergate_sdma,
1480 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
1481 .send_smc_msg = smu_cmn_send_smc_msg,
1482 .set_gfx_cgpg = smu_v12_0_set_gfx_cgpg,
1483 .gfx_off_control = smu_v12_0_gfx_off_control,
1484 .get_gfx_off_status = smu_v12_0_get_gfxoff_status,
1485 .init_smc_tables = renoir_init_smc_tables,
1486 .fini_smc_tables = smu_v12_0_fini_smc_tables,
1487 .set_default_dpm_table = smu_v12_0_set_default_dpm_tables,
1488 .get_enabled_mask = renoir_get_enabled_mask,
1489 .feature_is_enabled = smu_cmn_feature_is_enabled,
1490 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
1491 .get_dpm_ultimate_freq = renoir_get_dpm_ultimate_freq,
1492 .mode2_reset = smu_v12_0_mode2_reset,
1493 .set_soft_freq_limited_range = smu_v12_0_set_soft_freq_limited_range,
1494 .set_driver_table_location = smu_v12_0_set_driver_table_location,
1495 .is_dpm_running = renoir_is_dpm_running,
1496 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
1497 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
1498 .get_gpu_metrics = renoir_get_gpu_metrics,
1499 .gfx_state_change_set = renoir_gfx_state_change_set,
1500 .set_fine_grain_gfx_freq_parameters = renoir_set_fine_grain_gfx_freq_parameters,
1501 .od_edit_dpm_table = renoir_od_edit_dpm_table,
1502 .get_vbios_bootup_values = smu_v12_0_get_vbios_bootup_values,
1503 };
1504
renoir_set_ppt_funcs(struct smu_context * smu)1505 void renoir_set_ppt_funcs(struct smu_context *smu)
1506 {
1507 struct amdgpu_device *adev = smu->adev;
1508
1509 smu->ppt_funcs = &renoir_ppt_funcs;
1510 smu->message_map = renoir_message_map;
1511 smu->clock_map = renoir_clk_map;
1512 smu->table_map = renoir_table_map;
1513 smu->workload_map = renoir_workload_map;
1514 smu->smc_driver_if_version = SMU12_DRIVER_IF_VERSION;
1515 smu->is_apu = true;
1516 smu->param_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_82);
1517 smu->msg_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_66);
1518 smu->resp_reg = SOC15_REG_OFFSET(MP1, 0, mmMP1_SMN_C2PMSG_90);
1519 }
1520