1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 #ifndef __RADEON_OBJECT_H__ 29 #define __RADEON_OBJECT_H__ 30 31 #include <drm/radeon_drm.h> 32 #include "radeon.h" 33 34 /** 35 * radeon_mem_type_to_domain - return domain corresponding to mem_type 36 * @mem_type: ttm memory type 37 * 38 * Returns corresponding domain of the ttm mem_type 39 */ radeon_mem_type_to_domain(u32 mem_type)40 static inline unsigned radeon_mem_type_to_domain(u32 mem_type) 41 { 42 switch (mem_type) { 43 case TTM_PL_VRAM: 44 return RADEON_GEM_DOMAIN_VRAM; 45 case TTM_PL_TT: 46 return RADEON_GEM_DOMAIN_GTT; 47 case TTM_PL_SYSTEM: 48 return RADEON_GEM_DOMAIN_CPU; 49 default: 50 break; 51 } 52 return 0; 53 } 54 55 /** 56 * radeon_bo_reserve - reserve bo 57 * @bo: bo structure 58 * @no_intr: don't return -ERESTARTSYS on pending signal 59 * 60 * Returns: 61 * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by 62 * a signal. Release all buffer reservations and return to user-space. 63 */ radeon_bo_reserve(struct radeon_bo * bo,bool no_intr)64 static inline int radeon_bo_reserve(struct radeon_bo *bo, bool no_intr) 65 { 66 int r; 67 68 r = ttm_bo_reserve(&bo->tbo, !no_intr, false, NULL); 69 if (unlikely(r != 0)) { 70 if (r != -ERESTARTSYS) 71 dev_err(bo->rdev->dev, "%p reserve failed\n", bo); 72 return r; 73 } 74 return 0; 75 } 76 radeon_bo_unreserve(struct radeon_bo * bo)77 static inline void radeon_bo_unreserve(struct radeon_bo *bo) 78 { 79 ttm_bo_unreserve(&bo->tbo); 80 } 81 82 /** 83 * radeon_bo_gpu_offset - return GPU offset of bo 84 * @bo: radeon object for which we query the offset 85 * 86 * Returns current GPU offset of the object. 87 * 88 * Note: object should either be pinned or reserved when calling this 89 * function, it might be useful to add check for this for debugging. 90 */ radeon_bo_gpu_offset(struct radeon_bo * bo)91 static inline u64 radeon_bo_gpu_offset(struct radeon_bo *bo) 92 { 93 struct radeon_device *rdev; 94 u64 start = 0; 95 96 rdev = radeon_get_rdev(bo->tbo.bdev); 97 98 switch (bo->tbo.resource->mem_type) { 99 case TTM_PL_TT: 100 start = rdev->mc.gtt_start; 101 break; 102 case TTM_PL_VRAM: 103 start = rdev->mc.vram_start; 104 break; 105 } 106 107 return (bo->tbo.resource->start << PAGE_SHIFT) + start; 108 } 109 radeon_bo_size(struct radeon_bo * bo)110 static inline unsigned long radeon_bo_size(struct radeon_bo *bo) 111 { 112 return bo->tbo.base.size; 113 } 114 radeon_bo_ngpu_pages(struct radeon_bo * bo)115 static inline unsigned radeon_bo_ngpu_pages(struct radeon_bo *bo) 116 { 117 return bo->tbo.base.size / RADEON_GPU_PAGE_SIZE; 118 } 119 radeon_bo_gpu_page_alignment(struct radeon_bo * bo)120 static inline unsigned radeon_bo_gpu_page_alignment(struct radeon_bo *bo) 121 { 122 return (bo->tbo.page_alignment << PAGE_SHIFT) / RADEON_GPU_PAGE_SIZE; 123 } 124 125 /** 126 * radeon_bo_mmap_offset - return mmap offset of bo 127 * @bo: radeon object for which we query the offset 128 * 129 * Returns mmap offset of the object. 130 */ radeon_bo_mmap_offset(struct radeon_bo * bo)131 static inline u64 radeon_bo_mmap_offset(struct radeon_bo *bo) 132 { 133 return drm_vma_node_offset_addr(&bo->tbo.base.vma_node); 134 } 135 136 extern int radeon_bo_create(struct radeon_device *rdev, 137 unsigned long size, int byte_align, 138 bool kernel, u32 domain, u32 flags, 139 struct sg_table *sg, 140 struct dma_resv *resv, 141 struct radeon_bo **bo_ptr); 142 extern int radeon_bo_kmap(struct radeon_bo *bo, void **ptr); 143 extern void radeon_bo_kunmap(struct radeon_bo *bo); 144 extern struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo); 145 extern void radeon_bo_unref(struct radeon_bo **bo); 146 extern int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr); 147 extern int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, 148 u64 max_offset, u64 *gpu_addr); 149 extern void radeon_bo_unpin(struct radeon_bo *bo); 150 extern int radeon_bo_evict_vram(struct radeon_device *rdev); 151 extern void radeon_bo_force_delete(struct radeon_device *rdev); 152 extern int radeon_bo_init(struct radeon_device *rdev); 153 extern void radeon_bo_fini(struct radeon_device *rdev); 154 extern int radeon_bo_list_validate(struct radeon_device *rdev, 155 struct ww_acquire_ctx *ticket, 156 struct list_head *head, int ring); 157 extern int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 158 u32 tiling_flags, u32 pitch); 159 extern void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 160 u32 *tiling_flags, u32 *pitch); 161 extern int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 162 bool force_drop); 163 extern void radeon_bo_move_notify(struct ttm_buffer_object *bo); 164 extern vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo); 165 extern int radeon_bo_get_surface_reg(struct radeon_bo *bo); 166 extern void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 167 bool shared); 168 169 /* 170 * sub allocation 171 */ 172 static inline struct radeon_sa_manager * to_radeon_sa_manager(struct drm_suballoc_manager * manager)173 to_radeon_sa_manager(struct drm_suballoc_manager *manager) 174 { 175 return container_of(manager, struct radeon_sa_manager, base); 176 } 177 radeon_sa_bo_gpu_addr(struct drm_suballoc * sa_bo)178 static inline uint64_t radeon_sa_bo_gpu_addr(struct drm_suballoc *sa_bo) 179 { 180 return to_radeon_sa_manager(sa_bo->manager)->gpu_addr + 181 drm_suballoc_soffset(sa_bo); 182 } 183 radeon_sa_bo_cpu_addr(struct drm_suballoc * sa_bo)184 static inline void *radeon_sa_bo_cpu_addr(struct drm_suballoc *sa_bo) 185 { 186 return to_radeon_sa_manager(sa_bo->manager)->cpu_ptr + 187 drm_suballoc_soffset(sa_bo); 188 } 189 190 extern int radeon_sa_bo_manager_init(struct radeon_device *rdev, 191 struct radeon_sa_manager *sa_manager, 192 unsigned size, u32 align, u32 domain, 193 u32 flags); 194 extern void radeon_sa_bo_manager_fini(struct radeon_device *rdev, 195 struct radeon_sa_manager *sa_manager); 196 extern int radeon_sa_bo_manager_start(struct radeon_device *rdev, 197 struct radeon_sa_manager *sa_manager); 198 extern int radeon_sa_bo_manager_suspend(struct radeon_device *rdev, 199 struct radeon_sa_manager *sa_manager); 200 extern int radeon_sa_bo_new(struct radeon_sa_manager *sa_manager, 201 struct drm_suballoc **sa_bo, 202 unsigned int size, unsigned int align); 203 extern void radeon_sa_bo_free(struct drm_suballoc **sa_bo, 204 struct radeon_fence *fence); 205 #if defined(CONFIG_DEBUG_FS) 206 extern void radeon_sa_bo_dump_debug_info(struct radeon_sa_manager *sa_manager, 207 struct seq_file *m); 208 #endif 209 210 211 #endif 212