1 /* 2 * Copyright (c) 2013-2016, 2018-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Previously licensed under the ISC license by Qualcomm Atheros, Inc. 6 * 7 * 8 * Permission to use, copy, modify, and/or distribute this software for 9 * any purpose with or without fee is hereby granted, provided that the 10 * above copyright notice and this permission notice appear in all 11 * copies. 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 14 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 15 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 16 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 17 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 18 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 20 * PERFORMANCE OF THIS SOFTWARE. 21 */ 22 23 /* 24 * This file was originally distributed by Qualcomm Atheros, Inc. 25 * under proprietary terms before Copyright ownership was assigned 26 * to the Linux Foundation. 27 */ 28 #ifndef __WLAN_DEFS_H__ 29 #define __WLAN_DEFS_H__ 30 31 #include <a_osapi.h> /* A_COMPILE_TIME_ASSERT */ 32 33 /* 34 * This file contains WLAN definitions that may be used across both 35 * Host and Target software. 36 */ 37 38 39 /* 40 * MAX_SPATIAL_STREAM should be defined in a fwconfig_xxx.h file, 41 * but for now provide a default value here in case it's not defined 42 * in the fwconfig_xxx.h file. 43 */ 44 #ifndef MAX_SPATIAL_STREAM 45 #define MAX_SPATIAL_STREAM 3 46 #endif 47 48 /* 49 * NOTE: The CONFIG_160MHZ_SUPPORT is not used consistently - some code 50 * uses "#ifdef CONFIG_160MHZ_SUPPORT" while other code uses 51 * "#if CONFIG_160MHZ_SUPPORT". 52 * This use is being standardized in the recent versions of code to use 53 * #ifdef, but is being left as is in the legacy code branches. 54 * To minimize impact to legacy code branches, this file internally 55 * converts CONFIG_160MHZ_SUPPORT=0 to having CONFIG_160MHZ_SUPPORT 56 * undefined. 57 * For builds that explicitly set CONFIG_160MHZ_SUPPORT=0, the bottom of 58 * this file restores CONFIG_160MHZ_SUPPORT from being undefined to being 0. 59 */ 60 // OLD: 61 //#ifndef CONFIG_160MHZ_SUPPORT 62 //#define CONFIG_160MHZ_SUPPORT 0 /* default: 160 MHz channels not supported */ 63 //#endif 64 // NEW: 65 #ifdef CONFIG_160MHZ_SUPPORT 66 /* CONFIG_160MHZ_SUPPORT is explicitly enabled or explicitly disabled */ 67 #if !CONFIG_160MHZ_SUPPORT 68 /* CONFIG_160MHZ_SUPPORT is explicitly disabled */ 69 /* Change from CONFIG_160MHZ_SUPPORT=0 to CONFIG_160MHZ_SUPPORT=<undef> */ 70 #undef CONFIG_160MHZ_SUPPORT 71 /* 72 * Set a flag to indicate this CONFIG_160MHZ_SUPPORT = 0 --> undef 73 * change has been done, so we can undo the change at the bottom 74 * of the file. 75 */ 76 #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR 77 #endif 78 #else 79 /* 80 * For backwards compatibility, if CONFIG_160MHZ_SUPPORT is not defined, 81 * default it to 0, if this is either a host build or a Rome target build. 82 * This maintains the prior behavior for the host and Rome target builds. 83 */ 84 #if defined(AR6320) || !defined(ATH_TARGET) 85 /* 86 * Set a flag to indicate that at the end of the file, 87 * CONFIG_160MHZ_SUPPORT should be set to 0. 88 */ 89 #define CONFIG_160MHZ_SUPPORT_UNDEF_WAR 90 #endif 91 #endif 92 93 #ifndef SUPPORT_11AX 94 #define SUPPORT_11AX 0 /* 11ax not supported by default */ 95 #endif 96 97 /* 98 * MAX_SPATIAL_STREAM_ANY - 99 * what is the largest number of spatial streams that any target supports 100 */ 101 #define MAX_SPATIAL_STREAM_ANY_V2 4 /* pre-hawkeye */ 102 #define MAX_SPATIAL_STREAM_ANY_V3 8 /* includes hawkeye */ 103 /* 104 * (temporarily) leave the old MAX_SPATIAL_STREAM_ANY name in place as an alias, 105 * and in case some old code is using it 106 */ 107 #define MAX_SPATIAL_STREAM_ANY MAX_SPATIAL_STREAM_ANY_V2 /* DEPRECATED */ 108 109 /* defines to set Packet extension values which can be 0, 8, or 16 usec */ 110 /* NOTE: Below values cannot be changed without breaking WMI Compatibility */ 111 #define MAX_HE_NSS 8 112 #define MAX_HE_MODULATION 8 113 #define MAX_HE_RU 4 114 #define HE_MODULATION_NONE 7 115 #define HE_PET_0_USEC 0 116 #define HE_PET_8_USEC 1 117 #define HE_PET_16_USEC 2 118 119 #define DEFAULT_OFDMA_RU26_COUNT 0 120 121 typedef enum { 122 MODE_11A = 0, /* 11a Mode */ 123 MODE_11G = 1, /* 11b/g Mode */ 124 MODE_11B = 2, /* 11b Mode */ 125 MODE_11GONLY = 3, /* 11g only Mode */ 126 MODE_11NA_HT20 = 4, /* 11a HT20 mode */ 127 MODE_11NG_HT20 = 5, /* 11g HT20 mode */ 128 MODE_11NA_HT40 = 6, /* 11a HT40 mode */ 129 MODE_11NG_HT40 = 7, /* 11g HT40 mode */ 130 MODE_11AC_VHT20 = 8, 131 MODE_11AC_VHT40 = 9, 132 MODE_11AC_VHT80 = 10, 133 MODE_11AC_VHT20_2G = 11, 134 MODE_11AC_VHT40_2G = 12, 135 MODE_11AC_VHT80_2G = 13, 136 #ifdef CONFIG_160MHZ_SUPPORT 137 MODE_11AC_VHT80_80 = 14, 138 MODE_11AC_VHT160 = 15, 139 #endif 140 141 #if SUPPORT_11AX 142 MODE_11AX_HE20 = 16, 143 MODE_11AX_HE40 = 17, 144 MODE_11AX_HE80 = 18, 145 MODE_11AX_HE80_80 = 19, 146 MODE_11AX_HE160 = 20, 147 MODE_11AX_HE20_2G = 21, 148 MODE_11AX_HE40_2G = 22, 149 MODE_11AX_HE80_2G = 23, 150 #endif 151 152 #if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) 153 MODE_11BE_EHT20 = 24, 154 MODE_11BE_EHT40 = 25, 155 MODE_11BE_EHT80 = 26, 156 MODE_11BE_EHT80_80 = 27, 157 MODE_11BE_EHT160 = 28, 158 MODE_11BE_EHT160_160 = 29, 159 MODE_11BE_EHT320 = 30, 160 MODE_11BE_EHT20_2G = 31, /* For WIN */ 161 MODE_11BE_EHT40_2G = 32, /* For WIN */ 162 #endif 163 164 /* 165 * MODE_UNKNOWN should not be used within the host / target interface. 166 * Thus, it is permissible for MODE_UNKNOWN to be conditionally-defined, 167 * taking different values when compiling for different targets. 168 */ 169 MODE_UNKNOWN, 170 MODE_UNKNOWN_NO_160MHZ_SUPPORT = 14, /* not needed? */ 171 MODE_UNKNOWN_160MHZ_SUPPORT = MODE_UNKNOWN, /* not needed? */ 172 173 #ifdef ATHR_WIN_NWF 174 PHY_MODE_MAX = MODE_UNKNOWN, 175 PHY_MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, 176 PHY_MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, 177 #else 178 MODE_MAX = MODE_UNKNOWN, 179 MODE_MAX_NO_160_MHZ_SUPPORT = MODE_UNKNOWN_NO_160MHZ_SUPPORT, 180 MODE_MAX_160_MHZ_SUPPORT = MODE_UNKNOWN_160MHZ_SUPPORT, 181 #endif 182 } WLAN_PHY_MODE; 183 184 #if (!defined(CONFIG_160MHZ_SUPPORT)) && (!defined(SUPPORT_11AX)) 185 A_COMPILE_TIME_ASSERT( 186 mode_unknown_value_consistency_Check, 187 MODE_UNKNOWN == MODE_UNKNOWN_NO_160MHZ_SUPPORT); 188 #else 189 /* 190 * If SUPPORT_11AX is defined but CONFIG_160MHZ_SUPPORT is not defined, 191 * there will be a gap in the mode values, with 14 and 15 being unused. 192 * But MODE_UNKNOWN_NO_160MHZ_SUPPORT will have an invalid value, since 193 * mode values 16 through 23 will be used for 11AX modes. 194 * Thus, MODE_UNKNOWN would still be MODE_UNKNOWN_160MHZ_SUPPORT, for 195 * cases where 160 MHz is not supported by 11AX is supported. 196 * (Ideally, MODE_UNKNOWN_160MHZ_SUPPORT and NO_160MHZ_SUPPORT should be 197 * renamed to cover the 4 permutations of support or no support for 198 * 11AX and 160 MHZ, but that is impractical, due to backwards 199 * compatibility concerns.) 200 */ 201 A_COMPILE_TIME_ASSERT( 202 mode_unknown_value_consistency_Check, 203 MODE_UNKNOWN == MODE_UNKNOWN_160MHZ_SUPPORT); 204 #endif 205 206 typedef enum { 207 VHT_MODE_NONE = 0, /* NON VHT Mode, e.g., HT, DSSS, CCK */ 208 VHT_MODE_20M = 1, 209 VHT_MODE_40M = 2, 210 VHT_MODE_80M = 3, 211 VHT_MODE_160M = 4 212 } VHT_OPER_MODE; 213 214 typedef enum { 215 WLAN_11A_CAPABILITY = 1, 216 WLAN_11G_CAPABILITY = 2, 217 WLAN_11AG_CAPABILITY = 3, 218 } WLAN_CAPABILITY; 219 220 #ifdef CONFIG_160MHZ_SUPPORT 221 #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ 222 ((mode) == MODE_11AC_VHT40) || \ 223 ((mode) == MODE_11AC_VHT80) || \ 224 ((mode) == MODE_11AC_VHT80_80) || \ 225 ((mode) == MODE_11AC_VHT160)) 226 #else 227 #define IS_MODE_VHT(mode) (((mode) == MODE_11AC_VHT20) || \ 228 ((mode) == MODE_11AC_VHT40) || \ 229 ((mode) == MODE_11AC_VHT80)) 230 #endif 231 232 #if SUPPORT_11AX 233 #define IS_MODE_HE(mode) (((mode) == MODE_11AX_HE20) || \ 234 ((mode) == MODE_11AX_HE40) || \ 235 ((mode) == MODE_11AX_HE80) || \ 236 ((mode) == MODE_11AX_HE80_80) || \ 237 ((mode) == MODE_11AX_HE160) || \ 238 ((mode) == MODE_11AX_HE20_2G) || \ 239 ((mode) == MODE_11AX_HE40_2G) || \ 240 ((mode) == MODE_11AX_HE80_2G)) 241 #define IS_MODE_HE_5G_6G(mode) (((mode) == MODE_11AX_HE20) || \ 242 ((mode) == MODE_11AX_HE40) || \ 243 ((mode) == MODE_11AX_HE80) || \ 244 ((mode) == MODE_11AX_HE80_80) || \ 245 ((mode) == MODE_11AX_HE160)) 246 #define IS_MODE_HE_2G(mode) (((mode) == MODE_11AX_HE20_2G) || \ 247 ((mode) == MODE_11AX_HE40_2G) || \ 248 ((mode) == MODE_11AX_HE80_2G)) 249 #endif /* SUPPORT_11AX */ 250 251 #if (defined(SUPPORT_11BE) && SUPPORT_11BE) || defined(SUPPORT_11BE_ROM) 252 #define IS_MODE_EHT(mode) (((mode) == MODE_11BE_EHT20) || \ 253 ((mode) == MODE_11BE_EHT40) || \ 254 ((mode) == MODE_11BE_EHT80) || \ 255 ((mode) == MODE_11BE_EHT80_80) || \ 256 ((mode) == MODE_11BE_EHT160) || \ 257 ((mode) == MODE_11BE_EHT160_160)|| \ 258 ((mode) == MODE_11BE_EHT320) || \ 259 ((mode) == MODE_11BE_EHT20_2G) || \ 260 ((mode) == MODE_11BE_EHT40_2G)) 261 #define IS_MODE_EHT_2G(mode) (((mode) == MODE_11BE_EHT20_2G) || \ 262 ((mode) == MODE_11BE_EHT40_2G)) 263 #endif /* SUPPORT_11BE */ 264 265 #define IS_MODE_VHT_2G(mode) (((mode) == MODE_11AC_VHT20_2G) || \ 266 ((mode) == MODE_11AC_VHT40_2G) || \ 267 ((mode) == MODE_11AC_VHT80_2G)) 268 269 270 #define IS_MODE_11A(mode) (((mode) == MODE_11A) || \ 271 ((mode) == MODE_11NA_HT20) || \ 272 ((mode) == MODE_11NA_HT40) || \ 273 (IS_MODE_VHT(mode))) 274 275 #define IS_MODE_11B(mode) ((mode) == MODE_11B) 276 #define IS_MODE_11G(mode) (((mode) == MODE_11G) || \ 277 ((mode) == MODE_11GONLY) || \ 278 ((mode) == MODE_11NG_HT20) || \ 279 ((mode) == MODE_11NG_HT40) || \ 280 (IS_MODE_VHT_2G(mode))) 281 #define IS_MODE_11GN(mode) (((mode) == MODE_11NG_HT20) || \ 282 ((mode) == MODE_11NG_HT40)) 283 #define IS_MODE_11GONLY(mode) ((mode) == MODE_11GONLY) 284 285 #define IS_MODE_LEGACY(phymode) ((phymode == MODE_11A) || \ 286 (phymode == MODE_11G) || \ 287 (phymode == MODE_11B) || \ 288 (phymode == MODE_11GONLY)) 289 290 #define IS_MODE_11N(phymode) ((phymode >= MODE_11NA_HT20) && \ 291 (phymode <= MODE_11NG_HT40)) 292 #ifdef CONFIG_160MHZ_SUPPORT 293 #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \ 294 (phymode <= MODE_11AC_VHT160)) 295 #define IS_MODE_11AC_5G(phymode) ((phymode == MODE_11AC_VHT20) || \ 296 (phymode == MODE_11AC_VHT40) || \ 297 (phymode == MODE_11AC_VHT80) || \ 298 (phymode == MODE_11AC_VHT80_80) || \ 299 (phymode == MODE_11AC_VHT160)) 300 #else 301 #define IS_MODE_11AC(phymode) ((phymode >= MODE_11AC_VHT20) && \ 302 (phymode <= MODE_11AC_VHT80_2G)) 303 #define IS_MODE_11AC_5G(phymode) ((phymode == MODE_11AC_VHT20) || \ 304 (phymode == MODE_11AC_VHT40) || \ 305 (phymode == MODE_11AC_VHT80)) 306 #endif /* CONFIG_160MHZ_SUPPORT */ 307 308 #if SUPPORT_11AX 309 #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \ 310 (phymode == MODE_11AC_VHT80) || \ 311 (phymode == MODE_11AX_HE80) || \ 312 (phymode == MODE_11AX_HE80_2G)) 313 #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \ 314 (phymode == MODE_11AC_VHT40) || \ 315 (phymode == MODE_11NG_HT40) || \ 316 (phymode == MODE_11NA_HT40) || \ 317 (phymode == MODE_11AX_HE40) || \ 318 (phymode == MODE_11AX_HE40_2G)) 319 #else 320 #define IS_MODE_80MHZ(phymode) ((phymode == MODE_11AC_VHT80_2G) || \ 321 (phymode == MODE_11AC_VHT80)) 322 #define IS_MODE_40MHZ(phymode) ((phymode == MODE_11AC_VHT40_2G) || \ 323 (phymode == MODE_11AC_VHT40) || \ 324 (phymode == MODE_11NG_HT40) || \ 325 (phymode == MODE_11NA_HT40)) 326 #endif /* SUPPORT_11AX */ 327 328 enum { 329 REGDMN_MODE_11A_BIT = 0, /* 11a channels */ 330 REGDMN_MODE_TURBO_BIT = 1, /* 11a turbo-only channels */ 331 REGDMN_MODE_11B_BIT = 2, /* 11b channels */ 332 REGDMN_MODE_PUREG_BIT = 3, /* 11g channels (OFDM only) */ 333 REGDMN_MODE_11G_BIT = 3, /* XXX historical */ 334 /* bit 4 is reserved */ 335 REGDMN_MODE_108G_BIT = 5, /* 11g+Turbo channels */ 336 REGDMN_MODE_108A_BIT = 6, /* 11a+Turbo channels */ 337 /* bit 7 is reserved */ 338 REGDMN_MODE_XR_BIT = 8, /* XR channels */ 339 REGDMN_MODE_11A_HALF_RATE_BIT = 9, /* 11A half rate channels */ 340 REGDMN_MODE_11A_QUARTER_RATE_BIT = 10, /* 11A quarter rate channels */ 341 REGDMN_MODE_11NG_HT20_BIT = 11, /* 11N-G HT20 channels */ 342 REGDMN_MODE_11NA_HT20_BIT = 12, /* 11N-A HT20 channels */ 343 REGDMN_MODE_11NG_HT40PLUS_BIT = 13, /* 11N-G HT40 + channels */ 344 REGDMN_MODE_11NG_HT40MINUS_BIT = 14, /* 11N-G HT40 - channels */ 345 REGDMN_MODE_11NA_HT40PLUS_BIT = 15, /* 11N-A HT40 + channels */ 346 REGDMN_MODE_11NA_HT40MINUS_BIT = 16, /* 11N-A HT40 - channels */ 347 REGDMN_MODE_11AC_VHT20_BIT = 17, /* 5Ghz, VHT20 */ 348 REGDMN_MODE_11AC_VHT40PLUS_BIT = 18, /* 5Ghz, VHT40 + channels */ 349 REGDMN_MODE_11AC_VHT40MINUS_BIT = 19, /* 5Ghz VHT40 - channels */ 350 REGDMN_MODE_11AC_VHT80_BIT = 20, /* 5Ghz, VHT80 channels */ 351 REGDMN_MODE_11AC_VHT20_2G_BIT = 21, /* 2Ghz, VHT20 */ 352 REGDMN_MODE_11AC_VHT40_2G_BIT = 22, /* 2Ghz, VHT40 */ 353 REGDMN_MODE_11AC_VHT80_2G_BIT = 23, /* 2Ghz, VHT80 */ 354 REGDMN_MODE_11AC_VHT160_BIT = 24, /* 5Ghz, VHT160 */ 355 REGDMN_MODE_11AC_VHT40_2GPLUS_BIT = 25, /* 2Ghz, VHT40+ */ 356 REGDMN_MODE_11AC_VHT40_2GMINUS_BIT = 26, /* 2Ghz, VHT40- */ 357 REGDMN_MODE_11AC_VHT80_80_BIT = 27, /* 5GHz, VHT80+80 */ 358 /* bits 28 to 31 are reserved */ 359 REGDMN_MODE_11AXG_HE20_BIT = 32, /* 2Ghz, HE20 */ 360 REGDMN_MODE_11AXA_HE20_BIT = 33, /* 5Ghz, HE20 */ 361 REGDMN_MODE_11AXG_HE40PLUS_BIT = 34, /* 2Ghz, HE40+ */ 362 REGDMN_MODE_11AXG_HE40MINUS_BIT = 35, /* 2Ghz, HE40- */ 363 REGDMN_MODE_11AXA_HE40PLUS_BIT = 36, /* 5Ghz, HE40+ */ 364 REGDMN_MODE_11AXA_HE40MINUS_BIT = 37, /* 5Ghz, HE40- */ 365 REGDMN_MODE_11AXA_HE80_BIT = 38, /* 5Ghz, HE80 */ 366 REGDMN_MODE_11AXA_HE160_BIT = 39, /* 5Ghz, HE160 */ 367 REGDMN_MODE_11AXA_HE80_80_BIT = 40, /* 5Ghz, HE80+80 */ 368 REGDMN_MODE_11BEG_EHT20_BIT = 41, /* 2Ghz, EHT20 */ 369 REGDMN_MODE_11BEA_EHT20_BIT = 42, /* 5Ghz, EHT20 */ 370 REGDMN_MODE_11BEG_EHT40PLUS_BIT = 43, /* 2Ghz, EHT40+ */ 371 REGDMN_MODE_11BEG_EHT40MINUS_BIT = 44, /* 2Ghz, EHT40- */ 372 REGDMN_MODE_11BEA_EHT40PLUS_BIT = 45, /* 5Ghz, EHT40+ */ 373 REGDMN_MODE_11BEA_EHT40MINUS_BIT = 46, /* 5Ghz, EHT40- */ 374 REGDMN_MODE_11BEA_EHT80_BIT = 47, /* 5Ghz, EHT80 */ 375 REGDMN_MODE_11BEA_EHT160_BIT = 48, /* 5Ghz, EHT160 */ 376 REGDMN_MODE_11BEA_EHT320_BIT = 49, /* 5Ghz, EHT320 */ 377 }; 378 379 enum { 380 REGDMN_MODE_11A = 1 << REGDMN_MODE_11A_BIT, /* 11a channels */ 381 REGDMN_MODE_TURBO = 1 << REGDMN_MODE_TURBO_BIT, /* 11a turbo-only channels */ 382 REGDMN_MODE_11B = 1 << REGDMN_MODE_11B_BIT, /* 11b channels */ 383 REGDMN_MODE_PUREG = 1 << REGDMN_MODE_PUREG_BIT, /* 11g channels (OFDM only) */ 384 REGDMN_MODE_11G = 1 << REGDMN_MODE_11G_BIT, /* XXX historical */ 385 REGDMN_MODE_108G = 1 << REGDMN_MODE_108G_BIT, /* 11g+Turbo channels */ 386 REGDMN_MODE_108A = 1 << REGDMN_MODE_108A_BIT, /* 11a+Turbo channels */ 387 REGDMN_MODE_XR = 1 << REGDMN_MODE_XR_BIT, /* XR channels */ 388 REGDMN_MODE_11A_HALF_RATE = 1 << REGDMN_MODE_11A_HALF_RATE_BIT, /* 11A half rate channels */ 389 REGDMN_MODE_11A_QUARTER_RATE = 1 << REGDMN_MODE_11A_QUARTER_RATE_BIT, /* 11A quarter rate channels */ 390 REGDMN_MODE_11NG_HT20 = 1 << REGDMN_MODE_11NG_HT20_BIT, /* 11N-G HT20 channels */ 391 REGDMN_MODE_11NA_HT20 = 1 << REGDMN_MODE_11NA_HT20_BIT, /* 11N-A HT20 channels */ 392 REGDMN_MODE_11NG_HT40PLUS = 1 << REGDMN_MODE_11NG_HT40PLUS_BIT, /* 11N-G HT40 + channels */ 393 REGDMN_MODE_11NG_HT40MINUS = 1 << REGDMN_MODE_11NG_HT40MINUS_BIT, /* 11N-G HT40 - channels */ 394 REGDMN_MODE_11NA_HT40PLUS = 1 << REGDMN_MODE_11NA_HT40PLUS_BIT, /* 11N-A HT40 + channels */ 395 REGDMN_MODE_11NA_HT40MINUS = 1 << REGDMN_MODE_11NA_HT40MINUS_BIT, /* 11N-A HT40 - channels */ 396 REGDMN_MODE_11AC_VHT20 = 1 << REGDMN_MODE_11AC_VHT20_BIT, /* 5Ghz, VHT20 */ 397 REGDMN_MODE_11AC_VHT40PLUS = 1 << REGDMN_MODE_11AC_VHT40PLUS_BIT, /* 5Ghz, VHT40 + channels */ 398 REGDMN_MODE_11AC_VHT40MINUS = 1 << REGDMN_MODE_11AC_VHT40MINUS_BIT, /* 5Ghz VHT40 - channels */ 399 REGDMN_MODE_11AC_VHT80 = 1 << REGDMN_MODE_11AC_VHT80_BIT, /* 5Ghz, VHT80 channels */ 400 REGDMN_MODE_11AC_VHT20_2G = 1 << REGDMN_MODE_11AC_VHT20_2G_BIT, /* 2Ghz, VHT20 */ 401 REGDMN_MODE_11AC_VHT40_2G = 1 << REGDMN_MODE_11AC_VHT40_2G_BIT, /* 2Ghz, VHT40 */ 402 REGDMN_MODE_11AC_VHT80_2G = 1 << REGDMN_MODE_11AC_VHT80_2G_BIT, /* 2Ghz, VHT80 */ 403 REGDMN_MODE_11AC_VHT160 = 1 << REGDMN_MODE_11AC_VHT160_BIT, /* 5Ghz, VHT160 */ 404 REGDMN_MODE_11AC_VHT40_2GPLUS = 1 << REGDMN_MODE_11AC_VHT40_2GPLUS_BIT, /* 2Ghz, VHT40+ */ 405 REGDMN_MODE_11AC_VHT40_2GMINUS = 1 << REGDMN_MODE_11AC_VHT40_2GMINUS_BIT, /* 2Ghz, VHT40- */ 406 REGDMN_MODE_11AC_VHT80_80 = 1 << REGDMN_MODE_11AC_VHT80_80_BIT, /* 5GHz, VHT80+80 */ 407 }; 408 409 enum { 410 REGDMN_MODE_U32_11AXG_HE20 = 1 << (REGDMN_MODE_11AXG_HE20_BIT - 32), 411 REGDMN_MODE_U32_11AXA_HE20 = 1 << (REGDMN_MODE_11AXA_HE20_BIT - 32), 412 REGDMN_MODE_U32_11AXG_HE40PLUS = 1 << (REGDMN_MODE_11AXG_HE40PLUS_BIT - 32), 413 REGDMN_MODE_U32_11AXG_HE40MINUS = 1 << (REGDMN_MODE_11AXG_HE40MINUS_BIT - 32), 414 REGDMN_MODE_U32_11AXA_HE40PLUS = 1 << (REGDMN_MODE_11AXA_HE40PLUS_BIT - 32), 415 REGDMN_MODE_U32_11AXA_HE40MINUS = 1 << (REGDMN_MODE_11AXA_HE40MINUS_BIT - 32), 416 REGDMN_MODE_U32_11AXA_HE80 = 1 << (REGDMN_MODE_11AXA_HE80_BIT - 32), 417 REGDMN_MODE_U32_11AXA_HE160 = 1 << (REGDMN_MODE_11AXA_HE160_BIT - 32), 418 REGDMN_MODE_U32_11AXA_HE80_80 = 1 << (REGDMN_MODE_11AXA_HE80_80_BIT - 32), 419 REGDMN_MODE_U32_11BEG_EHT20 = 1 << (REGDMN_MODE_11BEG_EHT20_BIT - 32), 420 REGDMN_MODE_U32_11BEA_EHT20 = 1 << (REGDMN_MODE_11BEA_EHT20_BIT - 32), 421 REGDMN_MODE_U32_11BEG_EHT40PLUS = 1 << (REGDMN_MODE_11BEG_EHT40PLUS_BIT - 32), 422 REGDMN_MODE_U32_11BEG_EHT40MINUS = 1 << (REGDMN_MODE_11BEG_EHT40MINUS_BIT - 32), 423 REGDMN_MODE_U32_11BEA_EHT40PLUS = 1 << (REGDMN_MODE_11BEA_EHT40PLUS_BIT - 32), 424 REGDMN_MODE_U32_11BEA_EHT40MINUS = 1 << (REGDMN_MODE_11BEA_EHT40MINUS_BIT - 32), 425 REGDMN_MODE_U32_11BEA_EHT80 = 1 << (REGDMN_MODE_11BEA_EHT80_BIT - 32), 426 REGDMN_MODE_U32_11BEA_EHT160 = 1 << (REGDMN_MODE_11BEA_EHT160_BIT - 32), 427 REGDMN_MODE_U32_11BEA_EHT320 = 1 << (REGDMN_MODE_11BEA_EHT320_BIT - 32), 428 }; 429 430 #define REGDMN_MODE_ALL (0xFFFFFFFF) /* REGDMN_MODE_ALL is defined out of the enum 431 * to prevent the ARM compile "warning #66: 432 * enumeration value is out of int range" 433 * Anyway, this is a BIT-OR of all possible values. 434 */ 435 436 #define REGDMN_CAP1_CHAN_HALF_RATE 0x00000001 437 #define REGDMN_CAP1_CHAN_QUARTER_RATE 0x00000002 438 #define REGDMN_CAP1_CHAN_HAL49GHZ 0x00000004 439 440 441 /* regulatory capabilities */ 442 #define REGDMN_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 443 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 444 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U2 0x0100 445 #define REGDMN_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 446 #define REGDMN_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 447 #define REGDMN_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 448 449 typedef struct { 450 A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_HAL_REG_CAPABILITIES */ 451 A_UINT32 eeprom_rd; /* regdomain value specified in EEPROM */ 452 A_UINT32 eeprom_rd_ext; /* regdomain */ 453 A_UINT32 regcap1; /* CAP1 capabilities bit map. */ 454 A_UINT32 regcap2; /* REGDMN EEPROM CAP. */ 455 A_UINT32 wireless_modes; /* REGDMN MODE */ 456 A_UINT32 low_2ghz_chan; 457 A_UINT32 high_2ghz_chan; 458 A_UINT32 low_5ghz_chan; 459 A_UINT32 high_5ghz_chan; 460 A_UINT32 wireless_modes_ext; /* REGDMN MODE ext */ 461 A_UINT32 low_2ghz_chan_ext; 462 A_UINT32 high_2ghz_chan_ext; 463 A_UINT32 low_5ghz_chan_ext; 464 A_UINT32 high_5ghz_chan_ext; 465 } HAL_REG_CAPABILITIES; 466 467 #ifdef NUM_SPATIAL_STREAM 468 /* 469 * The rate control definitions below are only used in the target. 470 * (Host-based rate control is no longer applicable.) 471 * Maintain the defs in wlanfw_cmn for the sake of existing Rome / Helium 472 * targets, but for Lithium targets remove them from wlanfw_cmn and define 473 * them in a target-only location instead. 474 * SUPPORT_11AX is essentially used as a condition to identify Lithium targets. 475 * Some host drivers would also have SUPPORT_11AX defined, and thus would lose 476 * the definition of RATE_CODE, RC_TX_DONE_PARAMS, and related macros, but 477 * that's okay because the host should have no references to these 478 * target-only data structures. 479 */ 480 #if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) /* following N/A for Lithium */ 481 482 /* 483 * Used to update rate-control logic with the status of the tx-completion. 484 * In host-based implementation of the rate-control feature, this structure 485 * is used to create the payload for HTT message/s from target to host. 486 */ 487 #ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE 488 #if (NUM_SPATIAL_STREAM > 3) 489 #define A_RATEMASK A_UINT64 490 #else 491 #define A_RATEMASK A_UINT32 492 #endif 493 #endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */ 494 495 typedef A_UINT8 A_RATE; 496 typedef A_UINT8 A_RATECODE; 497 498 #define A_RATEMASK_NUM_OCTET (sizeof (A_RATEMASK)) 499 #define A_RATEMASK_NUM_BITS ((sizeof (A_RATEMASK)) << 3) 500 501 typedef struct { 502 A_RATECODE rateCode; 503 A_UINT8 flags; 504 } RATE_CODE; 505 506 typedef struct { 507 RATE_CODE ptx_rc; /* rate code, bw, chain mask sgi */ 508 A_UINT8 reserved[2]; 509 A_UINT32 flags; /* Encodes information such as excessive 510 retransmission, aggregate, some info 511 from .11 frame control, 512 STBC, LDPC, (SGI and Tx Chain Mask 513 are encoded in ptx_rc->flags field), 514 AMPDU truncation (BT/time based etc.), 515 RTS/CTS attempt */ 516 A_UINT32 num_enqued; /* # of MPDUs (for non-AMPDU 1) for this rate */ 517 A_UINT32 num_retries; /* Total # of transmission attempt for this rate */ 518 A_UINT32 num_failed; /* # of failed MPDUs in A-MPDU, 0 otherwise */ 519 A_UINT32 ack_rssi; /* ACK RSSI: b'7..b'0 avg RSSI across all chain */ 520 A_UINT32 time_stamp ; /* ACK timestamp (helps determine age) */ 521 A_UINT32 is_probe; /* Valid if probing. Else, 0 */ 522 A_UINT32 ba_win_size; /* b'7..b0, block Ack Window size, b'31..b8 Resvd */ 523 A_UINT32 failed_ba_bmap_0_31; /* failed BA bitmap 0..31 */ 524 A_UINT32 failed_ba_bmap_32_63; /* failed BA bitmap 32..63 */ 525 A_UINT32 bmap_tried_0_31; /* enqued bitmap 0..31 */ 526 A_UINT32 bmap_tried_32_63; /* enqued bitmap 32..63 */ 527 } RC_TX_DONE_PARAMS; 528 529 530 #define RC_SET_TX_DONE_INFO(_dst, _rc, _f, _nq, _nr, _nf, _rssi, _ts) \ 531 do { \ 532 (_dst).ptx_rc.rateCode = (_rc).rateCode; \ 533 (_dst).ptx_rc.flags = (_rc).flags; \ 534 (_dst).flags = (_f); \ 535 (_dst).num_enqued = (_nq); \ 536 (_dst).num_retries = (_nr); \ 537 (_dst).num_failed = (_nf); \ 538 (_dst).ack_rssi = (_rssi); \ 539 (_dst).time_stamp = (_ts); \ 540 } while (0) 541 542 #define RC_SET_TXBF_DONE_INFO(_dst, _f) \ 543 do { \ 544 (_dst).flags |= (_f); \ 545 } while (0) 546 547 /* 548 * NOTE: NUM_SCHED_ENTRIES is not used in the host/target interface, but for 549 * historical reasons has been defined in the host/target interface files. 550 * The NUM_SCHED_ENTRIES definition is being moved into a target-only 551 * header file for newer (Lithium) targets, but is being left here for 552 * non-Lithium cases, to avoid having to rework legacy targets to move 553 * the NUM_SCHED_ENTRIES definition into a target-only header file. 554 * Moving the NUM_SCHED_ENTRIES definition into a non-Lithium conditional 555 * block should have no impact on the host, since the host does not use 556 * NUM_SCHED_ENTRIES. 557 */ 558 #define NUM_SCHED_ENTRIES 2 559 560 #endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */ /* above N/A for Lithium */ 561 #endif /* NUM_SPATIAL_STREAM */ 562 563 /* NOTE: NUM_DYN_BW cannot be changed without breaking WMI Compatibility */ 564 #define NUM_DYN_BW_MAX 4 565 566 /* Some products only use 20/40/80; some use 20/40/80/160 */ 567 #ifndef NUM_DYN_BW 568 #define NUM_DYN_BW 3 /* default: support up through 80 MHz */ 569 #endif 570 571 #define NUM_DYN_BW_MASK 0x3 572 573 #define PROD_SCHED_BW_ENTRIES (NUM_SCHED_ENTRIES * NUM_DYN_BW) 574 575 #if NUM_DYN_BW > 5 576 /* Extend rate table module first */ 577 #error "Extend rate table module first" 578 #endif 579 580 #define MAX_IBSS_PEERS 32 581 582 #ifdef NUM_SPATIAL_STREAM 583 /* 584 * RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO defs are used only in the target. 585 * (Host-based rate control is no longer applicable.) 586 * Maintain the defs in wlanfw_cmn for the sake of existing Rome / Helium 587 * targets, but for Lithium targets remove them from wlanfw_cmn and define 588 * them in a target-only location instead. 589 * SUPPORT_11AX is essentially used as a condition to identify Lithium targets. 590 * Some host drivers would also have SUPPORT_11AX defined, and thus would lose 591 * the definition of RC_TX_RATE_SCHEDULE and RC_TX_RATE_INFO, but that's okay 592 * because the host should have no references to these target-only data 593 * structures. 594 */ 595 #ifndef CONFIG_MOVE_RC_STRUCT_TO_MACCORE 596 #if !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) 597 #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) 598 typedef struct{ 599 A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 600 A_UINT16 flags[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 601 A_RATE rix[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 602 A_UINT8 tpc[NUM_SCHED_ENTRIES][NUM_DYN_BW]; 603 A_UINT32 antmask[NUM_SCHED_ENTRIES]; 604 A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 605 A_UINT16 txbf_cv_len; 606 A_UINT32 txbf_cv_ptr; 607 A_UINT16 txbf_flags; 608 A_UINT16 txbf_cv_size; 609 A_UINT8 txbf_nc_idx; 610 A_UINT8 tries[NUM_SCHED_ENTRIES]; 611 A_UINT8 bw_mask[NUM_SCHED_ENTRIES]; 612 A_UINT8 max_bw[NUM_SCHED_ENTRIES]; 613 A_UINT8 num_sched_entries; 614 A_UINT8 paprd_mask; 615 A_RATE rts_rix; 616 A_UINT8 sh_pream; 617 A_UINT8 min_spacing_1_4_us; 618 A_UINT8 fixed_delims; 619 A_UINT8 bw_in_service; 620 A_RATE probe_rix; 621 A_UINT8 num_valid_rates; 622 A_UINT8 rtscts_tpc; 623 A_UINT8 dd_profile; 624 } RC_TX_RATE_SCHEDULE; 625 #else 626 typedef struct{ 627 A_UINT32 psdu_len[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 628 A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 629 A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 630 A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 631 A_UINT8 num_mpdus[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 632 A_UINT32 antmask[NUM_SCHED_ENTRIES]; 633 A_UINT32 txbf_cv_ptr; 634 A_UINT16 txbf_cv_len; 635 A_UINT8 tries[NUM_SCHED_ENTRIES]; 636 A_UINT8 num_valid_rates; 637 A_UINT8 paprd_mask; 638 A_RATE rts_rix; 639 A_UINT8 sh_pream; 640 A_UINT8 min_spacing_1_4_us; 641 A_UINT8 fixed_delims; 642 A_UINT8 bw_in_service; 643 A_RATE probe_rix; 644 } RC_TX_RATE_SCHEDULE; 645 #endif 646 647 typedef struct{ 648 A_UINT16 flags[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 649 A_RATE rix[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 650 #ifdef DYN_TPC_ENABLE 651 A_UINT8 tpc[NUM_DYN_BW * NUM_SCHED_ENTRIES]; 652 #endif 653 #ifdef SECTORED_ANTENNA 654 A_UINT32 antmask[NUM_SCHED_ENTRIES]; 655 #endif 656 A_UINT8 tries[NUM_SCHED_ENTRIES]; 657 A_UINT8 num_valid_rates; 658 A_RATE rts_rix; 659 A_UINT8 sh_pream; 660 A_UINT8 bw_in_service; 661 A_RATE probe_rix; 662 A_UINT8 dd_profile; 663 } RC_TX_RATE_INFO; 664 #endif /* !((NUM_SPATIAL_STREAM > 4) || SUPPORT_11AX) */ 665 #endif /* CONFIG_MOVE_RC_STRUCT_TO_MACCORE */ 666 #endif 667 668 /* 669 * Temporarily continue to provide the WHAL_RC_INIT_RC_MASKS def in wlan_defs.h 670 * for older targets. 671 * The WHAL_RX_INIT_RC_MASKS macro def needs to be moved into ratectrl_11ac.h 672 * for all targets, but until this is complete, the WHAL_RC_INIT_RC_MASKS def 673 * will be maintained here in its old location. 674 */ 675 #ifndef CONFIG_160MHZ_SUPPORT 676 #define WHAL_RC_INIT_RC_MASKS(_rm) do { \ 677 _rm[WHAL_RC_MASK_IDX_NON_HT] = A_RATEMASK_OFDM_CCK; \ 678 _rm[WHAL_RC_MASK_IDX_HT_20] = A_RATEMASK_HT_20; \ 679 _rm[WHAL_RC_MASK_IDX_HT_40] = A_RATEMASK_HT_40; \ 680 _rm[WHAL_RC_MASK_IDX_VHT_20] = A_RATEMASK_VHT_20; \ 681 _rm[WHAL_RC_MASK_IDX_VHT_40] = A_RATEMASK_VHT_40; \ 682 _rm[WHAL_RC_MASK_IDX_VHT_80] = A_RATEMASK_VHT_80; \ 683 } while (0) 684 #endif 685 686 /** 687 * structure describing host memory chunk. 688 */ 689 typedef struct { 690 A_UINT32 tlv_header; /* TLV tag and len; tag equals WMITLV_TAG_STRUC_wlan_host_memory_chunk */ 691 /** id of the request that is passed up in service ready */ 692 A_UINT32 req_id; 693 /** the physical address the memory chunk */ 694 A_UINT32 ptr; 695 /** size of the chunk */ 696 A_UINT32 size; 697 /** ptr_high 698 * most significant bits of physical address of the memory chunk 699 * Only applicable for addressing more than 32 bit. 700 * This will only be non-zero if the target has set 701 * WMI_SERVICE_SUPPORT_EXTEND_ADDRESS flag. 702 */ 703 A_UINT32 ptr_high; 704 } wlan_host_memory_chunk; 705 706 #define NUM_UNITS_IS_NUM_VDEVS 0x1 707 #define NUM_UNITS_IS_NUM_PEERS 0x2 708 #define NUM_UNITS_IS_NUM_ACTIVE_PEERS 0x4 709 /* request host to allocate memory contiguously */ 710 #define REQ_TO_HOST_FOR_CONT_MEMORY 0x8 711 712 /** 713 * structure used by FW for requesting host memory 714 */ 715 typedef struct { 716 A_UINT32 tlv_header; /* TLV tag and len; tag equals WMI_TLVTAG_STRUC_wlan_host_mem_req */ 717 718 /** ID of the request */ 719 A_UINT32 req_id; 720 /** size of the of each unit */ 721 A_UINT32 unit_size; 722 /** 723 * flags to indicate that 724 * the number units is dependent 725 * on number of resources(num vdevs num peers .. etc) 726 */ 727 A_UINT32 num_unit_info; 728 /* 729 * actual number of units to allocate . if flags in the num_unit_info 730 * indicate that number of units is tied to number of a particular 731 * resource to allocate then num_units filed is set to 0 and host 732 * will derive the number units from number of the resources it is 733 * requesting. 734 */ 735 A_UINT32 num_units; 736 } wlan_host_mem_req; 737 738 typedef enum { 739 IGNORE_DTIM = 0x01, 740 NORMAL_DTIM = 0x02, 741 STICK_DTIM = 0x03, 742 AUTO_DTIM = 0x04, 743 } BEACON_DTIM_POLICY; 744 745 /* During test it is observed that 6 * 400 = 2400 can 746 * be alloced in addition to CFG_TGT_NUM_MSDU_DESC. 747 * If there is any change memory requirement, this number 748 * needs to be revisited. */ 749 #define TOTAL_VOW_ALLOCABLE 2400 750 #define VOW_DESC_GRAB_MAX 800 751 752 #define VOW_GET_NUM_VI_STA(vow_config) (((vow_config) & 0xffff0000) >> 16) 753 #define VOW_GET_DESC_PER_VI_STA(vow_config) ((vow_config) & 0x0000ffff) 754 755 /***TODO!!! Get these values dynamically in WMI_READY event and use it to calculate the mem req*/ 756 /* size in bytes required for msdu descriptor. If it changes, this should be updated. LARGE_AP 757 * case is not considered. LARGE_AP is disabled when VoW is enabled.*/ 758 #define MSDU_DESC_SIZE 20 759 760 /* size in bytes required to support a peer in target. 761 * This obtained by considering Two tids per peer. 762 * peer structure = 168 bytes 763 * tid = 96 bytes (per sta 2 means we need 192 bytes) 764 * peer_cb = 16 * 2 765 * key = 52 * 2 766 * AST = 12 * 2 767 * rate, reorder.. = 384 768 * smart antenna = 50 769 */ 770 #define MEMORY_REQ_FOR_PEER 800 771 /* 772 * NB: it is important to keep all the fields in the structure dword long 773 * so that it is easy to handle the statistics in BE host. 774 */ 775 776 /* 777 * wlan_dbg_tx_stats_v1, _v2: 778 * differing versions of the wlan_dbg_tx_stats struct used by different 779 * targets 780 */ 781 struct wlan_dbg_tx_stats_v1 { 782 /* Num HTT cookies queued to dispatch list */ 783 A_INT32 comp_queued; 784 /* Num HTT cookies dispatched */ 785 A_INT32 comp_delivered; 786 /* Num MSDU queued to WAL */ 787 A_INT32 msdu_enqued; 788 /* Num MPDU queue to WAL */ 789 A_INT32 mpdu_enqued; 790 /* Num MSDUs dropped by WMM limit */ 791 A_INT32 wmm_drop; 792 /* Num Local frames queued */ 793 A_INT32 local_enqued; 794 /* Num Local frames done */ 795 A_INT32 local_freed; 796 /* Num queued to HW */ 797 A_INT32 hw_queued; 798 /* Num PPDU reaped from HW */ 799 A_INT32 hw_reaped; 800 /* Num underruns */ 801 A_INT32 underrun; 802 /* Num PPDUs cleaned up in TX abort */ 803 A_INT32 tx_abort; 804 /* Num MPDUs requed by SW */ 805 A_INT32 mpdus_requed; 806 /* excessive retries */ 807 A_UINT32 tx_ko; 808 /* data hw rate code */ 809 A_UINT32 data_rc; 810 /* Scheduler self triggers */ 811 A_UINT32 self_triggers; 812 /* frames dropped due to excessive sw retries */ 813 A_UINT32 sw_retry_failure; 814 /* illegal rate phy errors */ 815 A_UINT32 illgl_rate_phy_err; 816 /* wal pdev continuous xretry */ 817 A_UINT32 pdev_cont_xretry; 818 /* wal pdev continuous xretry */ 819 A_UINT32 pdev_tx_timeout; 820 /* wal pdev resets */ 821 A_UINT32 pdev_resets; 822 /* frames dropped due to non-availability of stateless TIDs */ 823 A_UINT32 stateless_tid_alloc_failure; 824 /* PhY/BB underrun */ 825 A_UINT32 phy_underrun; 826 /* MPDU is more than txop limit */ 827 A_UINT32 txop_ovf; 828 }; 829 830 struct wlan_dbg_tx_stats_v2 { 831 /* Num HTT cookies queued to dispatch list */ 832 A_INT32 comp_queued; 833 /* Num HTT cookies dispatched */ 834 A_INT32 comp_delivered; 835 /* Num MSDU queued to WAL */ 836 A_INT32 msdu_enqued; 837 /* Num MPDU queue to WAL */ 838 A_INT32 mpdu_enqued; 839 /* Num MSDUs dropped by WMM limit */ 840 A_INT32 wmm_drop; 841 /* Num Local frames queued */ 842 A_INT32 local_enqued; 843 /* Num Local frames done */ 844 A_INT32 local_freed; 845 /* Num queued to HW */ 846 A_INT32 hw_queued; 847 /* Num PPDU reaped from HW */ 848 A_INT32 hw_reaped; 849 /* Num underruns */ 850 A_INT32 underrun; 851 /* HW Paused. */ 852 A_UINT32 hw_paused; 853 /* Num PPDUs cleaned up in TX abort */ 854 A_INT32 tx_abort; 855 /* Num MPDUs requed by SW */ 856 A_INT32 mpdus_requed; 857 /* excessive retries */ 858 A_UINT32 tx_ko; 859 A_UINT32 tx_xretry; 860 /* data hw rate code */ 861 A_UINT32 data_rc; 862 /* Scheduler self triggers */ 863 A_UINT32 self_triggers; 864 /* frames dropped due to excessive sw retries */ 865 A_UINT32 sw_retry_failure; 866 /* illegal rate phy errors */ 867 A_UINT32 illgl_rate_phy_err; 868 /* wal pdev continuous xretry */ 869 A_UINT32 pdev_cont_xretry; 870 /* wal pdev continuous xretry */ 871 A_UINT32 pdev_tx_timeout; 872 /* wal pdev resets */ 873 A_UINT32 pdev_resets; 874 /* frames dropped due to non-availability of stateless TIDs */ 875 A_UINT32 stateless_tid_alloc_failure; 876 /* PhY/BB underrun */ 877 A_UINT32 phy_underrun; 878 /* MPDU is more than txop limit */ 879 A_UINT32 txop_ovf; 880 /* Number of Sequences posted */ 881 A_UINT32 seq_posted; 882 /* Number of Sequences failed queueing */ 883 A_UINT32 seq_failed_queueing; 884 /* Number of Sequences completed */ 885 A_UINT32 seq_completed; 886 /* Number of Sequences restarted */ 887 A_UINT32 seq_restarted; 888 /* Number of MU Sequences posted */ 889 A_UINT32 mu_seq_posted; 890 /* Num MPDUs flushed by SW, HWPAUSED, SW TXABORT (Reset,channel change) */ 891 A_INT32 mpdus_sw_flush; 892 /* Num MPDUs filtered by HW, all filter condition (TTL expired) */ 893 A_INT32 mpdus_hw_filter; 894 /* Num MPDUs truncated by PDG (TXOP, TBTT, PPDU_duration based on rate, dyn_bw) */ 895 A_INT32 mpdus_truncated; 896 /* Num MPDUs that was tried but didn't receive ACK or BA */ 897 A_INT32 mpdus_ack_failed; 898 /* Num MPDUs that was dropped du to expiry. */ 899 A_INT32 mpdus_expired; 900 }; 901 902 #if defined(AR900B) 903 #define wlan_dbg_tx_stats wlan_dbg_tx_stats_v2 904 #else 905 #define wlan_dbg_tx_stats wlan_dbg_tx_stats_v1 906 #endif 907 908 /* 909 * wlan_dbg_rx_stats_v1, _v2: 910 * differing versions of the wlan_dbg_rx_stats struct used by different 911 * targets 912 */ 913 struct wlan_dbg_rx_stats_v1 { 914 /* Cnts any change in ring routing mid-ppdu */ 915 A_INT32 mid_ppdu_route_change; 916 /* Total number of statuses processed */ 917 A_INT32 status_rcvd; 918 /* Extra frags on rings 0-3 */ 919 A_INT32 r0_frags; 920 A_INT32 r1_frags; 921 A_INT32 r2_frags; 922 A_INT32 r3_frags; 923 /* MSDUs / MPDUs delivered to HTT */ 924 A_INT32 htt_msdus; 925 A_INT32 htt_mpdus; 926 /* MSDUs / MPDUs delivered to local stack */ 927 A_INT32 loc_msdus; 928 A_INT32 loc_mpdus; 929 /* AMSDUs that have more MSDUs than the status ring size */ 930 A_INT32 oversize_amsdu; 931 /* Number of PHY errors */ 932 A_INT32 phy_errs; 933 /* Number of PHY errors drops */ 934 A_INT32 phy_err_drop; 935 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 936 A_INT32 mpdu_errs; 937 }; 938 939 struct wlan_dbg_rx_stats_v2 { 940 /* Cnts any change in ring routing mid-ppdu */ 941 A_INT32 mid_ppdu_route_change; 942 /* Total number of statuses processed */ 943 A_INT32 status_rcvd; 944 /* Extra frags on rings 0-3 */ 945 A_INT32 r0_frags; 946 A_INT32 r1_frags; 947 A_INT32 r2_frags; 948 A_INT32 r3_frags; 949 /* MSDUs / MPDUs delivered to HTT */ 950 A_INT32 htt_msdus; 951 A_INT32 htt_mpdus; 952 /* MSDUs / MPDUs delivered to local stack */ 953 A_INT32 loc_msdus; 954 A_INT32 loc_mpdus; 955 /* AMSDUs that have more MSDUs than the status ring size */ 956 A_INT32 oversize_amsdu; 957 /* Number of PHY errors */ 958 A_INT32 phy_errs; 959 /* Number of PHY errors drops */ 960 A_INT32 phy_err_drop; 961 /* Number of mpdu errors - FCS, MIC, ENC etc. */ 962 A_INT32 mpdu_errs; 963 /* Number of rx overflow errors. */ 964 A_INT32 rx_ovfl_errs; 965 }; 966 967 #if defined(AR900B) 968 #define wlan_dbg_rx_stats wlan_dbg_rx_stats_v2 969 #else 970 #define wlan_dbg_rx_stats wlan_dbg_rx_stats_v1 971 #endif 972 973 struct wlan_dbg_mem_stats { 974 A_UINT32 iram_free_size; 975 A_UINT32 dram_free_size; 976 }; 977 978 struct wlan_dbg_peer_stats { 979 A_INT32 dummy; /* REMOVE THIS ONCE REAL PEER STAT COUNTERS ARE ADDED */ 980 }; 981 982 /* 983 * wlan_dbg_rx_rate_info_v1a_t, _v1b_t: 984 * differing versions of the wlan_dbg_rx_rate_info struct used by different 985 * targets 986 */ 987 typedef struct { 988 A_UINT32 mcs[10]; 989 A_UINT32 sgi[10]; 990 A_UINT32 nss[4]; 991 A_UINT32 nsts; 992 A_UINT32 stbc[10]; 993 A_UINT32 bw[3]; 994 A_UINT32 pream[6]; 995 A_UINT32 ldpc; 996 A_UINT32 txbf; 997 A_UINT32 mgmt_rssi; 998 A_UINT32 data_rssi; 999 A_UINT32 rssi_chain0; 1000 A_UINT32 rssi_chain1; 1001 A_UINT32 rssi_chain2; 1002 } wlan_dbg_rx_rate_info_v1a_t; 1003 1004 typedef struct { 1005 A_UINT32 mcs[10]; 1006 A_UINT32 sgi[10]; 1007 A_UINT32 nss[4]; 1008 A_UINT32 nsts; 1009 A_UINT32 stbc[10]; 1010 A_UINT32 bw[3]; 1011 A_UINT32 pream[6]; 1012 A_UINT32 ldpc; 1013 A_UINT32 txbf; 1014 A_UINT32 mgmt_rssi; 1015 A_UINT32 data_rssi; 1016 A_UINT32 rssi_chain0; 1017 A_UINT32 rssi_chain1; 1018 A_UINT32 rssi_chain2; 1019 /* 1020 * TEMPORARY: leave rssi_chain3 in place for AR900B builds until code using 1021 * rssi_chain3 has been converted to use wlan_dbg_rx_rate_info_v2_t. 1022 */ 1023 A_UINT32 rssi_chain3; 1024 } wlan_dbg_rx_rate_info_v1b_t; 1025 1026 #if defined(AR900B) 1027 #define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1b_t 1028 #else 1029 #define wlan_dbg_rx_rate_info_t wlan_dbg_rx_rate_info_v1a_t 1030 #endif 1031 1032 typedef struct { 1033 A_UINT32 mcs[10]; 1034 A_UINT32 sgi[10]; 1035 /* 1036 * TEMPORARY: leave nss conditionally defined, until all code that 1037 * requires nss[4] is converted to use wlan_dbg_tx_rate_info_v2_t. 1038 * At that time, this nss array will be made length = 3 unconditionally. 1039 */ 1040 #if defined(CONFIG_AR900B_SUPPORT) || defined(AR900B) 1041 A_UINT32 nss[4]; 1042 #else 1043 A_UINT32 nss[3]; 1044 #endif 1045 A_UINT32 stbc[10]; 1046 A_UINT32 bw[3]; 1047 A_UINT32 pream[4]; 1048 A_UINT32 ldpc; 1049 A_UINT32 rts_cnt; 1050 A_UINT32 ack_rssi; 1051 } wlan_dbg_tx_rate_info_t ; 1052 1053 #define WLAN_MAX_MCS 10 1054 1055 typedef struct { 1056 A_UINT32 mcs[WLAN_MAX_MCS]; 1057 A_UINT32 sgi[WLAN_MAX_MCS]; 1058 A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; 1059 A_UINT32 nsts; 1060 A_UINT32 stbc[WLAN_MAX_MCS]; 1061 A_UINT32 bw[NUM_DYN_BW_MAX]; 1062 A_UINT32 pream[6]; 1063 A_UINT32 ldpc; 1064 A_UINT32 txbf; 1065 A_UINT32 mgmt_rssi; 1066 A_UINT32 data_rssi; 1067 A_UINT32 rssi_chain0; 1068 A_UINT32 rssi_chain1; 1069 A_UINT32 rssi_chain2; 1070 A_UINT32 rssi_chain3; 1071 A_UINT32 reserved[8]; 1072 } wlan_dbg_rx_rate_info_v2_t; 1073 1074 typedef struct { 1075 A_UINT32 mcs[WLAN_MAX_MCS]; 1076 A_UINT32 sgi[WLAN_MAX_MCS]; 1077 A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V2]; 1078 A_UINT32 stbc[WLAN_MAX_MCS]; 1079 A_UINT32 bw[NUM_DYN_BW_MAX]; 1080 A_UINT32 pream[4]; 1081 A_UINT32 ldpc; 1082 A_UINT32 rts_cnt; 1083 A_UINT32 ack_rssi; 1084 A_UINT32 reserved[8]; 1085 } wlan_dbg_tx_rate_info_v2_t; 1086 1087 typedef struct { 1088 A_UINT32 mcs[WLAN_MAX_MCS]; 1089 A_UINT32 sgi[WLAN_MAX_MCS]; 1090 A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; 1091 A_UINT32 nsts; 1092 A_UINT32 stbc[WLAN_MAX_MCS]; 1093 A_UINT32 bw[NUM_DYN_BW_MAX]; 1094 A_UINT32 pream[6]; 1095 A_UINT32 ldpc; 1096 A_UINT32 txbf; 1097 A_UINT32 mgmt_rssi; 1098 A_UINT32 data_rssi; 1099 A_UINT32 rssi_chain0; 1100 A_UINT32 rssi_chain1; 1101 A_UINT32 rssi_chain2; 1102 A_UINT32 rssi_chain3; 1103 A_UINT32 reserved[8]; 1104 } wlan_dbg_rx_rate_info_v3_t; 1105 1106 typedef struct { 1107 A_UINT32 mcs[WLAN_MAX_MCS]; 1108 A_UINT32 sgi[WLAN_MAX_MCS]; 1109 A_UINT32 nss[MAX_SPATIAL_STREAM_ANY_V3]; 1110 A_UINT32 stbc[WLAN_MAX_MCS]; 1111 A_UINT32 bw[NUM_DYN_BW_MAX]; 1112 A_UINT32 pream[4]; 1113 A_UINT32 ldpc; 1114 A_UINT32 rts_cnt; 1115 A_UINT32 ack_rssi; 1116 A_UINT32 reserved[8]; 1117 } wlan_dbg_tx_rate_info_v3_t; 1118 1119 #define WHAL_DBG_PHY_ERR_MAXCNT 18 1120 #define WHAL_DBG_SIFS_STATUS_MAXCNT 8 1121 #define WHAL_DBG_SIFS_ERR_MAXCNT 8 1122 #define WHAL_DBG_CMD_RESULT_MAXCNT 11 1123 #define WHAL_DBG_CMD_STALL_ERR_MAXCNT 4 1124 #define WHAL_DBG_FLUSH_REASON_MAXCNT 40 1125 1126 typedef enum { 1127 WIFI_URRN_STATS_FIRST_PKT, 1128 WIFI_URRN_STATS_BETWEEN_MPDU, 1129 WIFI_URRN_STATS_WITHIN_MPDU, 1130 WHAL_MAX_URRN_STATS 1131 } wifi_urrn_type_t; 1132 1133 typedef struct wlan_dbg_txbf_snd_stats { 1134 A_UINT32 cbf_20[4]; 1135 A_UINT32 cbf_40[4]; 1136 A_UINT32 cbf_80[4]; 1137 A_UINT32 sounding[9]; 1138 A_UINT32 cbf_160[4]; 1139 } wlan_dbg_txbf_snd_stats_t; 1140 1141 typedef struct wlan_dbg_wifi2_error_stats { 1142 A_UINT32 urrn_stats[WHAL_MAX_URRN_STATS]; 1143 A_UINT32 flush_errs[WHAL_DBG_FLUSH_REASON_MAXCNT]; 1144 A_UINT32 schd_stall_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; 1145 A_UINT32 schd_cmd_result[WHAL_DBG_CMD_RESULT_MAXCNT]; 1146 A_UINT32 sifs_status[WHAL_DBG_SIFS_STATUS_MAXCNT]; 1147 A_UINT8 phy_errs[WHAL_DBG_PHY_ERR_MAXCNT]; 1148 A_UINT32 rx_rate_inval; 1149 } wlan_dbg_wifi2_error_stats_t; 1150 1151 typedef struct wlan_dbg_wifi2_error2_stats { 1152 A_UINT32 schd_errs[WHAL_DBG_CMD_STALL_ERR_MAXCNT]; 1153 A_UINT32 sifs_errs[WHAL_DBG_SIFS_ERR_MAXCNT]; 1154 } wlan_dbg_wifi2_error2_stats_t; 1155 1156 #define WLAN_DBG_STATS_SIZE_TXBF_VHT 10 1157 #define WLAN_DBG_STATS_SIZE_TXBF_HT 8 1158 #define WLAN_DBG_STATS_SIZE_TXBF_OFDM 8 1159 #define WLAN_DBG_STATS_SIZE_TXBF_CCK 7 1160 1161 typedef struct wlan_dbg_txbf_data_stats { 1162 A_UINT32 tx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; 1163 A_UINT32 rx_txbf_vht[WLAN_DBG_STATS_SIZE_TXBF_VHT]; 1164 A_UINT32 tx_txbf_ht[WLAN_DBG_STATS_SIZE_TXBF_HT]; 1165 A_UINT32 tx_txbf_ofdm[WLAN_DBG_STATS_SIZE_TXBF_OFDM]; 1166 A_UINT32 tx_txbf_cck[WLAN_DBG_STATS_SIZE_TXBF_CCK]; 1167 } wlan_dbg_txbf_data_stats_t; 1168 1169 struct wlan_dbg_tx_mu_stats { 1170 A_UINT32 mu_sch_nusers_2; 1171 A_UINT32 mu_sch_nusers_3; 1172 A_UINT32 mu_mpdus_queued_usr[4]; 1173 A_UINT32 mu_mpdus_tried_usr[4]; 1174 A_UINT32 mu_mpdus_failed_usr[4]; 1175 A_UINT32 mu_mpdus_requeued_usr[4]; 1176 A_UINT32 mu_err_no_ba_usr[4]; 1177 A_UINT32 mu_mpdu_underrun_usr[4]; 1178 A_UINT32 mu_ampdu_underrun_usr[4]; 1179 }; 1180 1181 struct wlan_dbg_tx_selfgen_stats { 1182 A_UINT32 su_ndpa; 1183 A_UINT32 su_ndp; 1184 A_UINT32 mu_ndpa; 1185 A_UINT32 mu_ndp; 1186 A_UINT32 mu_brpoll_1; 1187 A_UINT32 mu_brpoll_2; 1188 A_UINT32 mu_bar_1; 1189 A_UINT32 mu_bar_2; 1190 A_UINT32 cts_burst; 1191 A_UINT32 su_ndp_err; 1192 A_UINT32 su_ndpa_err; 1193 A_UINT32 mu_ndp_err; 1194 A_UINT32 mu_brp1_err; 1195 A_UINT32 mu_brp2_err; 1196 }; 1197 1198 typedef struct wlan_dbg_sifs_resp_stats { 1199 A_UINT32 ps_poll_trigger; /* num ps-poll trigger frames */ 1200 A_UINT32 uapsd_trigger; /* num uapsd trigger frames */ 1201 A_UINT32 qb_data_trigger[2]; /* num data trigger frames; idx 0: explicit and idx 1: implicit */ 1202 A_UINT32 qb_bar_trigger[2]; /* num bar trigger frames; idx 0: explicit and idx 1: implicit */ 1203 A_UINT32 sifs_resp_data; /* num ppdus transmitted at SIFS interval */ 1204 A_UINT32 sifs_resp_err; /* num ppdus failed to meet SIFS resp timing */ 1205 } wlan_dgb_sifs_resp_stats_t; 1206 1207 1208 1209 /** wlan_dbg_wifi2_error_stats_t is not grouped with the 1210 * following structure as it is allocated differently and only 1211 * belongs to whal 1212 */ 1213 typedef struct wlan_dbg_stats_wifi2 { 1214 wlan_dbg_txbf_snd_stats_t txbf_snd_info; 1215 wlan_dbg_txbf_data_stats_t txbf_data_info; 1216 struct wlan_dbg_tx_selfgen_stats tx_selfgen; 1217 struct wlan_dbg_tx_mu_stats tx_mu; 1218 wlan_dgb_sifs_resp_stats_t sifs_resp_info; 1219 } wlan_dbg_wifi2_stats_t; 1220 1221 /* 1222 * wlan_dbg_rx_rate_info_v1a, _v1b: 1223 * differing versions of the wlan_dbg_rx_rate_info struct used by different 1224 * targets 1225 */ 1226 typedef struct { 1227 wlan_dbg_rx_rate_info_v1a_t rx_phy_info; 1228 wlan_dbg_tx_rate_info_t tx_rate_info; 1229 } wlan_dbg_rate_info_v1a_t; 1230 1231 typedef struct { 1232 wlan_dbg_rx_rate_info_v1b_t rx_phy_info; 1233 wlan_dbg_tx_rate_info_t tx_rate_info; 1234 } wlan_dbg_rate_info_v1b_t; 1235 1236 #if defined(AR900B) 1237 #define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1b_t 1238 #else 1239 #define wlan_dbg_rate_info_t wlan_dbg_rate_info_v1a_t 1240 #endif 1241 1242 typedef struct { 1243 wlan_dbg_rx_rate_info_v2_t rx_phy_info; 1244 wlan_dbg_tx_rate_info_v2_t tx_rate_info; 1245 } wlan_dbg_rate_info_v2_t; 1246 1247 /* 1248 * wlan_dbg_stats_v1, _v2: 1249 * differing versions of the wlan_dbg_stats struct used by different 1250 * targets 1251 */ 1252 struct wlan_dbg_stats_v1 { 1253 struct wlan_dbg_tx_stats_v1 tx; 1254 struct wlan_dbg_rx_stats_v1 rx; 1255 struct wlan_dbg_peer_stats peer; 1256 }; 1257 1258 struct wlan_dbg_stats_v2 { 1259 struct wlan_dbg_tx_stats_v2 tx; 1260 struct wlan_dbg_rx_stats_v2 rx; 1261 struct wlan_dbg_mem_stats mem; 1262 struct wlan_dbg_peer_stats peer; 1263 }; 1264 1265 #if defined(AR900B) 1266 #define wlan_dbg_stats wlan_dbg_stats_v2 1267 #else 1268 #define wlan_dbg_stats wlan_dbg_stats_v1 1269 #endif 1270 1271 #define DBG_STATS_MAX_HWQ_NUM 10 1272 #define DBG_STATS_MAX_TID_NUM 20 1273 #define DBG_STATS_MAX_CONG_NUM 16 1274 struct wlan_dbg_txq_stats { 1275 A_UINT16 num_pkts_queued[DBG_STATS_MAX_HWQ_NUM]; 1276 A_UINT16 tid_hw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ 1277 A_UINT16 tid_sw_qdepth[DBG_STATS_MAX_TID_NUM]; /* WAL_MAX_TID is 20 */ 1278 }; 1279 1280 struct wlan_dbg_tidq_stats { 1281 A_UINT32 wlan_dbg_tid_txq_status; 1282 struct wlan_dbg_txq_stats txq_st; 1283 }; 1284 1285 typedef enum { 1286 WLAN_DBG_DATA_STALL_NONE = 0, 1287 WLAN_DBG_DATA_STALL_VDEV_PAUSE = 1, 1288 WLAN_DBG_DATA_STALL_HWSCHED_CMD_FILTER = 2, 1289 WLAN_DBG_DATA_STALL_HWSCHED_CMD_FLUSH = 3, 1290 WLAN_DBG_DATA_STALL_RX_REFILL_FAILED = 4, 1291 WLAN_DBG_DATA_STALL_RX_FCS_LEN_ERROR = 5, 1292 WLAN_DBG_DATA_STALL_MAC_WDOG_ERRORS = 6, /* Mac watch dog */ 1293 WLAN_DBG_DATA_STALL_PHY_BB_WDOG_ERROR = 7, /* PHY watch dog */ 1294 WLAN_DBG_DATA_STALL_POST_TIM_NO_TXRX_ERROR = 8, 1295 WLAN_DBG_DATA_STALL_CONSECUTIVE_NON_FLUSH = 9, 1296 WLAN_DBG_DATA_STALL_CONSECUTIVE_NOACK = 10, 1297 WLAN_DBG_DATA_STALL_CONSECUTIVE_LT_EXPIRY = 11, 1298 WLAN_DBG_DATA_STALL_MAX, 1299 } wlan_dbg_data_stall_type_e; 1300 1301 typedef enum { 1302 WLAN_DBG_DATA_STALL_RECOVERY_NONE = 0, 1303 WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_DISCONNECT, 1304 WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_MAC_PHY_RESET, 1305 WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_PDR, 1306 WLAN_DBG_DATA_STALL_RECOVERY_CONNECT_SSR, 1307 } wlan_dbg_data_stall_recovery_type_e; 1308 1309 /* 1310 * NOTE: If necessary, restore the explicit disabling of CONFIG_160MHZ_SUPPORT 1311 * See the corresponding comment + pre-processor block at the top of the file. 1312 */ 1313 #ifdef CONFIG_160MHZ_SUPPORT_UNDEF_WAR 1314 #define CONFIG_160MHZ_SUPPORT 0 1315 #undef CONFIG_160MHZ_SUPPORT_UNDEF_WAR 1316 #endif 1317 1318 /** MGMT RX REO Changes */ 1319 /* Macros for having versioning info for compatibility check between host and firmware */ 1320 #define MLO_SHMEM_MAJOR_VERSION 2 1321 #define MLO_SHMEM_MINOR_VERSION 1 1322 1323 /** Helper Macros for tlv header of the given tlv buffer */ 1324 /* Size of the TLV Header which is the Tag and Length fields */ 1325 #define MLO_SHMEM_TLV_HDR_SIZE (1 * sizeof(A_UINT32)) 1326 1327 /* TLV Helper macro to get the TLV Header given the pointer to the TLV buffer. */ 1328 #define MLO_SHMEMTLV_GET_HDR(tlv_buf) (((A_UINT32 *) (tlv_buf))[0]) 1329 1330 /* TLV Helper macro to set the TLV Header given the pointer to the TLV buffer. */ 1331 #define MLO_SHMEMTLV_SET_HDR(tlv_buf, tag, len) \ 1332 (((A_UINT32 *)(tlv_buf))[0]) = ((tag << 16) | (len & 0x0000FFFF)) 1333 1334 /* TLV Helper macro to get the TLV Tag given the TLV header. */ 1335 #define MLO_SHMEMTLV_GET_TLVTAG(tlv_header) ((A_UINT32)((tlv_header) >> 16)) 1336 1337 /* 1338 * TLV Helper macro to get the TLV Buffer Length (minus TLV header size) 1339 * given the TLV header. 1340 */ 1341 #define MLO_SHMEMTLV_GET_TLVLEN(tlv_header) \ 1342 ((A_UINT32)((tlv_header) & 0x0000FFFF)) 1343 1344 /* 1345 * TLV Helper macro to get the TLV length from TLV structure size 1346 * by removing TLV header size. 1347 */ 1348 #define MLO_SHMEMTLV_GET_STRUCT_TLVLEN(tlv_struct) \ 1349 ((A_UINT32)(sizeof(tlv_struct)-MLO_SHMEM_TLV_HDR_SIZE)) 1350 1351 /** 1352 * Helper Macros for getting and setting the required number of bits 1353 * from the TLV params. 1354 */ 1355 #define MLO_SHMEM_GET_BITS(_val,_index,_num_bits) \ 1356 (((_val) >> (_index)) & ((1 << (_num_bits)) - 1)) 1357 1358 #define MLO_SHMEM_SET_BITS(_var,_index,_num_bits,_val) \ 1359 do { \ 1360 (_var) &= ~(((1 << (_num_bits)) - 1) << (_index)); \ 1361 (_var) |= (((_val) & ((1 << (_num_bits)) - 1)) << (_index)); \ 1362 } while (0) 1363 1364 /** 1365 * Enum which defines different versions of management Rx reorder snapshots. 1366 */ 1367 typedef enum { 1368 /** 1369 * DWORD Lower: 1370 * [15:0] : Management packet counter 1371 * [30:16] : Redundant global time stamp = Global time stamp[14:0] 1372 * [31] : Valid 1373 * 1374 * DWORD Upper: 1375 * [31:0] : Global time stamp 1376 * 1377 */ 1378 MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY = 0, 1379 1380 /** 1381 * DWORD Lower: 1382 * [14:0] : Global time stamp[14:0] 1383 * [30:15] : Management packet counter 1384 * [31] : Valid 1385 * 1386 * DWORD Upper: 1387 * [14:0] : Redundant management packet counter = Management packet 1388 * counter[14:0] 1389 * [31:15] : Global time stamp[31:15] 1390 */ 1391 MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY = 1, 1392 } MGMT_RX_REO_SNAPSHOT_VERSION; 1393 1394 /** Definition of the GLB_H_SHMEM arena tlv structures */ 1395 1396 typedef enum { 1397 MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT, 1398 MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO, 1399 MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO, 1400 MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK, 1401 MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO, 1402 MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM, 1403 MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO, 1404 MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO, 1405 } MLO_SHMEM_TLV_TAG_ID; 1406 1407 /** Helper macro for params GET/SET of mgmt_rx_reo_snapshot */ 1408 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 1) 1409 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_VALID_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 0, 1, value) 1410 1411 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_GET(mgmt_rx_reo_snapshot_low) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 1, 16) 1412 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_SET(mgmt_rx_reo_snapshot_low, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 1, 16, value) 1413 1414 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET(mgmt_rx_reo_snapshot) \ 1415 (MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17) << 15) | \ 1416 MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15) 1417 1418 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_SET(mgmt_rx_reo_snapshot, value) \ 1419 do { \ 1420 MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_high, 0, 17, ((value) >> 15)); \ 1421 MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low, 17, 15, ((value) & 0x7fff)); \ 1422 } while (0) 1423 1424 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_GET(mgmt_rx_reo_snapshot_high) MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 17, 15) 1425 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_MGMT_PKT_CTR_REDUNDANT_SET(mgmt_rx_reo_snapshot_high, value) MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_high, 17, 15, value) 1426 1427 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_IS_CONSISTENT(mgmt_pkt_ctr, mgmt_pkt_ctr_redundant) \ 1428 (MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15)) 1429 1430 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_PARAM_GLOBAL_TIMESTAMP_GET_FROM_DWORDS(mgmt_rx_reo_snapshot_low,mgmt_rx_reo_snapshot_high) \ 1431 (MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_high), 0, 17) << 15) | \ 1432 MLO_SHMEM_GET_BITS((mgmt_rx_reo_snapshot_low), 17, 15) 1433 1434 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GET_ADRESS(mgmt_rx_reo_snapshot) \ 1435 (&mgmt_rx_reo_snapshot->mgmt_rx_reo_snapshot_low) 1436 1437 /** 1438 * Helper macros/functions for params GET/SET of different hw version 1439 * of the mgmt_rx_reo_snapshot 1440 */ 1441 1442 static INLINE A_UINT8 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_GET(A_UINT32 mgmt_rx_reo_snapshot_low,A_UINT8 snapshot_ver)1443 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_GET( 1444 A_UINT32 mgmt_rx_reo_snapshot_low, A_UINT8 snapshot_ver) 1445 { 1446 if ((snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) && 1447 (snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY)) 1448 { 1449 A_ASSERT(0); 1450 } 1451 1452 return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 31, 1); 1453 } 1454 1455 static INLINE void MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_SET(A_UINT32 * mgmt_rx_reo_snapshot_low,A_UINT8 value,A_UINT8 snapshot_ver)1456 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_VALID_SET( 1457 A_UINT32 *mgmt_rx_reo_snapshot_low, A_UINT8 value, A_UINT8 snapshot_ver) 1458 { 1459 if ((snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) && 1460 (snapshot_ver != MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY)) { 1461 A_ASSERT(0); 1462 } 1463 1464 MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 31, 1, value); 1465 } 1466 1467 static INLINE A_UINT16 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_GET(A_UINT32 mgmt_rx_reo_snapshot_low,A_UINT8 snapshot_ver)1468 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_GET( 1469 A_UINT32 mgmt_rx_reo_snapshot_low, A_UINT8 snapshot_ver) 1470 { 1471 if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1472 return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 16); 1473 } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1474 return MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 15, 16); 1475 } else { 1476 A_ASSERT(0); 1477 return 0; 1478 } 1479 } 1480 1481 static INLINE void MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_SET(A_UINT32 * mgmt_rx_reo_snapshot_low,A_UINT16 value,A_UINT8 snapshot_ver)1482 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_SET( 1483 A_UINT32 *mgmt_rx_reo_snapshot_low, A_UINT16 value, A_UINT8 snapshot_ver) 1484 { 1485 if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1486 MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 0, 16, value); 1487 } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1488 MLO_SHMEM_SET_BITS(*mgmt_rx_reo_snapshot_low, 15, 16, value); 1489 } else { 1490 A_ASSERT(0); 1491 } 1492 } 1493 1494 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( \ 1495 mgmt_rx_reo_snapshot_high) \ 1496 MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 0, 15) 1497 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_SET( \ 1498 mgmt_rx_reo_snapshot_high, value) \ 1499 MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_high, 0, 15, value) 1500 1501 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( \ 1502 mgmt_rx_reo_snapshot_low) \ 1503 MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 16, 15) 1504 #define MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_SET( \ 1505 mgmt_rx_reo_snapshot_low, value) \ 1506 MLO_SHMEM_SET_BITS(mgmt_rx_reo_snapshot_low, 16, 15, value) 1507 1508 static INLINE A_UINT32 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_GET(A_UINT32 mgmt_rx_reo_snapshot_low,A_UINT32 mgmt_rx_reo_snapshot_high,A_UINT8 snapshot_ver)1509 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_GET( 1510 A_UINT32 mgmt_rx_reo_snapshot_low, 1511 A_UINT32 mgmt_rx_reo_snapshot_high, 1512 A_UINT8 snapshot_ver) 1513 { 1514 if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1515 return mgmt_rx_reo_snapshot_high; 1516 } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1517 return 1518 ((MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_high, 15, 17) << 15) | 1519 MLO_SHMEM_GET_BITS(mgmt_rx_reo_snapshot_low, 0, 15)); 1520 } else { 1521 A_ASSERT(0); 1522 return 0; 1523 } 1524 } 1525 1526 static INLINE void MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_SET(A_UINT32 * mgmt_rx_reo_snapshot_low,A_UINT32 * mgmt_rx_reo_snapshot_high,A_UINT32 value,A_UINT8 snapshot_ver)1527 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_SET( 1528 A_UINT32 *mgmt_rx_reo_snapshot_low, 1529 A_UINT32 *mgmt_rx_reo_snapshot_high, 1530 A_UINT32 value, 1531 A_UINT8 snapshot_ver) 1532 { 1533 if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1534 *mgmt_rx_reo_snapshot_high = value; 1535 } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1536 MLO_SHMEM_SET_BITS( 1537 *mgmt_rx_reo_snapshot_high, 15, 17, ((value) >> 15)); 1538 MLO_SHMEM_SET_BITS( 1539 *mgmt_rx_reo_snapshot_low, 0, 15, ((value) & 0x7fff)); 1540 } else { 1541 A_ASSERT(0); 1542 } 1543 } 1544 1545 static INLINE A_BOOL MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_CHECK_CONSISTENCY(A_UINT32 mgmt_rx_reo_snapshot_low,A_UINT32 mgmt_rx_reo_snapshot_high,A_UINT8 snapshot_ver)1546 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_CHECK_CONSISTENCY( 1547 A_UINT32 mgmt_rx_reo_snapshot_low, 1548 A_UINT32 mgmt_rx_reo_snapshot_high, 1549 A_UINT8 snapshot_ver) 1550 { 1551 if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_TIMESTAMP_REDUNDANCY) { 1552 A_UINT32 global_timestamp; 1553 A_UINT32 global_timestamp_redundant; 1554 1555 global_timestamp = MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_GET( 1556 mgmt_rx_reo_snapshot_low, mgmt_rx_reo_snapshot_high, snapshot_ver); 1557 global_timestamp_redundant = 1558 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_GLOBAL_TIMESTAMP_REDUNDANT_GET( 1559 mgmt_rx_reo_snapshot_low); 1560 1561 return 1562 (MLO_SHMEM_GET_BITS(global_timestamp, 0, 15) == 1563 MLO_SHMEM_GET_BITS(global_timestamp_redundant, 0, 15)); 1564 } else if (snapshot_ver == MGMT_RX_REO_SNAPSHOT_VERSION_PKT_CTR_REDUNDANCY){ 1565 A_UINT16 mgmt_pkt_ctr; 1566 A_UINT16 mgmt_pkt_ctr_redundant; 1567 1568 mgmt_pkt_ctr = MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_GET( 1569 mgmt_rx_reo_snapshot_low, snapshot_ver); 1570 mgmt_pkt_ctr_redundant = 1571 MLO_SHMEM_MGMT_RX_REO_SNAPSHOT_MGMT_PKT_CTR_REDUNDANT_GET( 1572 mgmt_rx_reo_snapshot_high); 1573 1574 return 1575 (MLO_SHMEM_GET_BITS(mgmt_pkt_ctr, 0, 15) == 1576 MLO_SHMEM_GET_BITS(mgmt_pkt_ctr_redundant, 0, 15)); 1577 } else { 1578 A_ASSERT(0); 1579 return 0; 1580 } 1581 } 1582 1583 /* REO snapshot structure */ 1584 typedef struct { 1585 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MGMT_RX_REO_SNAPSHOT */ 1586 A_UINT32 tlv_header; 1587 A_UINT32 reserved_alignment_padding; 1588 /** 1589 * mgmt_rx_reo_snapshot_low 1590 * 1591 * [0]: valid 1592 * [16:1]: mgmt_pkt_ctr 1593 * [31:17]: global_timestamp_low 1594 */ 1595 A_UINT32 mgmt_rx_reo_snapshot_low; 1596 1597 /** 1598 * mgmt_rx_reo_snapshot_high 1599 * 1600 * [16:0]: global_timestamp_high 1601 * [31:17]: mgmt_pkt_ctr_redundant 1602 */ 1603 A_UINT32 mgmt_rx_reo_snapshot_high; 1604 1605 } mgmt_rx_reo_snapshot; 1606 1607 A_COMPILE_TIME_ASSERT(check_mgmt_rx_reo_snapshot_8byte_size_quantum, 1608 (((sizeof(mgmt_rx_reo_snapshot) % sizeof(A_UINT64) == 0x0)))); 1609 1610 A_COMPILE_TIME_ASSERT(verify_mgmt_rx_reo_snapshot_low_offset, 1611 (A_OFFSETOF(mgmt_rx_reo_snapshot, mgmt_rx_reo_snapshot_low) % sizeof(A_UINT64) == 0)); 1612 1613 typedef struct { 1614 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_PER_LINK_SNAPSHOT_INFO */ 1615 A_UINT32 tlv_header; 1616 A_UINT32 reserved_alignment_padding; 1617 mgmt_rx_reo_snapshot fw_consumed; 1618 mgmt_rx_reo_snapshot fw_forwarded; 1619 mgmt_rx_reo_snapshot hw_forwarded; 1620 } mlo_glb_rx_reo_per_link_snapshot_info; 1621 1622 A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_per_link_snapshot_info_8byte_size_quantum, 1623 (((sizeof(mlo_glb_rx_reo_per_link_snapshot_info) % sizeof(A_UINT64) == 0x0)))); 1624 1625 A_COMPILE_TIME_ASSERT(verify_mlo_glb_rx_reo_per_link_snapshot_fw_consumed_offset, 1626 (A_OFFSETOF(mlo_glb_rx_reo_per_link_snapshot_info, fw_consumed) % sizeof(A_UINT64) == 0)); 1627 1628 /** Helper macro for params GET/SET of mlo_glb_rx_reo_snapshot_info */ 1629 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4) 1630 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value) 1631 1632 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16) 1633 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value) 1634 1635 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 0, 3) 1636 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_HW_FWD_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 0, 3, value) 1637 1638 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 3, 3) 1639 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_FWD_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 3, 3, value) 1640 1641 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_GET(snapshot_ver_info) MLO_SHMEM_GET_BITS(snapshot_ver_info, 6, 3) 1642 #define MLO_SHMEM_GLB_RX_REO_SNAPSHOT_PARAM_FW_CONSUMED_SNAPSHOT_VER_SET(snapshot_ver_info, value) MLO_SHMEM_SET_BITS(snapshot_ver_info, 6, 3, value) 1643 1644 /* Definition of the complete REO snapshot info */ 1645 typedef struct { 1646 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_RX_REO_SNAPSHOT_INFO */ 1647 A_UINT32 tlv_header; 1648 1649 /** 1650 * link_info 1651 * 1652 * [3:0]: no_of_links 1653 * [19:4]: valid_link_bmap 1654 * [31:20]: reserved 1655 */ 1656 A_UINT32 link_info; 1657 1658 /** 1659 * snapshot_ver_info 1660 * 1661 * [2:0]: hw_forwarded snapshot version 1662 * [5:3]: fw_forwarded snapshot version 1663 * [8:6]: fw_consumed snapshot version 1664 * [31:9]: reserved 1665 */ 1666 A_UINT32 snapshot_ver_info; 1667 A_UINT32 reserved_alignment_padding; 1668 1669 /* This TLV is followed by array of mlo_glb_rx_reo_per_link_snapshot_info: 1670 * mlo_glb_rx_reo_per_link_snapshot_info will have multiple instances 1671 * equal to num of hw links received by no_of_link 1672 * mlo_glb_rx_reo_per_link_snapshot_info per_link_info[]; 1673 */ 1674 } mlo_glb_rx_reo_snapshot_info; 1675 1676 A_COMPILE_TIME_ASSERT(check_mlo_glb_rx_reo_snapshot_info_8byte_size_quantum, 1677 (((sizeof(mlo_glb_rx_reo_snapshot_info) % sizeof(A_UINT64) == 0x0)))); 1678 1679 /** Helper macro for params GET/SET of mlo_glb_link */ 1680 #define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_GET(link_status) MLO_SHMEM_GET_BITS(link_status, 0, 8) 1681 #define MLO_SHMEM_GLB_LINK_PARAM_LINK_STATUS_SET(link_status, value) MLO_SHMEM_SET_BITS(link_status, 0, 8, value) 1682 1683 /*glb link info structures used for scratchpad memory (crash and recovery) */ 1684 typedef struct { 1685 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK */ 1686 A_UINT32 tlv_header; 1687 /** 1688 * link_status 1689 * 1690 * [7:0]: link_status 1691 * [31:8]: reserved 1692 */ 1693 A_UINT32 link_status; 1694 /* 1695 * Based on MLO timestamp, which is global across chips - 1696 * this will be first updated when MLO sync is completed. 1697 */ 1698 A_UINT32 boot_timestamp_low_us; 1699 A_UINT32 boot_timestamp_high_us; 1700 /* 1701 * Based on MLO timestamp, will be updated with a configurable 1702 * periodicity (default 1 sec) 1703 */ 1704 A_UINT32 health_check_timestamp_low_us; 1705 A_UINT32 health_check_timestamp_high_us; 1706 1707 } mlo_glb_link; 1708 1709 A_COMPILE_TIME_ASSERT(check_mlo_glb_link_8byte_size_quantum, 1710 (((sizeof(mlo_glb_link) % sizeof(A_UINT64) == 0x0)))); 1711 1712 A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_boot_timestamp_low_offset, 1713 (A_OFFSETOF(mlo_glb_link, boot_timestamp_low_us) % sizeof(A_UINT64) == 0)); 1714 1715 A_COMPILE_TIME_ASSERT(verify_mlo_glb_link_health_check_timestamp_low_offset, 1716 (A_OFFSETOF(mlo_glb_link, health_check_timestamp_low_us) % sizeof(A_UINT64) == 0)); 1717 1718 1719 /** Helper macro for params GET/SET of mlo_glb_link_info */ 1720 #define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 0, 4) 1721 #define MLO_SHMEM_GLB_LINK_INFO_PARAM_NO_OF_LINKS_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 0, 4, value) 1722 1723 #define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_GET(link_info) MLO_SHMEM_GET_BITS(link_info, 4, 16) 1724 #define MLO_SHMEM_GLB_LINK_INFO_PARAM_VALID_LINK_BMAP_SET(link_info, value) MLO_SHMEM_SET_BITS(link_info, 4, 16, value) 1725 1726 typedef struct { 1727 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_LINK_INFO */ 1728 A_UINT32 tlv_header; 1729 1730 /** 1731 * link_info 1732 * 1733 * [3:0]: no_of_links 1734 * [19:4]: valid_link_bmap 1735 * [31:20]: reserved 1736 */ 1737 A_UINT32 link_info; 1738 /* This TLV is followed by array of mlo_glb_link: 1739 * mlo_glb_link will have multiple instances equal to num of hw links 1740 * received by no_of_link 1741 * mlo_glb_link glb_link_info[]; 1742 */ 1743 } mlo_glb_link_info; 1744 1745 A_COMPILE_TIME_ASSERT(check_mlo_glb_link_info_8byte_size_quantum, 1746 (((sizeof(mlo_glb_link_info) % sizeof(A_UINT64) == 0x0)))); 1747 1748 typedef enum { 1749 MLO_SHMEM_CRASH_PARTNER_CHIPS = 1, 1750 MLO_SHMEM_CRASH_SW_PANIC = 2, 1751 MLO_SHMEM_CRASH_SW_ASSERT = 3, 1752 } MLO_SHMEM_CHIP_CRASH_REASON; 1753 1754 typedef enum { 1755 MLO_SHMEM_RECOVERY_CRASH_PARTNER_CHIPS = 1, 1756 MLO_SHMEM_RECOVER_NON_MLO_MODE = 2, 1757 MLO_SHMEM_RECOVER_NON_CRASH_MLO_MODE = 3, 1758 } MLO_SHMEM_CHIP_RECOVERY_MODE; 1759 1760 /* glb link info structures used for scratchpad memory (crash and recovery) */ 1761 typedef struct { 1762 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_PER_CHIP_CRASH_INFO */ 1763 A_UINT32 tlv_header; 1764 /** 1765 * crash reason, takes value in enum MLO_SHMEM_CHIP_CRASH_REASON 1766 */ 1767 A_UINT32 crash_reason; 1768 /** 1769 * crash reason, takes value in enum MLO_SHMEM_CHIP_RECOVERY_MODE 1770 */ 1771 A_UINT32 recovery_mode; 1772 /* reserved: added for padding to A_UINT64 size, available for future use */ 1773 A_UINT32 reserved; 1774 } mlo_glb_per_chip_crash_info; 1775 1776 A_COMPILE_TIME_ASSERT(check_mlo_glb_per_chip_crash_info, 1777 (((sizeof(mlo_glb_per_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); 1778 1779 /** Helper macro for params GET/SET of mlo_glb_chip_crash_info */ 1780 #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_GET(chip_info) \ 1781 (MLO_SHMEM_GET_BITS(chip_info, 0, 2) + \ 1782 (MLO_SHMEM_GET_BITS(chip_info, 12, 4) << 2)) 1783 #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_NO_OF_CHIPS_SET(chip_info, value) \ 1784 do { \ 1785 MLO_SHMEM_SET_BITS(chip_info, 0, 2, ((value) & 0x03)); \ 1786 MLO_SHMEM_SET_BITS(chip_info, 12, 4, ((value) >> 2)); \ 1787 } while (0) 1788 1789 #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_GET(chip_info) MLO_SHMEM_GET_BITS(chip_info, 2, 8) 1790 #define MLO_SHMEM_CHIP_CRASH_INFO_PARAM_VALID_CHIP_BMAP_SET(chip_info, value) MLO_SHMEM_SET_BITS(chip_info, 2, 8, value) 1791 1792 typedef struct { 1793 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_CHIP_CRASH_INFO */ 1794 A_UINT32 tlv_header; 1795 1796 /** 1797 * chip_info 1798 * 1799 * [1:0]: no_of_chips 1800 * [4:2]: valid_chip_bmap 1801 * For number of chips beyond 3, extension fields are added. 1802 * To maintain backward compatibility, with 3 chip board and 1803 * old host driver, valid chip bmap is extended in continuation from 1804 * existing bit 4 onwards, while extending no_of_chips information 1805 * would overlap with old valid_chip_bmap, hence extended from 1806 * bit 12:15. Now no_of_chip will have two parts, lower 2 bits from 0-1 and 1807 * upper 4 bits from 12-15. SET-GET macros are modified accordingly. 1808 * This helps in no change in respective processing files and don't need 1809 * to maintain two copy of information for backward compatibility. 1810 * [9:5]: valid_chip_bmap_ext 1811 * [15:12]: no_of_chips_ext 1812 * [31:16]: reserved 1813 */ 1814 A_UINT32 chip_info; 1815 /* This TLV is followed by array of mlo_glb_per_chip_crash_info: 1816 * mlo_glb_per_chip_crash_info will have multiple instances equal to num of partner chips 1817 * received by no_of_chips 1818 * mlo_glb_per_chip_crash_info per_chip_crash_info[]; 1819 */ 1820 } mlo_glb_chip_crash_info; 1821 1822 A_COMPILE_TIME_ASSERT(check_mlo_glb_chip_crash_info, 1823 (((sizeof(mlo_glb_chip_crash_info) % sizeof(A_UINT64) == 0x0)))); 1824 1825 /** Helper macro for params GET/SET of mlo_glb_h_shmem */ 1826 #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 0, 16) 1827 #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MINOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 0, 16, value) 1828 1829 #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_GET(major_minor_version) MLO_SHMEM_GET_BITS(major_minor_version, 16, 16) 1830 #define MLO_SHMEM_GLB_H_SHMEM_PARAM_MAJOR_VERSION_SET(major_minor_version, value) MLO_SHMEM_SET_BITS(major_minor_version, 16, 16, value) 1831 1832 /* Definition of Global H SHMEM Arena */ 1833 typedef struct { 1834 /* TLV tag and len; tag equals MLO_SHMEM_TLV_STRUCT_MLO_GLB_H_SHMEM */ 1835 A_UINT32 tlv_header; 1836 /** 1837 * major_minor_version 1838 * 1839 * [15:0]: minor version 1840 * [31:16]: major version 1841 */ 1842 A_UINT32 major_minor_version; 1843 /* This TLV is followed by TLVs 1844 * mlo_glb_rx_reo_snapshot_info reo_snapshot; 1845 * mlo_glb_link_info glb_info; 1846 * mlo_glb_chip_crash_info crash_info; 1847 */ 1848 } mlo_glb_h_shmem; 1849 1850 A_COMPILE_TIME_ASSERT(check_mlo_glb_h_shmem_8byte_size_quantum, 1851 (((sizeof(mlo_glb_h_shmem) % sizeof(A_UINT64) == 0x0)))); 1852 1853 /** 2 word representation of MAC addr */ 1854 typedef struct _wmi_mac_addr { 1855 /** upper 4 bytes of MAC address */ 1856 A_UINT32 mac_addr31to0; 1857 /** lower 2 bytes of MAC address */ 1858 A_UINT32 mac_addr47to32; 1859 } wmi_mac_addr; 1860 1861 #endif /* __WLANDEFS_H__ */ 1862