1 #ifndef __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
2 #define __src_common_sdk_nvidia_inc_ctrl_ctrl90f1_h__
3 
4 /* Excerpt of RM headers from https://github.com/NVIDIA/open-gpu-kernel-modules/tree/535.113.01 */
5 
6 /*
7  * SPDX-FileCopyrightText: Copyright (c) 2014-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
8  * SPDX-License-Identifier: MIT
9  *
10  * Permission is hereby granted, free of charge, to any person obtaining a
11  * copy of this software and associated documentation files (the "Software"),
12  * to deal in the Software without restriction, including without limitation
13  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14  * and/or sell copies of the Software, and to permit persons to whom the
15  * Software is furnished to do so, subject to the following conditions:
16  *
17  * The above copyright notice and this permission notice shall be included in
18  * all copies or substantial portions of the Software.
19  *
20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26  * DEALINGS IN THE SOFTWARE.
27  */
28 
29 #define GMMU_FMT_MAX_LEVELS  6U
30 
31 #define NV90F1_CTRL_CMD_VASPACE_COPY_SERVER_RESERVED_PDES (0x90f10106U) /* finn: Evaluated from "(FINN_FERMI_VASPACE_A_VASPACE_INTERFACE_ID << 8) | NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS_MESSAGE_ID" */
32 
33 typedef struct NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS {
34     /*!
35      * [in] GPU sub-device handle - this API only supports unicast.
36      *      Pass 0 to use subDeviceId instead.
37      */
38     NvHandle hSubDevice;
39 
40     /*!
41      * [in] GPU sub-device ID. Ignored if hSubDevice is non-zero.
42      */
43     NvU32    subDeviceId;
44 
45     /*!
46      * [in] Page size (VA coverage) of the level to reserve.
47      *      This need not be a leaf (page table) page size - it can be
48      *      the coverage of an arbitrary level (including root page directory).
49      */
50     NV_DECLARE_ALIGNED(NvU64 pageSize, 8);
51 
52     /*!
53      * [in] First GPU virtual address of the range to reserve.
54      *      This must be aligned to pageSize.
55      */
56     NV_DECLARE_ALIGNED(NvU64 virtAddrLo, 8);
57 
58     /*!
59      * [in] Last GPU virtual address of the range to reserve.
60      *      This (+1) must be aligned to pageSize.
61      */
62     NV_DECLARE_ALIGNED(NvU64 virtAddrHi, 8);
63 
64     /*!
65      * [in] Number of PDE levels to copy.
66      */
67     NvU32    numLevelsToCopy;
68 
69    /*!
70      * [in] Per-level information.
71      */
72     struct {
73         /*!
74          * Physical address of this page level instance.
75          */
76         NV_DECLARE_ALIGNED(NvU64 physAddress, 8);
77 
78         /*!
79          * Size in bytes allocated for this level instance.
80          */
81         NV_DECLARE_ALIGNED(NvU64 size, 8);
82 
83         /*!
84          * Aperture in which this page level instance resides.
85          */
86         NvU32 aperture;
87 
88         /*!
89          * Page shift corresponding to the level
90          */
91         NvU8  pageShift;
92     } levels[GMMU_FMT_MAX_LEVELS];
93 } NV90F1_CTRL_VASPACE_COPY_SERVER_RESERVED_PDES_PARAMS;
94 
95 #endif
96