1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26
27 #include "reg_helper.h"
28 #include "dcn10_optc.h"
29 #include "dc.h"
30 #include "dc_trace.h"
31
32 #define REG(reg)\
33 optc1->tg_regs->reg
34
35 #define CTX \
36 optc1->base.ctx
37
38 #undef FN
39 #define FN(reg_name, field_name) \
40 optc1->tg_shift->field_name, optc1->tg_mask->field_name
41
42 #define STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN 0x100
43
44 /**
45 * apply_front_porch_workaround() - This is a workaround for a bug that has
46 * existed since R5xx and has not been fixed
47 * keep Front porch at minimum 2 for Interlaced
48 * mode or 1 for progressive.
49 *
50 * @timing: Timing parameters used to configure DCN blocks.
51 */
apply_front_porch_workaround(struct dc_crtc_timing * timing)52 static void apply_front_porch_workaround(struct dc_crtc_timing *timing)
53 {
54 if (timing->flags.INTERLACE == 1) {
55 if (timing->v_front_porch < 2)
56 timing->v_front_porch = 2;
57 } else {
58 if (timing->v_front_porch < 1)
59 timing->v_front_porch = 1;
60 }
61 }
62
optc1_program_global_sync(struct timing_generator * optc,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,int pstate_keepout)63 void optc1_program_global_sync(
64 struct timing_generator *optc,
65 int vready_offset,
66 int vstartup_start,
67 int vupdate_offset,
68 int vupdate_width,
69 int pstate_keepout)
70 {
71 struct optc *optc1 = DCN10TG_FROM_TG(optc);
72
73 optc1->vready_offset = vready_offset;
74 optc1->vstartup_start = vstartup_start;
75 optc1->vupdate_offset = vupdate_offset;
76 optc1->vupdate_width = vupdate_width;
77 optc1->pstate_keepout = pstate_keepout;
78
79 if (optc1->vstartup_start == 0) {
80 BREAK_TO_DEBUGGER();
81 return;
82 }
83
84 REG_SET(OTG_VSTARTUP_PARAM, 0,
85 VSTARTUP_START, optc1->vstartup_start);
86
87 REG_SET_2(OTG_VUPDATE_PARAM, 0,
88 VUPDATE_OFFSET, optc1->vupdate_offset,
89 VUPDATE_WIDTH, optc1->vupdate_width);
90
91 REG_SET(OTG_VREADY_PARAM, 0,
92 VREADY_OFFSET, optc1->vready_offset);
93 }
94
optc1_disable_stereo(struct timing_generator * optc)95 static void optc1_disable_stereo(struct timing_generator *optc)
96 {
97 struct optc *optc1 = DCN10TG_FROM_TG(optc);
98
99 REG_SET(OTG_STEREO_CONTROL, 0,
100 OTG_STEREO_EN, 0);
101
102 REG_SET_2(OTG_3D_STRUCTURE_CONTROL, 0,
103 OTG_3D_STRUCTURE_EN, 0,
104 OTG_3D_STRUCTURE_STEREO_SEL_OVR, 0);
105 }
106
optc1_setup_vertical_interrupt0(struct timing_generator * optc,uint32_t start_line,uint32_t end_line)107 void optc1_setup_vertical_interrupt0(
108 struct timing_generator *optc,
109 uint32_t start_line,
110 uint32_t end_line)
111 {
112 struct optc *optc1 = DCN10TG_FROM_TG(optc);
113
114 REG_SET_2(OTG_VERTICAL_INTERRUPT0_POSITION, 0,
115 OTG_VERTICAL_INTERRUPT0_LINE_START, start_line,
116 OTG_VERTICAL_INTERRUPT0_LINE_END, end_line);
117 }
118
optc1_setup_vertical_interrupt1(struct timing_generator * optc,uint32_t start_line)119 void optc1_setup_vertical_interrupt1(
120 struct timing_generator *optc,
121 uint32_t start_line)
122 {
123 struct optc *optc1 = DCN10TG_FROM_TG(optc);
124
125 REG_SET(OTG_VERTICAL_INTERRUPT1_POSITION, 0,
126 OTG_VERTICAL_INTERRUPT1_LINE_START, start_line);
127 }
128
optc1_setup_vertical_interrupt2(struct timing_generator * optc,uint32_t start_line)129 void optc1_setup_vertical_interrupt2(
130 struct timing_generator *optc,
131 uint32_t start_line)
132 {
133 struct optc *optc1 = DCN10TG_FROM_TG(optc);
134
135 REG_SET(OTG_VERTICAL_INTERRUPT2_POSITION, 0,
136 OTG_VERTICAL_INTERRUPT2_LINE_START, start_line);
137 }
138
139 /**
140 * optc1_program_timing() - used by mode timing set Program
141 * CRTC Timing Registers - OTG_H_*,
142 * OTG_V_*, Pixel repetition.
143 * Including SYNC. Call BIOS command table to program Timings.
144 *
145 * @optc: timing_generator instance.
146 * @dc_crtc_timing: Timing parameters used to configure DCN blocks.
147 * @vready_offset: Vready's starting position.
148 * @vstartup_start: Vstartup period.
149 * @vupdate_offset: Vupdate starting position.
150 * @vupdate_width: Vupdate duration.
151 * @pstate_keepout: determines low power mode timing during refresh
152 * @signal: DC signal types.
153 * @use_vbios: to program timings from BIOS command table.
154 *
155 */
optc1_program_timing(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,int vready_offset,int vstartup_start,int vupdate_offset,int vupdate_width,int pstate_keepout,const enum signal_type signal,bool use_vbios)156 void optc1_program_timing(
157 struct timing_generator *optc,
158 const struct dc_crtc_timing *dc_crtc_timing,
159 int vready_offset,
160 int vstartup_start,
161 int vupdate_offset,
162 int vupdate_width,
163 int pstate_keepout,
164 const enum signal_type signal,
165 bool use_vbios)
166 {
167 struct dc_crtc_timing patched_crtc_timing;
168 uint32_t asic_blank_end;
169 uint32_t asic_blank_start;
170 uint32_t v_total;
171 uint32_t v_sync_end;
172 uint32_t h_sync_polarity, v_sync_polarity;
173 uint32_t start_point = 0;
174 uint32_t field_num = 0;
175 enum h_timing_div_mode h_div = H_TIMING_NO_DIV;
176
177 struct optc *optc1 = DCN10TG_FROM_TG(optc);
178
179 optc1->signal = signal;
180 optc1->vready_offset = vready_offset;
181 optc1->vstartup_start = vstartup_start;
182 optc1->vupdate_offset = vupdate_offset;
183 optc1->vupdate_width = vupdate_width;
184 optc1->pstate_keepout = pstate_keepout;
185 patched_crtc_timing = *dc_crtc_timing;
186 apply_front_porch_workaround(&patched_crtc_timing);
187 optc1->orginal_patched_timing = patched_crtc_timing;
188
189 /* Load horizontal timing */
190
191 /* CRTC_H_TOTAL = vesa.h_total - 1 */
192 REG_SET(OTG_H_TOTAL, 0,
193 OTG_H_TOTAL, patched_crtc_timing.h_total - 1);
194
195 /* h_sync_start = 0, h_sync_end = vesa.h_sync_width */
196 REG_UPDATE_2(OTG_H_SYNC_A,
197 OTG_H_SYNC_A_START, 0,
198 OTG_H_SYNC_A_END, patched_crtc_timing.h_sync_width);
199
200 /* blank_start = line end - front porch */
201 asic_blank_start = patched_crtc_timing.h_total -
202 patched_crtc_timing.h_front_porch;
203
204 /* blank_end = blank_start - active */
205 asic_blank_end = asic_blank_start -
206 patched_crtc_timing.h_border_right -
207 patched_crtc_timing.h_addressable -
208 patched_crtc_timing.h_border_left;
209
210 REG_UPDATE_2(OTG_H_BLANK_START_END,
211 OTG_H_BLANK_START, asic_blank_start,
212 OTG_H_BLANK_END, asic_blank_end);
213
214 /* h_sync polarity */
215 h_sync_polarity = patched_crtc_timing.flags.HSYNC_POSITIVE_POLARITY ?
216 0 : 1;
217
218 REG_UPDATE(OTG_H_SYNC_A_CNTL,
219 OTG_H_SYNC_A_POL, h_sync_polarity);
220
221 v_total = patched_crtc_timing.v_total - 1;
222
223 REG_SET(OTG_V_TOTAL, 0,
224 OTG_V_TOTAL, v_total);
225
226 /* In case of V_TOTAL_CONTROL is on, make sure OTG_V_TOTAL_MAX and
227 * OTG_V_TOTAL_MIN are equal to V_TOTAL.
228 */
229 optc->funcs->set_vtotal_min_max(optc, v_total, v_total);
230
231 /* v_sync_start = 0, v_sync_end = v_sync_width */
232 v_sync_end = patched_crtc_timing.v_sync_width;
233
234 REG_UPDATE_2(OTG_V_SYNC_A,
235 OTG_V_SYNC_A_START, 0,
236 OTG_V_SYNC_A_END, v_sync_end);
237
238 /* blank_start = frame end - front porch */
239 asic_blank_start = patched_crtc_timing.v_total -
240 patched_crtc_timing.v_front_porch;
241
242 /* blank_end = blank_start - active */
243 asic_blank_end = asic_blank_start -
244 patched_crtc_timing.v_border_bottom -
245 patched_crtc_timing.v_addressable -
246 patched_crtc_timing.v_border_top;
247
248 REG_UPDATE_2(OTG_V_BLANK_START_END,
249 OTG_V_BLANK_START, asic_blank_start,
250 OTG_V_BLANK_END, asic_blank_end);
251
252 /* v_sync polarity */
253 v_sync_polarity = patched_crtc_timing.flags.VSYNC_POSITIVE_POLARITY ?
254 0 : 1;
255
256 REG_UPDATE(OTG_V_SYNC_A_CNTL,
257 OTG_V_SYNC_A_POL, v_sync_polarity);
258
259 if (optc1->signal == SIGNAL_TYPE_DISPLAY_PORT ||
260 optc1->signal == SIGNAL_TYPE_DISPLAY_PORT_MST ||
261 optc1->signal == SIGNAL_TYPE_EDP) {
262 start_point = 1;
263 if (patched_crtc_timing.flags.INTERLACE == 1)
264 field_num = 1;
265 }
266
267 /* Interlace */
268 if (REG(OTG_INTERLACE_CONTROL)) {
269 if (patched_crtc_timing.flags.INTERLACE == 1)
270 REG_UPDATE(OTG_INTERLACE_CONTROL,
271 OTG_INTERLACE_ENABLE, 1);
272 else
273 REG_UPDATE(OTG_INTERLACE_CONTROL,
274 OTG_INTERLACE_ENABLE, 0);
275 }
276
277 /* VTG enable set to 0 first VInit */
278 REG_UPDATE(CONTROL,
279 VTG0_ENABLE, 0);
280
281 /* original code is using VTG offset to address OTG reg, seems wrong */
282 REG_UPDATE_2(OTG_CONTROL,
283 OTG_START_POINT_CNTL, start_point,
284 OTG_FIELD_NUMBER_CNTL, field_num);
285
286 optc->funcs->program_global_sync(optc,
287 vready_offset,
288 vstartup_start,
289 vupdate_offset,
290 vupdate_width,
291 pstate_keepout);
292
293 optc->funcs->set_vtg_params(optc, dc_crtc_timing, true);
294
295 /* TODO
296 * patched_crtc_timing.flags.HORZ_COUNT_BY_TWO == 1
297 * program_horz_count_by_2
298 * for DVI 30bpp mode, 0 otherwise
299 * program_horz_count_by_2(optc, &patched_crtc_timing);
300 */
301
302 /* Enable stereo - only when we need to pack 3D frame. Other types
303 * of stereo handled in explicit call
304 */
305
306 if (optc->funcs->is_two_pixels_per_container(&patched_crtc_timing) || optc1->opp_count == 2)
307 h_div = H_TIMING_DIV_BY2;
308
309 if (REG(OPTC_DATA_FORMAT_CONTROL) && optc1->tg_mask->OPTC_DATA_FORMAT != 0) {
310 uint32_t data_fmt = 0;
311
312 if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
313 data_fmt = 1;
314 else if (patched_crtc_timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
315 data_fmt = 2;
316
317 REG_UPDATE(OPTC_DATA_FORMAT_CONTROL, OPTC_DATA_FORMAT, data_fmt);
318 }
319
320 if (optc1->tg_mask->OTG_H_TIMING_DIV_MODE != 0) {
321 if (optc1->opp_count == 4)
322 h_div = H_TIMING_DIV_BY4;
323
324 REG_UPDATE(OTG_H_TIMING_CNTL,
325 OTG_H_TIMING_DIV_MODE, h_div);
326 } else {
327 REG_UPDATE(OTG_H_TIMING_CNTL,
328 OTG_H_TIMING_DIV_BY2, h_div);
329 }
330 }
331
332 /**
333 * optc1_set_vtg_params - Set Vertical Timing Generator (VTG) parameters
334 *
335 * @optc: timing_generator struct used to extract the optc parameters
336 * @dc_crtc_timing: Timing parameters configured
337 * @program_fp2: Boolean value indicating if FP2 will be programmed or not
338 *
339 * OTG is responsible for generating the global sync signals, including
340 * vertical timing information for each HUBP in the dcfclk domain. Each VTG is
341 * associated with one OTG that provides HUBP with vertical timing information
342 * (i.e., there is 1:1 correspondence between OTG and VTG). This function is
343 * responsible for setting the OTG parameters to the VTG during the pipe
344 * programming.
345 */
optc1_set_vtg_params(struct timing_generator * optc,const struct dc_crtc_timing * dc_crtc_timing,bool program_fp2)346 void optc1_set_vtg_params(struct timing_generator *optc,
347 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2)
348 {
349 struct dc_crtc_timing patched_crtc_timing;
350 uint32_t asic_blank_end;
351 uint32_t v_init;
352 uint32_t v_fp2 = 0;
353 int32_t vertical_line_start;
354
355 struct optc *optc1 = DCN10TG_FROM_TG(optc);
356
357 patched_crtc_timing = *dc_crtc_timing;
358 apply_front_porch_workaround(&patched_crtc_timing);
359
360 /* VCOUNT_INIT is the start of blank */
361 v_init = patched_crtc_timing.v_total - patched_crtc_timing.v_front_porch;
362
363 /* end of blank = v_init - active */
364 asic_blank_end = v_init -
365 patched_crtc_timing.v_border_bottom -
366 patched_crtc_timing.v_addressable -
367 patched_crtc_timing.v_border_top;
368
369 /* if VSTARTUP is before VSYNC, FP2 is the offset, otherwise 0 */
370 vertical_line_start = asic_blank_end - optc1->vstartup_start + 1;
371 if (vertical_line_start < 0)
372 v_fp2 = -vertical_line_start;
373
374 /* Interlace */
375 if (REG(OTG_INTERLACE_CONTROL)) {
376 if (patched_crtc_timing.flags.INTERLACE == 1) {
377 v_init = v_init / 2;
378 if ((optc1->vstartup_start/2)*2 > asic_blank_end)
379 v_fp2 = v_fp2 / 2;
380 }
381 }
382
383 if (program_fp2)
384 REG_UPDATE_2(CONTROL,
385 VTG0_FP2, v_fp2,
386 VTG0_VCOUNT_INIT, v_init);
387 else
388 REG_UPDATE(CONTROL, VTG0_VCOUNT_INIT, v_init);
389 }
390
optc1_set_blank_data_double_buffer(struct timing_generator * optc,bool enable)391 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable)
392 {
393 struct optc *optc1 = DCN10TG_FROM_TG(optc);
394
395 uint32_t blank_data_double_buffer_enable = enable ? 1 : 0;
396
397 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
398 OTG_BLANK_DATA_DOUBLE_BUFFER_EN, blank_data_double_buffer_enable);
399 }
400
401 /**
402 * optc1_set_timing_double_buffer() - DRR double buffering control
403 *
404 * Sets double buffer point for V_TOTAL, H_TOTAL, VTOTAL_MIN,
405 * VTOTAL_MAX, VTOTAL_MIN_SEL and VTOTAL_MAX_SEL registers.
406 *
407 * @optc: timing_generator instance.
408 * @enable: Enable DRR double buffering control if true, disable otherwise.
409 *
410 * Options: any time, start of frame, dp start of frame (range timing)
411 */
optc1_set_timing_double_buffer(struct timing_generator * optc,bool enable)412 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable)
413 {
414 struct optc *optc1 = DCN10TG_FROM_TG(optc);
415 uint32_t mode = enable ? 2 : 0;
416
417 REG_UPDATE(OTG_DOUBLE_BUFFER_CONTROL,
418 OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mode);
419 }
420
421 /**
422 * optc1_unblank_crtc() - Call ASIC Control Object to UnBlank CRTC.
423 *
424 * @optc: timing_generator instance.
425 */
optc1_unblank_crtc(struct timing_generator * optc)426 static void optc1_unblank_crtc(struct timing_generator *optc)
427 {
428 struct optc *optc1 = DCN10TG_FROM_TG(optc);
429
430 REG_UPDATE_2(OTG_BLANK_CONTROL,
431 OTG_BLANK_DATA_EN, 0,
432 OTG_BLANK_DE_MODE, 0);
433
434 /* W/A for automated testing
435 * Automated testing will fail underflow test as there
436 * sporadic underflows which occur during the optc blank
437 * sequence. As a w/a, clear underflow on unblank.
438 * This prevents the failure, but will not mask actual
439 * underflow that affect real use cases.
440 */
441 optc1_clear_optc_underflow(optc);
442 }
443
444 /**
445 * optc1_blank_crtc() - Call ASIC Control Object to Blank CRTC.
446 *
447 * @optc: timing_generator instance.
448 */
449
optc1_blank_crtc(struct timing_generator * optc)450 static void optc1_blank_crtc(struct timing_generator *optc)
451 {
452 struct optc *optc1 = DCN10TG_FROM_TG(optc);
453
454 REG_UPDATE_2(OTG_BLANK_CONTROL,
455 OTG_BLANK_DATA_EN, 1,
456 OTG_BLANK_DE_MODE, 0);
457
458 optc1_set_blank_data_double_buffer(optc, false);
459 }
460
optc1_set_blank(struct timing_generator * optc,bool enable_blanking)461 void optc1_set_blank(struct timing_generator *optc,
462 bool enable_blanking)
463 {
464 if (enable_blanking)
465 optc1_blank_crtc(optc);
466 else
467 optc1_unblank_crtc(optc);
468 }
469
optc1_is_blanked(struct timing_generator * optc)470 bool optc1_is_blanked(struct timing_generator *optc)
471 {
472 struct optc *optc1 = DCN10TG_FROM_TG(optc);
473 uint32_t blank_en;
474 uint32_t blank_state;
475
476 REG_GET_2(OTG_BLANK_CONTROL,
477 OTG_BLANK_DATA_EN, &blank_en,
478 OTG_CURRENT_BLANK_STATE, &blank_state);
479
480 return blank_en && blank_state;
481 }
482
optc1_enable_optc_clock(struct timing_generator * optc,bool enable)483 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable)
484 {
485 struct optc *optc1 = DCN10TG_FROM_TG(optc);
486
487 if (enable) {
488 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
489 OPTC_INPUT_CLK_EN, 1,
490 OPTC_INPUT_CLK_GATE_DIS, 1);
491
492 REG_WAIT(OPTC_INPUT_CLOCK_CONTROL,
493 OPTC_INPUT_CLK_ON, 1,
494 1, 1000);
495
496 /* Enable clock */
497 REG_UPDATE_2(OTG_CLOCK_CONTROL,
498 OTG_CLOCK_EN, 1,
499 OTG_CLOCK_GATE_DIS, 1);
500 REG_WAIT(OTG_CLOCK_CONTROL,
501 OTG_CLOCK_ON, 1,
502 1, 1000);
503 } else {
504
505 //last chance to clear underflow, otherwise, it will always there due to clock is off.
506 if (optc->funcs->is_optc_underflow_occurred(optc) == true)
507 optc->funcs->clear_optc_underflow(optc);
508
509 REG_UPDATE_2(OTG_CLOCK_CONTROL,
510 OTG_CLOCK_GATE_DIS, 0,
511 OTG_CLOCK_EN, 0);
512
513 REG_UPDATE_2(OPTC_INPUT_CLOCK_CONTROL,
514 OPTC_INPUT_CLK_GATE_DIS, 0,
515 OPTC_INPUT_CLK_EN, 0);
516 }
517 }
518
519 /**
520 * optc1_enable_crtc() - Enable CRTC - call ASIC Control Object to enable Timing generator.
521 *
522 * @optc: timing_generator instance.
523 */
optc1_enable_crtc(struct timing_generator * optc)524 static bool optc1_enable_crtc(struct timing_generator *optc)
525 {
526 /* TODO FPGA wait for answer
527 * OTG_MASTER_UPDATE_MODE != CRTC_MASTER_UPDATE_MODE
528 * OTG_MASTER_UPDATE_LOCK != CRTC_MASTER_UPDATE_LOCK
529 */
530 struct optc *optc1 = DCN10TG_FROM_TG(optc);
531
532 /* opp instance for OTG. For DCN1.0, ODM is remoed.
533 * OPP and OPTC should 1:1 mapping
534 */
535 REG_UPDATE(OPTC_DATA_SOURCE_SELECT,
536 OPTC_SRC_SEL, optc->inst);
537
538 /* VTG enable first is for HW workaround */
539 REG_UPDATE(CONTROL,
540 VTG0_ENABLE, 1);
541
542 REG_SEQ_START();
543
544 /* Enable CRTC */
545 REG_UPDATE_2(OTG_CONTROL,
546 OTG_DISABLE_POINT_CNTL, 3,
547 OTG_MASTER_EN, 1);
548
549 REG_SEQ_SUBMIT();
550 REG_SEQ_WAIT_DONE();
551
552 return true;
553 }
554
555 /* disable_crtc - call ASIC Control Object to disable Timing generator. */
optc1_disable_crtc(struct timing_generator * optc)556 bool optc1_disable_crtc(struct timing_generator *optc)
557 {
558 struct optc *optc1 = DCN10TG_FROM_TG(optc);
559
560 /* disable otg request until end of the first line
561 * in the vertical blank region
562 */
563 REG_UPDATE_2(OTG_CONTROL,
564 OTG_DISABLE_POINT_CNTL, 3,
565 OTG_MASTER_EN, 0);
566
567 REG_UPDATE(CONTROL,
568 VTG0_ENABLE, 0);
569
570 /* CRTC disabled, so disable clock. */
571 REG_WAIT(OTG_CLOCK_CONTROL,
572 OTG_BUSY, 0,
573 1, 100000);
574
575 return true;
576 }
577
578
optc1_program_blank_color(struct timing_generator * optc,const struct tg_color * black_color)579 void optc1_program_blank_color(
580 struct timing_generator *optc,
581 const struct tg_color *black_color)
582 {
583 struct optc *optc1 = DCN10TG_FROM_TG(optc);
584
585 REG_SET_3(OTG_BLACK_COLOR, 0,
586 OTG_BLACK_COLOR_B_CB, black_color->color_b_cb,
587 OTG_BLACK_COLOR_G_Y, black_color->color_g_y,
588 OTG_BLACK_COLOR_R_CR, black_color->color_r_cr);
589 }
590
optc1_validate_timing(struct timing_generator * optc,const struct dc_crtc_timing * timing)591 bool optc1_validate_timing(
592 struct timing_generator *optc,
593 const struct dc_crtc_timing *timing)
594 {
595 uint32_t v_blank;
596 uint32_t h_blank;
597 uint32_t min_v_blank;
598 struct optc *optc1 = DCN10TG_FROM_TG(optc);
599
600 ASSERT(timing != NULL);
601
602 v_blank = (timing->v_total - timing->v_addressable -
603 timing->v_border_top - timing->v_border_bottom);
604
605 h_blank = (timing->h_total - timing->h_addressable -
606 timing->h_border_right -
607 timing->h_border_left);
608
609 if (timing->timing_3d_format != TIMING_3D_FORMAT_NONE &&
610 timing->timing_3d_format != TIMING_3D_FORMAT_HW_FRAME_PACKING &&
611 timing->timing_3d_format != TIMING_3D_FORMAT_TOP_AND_BOTTOM &&
612 timing->timing_3d_format != TIMING_3D_FORMAT_SIDE_BY_SIDE &&
613 timing->timing_3d_format != TIMING_3D_FORMAT_FRAME_ALTERNATE &&
614 timing->timing_3d_format != TIMING_3D_FORMAT_INBAND_FA)
615 return false;
616
617 /* Temporarily blocking interlacing mode until it's supported */
618 if (timing->flags.INTERLACE == 1)
619 return false;
620
621 /* Check maximum number of pixels supported by Timing Generator
622 * (Currently will never fail, in order to fail needs display which
623 * needs more than 8192 horizontal and
624 * more than 8192 vertical total pixels)
625 */
626 if (timing->h_total > optc1->max_h_total ||
627 timing->v_total > optc1->max_v_total)
628 return false;
629
630
631 if (h_blank < optc1->min_h_blank)
632 return false;
633
634 if (timing->h_sync_width < optc1->min_h_sync_width ||
635 timing->v_sync_width < optc1->min_v_sync_width)
636 return false;
637
638 min_v_blank = timing->flags.INTERLACE?optc1->min_v_blank_interlace:optc1->min_v_blank;
639
640 if (v_blank < min_v_blank)
641 return false;
642
643 return true;
644
645 }
646
647 /*
648 * get_vblank_counter
649 *
650 * @brief
651 * Get counter for vertical blanks. use register CRTC_STATUS_FRAME_COUNT which
652 * holds the counter of frames.
653 *
654 * @param
655 * struct timing_generator *optc - [in] timing generator which controls the
656 * desired CRTC
657 *
658 * @return
659 * Counter of frames, which should equal to number of vblanks.
660 */
optc1_get_vblank_counter(struct timing_generator * optc)661 uint32_t optc1_get_vblank_counter(struct timing_generator *optc)
662 {
663 struct optc *optc1 = DCN10TG_FROM_TG(optc);
664 uint32_t frame_count;
665
666 REG_GET(OTG_STATUS_FRAME_COUNT,
667 OTG_FRAME_COUNT, &frame_count);
668
669 return frame_count;
670 }
671
optc1_lock(struct timing_generator * optc)672 void optc1_lock(struct timing_generator *optc)
673 {
674 struct optc *optc1 = DCN10TG_FROM_TG(optc);
675
676 REG_SET(OTG_GLOBAL_CONTROL0, 0,
677 OTG_MASTER_UPDATE_LOCK_SEL, optc->inst);
678 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
679 OTG_MASTER_UPDATE_LOCK, 1);
680
681 REG_WAIT(OTG_MASTER_UPDATE_LOCK,
682 UPDATE_LOCK_STATUS, 1,
683 1, 10);
684
685 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, true);
686 }
687
optc1_unlock(struct timing_generator * optc)688 void optc1_unlock(struct timing_generator *optc)
689 {
690 struct optc *optc1 = DCN10TG_FROM_TG(optc);
691
692 REG_SET(OTG_MASTER_UPDATE_LOCK, 0,
693 OTG_MASTER_UPDATE_LOCK, 0);
694
695 TRACE_OPTC_LOCK_UNLOCK_STATE(optc1, optc->inst, false);
696 }
697
optc1_get_position(struct timing_generator * optc,struct crtc_position * position)698 void optc1_get_position(struct timing_generator *optc,
699 struct crtc_position *position)
700 {
701 struct optc *optc1 = DCN10TG_FROM_TG(optc);
702
703 REG_GET_2(OTG_STATUS_POSITION,
704 OTG_HORZ_COUNT, &position->horizontal_count,
705 OTG_VERT_COUNT, &position->vertical_count);
706
707 REG_GET(OTG_NOM_VERT_POSITION,
708 OTG_VERT_COUNT_NOM, &position->nominal_vcount);
709 }
710
optc1_is_counter_moving(struct timing_generator * optc)711 bool optc1_is_counter_moving(struct timing_generator *optc)
712 {
713 struct crtc_position position1, position2;
714
715 optc->funcs->get_position(optc, &position1);
716 optc->funcs->get_position(optc, &position2);
717
718 if (position1.horizontal_count == position2.horizontal_count &&
719 position1.vertical_count == position2.vertical_count)
720 return false;
721 else
722 return true;
723 }
724
optc1_did_triggered_reset_occur(struct timing_generator * optc)725 bool optc1_did_triggered_reset_occur(
726 struct timing_generator *optc)
727 {
728 struct optc *optc1 = DCN10TG_FROM_TG(optc);
729 uint32_t occurred_force, occurred_vsync;
730
731 REG_GET(OTG_FORCE_COUNT_NOW_CNTL,
732 OTG_FORCE_COUNT_NOW_OCCURRED, &occurred_force);
733
734 REG_GET(OTG_VERT_SYNC_CONTROL,
735 OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, &occurred_vsync);
736
737 return occurred_vsync != 0 || occurred_force != 0;
738 }
739
optc1_disable_reset_trigger(struct timing_generator * optc)740 void optc1_disable_reset_trigger(struct timing_generator *optc)
741 {
742 struct optc *optc1 = DCN10TG_FROM_TG(optc);
743
744 REG_WRITE(OTG_TRIGA_CNTL, 0);
745
746 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
747 OTG_FORCE_COUNT_NOW_CLEAR, 1);
748
749 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
750 OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, 1);
751 }
752
optc1_enable_reset_trigger(struct timing_generator * optc,int source_tg_inst)753 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst)
754 {
755 struct optc *optc1 = DCN10TG_FROM_TG(optc);
756 uint32_t falling_edge;
757
758 REG_GET(OTG_V_SYNC_A_CNTL,
759 OTG_V_SYNC_A_POL, &falling_edge);
760
761 if (falling_edge)
762 REG_SET_3(OTG_TRIGA_CNTL, 0,
763 /* vsync signal from selected OTG pipe based
764 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
765 */
766 OTG_TRIGA_SOURCE_SELECT, 20,
767 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
768 /* always detect falling edge */
769 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 1);
770 else
771 REG_SET_3(OTG_TRIGA_CNTL, 0,
772 /* vsync signal from selected OTG pipe based
773 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
774 */
775 OTG_TRIGA_SOURCE_SELECT, 20,
776 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
777 /* always detect rising edge */
778 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1);
779
780 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
781 /* force H count to H_TOTAL and V count to V_TOTAL in
782 * progressive mode and V_TOTAL-1 in interlaced mode
783 */
784 OTG_FORCE_COUNT_NOW_MODE, 2);
785 }
786
optc1_enable_crtc_reset(struct timing_generator * optc,int source_tg_inst,struct crtc_trigger_info * crtc_tp)787 void optc1_enable_crtc_reset(
788 struct timing_generator *optc,
789 int source_tg_inst,
790 struct crtc_trigger_info *crtc_tp)
791 {
792 struct optc *optc1 = DCN10TG_FROM_TG(optc);
793 uint32_t falling_edge = 0;
794 uint32_t rising_edge = 0;
795
796 switch (crtc_tp->event) {
797
798 case CRTC_EVENT_VSYNC_RISING:
799 rising_edge = 1;
800 break;
801
802 case CRTC_EVENT_VSYNC_FALLING:
803 falling_edge = 1;
804 break;
805 }
806
807 REG_SET_4(OTG_TRIGA_CNTL, 0,
808 /* vsync signal from selected OTG pipe based
809 * on OTG_TRIG_SOURCE_PIPE_SELECT setting
810 */
811 OTG_TRIGA_SOURCE_SELECT, 20,
812 OTG_TRIGA_SOURCE_PIPE_SELECT, source_tg_inst,
813 /* always detect falling edge */
814 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, rising_edge,
815 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, falling_edge);
816
817 switch (crtc_tp->delay) {
818 case TRIGGER_DELAY_NEXT_LINE:
819 REG_SET(OTG_VERT_SYNC_CONTROL, 0,
820 OTG_AUTO_FORCE_VSYNC_MODE, 1);
821 break;
822 case TRIGGER_DELAY_NEXT_PIXEL:
823 REG_SET(OTG_FORCE_COUNT_NOW_CNTL, 0,
824 /* force H count to H_TOTAL and V count to V_TOTAL in
825 * progressive mode and V_TOTAL-1 in interlaced mode
826 */
827 OTG_FORCE_COUNT_NOW_MODE, 2);
828 break;
829 }
830 }
831
optc1_wait_for_state(struct timing_generator * optc,enum crtc_state state)832 void optc1_wait_for_state(struct timing_generator *optc,
833 enum crtc_state state)
834 {
835 struct optc *optc1 = DCN10TG_FROM_TG(optc);
836
837 switch (state) {
838 case CRTC_STATE_VBLANK:
839 REG_WAIT(OTG_STATUS,
840 OTG_V_BLANK, 1,
841 1, 100000); /* 1 vupdate at 10hz */
842 break;
843
844 case CRTC_STATE_VACTIVE:
845 REG_WAIT(OTG_STATUS,
846 OTG_V_ACTIVE_DISP, 1,
847 1, 100000); /* 1 vupdate at 10hz */
848 break;
849
850 default:
851 break;
852 }
853 }
854
optc1_set_early_control(struct timing_generator * optc,uint32_t early_cntl)855 void optc1_set_early_control(
856 struct timing_generator *optc,
857 uint32_t early_cntl)
858 {
859 /* asic design change, do not need this control
860 * empty for share caller logic
861 */
862 }
863
864
optc1_set_static_screen_control(struct timing_generator * optc,uint32_t event_triggers,uint32_t num_frames)865 void optc1_set_static_screen_control(
866 struct timing_generator *optc,
867 uint32_t event_triggers,
868 uint32_t num_frames)
869 {
870 struct optc *optc1 = DCN10TG_FROM_TG(optc);
871
872 // By register spec, it only takes 8 bit value
873 if (num_frames > 0xFF)
874 num_frames = 0xFF;
875
876 /* Bit 8 is no longer applicable in RV for PSR case,
877 * set bit 8 to 0 if given
878 */
879 if ((event_triggers & STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN)
880 != 0)
881 event_triggers = event_triggers &
882 ~STATIC_SCREEN_EVENT_MASK_RANGETIMING_DOUBLE_BUFFER_UPDATE_EN;
883
884 REG_SET_2(OTG_STATIC_SCREEN_CONTROL, 0,
885 OTG_STATIC_SCREEN_EVENT_MASK, event_triggers,
886 OTG_STATIC_SCREEN_FRAME_COUNT, num_frames);
887 }
888
optc1_setup_manual_trigger(struct timing_generator * optc)889 static void optc1_setup_manual_trigger(struct timing_generator *optc)
890 {
891 struct optc *optc1 = DCN10TG_FROM_TG(optc);
892
893 REG_SET(OTG_GLOBAL_CONTROL2, 0,
894 MANUAL_FLOW_CONTROL_SEL, optc->inst);
895
896 REG_SET_8(OTG_TRIGA_CNTL, 0,
897 OTG_TRIGA_SOURCE_SELECT, 22,
898 OTG_TRIGA_SOURCE_PIPE_SELECT, optc->inst,
899 OTG_TRIGA_RISING_EDGE_DETECT_CNTL, 1,
900 OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, 0,
901 OTG_TRIGA_POLARITY_SELECT, 0,
902 OTG_TRIGA_FREQUENCY_SELECT, 0,
903 OTG_TRIGA_DELAY, 0,
904 OTG_TRIGA_CLEAR, 1);
905 }
906
optc1_program_manual_trigger(struct timing_generator * optc)907 static void optc1_program_manual_trigger(struct timing_generator *optc)
908 {
909 struct optc *optc1 = DCN10TG_FROM_TG(optc);
910
911 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
912 MANUAL_FLOW_CONTROL, 1);
913
914 REG_SET(OTG_MANUAL_FLOW_CONTROL, 0,
915 MANUAL_FLOW_CONTROL, 0);
916 }
917
918 /**
919 * optc1_set_drr() - Program dynamic refresh rate registers m_OTGx_OTG_V_TOTAL_*.
920 *
921 * @optc: timing_generator instance.
922 * @params: parameters used for Dynamic Refresh Rate.
923 */
optc1_set_drr(struct timing_generator * optc,const struct drr_params * params)924 void optc1_set_drr(
925 struct timing_generator *optc,
926 const struct drr_params *params)
927 {
928 struct optc *optc1 = DCN10TG_FROM_TG(optc);
929
930 if (params != NULL &&
931 params->vertical_total_max > 0 &&
932 params->vertical_total_min > 0) {
933
934 if (params->vertical_total_mid != 0) {
935
936 REG_SET(OTG_V_TOTAL_MID, 0,
937 OTG_V_TOTAL_MID, params->vertical_total_mid - 1);
938
939 REG_UPDATE_2(OTG_V_TOTAL_CONTROL,
940 OTG_VTOTAL_MID_REPLACING_MAX_EN, 1,
941 OTG_VTOTAL_MID_FRAME_NUM,
942 (uint8_t)params->vertical_total_mid_frame_num);
943
944 }
945
946 optc->funcs->set_vtotal_min_max(optc, params->vertical_total_min - 1, params->vertical_total_max - 1);
947
948 REG_UPDATE_5(OTG_V_TOTAL_CONTROL,
949 OTG_V_TOTAL_MIN_SEL, 1,
950 OTG_V_TOTAL_MAX_SEL, 1,
951 OTG_FORCE_LOCK_ON_EVENT, 0,
952 OTG_SET_V_TOTAL_MIN_MASK_EN, 0,
953 OTG_SET_V_TOTAL_MIN_MASK, 0);
954 }
955
956 // Setup manual flow control for EOF via TRIG_A
957 optc->funcs->setup_manual_trigger(optc);
958 }
959
optc1_set_vtotal_min_max(struct timing_generator * optc,int vtotal_min,int vtotal_max)960 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max)
961 {
962 struct optc *optc1 = DCN10TG_FROM_TG(optc);
963
964 REG_SET(OTG_V_TOTAL_MAX, 0,
965 OTG_V_TOTAL_MAX, vtotal_max);
966
967 REG_SET(OTG_V_TOTAL_MIN, 0,
968 OTG_V_TOTAL_MIN, vtotal_min);
969 }
970
optc1_set_test_pattern(struct timing_generator * optc,enum controller_dp_test_pattern test_pattern,enum dc_color_depth color_depth)971 static void optc1_set_test_pattern(
972 struct timing_generator *optc,
973 /* TODO: replace 'controller_dp_test_pattern' by 'test_pattern_mode'
974 * because this is not DP-specific (which is probably somewhere in DP
975 * encoder) */
976 enum controller_dp_test_pattern test_pattern,
977 enum dc_color_depth color_depth)
978 {
979 struct optc *optc1 = DCN10TG_FROM_TG(optc);
980 enum test_pattern_color_format bit_depth;
981 enum test_pattern_dyn_range dyn_range;
982 enum test_pattern_mode mode;
983 uint32_t pattern_mask;
984 uint32_t pattern_data;
985 /* color ramp generator mixes 16-bits color */
986 uint32_t src_bpc = 16;
987 /* requested bpc */
988 uint32_t dst_bpc;
989 uint32_t index;
990 /* RGB values of the color bars.
991 * Produce two RGB colors: RGB0 - white (all Fs)
992 * and RGB1 - black (all 0s)
993 * (three RGB components for two colors)
994 */
995 uint16_t src_color[6] = {0xFFFF, 0xFFFF, 0xFFFF, 0x0000,
996 0x0000, 0x0000};
997 /* dest color (converted to the specified color format) */
998 uint16_t dst_color[6];
999 uint32_t inc_base;
1000
1001 /* translate to bit depth */
1002 switch (color_depth) {
1003 case COLOR_DEPTH_666:
1004 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_6;
1005 break;
1006 case COLOR_DEPTH_888:
1007 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1008 break;
1009 case COLOR_DEPTH_101010:
1010 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_10;
1011 break;
1012 case COLOR_DEPTH_121212:
1013 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_12;
1014 break;
1015 default:
1016 bit_depth = TEST_PATTERN_COLOR_FORMAT_BPC_8;
1017 break;
1018 }
1019
1020 switch (test_pattern) {
1021 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES:
1022 case CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA:
1023 {
1024 dyn_range = (test_pattern ==
1025 CONTROLLER_DP_TEST_PATTERN_COLORSQUARES_CEA ?
1026 TEST_PATTERN_DYN_RANGE_CEA :
1027 TEST_PATTERN_DYN_RANGE_VESA);
1028 mode = TEST_PATTERN_MODE_COLORSQUARES_RGB;
1029
1030 REG_UPDATE_2(OTG_TEST_PATTERN_PARAMETERS,
1031 OTG_TEST_PATTERN_VRES, 6,
1032 OTG_TEST_PATTERN_HRES, 6);
1033
1034 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1035 OTG_TEST_PATTERN_EN, 1,
1036 OTG_TEST_PATTERN_MODE, mode,
1037 OTG_TEST_PATTERN_DYNAMIC_RANGE, dyn_range,
1038 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1039 }
1040 break;
1041
1042 case CONTROLLER_DP_TEST_PATTERN_VERTICALBARS:
1043 case CONTROLLER_DP_TEST_PATTERN_HORIZONTALBARS:
1044 {
1045 mode = (test_pattern ==
1046 CONTROLLER_DP_TEST_PATTERN_VERTICALBARS ?
1047 TEST_PATTERN_MODE_VERTICALBARS :
1048 TEST_PATTERN_MODE_HORIZONTALBARS);
1049
1050 switch (bit_depth) {
1051 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1052 dst_bpc = 6;
1053 break;
1054 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1055 dst_bpc = 8;
1056 break;
1057 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1058 dst_bpc = 10;
1059 break;
1060 default:
1061 dst_bpc = 8;
1062 break;
1063 }
1064
1065 /* adjust color to the required colorFormat */
1066 for (index = 0; index < 6; index++) {
1067 /* dst = 2^dstBpc * src / 2^srcBpc = src >>
1068 * (srcBpc - dstBpc);
1069 */
1070 dst_color[index] =
1071 src_color[index] >> (src_bpc - dst_bpc);
1072 /* CRTC_TEST_PATTERN_DATA has 16 bits,
1073 * lowest 6 are hardwired to ZERO
1074 * color bits should be left aligned to MSB
1075 * XXXXXXXXXX000000 for 10 bit,
1076 * XXXXXXXX00000000 for 8 bit and XXXXXX0000000000 for 6
1077 */
1078 dst_color[index] <<= (16 - dst_bpc);
1079 }
1080
1081 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1082
1083 /* We have to write the mask before data, similar to pipeline.
1084 * For example, for 8 bpc, if we want RGB0 to be magenta,
1085 * and RGB1 to be cyan,
1086 * we need to make 7 writes:
1087 * MASK DATA
1088 * 000001 00000000 00000000 set mask to R0
1089 * 000010 11111111 00000000 R0 255, 0xFF00, set mask to G0
1090 * 000100 00000000 00000000 G0 0, 0x0000, set mask to B0
1091 * 001000 11111111 00000000 B0 255, 0xFF00, set mask to R1
1092 * 010000 00000000 00000000 R1 0, 0x0000, set mask to G1
1093 * 100000 11111111 00000000 G1 255, 0xFF00, set mask to B1
1094 * 100000 11111111 00000000 B1 255, 0xFF00
1095 *
1096 * we will make a loop of 6 in which we prepare the mask,
1097 * then write, then prepare the color for next write.
1098 * first iteration will write mask only,
1099 * but each next iteration color prepared in
1100 * previous iteration will be written within new mask,
1101 * the last component will written separately,
1102 * mask is not changing between 6th and 7th write
1103 * and color will be prepared by last iteration
1104 */
1105
1106 /* write color, color values mask in CRTC_TEST_PATTERN_MASK
1107 * is B1, G1, R1, B0, G0, R0
1108 */
1109 pattern_data = 0;
1110 for (index = 0; index < 6; index++) {
1111 /* prepare color mask, first write PATTERN_DATA
1112 * will have all zeros
1113 */
1114 pattern_mask = (1 << index);
1115
1116 /* write color component */
1117 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1118 OTG_TEST_PATTERN_MASK, pattern_mask,
1119 OTG_TEST_PATTERN_DATA, pattern_data);
1120
1121 /* prepare next color component,
1122 * will be written in the next iteration
1123 */
1124 pattern_data = dst_color[index];
1125 }
1126 /* write last color component,
1127 * it's been already prepared in the loop
1128 */
1129 REG_SET_2(OTG_TEST_PATTERN_COLOR, 0,
1130 OTG_TEST_PATTERN_MASK, pattern_mask,
1131 OTG_TEST_PATTERN_DATA, pattern_data);
1132
1133 /* enable test pattern */
1134 REG_UPDATE_4(OTG_TEST_PATTERN_CONTROL,
1135 OTG_TEST_PATTERN_EN, 1,
1136 OTG_TEST_PATTERN_MODE, mode,
1137 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1138 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1139 }
1140 break;
1141
1142 case CONTROLLER_DP_TEST_PATTERN_COLORRAMP:
1143 {
1144 mode = (bit_depth ==
1145 TEST_PATTERN_COLOR_FORMAT_BPC_10 ?
1146 TEST_PATTERN_MODE_DUALRAMP_RGB :
1147 TEST_PATTERN_MODE_SINGLERAMP_RGB);
1148
1149 switch (bit_depth) {
1150 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1151 dst_bpc = 6;
1152 break;
1153 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1154 dst_bpc = 8;
1155 break;
1156 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1157 dst_bpc = 10;
1158 break;
1159 default:
1160 dst_bpc = 8;
1161 break;
1162 }
1163
1164 /* increment for the first ramp for one color gradation
1165 * 1 gradation for 6-bit color is 2^10
1166 * gradations in 16-bit color
1167 */
1168 inc_base = (src_bpc - dst_bpc);
1169
1170 switch (bit_depth) {
1171 case TEST_PATTERN_COLOR_FORMAT_BPC_6:
1172 {
1173 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1174 OTG_TEST_PATTERN_INC0, inc_base,
1175 OTG_TEST_PATTERN_INC1, 0,
1176 OTG_TEST_PATTERN_HRES, 6,
1177 OTG_TEST_PATTERN_VRES, 6,
1178 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1179 }
1180 break;
1181 case TEST_PATTERN_COLOR_FORMAT_BPC_8:
1182 {
1183 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1184 OTG_TEST_PATTERN_INC0, inc_base,
1185 OTG_TEST_PATTERN_INC1, 0,
1186 OTG_TEST_PATTERN_HRES, 8,
1187 OTG_TEST_PATTERN_VRES, 6,
1188 OTG_TEST_PATTERN_RAMP0_OFFSET, 0);
1189 }
1190 break;
1191 case TEST_PATTERN_COLOR_FORMAT_BPC_10:
1192 {
1193 REG_UPDATE_5(OTG_TEST_PATTERN_PARAMETERS,
1194 OTG_TEST_PATTERN_INC0, inc_base,
1195 OTG_TEST_PATTERN_INC1, inc_base + 2,
1196 OTG_TEST_PATTERN_HRES, 8,
1197 OTG_TEST_PATTERN_VRES, 5,
1198 OTG_TEST_PATTERN_RAMP0_OFFSET, 384 << 6);
1199 }
1200 break;
1201 default:
1202 break;
1203 }
1204
1205 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1206
1207 /* enable test pattern */
1208 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1209
1210 REG_SET_4(OTG_TEST_PATTERN_CONTROL, 0,
1211 OTG_TEST_PATTERN_EN, 1,
1212 OTG_TEST_PATTERN_MODE, mode,
1213 OTG_TEST_PATTERN_DYNAMIC_RANGE, 0,
1214 OTG_TEST_PATTERN_COLOR_FORMAT, bit_depth);
1215 }
1216 break;
1217 case CONTROLLER_DP_TEST_PATTERN_VIDEOMODE:
1218 {
1219 REG_WRITE(OTG_TEST_PATTERN_CONTROL, 0);
1220 REG_WRITE(OTG_TEST_PATTERN_COLOR, 0);
1221 REG_WRITE(OTG_TEST_PATTERN_PARAMETERS, 0);
1222 }
1223 break;
1224 default:
1225 break;
1226
1227 }
1228 }
1229
optc1_get_crtc_scanoutpos(struct timing_generator * optc,uint32_t * v_blank_start,uint32_t * v_blank_end,uint32_t * h_position,uint32_t * v_position)1230 void optc1_get_crtc_scanoutpos(
1231 struct timing_generator *optc,
1232 uint32_t *v_blank_start,
1233 uint32_t *v_blank_end,
1234 uint32_t *h_position,
1235 uint32_t *v_position)
1236 {
1237 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1238 struct crtc_position position;
1239
1240 REG_GET_2(OTG_V_BLANK_START_END,
1241 OTG_V_BLANK_START, v_blank_start,
1242 OTG_V_BLANK_END, v_blank_end);
1243
1244 optc1_get_position(optc, &position);
1245
1246 *h_position = position.horizontal_count;
1247 *v_position = position.vertical_count;
1248 }
1249
optc1_enable_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1250 static void optc1_enable_stereo(struct timing_generator *optc,
1251 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1252 {
1253 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1254
1255 if (flags) {
1256 uint32_t stereo_en;
1257 stereo_en = flags->FRAME_PACKED == 0 ? 1 : 0;
1258
1259 if (flags->PROGRAM_STEREO)
1260 REG_UPDATE_3(OTG_STEREO_CONTROL,
1261 OTG_STEREO_EN, stereo_en,
1262 OTG_STEREO_SYNC_OUTPUT_LINE_NUM, 0,
1263 OTG_STEREO_SYNC_OUTPUT_POLARITY, flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1264
1265 if (flags->PROGRAM_POLARITY)
1266 REG_UPDATE(OTG_STEREO_CONTROL,
1267 OTG_STEREO_EYE_FLAG_POLARITY,
1268 flags->RIGHT_EYE_POLARITY == 0 ? 0 : 1);
1269
1270 if (flags->DISABLE_STEREO_DP_SYNC)
1271 REG_UPDATE(OTG_STEREO_CONTROL,
1272 OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, 1);
1273
1274 if (flags->PROGRAM_STEREO)
1275 REG_UPDATE_2(OTG_3D_STRUCTURE_CONTROL,
1276 OTG_3D_STRUCTURE_EN, flags->FRAME_PACKED,
1277 OTG_3D_STRUCTURE_STEREO_SEL_OVR, flags->FRAME_PACKED);
1278
1279 }
1280 }
1281
optc1_program_stereo(struct timing_generator * optc,const struct dc_crtc_timing * timing,struct crtc_stereo_flags * flags)1282 void optc1_program_stereo(struct timing_generator *optc,
1283 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags)
1284 {
1285 if (flags->PROGRAM_STEREO)
1286 optc1_enable_stereo(optc, timing, flags);
1287 else
1288 optc1_disable_stereo(optc);
1289 }
1290
1291
optc1_is_stereo_left_eye(struct timing_generator * optc)1292 bool optc1_is_stereo_left_eye(struct timing_generator *optc)
1293 {
1294 bool ret = false;
1295 uint32_t left_eye = 0;
1296 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1297
1298 REG_GET(OTG_STEREO_STATUS,
1299 OTG_STEREO_CURRENT_EYE, &left_eye);
1300 if (left_eye == 1)
1301 ret = true;
1302 else
1303 ret = false;
1304
1305 return ret;
1306 }
1307
optc1_get_hw_timing(struct timing_generator * tg,struct dc_crtc_timing * hw_crtc_timing)1308 bool optc1_get_hw_timing(struct timing_generator *tg,
1309 struct dc_crtc_timing *hw_crtc_timing)
1310 {
1311 struct dcn_otg_state s = {0};
1312
1313 if (tg == NULL || hw_crtc_timing == NULL)
1314 return false;
1315
1316 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s);
1317
1318 hw_crtc_timing->h_total = s.h_total + 1;
1319 hw_crtc_timing->h_addressable = s.h_total - ((s.h_total - s.h_blank_start) + s.h_blank_end);
1320 hw_crtc_timing->h_front_porch = s.h_total + 1 - s.h_blank_start;
1321 hw_crtc_timing->h_sync_width = s.h_sync_a_end - s.h_sync_a_start;
1322
1323 hw_crtc_timing->v_total = s.v_total + 1;
1324 hw_crtc_timing->v_addressable = s.v_total - ((s.v_total - s.v_blank_start) + s.v_blank_end);
1325 hw_crtc_timing->v_front_porch = s.v_total + 1 - s.v_blank_start;
1326 hw_crtc_timing->v_sync_width = s.v_sync_a_end - s.v_sync_a_start;
1327
1328 return true;
1329 }
1330
1331
optc1_read_otg_state(struct optc * optc1,struct dcn_otg_state * s)1332 void optc1_read_otg_state(struct optc *optc1,
1333 struct dcn_otg_state *s)
1334 {
1335 REG_GET(OTG_CONTROL,
1336 OTG_MASTER_EN, &s->otg_enabled);
1337
1338 REG_GET_2(OTG_V_BLANK_START_END,
1339 OTG_V_BLANK_START, &s->v_blank_start,
1340 OTG_V_BLANK_END, &s->v_blank_end);
1341
1342 REG_GET(OTG_V_SYNC_A_CNTL,
1343 OTG_V_SYNC_A_POL, &s->v_sync_a_pol);
1344
1345 REG_GET(OTG_V_TOTAL,
1346 OTG_V_TOTAL, &s->v_total);
1347
1348 REG_GET(OTG_V_TOTAL_MAX,
1349 OTG_V_TOTAL_MAX, &s->v_total_max);
1350
1351 REG_GET(OTG_V_TOTAL_MIN,
1352 OTG_V_TOTAL_MIN, &s->v_total_min);
1353
1354 REG_GET(OTG_V_TOTAL_CONTROL,
1355 OTG_V_TOTAL_MAX_SEL, &s->v_total_max_sel);
1356
1357 REG_GET(OTG_V_TOTAL_CONTROL,
1358 OTG_V_TOTAL_MIN_SEL, &s->v_total_min_sel);
1359
1360 REG_GET_2(OTG_V_SYNC_A,
1361 OTG_V_SYNC_A_START, &s->v_sync_a_start,
1362 OTG_V_SYNC_A_END, &s->v_sync_a_end);
1363
1364 REG_GET_2(OTG_H_BLANK_START_END,
1365 OTG_H_BLANK_START, &s->h_blank_start,
1366 OTG_H_BLANK_END, &s->h_blank_end);
1367
1368 REG_GET_2(OTG_H_SYNC_A,
1369 OTG_H_SYNC_A_START, &s->h_sync_a_start,
1370 OTG_H_SYNC_A_END, &s->h_sync_a_end);
1371
1372 REG_GET(OTG_H_SYNC_A_CNTL,
1373 OTG_H_SYNC_A_POL, &s->h_sync_a_pol);
1374
1375 REG_GET(OTG_H_TOTAL,
1376 OTG_H_TOTAL, &s->h_total);
1377
1378 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1379 OPTC_UNDERFLOW_OCCURRED_STATUS, &s->underflow_occurred_status);
1380
1381 REG_GET(OTG_VERTICAL_INTERRUPT1_CONTROL,
1382 OTG_VERTICAL_INTERRUPT1_INT_ENABLE, &s->vertical_interrupt1_en);
1383
1384 REG_GET(OTG_VERTICAL_INTERRUPT1_POSITION,
1385 OTG_VERTICAL_INTERRUPT1_LINE_START, &s->vertical_interrupt1_line);
1386
1387 REG_GET(OTG_VERTICAL_INTERRUPT2_CONTROL,
1388 OTG_VERTICAL_INTERRUPT2_INT_ENABLE, &s->vertical_interrupt2_en);
1389
1390 REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
1391 OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
1392
1393 s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
1394 s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
1395 }
1396
optc1_get_otg_active_size(struct timing_generator * optc,uint32_t * otg_active_width,uint32_t * otg_active_height)1397 bool optc1_get_otg_active_size(struct timing_generator *optc,
1398 uint32_t *otg_active_width,
1399 uint32_t *otg_active_height)
1400 {
1401 uint32_t otg_enabled;
1402 uint32_t v_blank_start;
1403 uint32_t v_blank_end;
1404 uint32_t h_blank_start;
1405 uint32_t h_blank_end;
1406 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1407
1408
1409 REG_GET(OTG_CONTROL,
1410 OTG_MASTER_EN, &otg_enabled);
1411
1412 if (otg_enabled == 0)
1413 return false;
1414
1415 REG_GET_2(OTG_V_BLANK_START_END,
1416 OTG_V_BLANK_START, &v_blank_start,
1417 OTG_V_BLANK_END, &v_blank_end);
1418
1419 REG_GET_2(OTG_H_BLANK_START_END,
1420 OTG_H_BLANK_START, &h_blank_start,
1421 OTG_H_BLANK_END, &h_blank_end);
1422
1423 *otg_active_width = h_blank_start - h_blank_end;
1424 *otg_active_height = v_blank_start - v_blank_end;
1425 return true;
1426 }
1427
optc1_clear_optc_underflow(struct timing_generator * optc)1428 void optc1_clear_optc_underflow(struct timing_generator *optc)
1429 {
1430 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1431
1432 REG_UPDATE(OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, 1);
1433 }
1434
optc1_tg_init(struct timing_generator * optc)1435 void optc1_tg_init(struct timing_generator *optc)
1436 {
1437 optc1_set_blank_data_double_buffer(optc, true);
1438 optc1_set_timing_double_buffer(optc, true);
1439 optc1_clear_optc_underflow(optc);
1440 }
1441
optc1_is_tg_enabled(struct timing_generator * optc)1442 bool optc1_is_tg_enabled(struct timing_generator *optc)
1443 {
1444 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1445 uint32_t otg_enabled = 0;
1446
1447 REG_GET(OTG_CONTROL, OTG_MASTER_EN, &otg_enabled);
1448
1449 return (otg_enabled != 0);
1450
1451 }
1452
optc1_is_optc_underflow_occurred(struct timing_generator * optc)1453 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc)
1454 {
1455 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1456 uint32_t underflow_occurred = 0;
1457
1458 REG_GET(OPTC_INPUT_GLOBAL_CONTROL,
1459 OPTC_UNDERFLOW_OCCURRED_STATUS,
1460 &underflow_occurred);
1461
1462 return (underflow_occurred == 1);
1463 }
1464
optc1_configure_crc(struct timing_generator * optc,const struct crc_params * params)1465 bool optc1_configure_crc(struct timing_generator *optc,
1466 const struct crc_params *params)
1467 {
1468 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1469
1470 /* Cannot configure crc on a CRTC that is disabled */
1471 if (!optc1_is_tg_enabled(optc))
1472 return false;
1473
1474 REG_WRITE(OTG_CRC_CNTL, 0);
1475
1476 if (!params->enable)
1477 return true;
1478
1479 /* Program frame boundaries */
1480 /* Window A x axis start and end. */
1481 REG_UPDATE_2(OTG_CRC0_WINDOWA_X_CONTROL,
1482 OTG_CRC0_WINDOWA_X_START, params->windowa_x_start,
1483 OTG_CRC0_WINDOWA_X_END, params->windowa_x_end);
1484
1485 /* Window A y axis start and end. */
1486 REG_UPDATE_2(OTG_CRC0_WINDOWA_Y_CONTROL,
1487 OTG_CRC0_WINDOWA_Y_START, params->windowa_y_start,
1488 OTG_CRC0_WINDOWA_Y_END, params->windowa_y_end);
1489
1490 /* Window B x axis start and end. */
1491 REG_UPDATE_2(OTG_CRC0_WINDOWB_X_CONTROL,
1492 OTG_CRC0_WINDOWB_X_START, params->windowb_x_start,
1493 OTG_CRC0_WINDOWB_X_END, params->windowb_x_end);
1494
1495 /* Window B y axis start and end. */
1496 REG_UPDATE_2(OTG_CRC0_WINDOWB_Y_CONTROL,
1497 OTG_CRC0_WINDOWB_Y_START, params->windowb_y_start,
1498 OTG_CRC0_WINDOWB_Y_END, params->windowb_y_end);
1499
1500 /* Set crc mode and selection, and enable. Only using CRC0*/
1501 REG_UPDATE_3(OTG_CRC_CNTL,
1502 OTG_CRC_CONT_EN, params->continuous_mode ? 1 : 0,
1503 OTG_CRC0_SELECT, params->selection,
1504 OTG_CRC_EN, 1);
1505
1506 return true;
1507 }
1508
1509 /**
1510 * optc1_get_crc - Capture CRC result per component
1511 *
1512 * @optc: timing_generator instance.
1513 * @r_cr: 16-bit primary CRC signature for red data.
1514 * @g_y: 16-bit primary CRC signature for green data.
1515 * @b_cb: 16-bit primary CRC signature for blue data.
1516 *
1517 * This function reads the CRC signature from the OPTC registers. Notice that
1518 * we have three registers to keep the CRC result per color component (RGB).
1519 *
1520 * Returns:
1521 * If CRC is disabled, return false; otherwise, return true, and the CRC
1522 * results in the parameters.
1523 */
optc1_get_crc(struct timing_generator * optc,uint32_t * r_cr,uint32_t * g_y,uint32_t * b_cb)1524 bool optc1_get_crc(struct timing_generator *optc,
1525 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb)
1526 {
1527 uint32_t field = 0;
1528 struct optc *optc1 = DCN10TG_FROM_TG(optc);
1529
1530 REG_GET(OTG_CRC_CNTL, OTG_CRC_EN, &field);
1531
1532 /* Early return if CRC is not enabled for this CRTC */
1533 if (!field)
1534 return false;
1535
1536 /* OTG_CRC0_DATA_RG has the CRC16 results for the red and green component */
1537 REG_GET_2(OTG_CRC0_DATA_RG,
1538 CRC0_R_CR, r_cr,
1539 CRC0_G_Y, g_y);
1540
1541 /* OTG_CRC0_DATA_B has the CRC16 results for the blue component */
1542 REG_GET(OTG_CRC0_DATA_B,
1543 CRC0_B_CB, b_cb);
1544
1545 return true;
1546 }
1547
1548 /* "Container" vs. "pixel" is a concept within HW blocks, mostly those closer to the back-end. It works like this:
1549 *
1550 * - In most of the formats (RGB or YCbCr 4:4:4, 4:2:2 uncompressed and DSC 4:2:2 Simple) pixel rate is the same as
1551 * container rate.
1552 *
1553 * - In 4:2:0 (DSC or uncompressed) there are two pixels per container, hence the target container rate has to be
1554 * halved to maintain the correct pixel rate.
1555 *
1556 * - Unlike 4:2:2 uncompressed, DSC 4:2:2 Native also has two pixels per container (this happens when DSC is applied
1557 * to it) and has to be treated the same as 4:2:0, i.e. target containter rate has to be halved in this case as well.
1558 *
1559 */
optc1_is_two_pixels_per_container(const struct dc_crtc_timing * timing)1560 bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing)
1561 {
1562 bool two_pix = timing->pixel_encoding == PIXEL_ENCODING_YCBCR420;
1563
1564 two_pix = two_pix || (timing->flags.DSC && timing->pixel_encoding == PIXEL_ENCODING_YCBCR422
1565 && !timing->dsc_cfg.ycbcr422_simple);
1566 return two_pix;
1567 }
1568
1569 static const struct timing_generator_funcs dcn10_tg_funcs = {
1570 .validate_timing = optc1_validate_timing,
1571 .program_timing = optc1_program_timing,
1572 .setup_vertical_interrupt0 = optc1_setup_vertical_interrupt0,
1573 .setup_vertical_interrupt1 = optc1_setup_vertical_interrupt1,
1574 .setup_vertical_interrupt2 = optc1_setup_vertical_interrupt2,
1575 .program_global_sync = optc1_program_global_sync,
1576 .enable_crtc = optc1_enable_crtc,
1577 .disable_crtc = optc1_disable_crtc,
1578 /* used by enable_timing_synchronization. Not need for FPGA */
1579 .is_counter_moving = optc1_is_counter_moving,
1580 .get_position = optc1_get_position,
1581 .get_frame_count = optc1_get_vblank_counter,
1582 .get_scanoutpos = optc1_get_crtc_scanoutpos,
1583 .get_otg_active_size = optc1_get_otg_active_size,
1584 .set_early_control = optc1_set_early_control,
1585 /* used by enable_timing_synchronization. Not need for FPGA */
1586 .wait_for_state = optc1_wait_for_state,
1587 .set_blank = optc1_set_blank,
1588 .is_blanked = optc1_is_blanked,
1589 .set_blank_color = optc1_program_blank_color,
1590 .did_triggered_reset_occur = optc1_did_triggered_reset_occur,
1591 .enable_reset_trigger = optc1_enable_reset_trigger,
1592 .enable_crtc_reset = optc1_enable_crtc_reset,
1593 .disable_reset_trigger = optc1_disable_reset_trigger,
1594 .lock = optc1_lock,
1595 .unlock = optc1_unlock,
1596 .enable_optc_clock = optc1_enable_optc_clock,
1597 .set_drr = optc1_set_drr,
1598 .get_last_used_drr_vtotal = NULL,
1599 .set_vtotal_min_max = optc1_set_vtotal_min_max,
1600 .set_static_screen_control = optc1_set_static_screen_control,
1601 .set_test_pattern = optc1_set_test_pattern,
1602 .program_stereo = optc1_program_stereo,
1603 .is_stereo_left_eye = optc1_is_stereo_left_eye,
1604 .set_blank_data_double_buffer = optc1_set_blank_data_double_buffer,
1605 .tg_init = optc1_tg_init,
1606 .is_tg_enabled = optc1_is_tg_enabled,
1607 .is_optc_underflow_occurred = optc1_is_optc_underflow_occurred,
1608 .clear_optc_underflow = optc1_clear_optc_underflow,
1609 .get_crc = optc1_get_crc,
1610 .configure_crc = optc1_configure_crc,
1611 .set_vtg_params = optc1_set_vtg_params,
1612 .program_manual_trigger = optc1_program_manual_trigger,
1613 .setup_manual_trigger = optc1_setup_manual_trigger,
1614 .get_hw_timing = optc1_get_hw_timing,
1615 .is_two_pixels_per_container = optc1_is_two_pixels_per_container,
1616 };
1617
dcn10_timing_generator_init(struct optc * optc1)1618 void dcn10_timing_generator_init(struct optc *optc1)
1619 {
1620 optc1->base.funcs = &dcn10_tg_funcs;
1621
1622 optc1->max_h_total = optc1->tg_mask->OTG_H_TOTAL + 1;
1623 optc1->max_v_total = optc1->tg_mask->OTG_V_TOTAL + 1;
1624
1625 optc1->min_h_blank = 32;
1626 optc1->min_v_blank = 3;
1627 optc1->min_v_blank_interlace = 5;
1628 optc1->min_h_sync_width = 4;
1629 optc1->min_v_sync_width = 1;
1630 }
1631