1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "cgrp.h"
26 #include "chan.h"
27 #include "runl.h"
28
29 #include <core/gpuobj.h>
30 #include <subdev/instmem.h>
31
32 #include "regsnv04.h"
33
34 #include <nvif/class.h>
35
36 static int
nv10_chan_ramfc_write(struct nvkm_chan * chan,u64 offset,u64 length,u32 devm,bool priv)37 nv10_chan_ramfc_write(struct nvkm_chan *chan, u64 offset, u64 length, u32 devm, bool priv)
38 {
39 struct nvkm_memory *ramfc = chan->cgrp->runl->fifo->engine.subdev.device->imem->ramfc;
40 const u32 base = chan->id * 32;
41
42 chan->ramfc_offset = base;
43
44 nvkm_kmap(ramfc);
45 nvkm_wo32(ramfc, base + 0x00, offset);
46 nvkm_wo32(ramfc, base + 0x04, offset);
47 nvkm_wo32(ramfc, base + 0x0c, chan->push->addr >> 4);
48 nvkm_wo32(ramfc, base + 0x14, NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
49 NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
50 #ifdef __BIG_ENDIAN
51 NV_PFIFO_CACHE1_BIG_ENDIAN |
52 #endif
53 NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8);
54 nvkm_done(ramfc);
55 return 0;
56 }
57
58 static const struct nvkm_chan_func_ramfc
59 nv10_chan_ramfc = {
60 .layout = (const struct nvkm_ramfc_layout[]) {
61 { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT },
62 { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET },
63 { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT },
64 { 16, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE },
65 { 16, 16, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT },
66 { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_STATE },
67 { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_FETCH },
68 { 32, 0, 0x18, 0, NV04_PFIFO_CACHE1_ENGINE },
69 { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_PULL1 },
70 {}
71 },
72 .write = nv10_chan_ramfc_write,
73 .clear = nv04_chan_ramfc_clear,
74 .ctxdma = true,
75 };
76
77 static const struct nvkm_chan_func
78 nv10_chan = {
79 .inst = &nv04_chan_inst,
80 .userd = &nv04_chan_userd,
81 .ramfc = &nv10_chan_ramfc,
82 .start = nv04_chan_start,
83 .stop = nv04_chan_stop,
84 };
85
86 int
nv10_fifo_chid_nr(struct nvkm_fifo * fifo)87 nv10_fifo_chid_nr(struct nvkm_fifo *fifo)
88 {
89 return 32;
90 }
91
92 static const struct nvkm_fifo_func
93 nv10_fifo = {
94 .chid_nr = nv10_fifo_chid_nr,
95 .chid_ctor = nv04_fifo_chid_ctor,
96 .runl_ctor = nv04_fifo_runl_ctor,
97 .init = nv04_fifo_init,
98 .intr = nv04_fifo_intr,
99 .pause = nv04_fifo_pause,
100 .start = nv04_fifo_start,
101 .runl = &nv04_runl,
102 .engn = &nv04_engn,
103 .engn_sw = &nv04_engn,
104 .cgrp = {{ }, &nv04_cgrp },
105 .chan = {{ 0, 0, NV10_CHANNEL_DMA }, &nv10_chan },
106 };
107
108 int
nv10_fifo_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_fifo ** pfifo)109 nv10_fifo_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
110 struct nvkm_fifo **pfifo)
111 {
112 return nvkm_fifo_new_(&nv10_fifo, device, type, inst, pfifo);
113 }
114