1  // SPDX-License-Identifier: MIT
2  //
3  // Copyright 2024 Advanced Micro Devices, Inc.
4  
5  #ifndef __DML_TOP_SOC_PARAMETER_TYPES_H__
6  #define __DML_TOP_SOC_PARAMETER_TYPES_H__
7  
8  #include "dml2_external_lib_deps.h"
9  
10  #define DML_MAX_CLK_TABLE_SIZE 20
11  
12  struct dml2_soc_derate_values {
13  	unsigned int dram_derate_percent_pixel;
14  	unsigned int dram_derate_percent_vm;
15  	unsigned int dram_derate_percent_pixel_and_vm;
16  
17  	unsigned int fclk_derate_percent;
18  	unsigned int dcfclk_derate_percent;
19  };
20  
21  struct dml2_soc_derates {
22  	struct dml2_soc_derate_values system_active_urgent;
23  	struct dml2_soc_derate_values system_active_average;
24  	struct dml2_soc_derate_values dcn_mall_prefetch_urgent;
25  	struct dml2_soc_derate_values dcn_mall_prefetch_average;
26  	struct dml2_soc_derate_values system_idle_average;
27  };
28  
29  struct dml2_dcn32x_soc_qos_params {
30  	struct {
31  		unsigned int base_latency_us;
32  		unsigned int base_latency_pixel_vm_us;
33  		unsigned int base_latency_vm_us;
34  		unsigned int scaling_factor_fclk_us;
35  		unsigned int scaling_factor_mhz;
36  	} urgent_latency_us;
37  
38  	unsigned int loaded_round_trip_latency_fclk_cycles;
39  	unsigned int urgent_out_of_order_return_per_channel_pixel_only_bytes;
40  	unsigned int urgent_out_of_order_return_per_channel_pixel_and_vm_bytes;
41  	unsigned int urgent_out_of_order_return_per_channel_vm_only_bytes;
42  };
43  
44  struct dml2_dcn4_uclk_dpm_dependent_qos_params {
45  	unsigned long minimum_uclk_khz;
46  	unsigned int urgent_ramp_uclk_cycles;
47  	unsigned int trip_to_memory_uclk_cycles;
48  	unsigned int meta_trip_to_memory_uclk_cycles;
49  	unsigned int maximum_latency_when_urgent_uclk_cycles;
50  	unsigned int average_latency_when_urgent_uclk_cycles;
51  	unsigned int maximum_latency_when_non_urgent_uclk_cycles;
52  	unsigned int average_latency_when_non_urgent_uclk_cycles;
53  };
54  
55  struct dml2_dcn4x_soc_qos_params {
56  	unsigned int df_qos_response_time_fclk_cycles;
57  	unsigned int max_round_trip_to_furthest_cs_fclk_cycles;
58  	unsigned int mall_overhead_fclk_cycles;
59  	unsigned int meta_trip_adder_fclk_cycles;
60  	unsigned int average_transport_distance_fclk_cycles;
61  	double umc_urgent_ramp_latency_margin;
62  	double umc_max_latency_margin;
63  	double umc_average_latency_margin;
64  	double fabric_max_transport_latency_margin;
65  	double fabric_average_transport_latency_margin;
66  	struct dml2_dcn4_uclk_dpm_dependent_qos_params per_uclk_dpm_params[DML_MAX_CLK_TABLE_SIZE];
67  };
68  
69  enum dml2_qos_param_type {
70  	dml2_qos_param_type_dcn3,
71  	dml2_qos_param_type_dcn4x
72  };
73  
74  struct dml2_soc_qos_parameters {
75  	struct dml2_soc_derates derate_table;
76  	struct {
77  		unsigned int base_latency_us;
78  		unsigned int scaling_factor_us;
79  		unsigned int scaling_factor_mhz;
80  	} writeback;
81  
82  	union {
83  		struct dml2_dcn32x_soc_qos_params dcn32x;
84  		struct dml2_dcn4x_soc_qos_params dcn4x;
85  	} qos_params;
86  
87  	enum dml2_qos_param_type qos_type;
88  };
89  
90  struct dml2_soc_power_management_parameters {
91  	double dram_clk_change_blackout_us;
92  	double dram_clk_change_read_only_us;
93  	double dram_clk_change_write_only_us;
94  	double fclk_change_blackout_us;
95  	double g7_ppt_blackout_us;
96  	double stutter_enter_plus_exit_latency_us;
97  	double stutter_exit_latency_us;
98  	double z8_stutter_enter_plus_exit_latency_us;
99  	double z8_stutter_exit_latency_us;
100  	double z8_min_idle_time;
101  	double g6_temp_read_blackout_us[DML_MAX_CLK_TABLE_SIZE];
102  };
103  
104  struct dml2_clk_table {
105  	unsigned long clk_values_khz[DML_MAX_CLK_TABLE_SIZE];
106  	unsigned char num_clk_values;
107  };
108  
109  struct dml2_dram_params {
110  	unsigned int channel_width_bytes;
111  	unsigned int channel_count;
112  	unsigned int transactions_per_clock;
113  };
114  
115  struct dml2_soc_state_table {
116  	struct dml2_clk_table uclk;
117  	struct dml2_clk_table fclk;
118  	struct dml2_clk_table dcfclk;
119  	struct dml2_clk_table dispclk;
120  	struct dml2_clk_table dppclk;
121  	struct dml2_clk_table dtbclk;
122  	struct dml2_clk_table phyclk;
123  	struct dml2_clk_table socclk;
124  	struct dml2_clk_table dscclk;
125  	struct dml2_clk_table phyclk_d18;
126  	struct dml2_clk_table phyclk_d32;
127  
128  	struct dml2_dram_params dram_config;
129  };
130  
131  struct dml2_soc_vmin_clock_limits {
132  	unsigned long dispclk_khz;
133  };
134  
135  struct dml2_soc_bb {
136  	struct dml2_soc_state_table clk_table;
137  	struct dml2_soc_qos_parameters qos_parameters;
138  	struct dml2_soc_power_management_parameters power_management_parameters;
139  	struct dml2_soc_vmin_clock_limits vmin_limit;
140  
141  	unsigned int dprefclk_mhz;
142  	unsigned int xtalclk_mhz;
143  	unsigned int pcie_refclk_mhz;
144  	unsigned int dchub_refclk_mhz;
145  	unsigned int mall_allocated_for_dcn_mbytes;
146  	unsigned int max_outstanding_reqs;
147  	unsigned long fabric_datapath_to_dcn_data_return_bytes;
148  	unsigned long return_bus_width_bytes;
149  	unsigned long hostvm_min_page_size_kbytes;
150  	unsigned long gpuvm_min_page_size_kbytes;
151  	double phy_downspread_percent;
152  	double dcn_downspread_percent;
153  	double dispclk_dppclk_vco_speed_mhz;
154  	bool no_dfs;
155  	bool do_urgent_latency_adjustment;
156  	unsigned int mem_word_bytes;
157  	unsigned int num_dcc_mcaches;
158  	unsigned int mcache_size_bytes;
159  	unsigned int mcache_line_size_bytes;
160  	unsigned long max_fclk_for_uclk_dpm_khz;
161  };
162  
163  struct dml2_ip_capabilities {
164  	unsigned int pipe_count;
165  	unsigned int otg_count;
166  	unsigned int num_dsc;
167  	unsigned int max_num_dp2p0_streams;
168  	unsigned int max_num_hdmi_frl_outputs;
169  	unsigned int max_num_dp2p0_outputs;
170  	unsigned int rob_buffer_size_kbytes;
171  	unsigned int config_return_buffer_size_in_kbytes;
172  	unsigned int config_return_buffer_segment_size_in_kbytes;
173  	unsigned int meta_fifo_size_in_kentries;
174  	unsigned int compressed_buffer_segment_size_in_kbytes;
175  	unsigned int max_flip_time_us;
176  	unsigned int max_flip_time_lines;
177  	unsigned int hostvm_mode;
178  	unsigned int subvp_drr_scheduling_margin_us;
179  	unsigned int subvp_prefetch_end_to_mall_start_us;
180  	unsigned int subvp_fw_processing_delay;
181  	unsigned int max_vactive_det_fill_delay_us;
182  
183  	/* FAMS2 delays */
184  	struct {
185  		unsigned int max_allow_delay_us;
186  		unsigned int scheduling_delay_us;
187  		unsigned int vertical_interrupt_ack_delay_us; // delay to acknowledge vline int
188  		unsigned int allow_programming_delay_us; // time requires to program allow
189  		unsigned int min_allow_width_us;
190  		unsigned int subvp_df_throttle_delay_us;
191  		unsigned int subvp_programming_delay_us;
192  		unsigned int subvp_prefetch_to_mall_delay_us;
193  		unsigned int drr_programming_delay_us;
194  
195  		unsigned int lock_timeout_us;
196  		unsigned int recovery_timeout_us;
197  		unsigned int flip_programming_delay_us;
198  	} fams2;
199  };
200  
201  #endif
202