1 /* 2 * Copyright (c) 2021, The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for any 6 * purpose with or without fee is hereby granted, provided that the above 7 * copyright notice and this permission notice appear in all copies. 8 * 9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 16 */ 17 18 #ifndef _HAL_BE_API_MON_H_ 19 #define _HAL_BE_API_MON_H_ 20 21 #include "hal_be_hw_headers.h" 22 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 23 defined(WLAN_PKT_CAPTURE_RX_2_0) 24 #include <mon_ingress_ring.h> 25 #include <mon_destination_ring.h> 26 #include <mon_drop.h> 27 #endif 28 #include <hal_be_hw_headers.h> 29 #include "hal_api_mon.h" 30 #include <hal_generic_api.h> 31 #include <hal_generic_api.h> 32 #include <hal_api_mon.h> 33 34 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 35 defined(WLAN_PKT_CAPTURE_RX_2_0) || \ 36 defined(QCA_SINGLE_WIFI_3_0) 37 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET 0x00000000 38 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 0 39 #define HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 0xffffffff 40 41 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET 0x00000004 42 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 0 43 #define HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 0x000000ff 44 45 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET 0x00000008 46 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB 0 47 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MSB 31 48 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK 0xffffffff 49 50 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET 0x0000000c 51 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB 0 52 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MSB 31 53 #define HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK 0xffffffff 54 55 #define HAL_MON_PADDR_LO_SET(buff_addr_info, paddr_lo) \ 56 ((*(((unsigned int *) buff_addr_info) + \ 57 (HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_OFFSET >> 2))) = \ 58 ((paddr_lo) << HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB) & \ 59 HAL_MON_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK) 60 61 #define HAL_MON_PADDR_HI_SET(buff_addr_info, paddr_hi) \ 62 ((*(((unsigned int *) buff_addr_info) + \ 63 (HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_OFFSET >> 2))) = \ 64 ((paddr_hi) << HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB) & \ 65 HAL_MON_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK) 66 67 #define HAL_MON_VADDR_LO_SET(buff_addr_info, vaddr_lo) \ 68 ((*(((unsigned int *) buff_addr_info) + \ 69 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_OFFSET >> 2))) = \ 70 ((vaddr_lo) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_LSB) & \ 71 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_31_0_MASK) 72 73 #define HAL_MON_VADDR_HI_SET(buff_addr_info, vaddr_hi) \ 74 ((*(((unsigned int *) buff_addr_info) + \ 75 (HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_OFFSET >> 2))) = \ 76 ((vaddr_hi) << HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_LSB) & \ 77 HAL_MON_MON_INGRESS_RING_BUFFER_VIRT_ADDR_63_32_MASK) 78 #endif 79 80 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 81 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_OFFSET 82 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 83 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_MASK 84 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 85 RXPCU_PPDU_END_INFO_RX_PPDU_DURATION_LSB 86 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 87 PHYRX_HT_SIG_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 88 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 89 PHYRX_L_SIG_B_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 90 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 91 PHYRX_L_SIG_A_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 92 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 93 PHYRX_VHT_SIG_A_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 94 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 95 PHYRX_HE_SIG_A_SU_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 96 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 97 PHYRX_HE_SIG_A_MU_DL_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 98 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 99 PHYRX_HE_SIG_B1_MU_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 100 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 101 PHYRX_HE_SIG_B2_MU_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 102 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 103 PHYRX_HE_SIG_B2_OFDMA_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 104 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 105 PHYRX_RSSI_LEGACY_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 106 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 107 PHYRX_RSSI_LEGACY_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 108 109 110 #define RX_MON_MPDU_START_WMASK 0x07F0 111 #define RX_MON_MPDU_END_WMASK 0x7 112 #define RX_MON_MPDU_START_WMASK_V2 0x007F0 113 #define RX_MON_MPDU_END_WMASK_V2 0xFF 114 #define RX_MON_MSDU_END_WMASK 0x0AE1 115 #define RX_MON_PPDU_END_USR_STATS_WMASK 0xB7E 116 117 #define MAX_USR_INFO_STR_CNT 4 118 119 #ifdef CONFIG_MON_WORD_BASED_TLV 120 #ifndef BIG_ENDIAN_HOST 121 struct rx_mpdu_start_mon_data { 122 uint32_t peer_meta_data : 32; 123 uint32_t rxpcu_mpdu_filter_in_category : 2, 124 sw_frame_group_id : 7, 125 ndp_frame : 1, 126 phy_err : 1, 127 phy_err_during_mpdu_header : 1, 128 protocol_version_err : 1, 129 ast_based_lookup_valid : 1, 130 reserved_0a : 2, 131 phy_ppdu_id : 16; 132 uint32_t ast_index : 16, 133 sw_peer_id : 16; 134 uint32_t mpdu_frame_control_valid : 1, 135 mpdu_duration_valid : 1, 136 mac_addr_ad1_valid : 1, 137 mac_addr_ad2_valid : 1, 138 mac_addr_ad3_valid : 1, 139 mac_addr_ad4_valid : 1, 140 mpdu_sequence_control_valid : 1, 141 mpdu_qos_control_valid : 1, 142 mpdu_ht_control_valid : 1, 143 frame_encryption_info_valid : 1, 144 mpdu_fragment_number : 4, 145 more_fragment_flag : 1, 146 reserved_11a : 1, 147 fr_ds : 1, 148 to_ds : 1, 149 encrypted : 1, 150 mpdu_retry : 1, 151 mpdu_sequence_number : 12; 152 uint32_t key_id_octet : 8, 153 new_peer_entry : 1, 154 decrypt_needed : 1, 155 decap_type : 2, 156 rx_insert_vlan_c_tag_padding : 1, 157 rx_insert_vlan_s_tag_padding : 1, 158 strip_vlan_c_tag_decap : 1, 159 strip_vlan_s_tag_decap : 1, 160 pre_delim_count : 12, 161 ampdu_flag : 1, 162 bar_frame : 1, 163 raw_mpdu : 1, 164 reserved_12 : 1; 165 uint32_t mpdu_length : 14, 166 first_mpdu : 1, 167 mcast_bcast : 1, 168 ast_index_not_found : 1, 169 ast_index_timeout : 1, 170 power_mgmt : 1, 171 non_qos : 1, 172 null_data : 1, 173 mgmt_type : 1, 174 ctrl_type : 1, 175 more_data : 1, 176 eosp : 1, 177 fragment_flag : 1, 178 order : 1, 179 u_apsd_trigger : 1, 180 encrypt_required : 1, 181 directed : 1, 182 amsdu_present : 1, 183 reserved_13 : 1; 184 uint32_t mpdu_frame_control_field : 16, 185 mpdu_duration_field : 16; 186 uint32_t mac_addr_ad1_31_0 : 32; 187 uint32_t mac_addr_ad1_47_32 : 16, 188 mac_addr_ad2_15_0 : 16; 189 uint32_t mac_addr_ad2_47_16 : 32; 190 uint32_t mac_addr_ad3_31_0 : 32; 191 uint32_t mac_addr_ad3_47_32 : 16, 192 mpdu_sequence_control_field : 16; 193 uint32_t mac_addr_ad4_31_0 : 32; 194 uint32_t mac_addr_ad4_47_32 : 16, 195 mpdu_qos_control_field : 16; 196 }; 197 198 struct rx_msdu_end_mon_data { 199 uint32_t rxpcu_mpdu_filter_in_category : 2, 200 sw_frame_group_id : 7, 201 reserved_0 : 7, 202 phy_ppdu_id : 16; 203 uint32_t ip_hdr_chksum : 16, 204 reported_mpdu_length : 14, 205 reserved_1a : 2; 206 uint32_t sa_sw_peer_id : 16, 207 sa_idx_timeout : 1, 208 da_idx_timeout : 1, 209 to_ds : 1, 210 tid : 4, 211 sa_is_valid : 1, 212 da_is_valid : 1, 213 da_is_mcbc : 1, 214 l3_header_padding : 2, 215 first_msdu : 1, 216 last_msdu : 1, 217 fr_ds : 1, 218 ip_chksum_fail_copy : 1; 219 uint32_t sa_idx : 16, 220 da_idx_or_sw_peer_id : 16; 221 uint32_t msdu_drop : 1, 222 reo_destination_indication : 5, 223 flow_idx : 20, 224 use_ppe : 1, 225 mesh_sta : 2, 226 vlan_ctag_stripped : 1, 227 vlan_stag_stripped : 1, 228 fragment_flag : 1; 229 uint32_t fse_metadata : 32; 230 uint32_t cce_metadata : 16, 231 tcp_udp_chksum : 16; 232 uint32_t aggregation_count : 8, 233 flow_aggregation_continuation : 1, 234 fisa_timeout : 1, 235 tcp_udp_chksum_fail_copy : 1, 236 msdu_limit_error : 1, 237 flow_idx_timeout : 1, 238 flow_idx_invalid : 1, 239 cce_match : 1, 240 amsdu_parser_error : 1, 241 cumulative_ip_length : 16; 242 uint32_t msdu_length : 14, 243 stbc : 1, 244 ipsec_esp : 1, 245 l3_offset : 7, 246 ipsec_ah : 1, 247 l4_offset : 8; 248 uint32_t msdu_number : 8, 249 decap_format : 2, 250 ipv4_proto : 1, 251 ipv6_proto : 1, 252 tcp_proto : 1, 253 udp_proto : 1, 254 ip_frag : 1, 255 tcp_only_ack : 1, 256 da_is_bcast_mcast : 1, 257 toeplitz_hash_sel : 2, 258 ip_fixed_header_valid : 1, 259 ip_extn_header_valid : 1, 260 tcp_udp_header_valid : 1, 261 mesh_control_present : 1, 262 ldpc : 1, 263 ip4_protocol_ip6_next_header : 8; 264 uint32_t user_rssi : 8, 265 pkt_type : 4, 266 sgi : 2, 267 rate_mcs : 4, 268 receive_bandwidth : 3, 269 reception_type : 3, 270 mimo_ss_bitmap : 7, 271 msdu_done_copy : 1; 272 uint32_t flow_id_toeplitz : 32; 273 }; 274 275 struct rx_ppdu_end_user_mon_data { 276 uint32_t sw_peer_id : 16, 277 mpdu_cnt_fcs_err : 11, 278 sw2rxdma0_buf_source_used : 1, 279 fw2rxdma_pmac0_buf_source_used : 1, 280 sw2rxdma1_buf_source_used : 1, 281 sw2rxdma_exception_buf_source_used: 1, 282 fw2rxdma_pmac1_buf_source_used : 1; 283 uint32_t mpdu_cnt_fcs_ok : 11, 284 frame_control_info_valid : 1, 285 qos_control_info_valid : 1, 286 ht_control_info_valid : 1, 287 data_sequence_control_info_valid : 1, 288 ht_control_info_null_valid : 1, 289 rxdma2fw_pmac1_ring_used : 1, 290 rxdma2reo_ring_used : 1, 291 rxdma2fw_pmac0_ring_used : 1, 292 rxdma2sw_ring_used : 1, 293 rxdma_release_ring_used : 1, 294 ht_control_field_pkt_type : 4, 295 rxdma2reo_remote0_ring_used : 1, 296 rxdma2reo_remote1_ring_used : 1, 297 reserved_3b : 5; 298 uint32_t ast_index : 16, 299 frame_control_field : 16; 300 uint32_t first_data_seq_ctrl : 16, 301 qos_control_field : 16; 302 uint32_t ht_control_field : 32; 303 uint32_t fcs_ok_bitmap_31_0 : 32; 304 uint32_t fcs_ok_bitmap_63_32 : 32; 305 uint32_t udp_msdu_count : 16, 306 tcp_msdu_count : 16; 307 uint32_t other_msdu_count : 16, 308 tcp_ack_msdu_count : 16; 309 uint32_t sw_response_reference_ptr : 32; 310 uint32_t received_qos_data_tid_bitmap : 16, 311 received_qos_data_tid_eosp_bitmap : 16; 312 uint32_t qosctrl_15_8_tid0 : 8, 313 qosctrl_15_8_tid1 : 8, 314 qosctrl_15_8_tid2 : 8, 315 qosctrl_15_8_tid3 : 8; 316 uint32_t qosctrl_15_8_tid12 : 8, 317 qosctrl_15_8_tid13 : 8, 318 qosctrl_15_8_tid14 : 8, 319 qosctrl_15_8_tid15 : 8; 320 uint32_t mpdu_ok_byte_count : 25, 321 ampdu_delim_ok_count_6_0 : 7; 322 uint32_t ampdu_delim_err_count : 25, 323 ampdu_delim_ok_count_13_7 : 7; 324 uint32_t mpdu_err_byte_count : 25, 325 ampdu_delim_ok_count_20_14 : 7; 326 uint32_t sw_response_reference_ptr_ext : 32; 327 uint32_t corrupted_due_to_fifo_delay : 1, 328 frame_control_info_null_valid : 1, 329 frame_control_field_null : 16, 330 retried_mpdu_count : 11, 331 reserved_23a : 3; 332 }; 333 #else 334 struct rx_mpdu_start_mon_data { 335 uint32_t peer_meta_data : 32; 336 uint32_t phy_ppdu_id : 16, 337 reserved_0a : 2, 338 ast_based_lookup_valid : 1, 339 protocol_version_err : 1, 340 phy_err_during_mpdu_header : 1, 341 phy_err : 1, 342 ndp_frame : 1, 343 sw_frame_group_id : 7, 344 rxpcu_mpdu_filter_in_category : 2; 345 uint32_t sw_peer_id : 16, 346 ast_index : 16; 347 uint32_t mpdu_sequence_number : 12, 348 mpdu_retry : 1, 349 encrypted : 1, 350 to_ds : 1, 351 fr_ds : 1, 352 reserved_11a : 1, 353 more_fragment_flag : 1, 354 mpdu_fragment_number : 4, 355 frame_encryption_info_valid : 1, 356 mpdu_ht_control_valid : 1, 357 mpdu_qos_control_valid : 1, 358 mpdu_sequence_control_valid : 1, 359 mac_addr_ad4_valid : 1, 360 mac_addr_ad3_valid : 1, 361 mac_addr_ad2_valid : 1, 362 mac_addr_ad1_valid : 1, 363 mpdu_duration_valid : 1, 364 mpdu_frame_control_valid : 1; 365 uint32_t reserved_12 : 1, 366 raw_mpdu : 1, 367 bar_frame : 1, 368 ampdu_flag : 1, 369 pre_delim_count : 12, 370 strip_vlan_s_tag_decap : 1, 371 strip_vlan_c_tag_decap : 1, 372 rx_insert_vlan_s_tag_padding : 1, 373 rx_insert_vlan_c_tag_padding : 1, 374 decap_type : 2, 375 decrypt_needed : 1, 376 new_peer_entry : 1, 377 key_id_octet : 8; 378 uint32_t reserved_13 : 1, 379 amsdu_present : 1, 380 directed : 1, 381 encrypt_required : 1, 382 u_apsd_trigger : 1, 383 order : 1, 384 fragment_flag : 1, 385 eosp : 1, 386 more_data : 1, 387 ctrl_type : 1, 388 mgmt_type : 1, 389 null_data : 1, 390 non_qos : 1, 391 power_mgmt : 1, 392 ast_index_timeout : 1, 393 ast_index_not_found : 1, 394 mcast_bcast : 1, 395 first_mpdu : 1, 396 mpdu_length : 14; 397 uint32_t mpdu_duration_field : 16, 398 mpdu_frame_control_field : 16; 399 uint32_t mac_addr_ad1_31_0 : 32; 400 uint32_t mac_addr_ad2_15_0 : 16, 401 mac_addr_ad1_47_32 : 16; 402 uint32_t mac_addr_ad2_47_16 : 32; 403 uint32_t mac_addr_ad3_31_0 : 32; 404 uint32_t mpdu_sequence_control_field : 16, 405 mac_addr_ad3_47_32 : 16; 406 uint32_t mac_addr_ad4_31_0 : 32; 407 uint32_t mpdu_qos_control_field : 16, 408 mac_addr_ad4_47_32 : 16; 409 }; 410 411 struct rx_msdu_end_mon_data { 412 uint32_t phy_ppdu_id : 16, 413 reserved_0 : 7, 414 sw_frame_group_id : 7, 415 rxpcu_mpdu_filter_in_category : 2; 416 uint32_t reserved_1a : 2, 417 reported_mpdu_length : 14, 418 ip_hdr_chksum : 16; 419 uint32_t ip_chksum_fail_copy : 1, 420 fr_ds : 1, 421 last_msdu : 1, 422 first_msdu : 1, 423 l3_header_padding : 2, 424 da_is_mcbc : 1, 425 da_is_valid : 1, 426 sa_is_valid : 1, 427 tid : 4, 428 to_ds : 1, 429 da_idx_timeout : 1, 430 sa_idx_timeout : 1, 431 sa_sw_peer_id : 16; 432 uint32_t da_idx_or_sw_peer_id : 16, 433 sa_idx : 16; 434 uint32_t fragment_flag : 1, 435 vlan_stag_stripped : 1, 436 vlan_ctag_stripped : 1, 437 mesh_sta : 2, 438 use_ppe : 1, 439 flow_idx : 20, 440 reo_destination_indication : 5, 441 msdu_drop : 1; 442 uint32_t fse_metadata : 32; 443 uint32_t cce_metadata : 16, 444 tcp_udp_chksum : 16; 445 uint32_t cumulative_ip_length : 16, 446 amsdu_parser_error : 1, 447 cce_match : 1, 448 flow_idx_invalid : 1, 449 flow_idx_timeout : 1, 450 msdu_limit_error : 1, 451 tcp_udp_chksum_fail_copy : 1, 452 fisa_timeout : 1, 453 flow_aggregation_continuation : 1, 454 aggregation_count : 8; 455 uint32_t l4_offset : 8, 456 ipsec_ah : 1, 457 l3_offset : 7, 458 ipsec_esp : 1, 459 stbc : 1, 460 msdu_length : 14; 461 uint32_t ip4_protocol_ip6_next_header : 8, 462 ldpc : 1, 463 mesh_control_present : 1, 464 tcp_udp_header_valid : 1, 465 ip_extn_header_valid : 1, 466 ip_fixed_header_valid : 1, 467 toeplitz_hash_sel : 2, 468 da_is_bcast_mcast : 1, 469 tcp_only_ack : 1, 470 ip_frag : 1, 471 udp_proto : 1, 472 tcp_proto : 1, 473 ipv6_proto : 1, 474 ipv4_proto : 1, 475 decap_format : 2, 476 msdu_number : 8; 477 uint32_t msdu_done_copy : 1, 478 mimo_ss_bitmap : 7, 479 reception_type : 3, 480 receive_bandwidth : 3, 481 rate_mcs : 4, 482 sgi : 2, 483 pkt_type : 4, 484 user_rssi : 8; 485 uint32_t flow_id_toeplitz : 32; 486 }; 487 488 struct rx_ppdu_end_user_mon_data { 489 uint32_t fw2rxdma_pmac1_buf_source_used : 1, 490 sw2rxdma_exception_buf_source_used: 1, 491 sw2rxdma1_buf_source_used : 1, 492 fw2rxdma_pmac0_buf_source_used : 1, 493 sw2rxdma0_buf_source_used : 1, 494 mpdu_cnt_fcs_err : 11, 495 sw_peer_id : 16; 496 uint32_t reserved_3b : 5, 497 rxdma2reo_remote1_ring_used : 1, 498 rxdma2reo_remote0_ring_used : 1, 499 ht_control_field_pkt_type : 4, 500 rxdma_release_ring_used : 1, 501 rxdma2sw_ring_used : 1, 502 rxdma2fw_pmac0_ring_used : 1, 503 rxdma2reo_ring_used : 1, 504 rxdma2fw_pmac1_ring_used : 1, 505 ht_control_info_null_valid : 1, 506 data_sequence_control_info_valid : 1, 507 ht_control_info_valid : 1, 508 qos_control_info_valid : 1, 509 frame_control_info_valid : 1, 510 mpdu_cnt_fcs_ok : 11; 511 uint32_t frame_control_field : 16, 512 ast_index : 16; 513 uint32_t qos_control_field : 16, 514 first_data_seq_ctrl : 16; 515 uint32_t ht_control_field : 32; 516 uint32_t fcs_ok_bitmap_31_0 : 32; 517 uint32_t fcs_ok_bitmap_63_32 : 32; 518 uint32_t tcp_msdu_count : 16, 519 udp_msdu_count : 16; 520 uint32_t tcp_ack_msdu_count : 16, 521 other_msdu_count : 16; 522 uint32_t sw_response_reference_ptr : 32; 523 uint32_t received_qos_data_tid_eosp_bitmap : 16, 524 received_qos_data_tid_bitmap : 16; 525 uint32_t qosctrl_15_8_tid3 : 8, 526 qosctrl_15_8_tid2 : 8, 527 qosctrl_15_8_tid1 : 8, 528 qosctrl_15_8_tid0 : 8; 529 uint32_t qosctrl_15_8_tid15 : 8, 530 qosctrl_15_8_tid14 : 8, 531 qosctrl_15_8_tid13 : 8, 532 qosctrl_15_8_tid12 : 8; 533 uint32_t ampdu_delim_ok_count_6_0 : 7, 534 mpdu_ok_byte_count : 25; 535 uint32_t ampdu_delim_ok_count_13_7 : 7, 536 ampdu_delim_err_count : 25; 537 uint32_t ampdu_delim_ok_count_20_14 : 7, 538 mpdu_err_byte_count : 25; 539 uint32_t sw_response_reference_ptr_ext : 32; 540 uint32_t reserved_23a : 3, 541 retried_mpdu_count : 11, 542 frame_control_field_null : 16, 543 frame_control_info_null_valid : 1, 544 corrupted_due_to_fifo_delay : 1; 545 }; 546 #endif 547 548 struct rx_mpdu_start_mon_data_t { 549 struct rx_mpdu_start_mon_data rx_mpdu_info_details; 550 }; 551 552 struct rx_msdu_end_mon_data_t { 553 struct rx_msdu_end_mon_data rx_mpdu_info_details; 554 }; 555 /* TLV struct for word based Tlv */ 556 typedef struct rx_mpdu_start_mon_data_t hal_rx_mon_mpdu_start_t; 557 typedef struct rx_msdu_end_mon_data hal_rx_mon_msdu_end_t; 558 typedef struct rx_ppdu_end_user_mon_data hal_rx_mon_ppdu_end_user_t; 559 560 #else 561 562 typedef struct rx_mpdu_start hal_rx_mon_mpdu_start_t; 563 typedef struct rx_msdu_end hal_rx_mon_msdu_end_t; 564 typedef struct rx_ppdu_end_user_stats hal_rx_mon_ppdu_end_user_t; 565 #endif 566 567 /* 568 * struct mon_destination_drop - monitor drop descriptor 569 * 570 * @ppdu_drop_cnt: PPDU drop count 571 * @mpdu_drop_cnt: MPDU drop count 572 * @tlv_drop_cnt: TLV drop count 573 * @end_of_ppdu_seen: end of ppdu seen 574 * @reserved_0a: rsvd 575 * @reserved_1a: rsvd 576 * @ppdu_id: PPDU ID 577 * @reserved_3a: rsvd 578 * @initiator: initiator ppdu 579 * @empty_descriptor: empty descriptor 580 * @ring_id: ring id 581 * @looping_count: looping count 582 */ 583 struct mon_destination_drop { 584 uint32_t ppdu_drop_cnt : 10, 585 mpdu_drop_cnt : 10, 586 tlv_drop_cnt : 10, 587 end_of_ppdu_seen : 1, 588 reserved_0a : 1; 589 uint32_t reserved_1a : 32; 590 uint32_t ppdu_id : 32; 591 uint32_t reserved_3a : 18, 592 initiator : 1, 593 empty_descriptor : 1, 594 ring_id : 8, 595 looping_count : 4; 596 }; 597 598 #define HAL_MON_BUFFER_ADDR_31_0_GET(buff_addr_info) \ 599 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 600 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET)), \ 601 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK, \ 602 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB)) 603 604 #define HAL_MON_BUFFER_ADDR_39_32_GET(buff_addr_info) \ 605 (_HAL_MS((*_OFFSET_TO_WORD_PTR(buff_addr_info, \ 606 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET)), \ 607 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK, \ 608 HAL_BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB)) 609 610 /** 611 * struct hal_rx_status_buffer_done - status buffer done tlv 612 * placeholder structure 613 * 614 * @ppdu_start_offset: ppdu start 615 * @first_ppdu_start_user_info_offset: 616 * @mult_ppdu_start_user_info: 617 * @end_offset: 618 * @ppdu_end_detected: 619 * @flush_detected: 620 * @rsvd: 621 */ 622 struct hal_rx_status_buffer_done { 623 uint32_t ppdu_start_offset : 3, 624 first_ppdu_start_user_info_offset : 6, 625 mult_ppdu_start_user_info : 1, 626 end_offset : 13, 627 ppdu_end_detected : 1, 628 flush_detected : 1, 629 rsvd : 7; 630 }; 631 632 /** 633 * enum hal_mon_status_end_reason - ppdu status buffer end reason 634 * 635 * @HAL_MON_STATUS_BUFFER_FULL: status buffer full 636 * @HAL_MON_FLUSH_DETECTED: flush detected 637 * @HAL_MON_END_OF_PPDU: end of ppdu detected 638 * @HAL_MON_PPDU_TRUNCATED: truncated ppdu status 639 */ 640 enum hal_mon_status_end_reason { 641 HAL_MON_STATUS_BUFFER_FULL, 642 HAL_MON_FLUSH_DETECTED, 643 HAL_MON_END_OF_PPDU, 644 HAL_MON_PPDU_TRUNCATED, 645 }; 646 647 /** 648 * struct hal_mon_desc - HAL Monitor descriptor 649 * 650 * @buf_addr: virtual buffer address 651 * @ppdu_id: ppdu id 652 * - TxMon fills scheduler id 653 * - RxMON fills phy_ppdu_id 654 * @end_offset: offset (units in 4 bytes) where status buffer ended 655 * i.e offset of TLV + last TLV size 656 * @reserved_3a: reserved bits 657 * @end_reason: ppdu end reason 658 * 0 - status buffer is full 659 * 1 - flush detected 660 * 2 - TX_FES_STATUS_END or RX_PPDU_END 661 * 3 - PPDU truncated due to system error 662 * @initiator: 1 - descriptor belongs to TX FES 663 * 0 - descriptor belongs to TX RESPONSE 664 * @empty_descriptor: 0 - this descriptor is written on a flush 665 * or end of ppdu or end of status buffer 666 * 1 - descriptor provided to indicate drop 667 * @ring_id: ring id for debugging 668 * @looping_count: count to indicate number of times producer 669 * of entries has looped around the ring 670 * @flush_detected: if flush detected 671 * @end_of_ppdu_dropped: if end_of_ppdu is dropped 672 * @ppdu_drop_count: PPDU drop count 673 * @mpdu_drop_count: MPDU drop count 674 * @tlv_drop_count: TLV drop count 675 */ 676 struct hal_mon_desc { 677 uint64_t buf_addr; 678 uint32_t ppdu_id; 679 uint32_t end_offset:12, 680 reserved_3a:4, 681 end_reason:2, 682 initiator:1, 683 empty_descriptor:1, 684 ring_id:8, 685 looping_count:4; 686 uint16_t flush_detected:1, 687 end_of_ppdu_dropped:1; 688 uint32_t ppdu_drop_count; 689 uint32_t mpdu_drop_count; 690 uint32_t tlv_drop_count; 691 }; 692 693 typedef struct hal_mon_desc *hal_mon_desc_t; 694 695 /** 696 * struct hal_mon_buf_addr_status - HAL buffer address tlv get status 697 * 698 * @buffer_virt_addr_31_0: Lower 32 bits of virtual address of status buffer 699 * @buffer_virt_addr_63_32: Upper 32 bits of virtual address of status buffer 700 * @dma_length: DMA length 701 * @reserved_2a: reserved bits 702 * @msdu_continuation: is msdu size more than fragment size 703 * @truncated: is msdu got truncated 704 * @reserved_2b: reserved bits 705 * @tlv64_padding: tlv paddding 706 */ 707 struct hal_mon_buf_addr_status { 708 uint32_t buffer_virt_addr_31_0; 709 uint32_t buffer_virt_addr_63_32; 710 uint32_t dma_length:12, 711 reserved_2a:4, 712 msdu_continuation:1, 713 truncated:1, 714 reserved_2b:14; 715 uint32_t tlv64_padding; 716 }; 717 718 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 719 defined(WLAN_PKT_CAPTURE_RX_2_0) 720 721 /** 722 * hal_be_get_mon_dest_status() - Get monitor descriptor status 723 * @hal_soc: HAL Soc handle 724 * @hw_desc: HAL monitor descriptor 725 * @status: pointer to write descriptor status 726 * 727 * Return: none 728 */ 729 static inline void 730 hal_be_get_mon_dest_status(hal_soc_handle_t hal_soc, 731 void *hw_desc, 732 struct hal_mon_desc *status) 733 { 734 struct mon_destination_ring *desc = hw_desc; 735 736 status->empty_descriptor = desc->empty_descriptor; 737 if (status->empty_descriptor) { 738 struct mon_destination_drop *drop_desc = hw_desc; 739 740 status->buf_addr = 0; 741 status->ppdu_drop_count = drop_desc->ppdu_drop_cnt; 742 status->mpdu_drop_count = drop_desc->mpdu_drop_cnt; 743 status->tlv_drop_count = drop_desc->tlv_drop_cnt; 744 status->end_of_ppdu_dropped = drop_desc->end_of_ppdu_seen; 745 } else { 746 status->buf_addr = HAL_RX_GET(desc, MON_DESTINATION_RING_STAT,BUF_VIRT_ADDR_31_0) | 747 (((uint64_t)HAL_RX_GET(desc, 748 MON_DESTINATION_RING_STAT, 749 BUF_VIRT_ADDR_63_32)) << 32); 750 status->end_reason = desc->end_reason; 751 status->end_offset = desc->end_offset; 752 } 753 status->ppdu_id = desc->ppdu_id; 754 status->initiator = desc->initiator; 755 status->looping_count = desc->looping_count; 756 } 757 #endif 758 759 #if defined(RX_PPDU_END_USER_STATS_OFDMA_INFO_VALID_OFFSET) && \ 760 defined(RX_PPDU_END_USER_STATS_SW_RESPONSE_REFERENCE_PTR_EXT_OFFSET) 761 762 static inline void 763 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 764 struct mon_rx_user_status *mon_rx_user_status) 765 { 766 mon_rx_user_status->mu_ul_user_v0_word0 = 767 rx_ppdu_end_user->sw_response_reference_ptr; 768 769 mon_rx_user_status->mu_ul_user_v0_word1 = 770 rx_ppdu_end_user->sw_response_reference_ptr_ext; 771 } 772 #else 773 static inline void 774 hal_rx_handle_mu_ul_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 775 struct mon_rx_user_status *mon_rx_user_status) 776 { 777 } 778 #endif 779 780 static inline void 781 hal_rx_populate_byte_count(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 782 void *ppduinfo, 783 struct mon_rx_user_status *mon_rx_user_status) 784 { 785 mon_rx_user_status->mpdu_ok_byte_count = 786 rx_ppdu_end_user->mpdu_ok_byte_count; 787 mon_rx_user_status->mpdu_err_byte_count = 788 rx_ppdu_end_user->mpdu_err_byte_count; 789 } 790 791 static inline void 792 hal_rx_populate_mu_user_info(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 793 void *ppduinfo, uint32_t user_id, 794 struct mon_rx_user_status *mon_rx_user_status) 795 { 796 struct mon_rx_info *mon_rx_info; 797 struct mon_rx_user_info *mon_rx_user_info; 798 struct hal_rx_ppdu_info *ppdu_info = 799 (struct hal_rx_ppdu_info *)ppduinfo; 800 801 mon_rx_info = &ppdu_info->rx_info; 802 mon_rx_user_info = &ppdu_info->rx_user_info[user_id]; 803 mon_rx_user_info->qos_control_info_valid = 804 mon_rx_info->qos_control_info_valid; 805 mon_rx_user_info->qos_control = mon_rx_info->qos_control; 806 807 mon_rx_user_status->ast_index = ppdu_info->rx_status.ast_index; 808 mon_rx_user_status->tid = ppdu_info->rx_status.tid; 809 mon_rx_user_status->tcp_msdu_count = 810 ppdu_info->rx_status.tcp_msdu_count; 811 mon_rx_user_status->udp_msdu_count = 812 ppdu_info->rx_status.udp_msdu_count; 813 mon_rx_user_status->other_msdu_count = 814 ppdu_info->rx_status.other_msdu_count; 815 mon_rx_user_status->frame_control = ppdu_info->rx_status.frame_control; 816 mon_rx_user_status->frame_control_info_valid = 817 ppdu_info->rx_status.frame_control_info_valid; 818 mon_rx_user_status->data_sequence_control_info_valid = 819 ppdu_info->rx_status.data_sequence_control_info_valid; 820 mon_rx_user_status->first_data_seq_ctrl = 821 ppdu_info->rx_status.first_data_seq_ctrl; 822 mon_rx_user_status->preamble_type = ppdu_info->rx_status.preamble_type; 823 mon_rx_user_status->ht_flags = ppdu_info->rx_status.ht_flags; 824 mon_rx_user_status->rtap_flags = ppdu_info->rx_status.rtap_flags; 825 mon_rx_user_status->vht_flags = ppdu_info->rx_status.vht_flags; 826 if (mon_rx_user_status->vht_flags) { 827 mon_rx_user_status->vht_flag_values2 = 828 ppdu_info->rx_status.vht_flag_values2; 829 qdf_mem_copy(mon_rx_user_status->vht_flag_values3, 830 ppdu_info->rx_status.vht_flag_values3, 831 sizeof(mon_rx_user_status->vht_flag_values3)); 832 mon_rx_user_status->vht_flag_values4 = 833 ppdu_info->rx_status.vht_flag_values4; 834 mon_rx_user_status->vht_flag_values5 = 835 ppdu_info->rx_status.vht_flag_values5; 836 mon_rx_user_status->vht_flag_values6 = 837 ppdu_info->rx_status.vht_flag_values6; 838 } 839 mon_rx_user_status->he_flags = ppdu_info->rx_status.he_flags; 840 mon_rx_user_status->rs_flags = ppdu_info->rx_status.rs_flags; 841 842 mon_rx_user_status->mpdu_cnt_fcs_ok = 843 ppdu_info->com_info.mpdu_cnt_fcs_ok; 844 mon_rx_user_status->mpdu_cnt_fcs_err = 845 ppdu_info->com_info.mpdu_cnt_fcs_err; 846 qdf_mem_copy(&mon_rx_user_status->mpdu_fcs_ok_bitmap, 847 &ppdu_info->com_info.mpdu_fcs_ok_bitmap, 848 HAL_RX_NUM_WORDS_PER_PPDU_BITMAP * 849 sizeof(ppdu_info->com_info.mpdu_fcs_ok_bitmap[0])); 850 mon_rx_user_status->retry_mpdu = 851 ppdu_info->rx_status.mpdu_retry_cnt; 852 hal_rx_populate_byte_count(rx_ppdu_end_user, ppdu_info, 853 mon_rx_user_status); 854 } 855 856 #define HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(chain, \ 857 ppdu_info, rssi_info_tlv) \ 858 { \ 859 ppdu_info->rx_status.rssi_chain[chain][0] = \ 860 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 861 RSSI_PRI20_CHAIN##chain); \ 862 ppdu_info->rx_status.rssi_chain[chain][1] = \ 863 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 864 RSSI_EXT20_CHAIN##chain); \ 865 ppdu_info->rx_status.rssi_chain[chain][2] = \ 866 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 867 RSSI_EXT40_LOW20_CHAIN##chain); \ 868 ppdu_info->rx_status.rssi_chain[chain][3] = \ 869 HAL_RX_GET(rssi_info_tlv, RECEIVE_RSSI_INFO,\ 870 RSSI_EXT40_HIGH20_CHAIN##chain); \ 871 } \ 872 873 #define HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) \ 874 {HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(0, ppdu_info, rssi_info_tlv) \ 875 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(1, ppdu_info, rssi_info_tlv) \ 876 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(2, ppdu_info, rssi_info_tlv) \ 877 HAL_RX_UPDATE_RSSI_PER_CHAIN_BW(3, ppdu_info, rssi_info_tlv) \ 878 } \ 879 880 static inline uint32_t 881 hal_rx_update_rssi_chain(struct hal_rx_ppdu_info *ppdu_info, 882 uint8_t *rssi_info_tlv) 883 { 884 HAL_RX_PPDU_UPDATE_RSSI(ppdu_info, rssi_info_tlv) 885 return 0; 886 } 887 888 #ifdef WLAN_TX_PKT_CAPTURE_ENH 889 static inline void 890 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 891 struct hal_rx_ppdu_info *ppdu_info) 892 { 893 ppdu_info->rx_info.qos_control_info_valid = 894 rx_ppdu_end_user->qos_control_info_valid; 895 896 if (ppdu_info->rx_info.qos_control_info_valid) 897 ppdu_info->rx_info.qos_control = 898 rx_ppdu_end_user->qos_control_field; 899 } 900 901 static inline void 902 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 903 struct hal_rx_ppdu_info *ppdu_info) 904 { 905 if ((ppdu_info->sw_frame_group_id 906 == HAL_MPDU_SW_FRAME_GROUP_MGMT_PROBE_REQ) || 907 (ppdu_info->sw_frame_group_id == 908 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS)) { 909 ppdu_info->rx_info.mac_addr1_valid = 910 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_valid; 911 912 *(uint32_t *)&ppdu_info->rx_info.mac_addr1[0] = 913 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_31_0; 914 if (ppdu_info->sw_frame_group_id == 915 HAL_MPDU_SW_FRAME_GROUP_CTRL_RTS) { 916 *(uint16_t *)&ppdu_info->rx_info.mac_addr1[4] = 917 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad1_47_32; 918 } 919 } 920 } 921 #else 922 static inline void 923 hal_get_qos_control(hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user, 924 struct hal_rx_ppdu_info *ppdu_info) 925 { 926 } 927 928 static inline void 929 hal_get_mac_addr1(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 930 struct hal_rx_ppdu_info *ppdu_info) 931 { 932 } 933 #endif 934 935 #ifdef QCA_SUPPORT_SCAN_SPCL_VAP_STATS 936 static inline void 937 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 938 struct hal_rx_ppdu_info *ppdu_info) 939 { 940 uint16_t frame_ctrl; 941 uint8_t fc_type; 942 943 if (rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid) { 944 frame_ctrl = rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 945 fc_type = HAL_RX_GET_FRAME_CTRL_TYPE(frame_ctrl); 946 if (fc_type == HAL_RX_FRAME_CTRL_TYPE_MGMT) 947 ppdu_info->frm_type_info.rx_mgmt_cnt++; 948 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_CTRL) 949 ppdu_info->frm_type_info.rx_ctrl_cnt++; 950 else if (fc_type == HAL_RX_FRAME_CTRL_TYPE_DATA) 951 ppdu_info->frm_type_info.rx_data_cnt++; 952 } 953 } 954 #else 955 static inline void 956 hal_update_frame_type_cnt(hal_rx_mon_mpdu_start_t *rx_mpdu_start, 957 struct hal_rx_ppdu_info *ppdu_info) 958 { 959 } 960 #endif 961 962 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \ 963 defined(WLAN_PKT_CAPTURE_RX_2_0) 964 /** 965 * hal_mon_buff_addr_info_set() - set desc address in cookie 966 * @hal_soc_hdl: HAL Soc handle 967 * @mon_entry: monitor srng 968 * @mon_desc_addr: HAL monitor descriptor virtual address 969 * @phy_addr: HAL monitor descriptor physical address 970 * 971 * Return: none 972 */ 973 static inline 974 void hal_mon_buff_addr_info_set(hal_soc_handle_t hal_soc_hdl, 975 void *mon_entry, 976 unsigned long long mon_desc_addr, 977 qdf_dma_addr_t phy_addr) 978 { 979 uint32_t paddr_lo = ((uintptr_t)phy_addr & 0x00000000ffffffff); 980 uint32_t paddr_hi = ((uintptr_t)phy_addr & 0xffffffff00000000) >> 32; 981 uint32_t vaddr_lo = ((unsigned long long)mon_desc_addr & 0x00000000ffffffff); 982 uint32_t vaddr_hi = ((unsigned long long)mon_desc_addr & 0xffffffff00000000) >> 32; 983 984 HAL_MON_PADDR_LO_SET(mon_entry, paddr_lo); 985 HAL_MON_PADDR_HI_SET(mon_entry, paddr_hi); 986 HAL_MON_VADDR_LO_SET(mon_entry, vaddr_lo); 987 HAL_MON_VADDR_HI_SET(mon_entry, vaddr_hi); 988 } 989 #endif 990 991 #ifdef WLAN_PKT_CAPTURE_TX_2_0 992 993 /* TX monitor */ 994 #define TX_MON_STATUS_BUF_SIZE 2048 995 996 #define HAL_INVALID_PPDU_ID 0xFFFFFFFF 997 998 #define HAL_MAX_DL_MU_USERS 37 999 #define HAL_MAX_RU_INDEX 7 1000 1001 enum hal_tx_tlv_status { 1002 HAL_MON_TX_FES_SETUP, 1003 HAL_MON_TX_FES_STATUS_END, 1004 HAL_MON_RX_RESPONSE_REQUIRED_INFO, 1005 HAL_MON_RESPONSE_END_STATUS_INFO, 1006 1007 HAL_MON_TX_PCU_PPDU_SETUP_INIT, 1008 1009 HAL_MON_TX_MPDU_START, 1010 HAL_MON_TX_MSDU_START, 1011 HAL_MON_TX_BUFFER_ADDR, 1012 HAL_MON_TX_DATA, 1013 1014 HAL_MON_TX_FES_STATUS_START, 1015 1016 HAL_MON_TX_FES_STATUS_PROT, 1017 HAL_MON_TX_FES_STATUS_START_PROT, 1018 1019 HAL_MON_TX_FES_STATUS_START_PPDU, 1020 HAL_MON_TX_FES_STATUS_USER_PPDU, 1021 HAL_MON_TX_QUEUE_EXTENSION, 1022 1023 HAL_MON_RX_FRAME_BITMAP_ACK, 1024 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_256, 1025 HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K, 1026 HAL_MON_COEX_TX_STATUS, 1027 1028 HAL_MON_MACTX_HE_SIG_A_SU, 1029 HAL_MON_MACTX_HE_SIG_A_MU_DL, 1030 HAL_MON_MACTX_HE_SIG_B1_MU, 1031 HAL_MON_MACTX_HE_SIG_B2_MU, 1032 HAL_MON_MACTX_HE_SIG_B2_OFDMA, 1033 HAL_MON_MACTX_L_SIG_A, 1034 HAL_MON_MACTX_L_SIG_B, 1035 HAL_MON_MACTX_HT_SIG, 1036 HAL_MON_MACTX_VHT_SIG_A, 1037 1038 HAL_MON_MACTX_USER_DESC_PER_USER, 1039 HAL_MON_MACTX_USER_DESC_COMMON, 1040 HAL_MON_MACTX_PHY_DESC, 1041 1042 HAL_MON_TX_FW2SW, 1043 HAL_MON_TX_STATUS_PPDU_NOT_DONE, 1044 }; 1045 1046 enum txmon_coex_tx_status_reason { 1047 COEX_FES_TX_START, 1048 COEX_FES_TX_END, 1049 COEX_FES_END, 1050 COEX_RESPONSE_TX_START, 1051 COEX_RESPONSE_TX_END, 1052 COEX_NO_TX_ONGOING, 1053 }; 1054 1055 enum txmon_transmission_type { 1056 TXMON_SU_TRANSMISSION = 0, 1057 TXMON_MU_TRANSMISSION, 1058 TXMON_MU_SU_TRANSMISSION, 1059 TXMON_MU_MIMO_TRANSMISSION = 1, 1060 TXMON_MU_OFDMA_TRANMISSION 1061 }; 1062 1063 enum txmon_he_ppdu_subtype { 1064 TXMON_HE_SUBTYPE_SU = 0, 1065 TXMON_HE_SUBTYPE_TRIG, 1066 TXMON_HE_SUBTYPE_MU, 1067 TXMON_HE_SUBTYPE_EXT_SU 1068 }; 1069 1070 enum txmon_pkt_type { 1071 TXMON_PKT_TYPE_11A = 0, 1072 TXMON_PKT_TYPE_11B, 1073 TXMON_PKT_TYPE_11N_MM, 1074 TXMON_PKT_TYPE_11AC, 1075 TXMON_PKT_TYPE_11AX, 1076 TXMON_PKT_TYPE_11BA, 1077 TXMON_PKT_TYPE_11BE, 1078 TXMON_PKT_TYPE_11AZ 1079 }; 1080 1081 enum txmon_generated_response { 1082 TXMON_GEN_RESP_SELFGEN_ACK = 0, 1083 TXMON_GEN_RESP_SELFGEN_CTS, 1084 TXMON_GEN_RESP_SELFGEN_BA, 1085 TXMON_GEN_RESP_SELFGEN_MBA, 1086 TXMON_GEN_RESP_SELFGEN_CBF, 1087 TXMON_GEN_RESP_SELFGEN_TRIG, 1088 TXMON_GEN_RESP_SELFGEN_NDP_LMR 1089 }; 1090 1091 #ifdef MONITOR_TLV_RECORDING_ENABLE 1092 1093 /* 1094 * Please make sure that the maximum total size of fields in each TLV 1095 * is 22 bits. 1096 * 10 bits are reserved for tlv_tag 1097 */ 1098 struct hal_ppdu_start_tlv_record { 1099 uint32_t ppdu_id:10; 1100 }; 1101 1102 struct hal_ppdu_start_user_info_tlv_record { 1103 uint32_t user_id:6, 1104 rate_mcs:4, 1105 nss:3, 1106 reception_type:3, 1107 sgi:2; 1108 }; 1109 1110 struct hal_mpdu_start_tlv_record { 1111 uint32_t user_id:6, 1112 wrap_flag:1; 1113 }; 1114 1115 struct hal_mpdu_end_tlv_record { 1116 uint32_t user_id:6, 1117 fcs_err:1, 1118 wrap_flag:1; 1119 }; 1120 1121 struct hal_header_tlv_record { 1122 uint32_t wrap_flag:1; 1123 }; 1124 1125 struct hal_msdu_end_tlv_record { 1126 uint32_t user_id:6, 1127 msdu_num:8, 1128 tid:4, 1129 tcp_proto:1, 1130 udp_proto:1, 1131 wrap_flag:1; 1132 }; 1133 1134 struct hal_mon_buffer_addr_tlv_record { 1135 uint32_t dma_length:12, 1136 truncation:1, 1137 continuation:1, 1138 wrap_flag:1; 1139 }; 1140 1141 struct hal_phy_location_tlv_record { 1142 uint32_t rtt_cfr_status:8, 1143 rtt_num_streams:8, 1144 rx_location_info_valid:1; 1145 }; 1146 1147 struct hal_ppdu_end_user_stats_tlv_record { 1148 uint32_t ast_index:16, 1149 pkt_type:4; 1150 }; 1151 1152 struct hal_pcu_ppdu_end_info_tlv_record { 1153 uint32_t dialog_topken:8, 1154 bb_captured_reason:3, 1155 bb_captured_channel:1, 1156 bb_captured_timeout:1, 1157 mpdu_delimiter_error_seen:1; 1158 }; 1159 1160 struct hal_phy_rx_ht_sig_tlv_record { 1161 uint32_t crc:8, 1162 mcs:7, 1163 stbc:2, 1164 aggregation:1, 1165 short_gi:1, 1166 fes_coding:1, 1167 cbw:1; 1168 }; 1169 1170 /* Tx TLVs - structs of Tx TLV with fields to be added here*/ 1171 1172 /* 1173 * enum hal_ppdu_tlv_category - Categories of TLV 1174 * @PPDU_START: PPDU start level TLV 1175 * @MPDU: MPDU level TLV 1176 * @PPDU_END: PPDU end level TLV 1177 * 1178 */ 1179 enum hal_ppdu_tlv_category { 1180 CATEGORY_PPDU_START = 1, 1181 CATEGORY_MPDU, 1182 CATEGORY_PPDU_END 1183 }; 1184 #endif 1185 1186 /** 1187 * struct hal_txmon_user_desc_per_user - user desc per user information 1188 * @psdu_length: PSDU length of the user in octet 1189 * @ru_start_index: RU number to which user is assigned 1190 * @ru_size: Size of the RU for that user 1191 * @ofdma_mu_mimo_enabled: mu mimo transmission within the RU 1192 * @nss: Number of spatial stream occupied by the user 1193 * @stream_offset: Stream Offset from which the User occupies the Streams 1194 * @mcs: Modulation Coding Scheme for the User 1195 * @dcm: Indicates whether dual sub-carrier modulation is applied 1196 * @fec_type: Indicates whether it is BCC or LDPC 1197 * @user_bf_type: user beamforming type 1198 * @drop_user_cbf: frame dropped because of CBF FCS failure 1199 * @ldpc_extra_symbol: LDPC encoding process 1200 * @force_extra_symbol: force an extra OFDM symbol 1201 * @reserved: reserved 1202 * @sw_peer_id: user sw peer id 1203 * @per_user_subband_mask: Per user sub band mask 1204 */ 1205 struct hal_txmon_user_desc_per_user { 1206 uint32_t psdu_length; 1207 uint32_t ru_start_index :8, 1208 ru_size :4, 1209 ofdma_mu_mimo_enabled :1, 1210 nss :3, 1211 stream_offset :3, 1212 mcs :4, 1213 dcm :1, 1214 fec_type :1, 1215 user_bf_type :2, 1216 drop_user_cbf :1, 1217 ldpc_extra_symbol :1, 1218 force_extra_symbol :1, 1219 reserved :2; 1220 uint32_t sw_peer_id :16, 1221 per_user_subband_mask :16; 1222 }; 1223 1224 /** 1225 * struct hal_txmon_usr_desc_common - user desc common information 1226 * @num_users: Number of users 1227 * @ltf_size: LTF size 1228 * @pkt_extn_pe: packet extension duration of the trigger-based PPDU 1229 * @a_factor: packet extension duration of the trigger-based PPDU 1230 * @center_ru_0: Center RU is occupied in the lower 80 MHz band 1231 * @center_ru_1: Center RU is occupied in the upper 80 MHz band 1232 * @num_ltf_symbols: number of LTF symbols 1233 * @doppler_indication: doppler indication 1234 * @reserved: reserved 1235 * @spatial_reuse: spatial reuse 1236 * @ru_channel_0: RU arrangement for band 0 1237 * @ru_channel_1: RU arrangement for band 1 1238 */ 1239 struct hal_txmon_usr_desc_common { 1240 uint32_t num_users :6, 1241 ltf_size :2, 1242 pkt_extn_pe :1, 1243 a_factor :2, 1244 center_ru_0 :1, 1245 center_ru_1 :1, 1246 num_ltf_symbols :16, 1247 doppler_indication :1, 1248 reserved :2; 1249 uint16_t spatial_reuse; 1250 uint16_t ru_channel_0[8]; 1251 uint16_t ru_channel_1[8]; 1252 }; 1253 1254 #define IS_MULTI_USERS(num_users) (!!(0xFFFE & num_users)) 1255 1256 #define TXMON_HAL(hal_tx_ppdu_info, field) \ 1257 hal_tx_ppdu_info->field 1258 #define TXMON_HAL_STATUS(hal_tx_ppdu_info, field) \ 1259 hal_tx_ppdu_info->rx_status.field 1260 #define TXMON_HAL_USER(hal_tx_ppdu_info, user_id, field) \ 1261 hal_tx_ppdu_info->rx_user_status[user_id].field 1262 1263 #define TXMON_STATUS_INFO(hal_tx_status_info, field) \ 1264 hal_tx_status_info->field 1265 1266 #ifdef MONITOR_TLV_RECORDING_ENABLE 1267 struct hal_tx_tlv_info { 1268 uint32_t tlv_tag; 1269 uint8_t tlv_category; 1270 uint8_t is_data_ppdu_info; 1271 }; 1272 #endif 1273 1274 /** 1275 * struct hal_tx_status_info - status info that wasn't populated in rx_status 1276 * @reception_type: su or uplink mu reception type 1277 * @transmission_type: su or mu transmission type 1278 * @medium_prot_type: medium protection type 1279 * @generated_response: Generated frame in response window 1280 * @band_center_freq1: 1281 * @band_center_freq2: 1282 * @freq: 1283 * @phy_mode: 1284 * @schedule_id: 1285 * @no_bitmap_avail: Bitmap available flag 1286 * @explicit_ack: Explicit Acknowledge flag 1287 * @explicit_ack_type: Explicit Acknowledge type 1288 * @r2r_end_status_follow: Response to Response status flag 1289 * @response_type: Response type in response window 1290 * @ndp_frame: NDP frame 1291 * @num_users: number of users 1292 * @reserved: reserved bits 1293 * @mba_count: MBA count 1294 * @mba_fake_bitmap_count: MBA fake bitmap count 1295 * @sw_frame_group_id: software frame group ID 1296 * @r2r_to_follow: Response to Response follow flag 1297 * @phy_abort_reason: Reason for PHY abort 1298 * @phy_abort_user_number: User number for PHY abort 1299 * @buffer: Packet buffer pointer address 1300 * @offset: Packet buffer offset 1301 * @length: Packet buffer length 1302 * @protection_addr: Protection Address flag 1303 * @addr1: MAC address 1 1304 * @addr2: MAC address 2 1305 * @addr3: MAC address 3 1306 * @addr4: MAC address 4 1307 */ 1308 struct hal_tx_status_info { 1309 uint8_t reception_type; 1310 uint8_t transmission_type; 1311 uint8_t medium_prot_type; 1312 uint8_t generated_response; 1313 1314 uint16_t band_center_freq1; 1315 uint16_t band_center_freq2; 1316 uint16_t freq; 1317 uint16_t phy_mode; 1318 uint32_t schedule_id; 1319 1320 uint32_t no_bitmap_avail :1, 1321 explicit_ack :1, 1322 explicit_ack_type :4, 1323 r2r_end_status_follow :1, 1324 response_type :5, 1325 ndp_frame :2, 1326 num_users :8, 1327 reserved :10; 1328 1329 uint8_t mba_count; 1330 uint8_t mba_fake_bitmap_count; 1331 1332 uint8_t sw_frame_group_id; 1333 uint32_t r2r_to_follow; 1334 1335 uint16_t phy_abort_reason; 1336 uint8_t phy_abort_user_number; 1337 1338 void *buffer; 1339 uint32_t offset; 1340 uint32_t length; 1341 1342 uint8_t protection_addr; 1343 uint8_t addr1[QDF_MAC_ADDR_SIZE]; 1344 uint8_t addr2[QDF_MAC_ADDR_SIZE]; 1345 uint8_t addr3[QDF_MAC_ADDR_SIZE]; 1346 uint8_t addr4[QDF_MAC_ADDR_SIZE]; 1347 }; 1348 1349 /** 1350 * struct hal_tx_ppdu_info - tx monitor ppdu information 1351 * @ppdu_id: Id of the PLCP protocol data unit 1352 * @num_users: number of users 1353 * @is_used: boolean flag to identify valid ppdu info 1354 * @is_data: boolean flag to identify data frame 1355 * @cur_usr_idx: Current user index of the PPDU 1356 * @reserved: for future purpose 1357 * @prot_tlv_status: protection tlv status 1358 * @tx_tlv_info: store tx tlv info for recording 1359 * @packet_info: packet information 1360 * @rx_status: monitor mode rx status information 1361 * @rx_user_status: monitor mode rx user status information 1362 */ 1363 struct hal_tx_ppdu_info { 1364 uint32_t ppdu_id; 1365 uint32_t num_users :8, 1366 is_used :1, 1367 is_data :1, 1368 cur_usr_idx :8, 1369 reserved :15; 1370 1371 uint32_t prot_tlv_status; 1372 1373 #ifdef MONITOR_TLV_RECORDING_ENABLE 1374 struct hal_tx_tlv_info tx_tlv_info; 1375 #endif 1376 /* placeholder to hold packet buffer info */ 1377 struct hal_mon_packet_info packet_info; 1378 struct mon_rx_status rx_status; 1379 struct mon_rx_user_status rx_user_status[]; 1380 }; 1381 1382 /** 1383 * hal_tx_status_get_next_tlv() - get next tx status TLV 1384 * @tx_tlv: pointer to TLV header 1385 * @is_tlv_hdr_64_bit: Flag to indicate tlv hdr 64 bit 1386 * 1387 * Return: pointer to next tlv info 1388 */ 1389 static inline uint8_t* 1390 hal_tx_status_get_next_tlv(uint8_t *tx_tlv, bool is_tlv_hdr_64_bit) { 1391 uint32_t tlv_len, tlv_hdr_size; 1392 1393 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv); 1394 tlv_hdr_size = is_tlv_hdr_64_bit ? HAL_RX_TLV64_HDR_SIZE : 1395 HAL_RX_TLV32_HDR_SIZE; 1396 1397 return (uint8_t *)(uintptr_t)qdf_align((uint64_t)((uintptr_t)tx_tlv + 1398 tlv_len + 1399 tlv_hdr_size), 1400 tlv_hdr_size); 1401 } 1402 1403 /** 1404 * hal_txmon_status_parse_tlv() - process transmit info TLV 1405 * @hal_soc_hdl: HAL soc handle 1406 * @data_ppdu_info: pointer to hal data ppdu info 1407 * @prot_ppdu_info: pointer to hal prot ppdu info 1408 * @data_status_info: pointer to data status info 1409 * @prot_status_info: pointer to prot status info 1410 * @tx_tlv_hdr: pointer to TLV header 1411 * @status_frag: pointer to status frag 1412 * 1413 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE 1414 */ 1415 static inline uint32_t 1416 hal_txmon_status_parse_tlv(hal_soc_handle_t hal_soc_hdl, 1417 void *data_ppdu_info, 1418 void *prot_ppdu_info, 1419 void *data_status_info, 1420 void *prot_status_info, 1421 void *tx_tlv_hdr, 1422 qdf_frag_t status_frag) 1423 { 1424 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1425 1426 return hal_soc->ops->hal_txmon_status_parse_tlv(data_ppdu_info, 1427 prot_ppdu_info, 1428 data_status_info, 1429 prot_status_info, 1430 tx_tlv_hdr, 1431 status_frag); 1432 } 1433 1434 /** 1435 * hal_txmon_status_get_num_users() - api to get num users from start of fes 1436 * window 1437 * @hal_soc_hdl: HAL soc handle 1438 * @tx_tlv_hdr: pointer to TLV header 1439 * @num_users: reference to number of user 1440 * 1441 * Return: status 1442 */ 1443 static inline uint32_t 1444 hal_txmon_status_get_num_users(hal_soc_handle_t hal_soc_hdl, 1445 void *tx_tlv_hdr, uint8_t *num_users) 1446 { 1447 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1448 1449 return hal_soc->ops->hal_txmon_status_get_num_users(tx_tlv_hdr, 1450 num_users); 1451 } 1452 1453 /** 1454 * hal_tx_status_get_tlv_tag() - api to get tlv tag 1455 * @tx_tlv_hdr: pointer to TLV header 1456 * 1457 * Return tlv_tag 1458 */ 1459 static inline uint32_t 1460 hal_tx_status_get_tlv_tag(void *tx_tlv_hdr) 1461 { 1462 uint32_t tlv_tag = 0; 1463 1464 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 1465 1466 return tlv_tag; 1467 } 1468 1469 /** 1470 * hal_txmon_get_word_mask() - api to get word mask for tx monitor 1471 * @hal_soc_hdl: HAL soc handle 1472 * @wmask: pointer to hal_txmon_word_mask_config_t 1473 * 1474 * Return: bool 1475 */ 1476 static inline bool 1477 hal_txmon_get_word_mask(hal_soc_handle_t hal_soc_hdl, 1478 hal_txmon_word_mask_config_t *wmask) 1479 { 1480 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1481 1482 if (hal_soc->ops->hal_txmon_get_word_mask) { 1483 hal_soc->ops->hal_txmon_get_word_mask(wmask); 1484 return true; 1485 } 1486 1487 return false; 1488 } 1489 1490 /** 1491 * hal_txmon_is_mon_buf_addr_tlv() - api to find packet buffer addr tlv 1492 * @hal_soc_hdl: HAL soc handle 1493 * @tx_tlv_hdr: pointer to TLV header 1494 * 1495 * Return: bool 1496 */ 1497 static inline bool 1498 hal_txmon_is_mon_buf_addr_tlv(hal_soc_handle_t hal_soc_hdl, void *tx_tlv_hdr) 1499 { 1500 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1501 1502 if (qdf_unlikely(!hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv)) 1503 return false; 1504 1505 return hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv(tx_tlv_hdr); 1506 } 1507 1508 /** 1509 * hal_txmon_populate_packet_info() - api to populate packet info 1510 * @hal_soc_hdl: HAL soc handle 1511 * @tx_tlv_hdr: pointer to TLV header 1512 * @packet_info: pointer to placeholder for packet info 1513 * 1514 * Return void 1515 */ 1516 static inline void 1517 hal_txmon_populate_packet_info(hal_soc_handle_t hal_soc_hdl, 1518 void *tx_tlv_hdr, 1519 void *packet_info) 1520 { 1521 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 1522 1523 if (qdf_unlikely(!hal_soc->ops->hal_txmon_populate_packet_info)) 1524 return; 1525 1526 hal_soc->ops->hal_txmon_populate_packet_info(tx_tlv_hdr, packet_info); 1527 } 1528 #endif 1529 1530 static inline uint32_t 1531 hal_rx_parse_u_sig_cmn(struct hal_soc *hal_soc, void *rx_tlv, 1532 struct hal_rx_ppdu_info *ppdu_info) 1533 { 1534 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1535 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1536 uint8_t bad_usig_crc; 1537 1538 bad_usig_crc = HAL_RX_MON_USIG_GET_RX_INTEGRITY_CHECK_PASSED(rx_tlv) ? 1539 0 : 1; 1540 ppdu_info->rx_status.usig_common |= 1541 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 1542 QDF_MON_STATUS_USIG_BW_KNOWN | 1543 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 1544 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 1545 QDF_MON_STATUS_USIG_TXOP_KNOWN; 1546 1547 ppdu_info->rx_status.usig_common |= (usig_1->phy_version << 1548 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 1549 ppdu_info->rx_status.usig_common |= (usig_1->bw << 1550 QDF_MON_STATUS_USIG_BW_SHIFT); 1551 ppdu_info->rx_status.usig_common |= (usig_1->ul_dl << 1552 QDF_MON_STATUS_USIG_UL_DL_SHIFT); 1553 ppdu_info->rx_status.usig_common |= (usig_1->bss_color << 1554 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 1555 ppdu_info->rx_status.usig_common |= (usig_1->txop << 1556 QDF_MON_STATUS_USIG_TXOP_SHIFT); 1557 ppdu_info->rx_status.usig_common |= bad_usig_crc; 1558 1559 ppdu_info->u_sig_info.ul_dl = usig_1->ul_dl; 1560 ppdu_info->u_sig_info.bw = usig_1->bw; 1561 ppdu_info->rx_status.bw = usig_1->bw; 1562 1563 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1564 } 1565 1566 static inline uint32_t 1567 hal_rx_parse_u_sig_tb(struct hal_soc *hal_soc, void *rx_tlv, 1568 struct hal_rx_ppdu_info *ppdu_info) 1569 { 1570 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1571 struct hal_mon_usig_tb *usig_tb = &usig->usig_2.tb; 1572 1573 ppdu_info->rx_status.usig_mask |= 1574 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1575 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1576 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1577 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 1578 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 1579 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 1580 QDF_MON_STATUS_USIG_CRC_KNOWN | 1581 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1582 1583 ppdu_info->rx_status.usig_value |= (0x3F << 1584 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1585 ppdu_info->rx_status.usig_value |= (usig_tb->ppdu_type_comp_mode << 1586 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1587 ppdu_info->rx_status.usig_value |= (0x1 << 1588 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1589 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_1 << 1590 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 1591 ppdu_info->rx_status.usig_value |= (usig_tb->spatial_reuse_2 << 1592 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 1593 ppdu_info->rx_status.usig_value |= (0x1F << 1594 QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 1595 ppdu_info->rx_status.usig_value |= (usig_tb->crc << 1596 QDF_MON_STATUS_USIG_CRC_SHIFT); 1597 ppdu_info->rx_status.usig_value |= (usig_tb->tail << 1598 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1599 1600 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1601 usig_tb->ppdu_type_comp_mode; 1602 1603 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1604 } 1605 1606 static inline uint32_t 1607 hal_rx_parse_u_sig_mu(struct hal_soc *hal_soc, void *rx_tlv, 1608 struct hal_rx_ppdu_info *ppdu_info) 1609 { 1610 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1611 struct hal_mon_usig_mu *usig_mu = &usig->usig_2.mu; 1612 1613 ppdu_info->rx_status.usig_mask |= 1614 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 1615 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 1616 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 1617 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 1618 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 1619 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 1620 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 1621 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 1622 QDF_MON_STATUS_USIG_CRC_KNOWN | 1623 QDF_MON_STATUS_USIG_TAIL_KNOWN; 1624 1625 ppdu_info->rx_status.usig_value |= (0x1F << 1626 QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 1627 ppdu_info->rx_status.usig_value |= (0x1 << 1628 QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 1629 ppdu_info->rx_status.usig_value |= (usig_mu->ppdu_type_comp_mode << 1630 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 1631 ppdu_info->rx_status.usig_value |= (0x1 << 1632 QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 1633 ppdu_info->rx_status.usig_value |= (usig_mu->punc_ch_info << 1634 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 1635 ppdu_info->rx_status.usig_value |= (0x1 << 1636 QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 1637 ppdu_info->rx_status.usig_value |= (usig_mu->eht_sig_mcs << 1638 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 1639 ppdu_info->rx_status.usig_value |= (usig_mu->num_eht_sig_sym << 1640 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 1641 ppdu_info->rx_status.usig_value |= (usig_mu->crc << 1642 QDF_MON_STATUS_USIG_CRC_SHIFT); 1643 ppdu_info->rx_status.usig_value |= (usig_mu->tail << 1644 QDF_MON_STATUS_USIG_TAIL_SHIFT); 1645 1646 ppdu_info->u_sig_info.ppdu_type_comp_mode = 1647 usig_mu->ppdu_type_comp_mode; 1648 ppdu_info->u_sig_info.eht_sig_mcs = usig_mu->eht_sig_mcs; 1649 ppdu_info->u_sig_info.num_eht_sig_sym = usig_mu->num_eht_sig_sym; 1650 1651 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1652 } 1653 1654 static inline uint32_t 1655 hal_rx_parse_u_sig_hdr(struct hal_soc *hal_soc, void *rx_tlv, 1656 struct hal_rx_ppdu_info *ppdu_info) 1657 { 1658 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)rx_tlv; 1659 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 1660 1661 ppdu_info->rx_status.usig_flags = 1; 1662 1663 ppdu_info->rx_status.user_info_skip = 1; 1664 1665 hal_rx_parse_u_sig_cmn(hal_soc, rx_tlv, ppdu_info); 1666 1667 if (HAL_RX_MON_USIG_GET_PPDU_TYPE_N_COMP_MODE(rx_tlv) == 0 && 1668 usig_1->ul_dl == 1) 1669 return hal_rx_parse_u_sig_tb(hal_soc, rx_tlv, ppdu_info); 1670 else 1671 return hal_rx_parse_u_sig_mu(hal_soc, rx_tlv, ppdu_info); 1672 } 1673 1674 static inline uint32_t 1675 hal_rx_parse_usig_overflow(struct hal_soc *hal_soc, void *tlv, 1676 struct hal_rx_ppdu_info *ppdu_info) 1677 { 1678 struct hal_eht_sig_cc_usig_overflow *usig_ovflow = 1679 (struct hal_eht_sig_cc_usig_overflow *)tlv; 1680 1681 ppdu_info->rx_status.eht_known |= 1682 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1683 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1684 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN | 1685 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1686 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1687 QDF_MON_STATUS_EHT_DISREARD_KNOWN; 1688 1689 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->spatial_reuse << 1690 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1691 /* 1692 * GI and LTF size are separately indicated in radiotap header 1693 * and hence will be parsed from other TLV 1694 **/ 1695 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->num_ltf_sym << 1696 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1697 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->ldpc_extra_sym << 1698 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 1699 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pre_fec_pad_factor << 1700 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1701 ppdu_info->rx_status.eht_data[0] |= (usig_ovflow->pe_disambiguity << 1702 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1703 ppdu_info->rx_status.eht_data[0] |= (0xF << 1704 QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1705 1706 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1707 } 1708 1709 static inline uint32_t 1710 hal_rx_parse_non_ofdma_users(struct hal_soc *hal_soc, void *tlv, 1711 struct hal_rx_ppdu_info *ppdu_info) 1712 { 1713 struct hal_eht_sig_non_ofdma_cmn_eb *non_ofdma_cmn_eb = 1714 (struct hal_eht_sig_non_ofdma_cmn_eb *)tlv; 1715 1716 ppdu_info->rx_status.eht_known |= 1717 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_KNOWN; 1718 1719 ppdu_info->rx_status.eht_data[7] |= (non_ofdma_cmn_eb->num_users << 1720 QDF_MON_STATUS_EHT_NUM_NON_OFDMA_USERS_SHIFT); 1721 1722 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1723 } 1724 1725 static inline void 1726 hal_rx_parse_eht_mumimo_user_info(uint32_t *eht_user_info, 1727 struct hal_eht_sig_mu_mimo_user_info 1728 *user_info) 1729 { 1730 *eht_user_info |= QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1731 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1732 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1733 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1734 1735 *eht_user_info |= (user_info->sta_id << 1736 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1737 *eht_user_info |= (user_info->mcs << 1738 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1739 1740 *eht_user_info |= (user_info->coding << 1741 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1742 *eht_user_info |= (user_info->spatial_coding << 1743 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1744 } 1745 1746 static inline uint32_t 1747 hal_rx_parse_eht_sig_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1748 struct hal_rx_ppdu_info *ppdu_info) 1749 { 1750 struct hal_eht_sig_mu_mimo_user_info *user_info; 1751 struct mon_rx_status *rx_status; 1752 struct mon_rx_user_status *rx_user_status; 1753 uint32_t *eht_user_info; 1754 uint32_t user_idx, i; 1755 uint32_t *user_field; 1756 1757 i = 0; 1758 rx_status = &ppdu_info->rx_status; 1759 user_field = (uint32_t *)((uint8_t *)tlv + ppdu_info->tlv_aggr.rd_idx); 1760 1761 while ((i++ < MAX_USR_INFO_STR_CNT) && 1762 (ppdu_info->tlv_aggr.rd_idx < ppdu_info->tlv_aggr.cur_len)) { 1763 user_idx = rx_status->num_eht_user_info_valid; 1764 rx_user_status = &ppdu_info->rx_user_status[user_idx]; 1765 user_info = (struct hal_eht_sig_mu_mimo_user_info *)user_field; 1766 eht_user_info = &rx_user_status->eht_user_info; 1767 1768 hal_rx_parse_eht_mumimo_user_info(eht_user_info, user_info); 1769 rx_status->mcs = user_info->mcs; 1770 1771 /* CRC for matched user block */ 1772 rx_user_status->eht_known |= 1773 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1774 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1775 rx_user_status->eht_data[7] |= 1776 (user_info->crc << 1777 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1778 1779 ppdu_info->tlv_aggr.rd_idx += 4; 1780 user_field++; 1781 rx_status->num_eht_user_info_valid++; 1782 } 1783 1784 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1785 } 1786 1787 static inline void 1788 hal_rx_parse_eht_sig_mumimo_all_user_info(struct hal_soc *hal_soc, void *tlv, 1789 struct hal_rx_ppdu_info *ppdu_info) 1790 { 1791 struct hal_eht_sig_mu_mimo_user_info *user_info; 1792 uint32_t *eht_user_info; 1793 uint32_t user_idx = ppdu_info->rx_status.num_eht_all_user_info_valid; 1794 1795 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tlv; 1796 1797 eht_user_info = &ppdu_info->rx_status.eht_user_info[user_idx]; 1798 1799 hal_rx_parse_eht_mumimo_user_info(eht_user_info, user_info); 1800 1801 ppdu_info->rx_status.num_eht_all_user_info_valid++; 1802 } 1803 1804 static inline void 1805 hal_rx_parse_eht_non_mumimo_user_info(uint32_t *eht_user_info, 1806 struct hal_eht_sig_non_mu_mimo_user_info 1807 *user_info) 1808 { 1809 *eht_user_info |= QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1810 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1811 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1812 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1813 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1814 *eht_user_info |= (user_info->sta_id << 1815 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1816 *eht_user_info |= (user_info->mcs << 1817 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1818 *eht_user_info |= (user_info->nss << 1819 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1820 *eht_user_info |= (user_info->beamformed << 1821 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1822 *eht_user_info |= (user_info->coding << 1823 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1824 } 1825 1826 static inline void 1827 hal_rx_parse_eht_sig_non_mumimo_user_info(struct hal_soc *hal_soc, void *tlv, 1828 struct hal_rx_ppdu_info *ppdu_info) 1829 { 1830 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1831 struct mon_rx_status *rx_status; 1832 struct mon_rx_user_status *rx_user_status; 1833 uint32_t *eht_user_info; 1834 uint32_t user_idx, i; 1835 uint32_t *user_field; 1836 1837 i = 0; 1838 rx_status = &ppdu_info->rx_status; 1839 user_field = (uint32_t *)((uint8_t *)tlv + ppdu_info->tlv_aggr.rd_idx); 1840 1841 while ((i++ < MAX_USR_INFO_STR_CNT) && 1842 (ppdu_info->tlv_aggr.rd_idx < ppdu_info->tlv_aggr.cur_len)) { 1843 user_idx = rx_status->num_eht_user_info_valid; 1844 1845 rx_user_status = &ppdu_info->rx_user_status[user_idx]; 1846 user_info = 1847 (struct hal_eht_sig_non_mu_mimo_user_info *)user_field; 1848 eht_user_info = &rx_user_status->eht_user_info; 1849 hal_rx_parse_eht_non_mumimo_user_info(eht_user_info, user_info); 1850 1851 ppdu_info->rx_status.mcs = user_info->mcs; 1852 1853 /* CRC for matched user block */ 1854 rx_user_status->eht_known |= 1855 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_KNOWN | 1856 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_TAIL_KNOWN; 1857 rx_user_status->eht_data[7] |= 1858 (user_info->crc << 1859 QDF_MON_STATUS_EHT_USER_ENC_BLOCK_CRC_SHIFT); 1860 1861 ppdu_info->tlv_aggr.rd_idx += 4; 1862 user_field++; 1863 rx_status->num_eht_user_info_valid++; 1864 } 1865 } 1866 1867 static inline void 1868 hal_rx_parse_eht_sig_non_mumimo_all_user_info(struct hal_soc *hal_soc, 1869 void *tlv, struct hal_rx_ppdu_info 1870 *ppdu_info) 1871 { 1872 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1873 uint32_t *eht_user_info; 1874 uint32_t user_idx = ppdu_info->rx_status.num_eht_all_user_info_valid; 1875 1876 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tlv; 1877 1878 eht_user_info = &ppdu_info->rx_status.eht_user_info[user_idx]; 1879 1880 hal_rx_parse_eht_non_mumimo_user_info(eht_user_info, user_info); 1881 1882 ppdu_info->rx_status.num_eht_all_user_info_valid++; 1883 } 1884 1885 static inline bool hal_rx_is_ofdma(struct hal_soc *hal_soc, 1886 struct hal_rx_ppdu_info *ppdu_info) 1887 { 1888 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 0 && 1889 ppdu_info->u_sig_info.ul_dl == 0) 1890 return true; 1891 1892 return false; 1893 } 1894 1895 static inline bool hal_rx_is_non_ofdma(struct hal_soc *hal_soc, 1896 struct hal_rx_ppdu_info *ppdu_info) 1897 { 1898 uint32_t ppdu_type_comp_mode = 1899 ppdu_info->u_sig_info.ppdu_type_comp_mode; 1900 uint32_t ul_dl = ppdu_info->u_sig_info.ul_dl; 1901 1902 if ((ppdu_type_comp_mode == 1 && ul_dl == 0) || 1903 (ppdu_type_comp_mode == 2 && ul_dl == 0) || 1904 (ppdu_type_comp_mode == 1 && ul_dl == 1)) 1905 return true; 1906 1907 return false; 1908 } 1909 1910 static inline bool hal_rx_is_mu_mimo_user(struct hal_soc *hal_soc, 1911 struct hal_rx_ppdu_info *ppdu_info) 1912 { 1913 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 2 && 1914 ppdu_info->u_sig_info.ul_dl == 0) 1915 return true; 1916 1917 return false; 1918 } 1919 1920 static inline bool 1921 hal_rx_is_frame_type_ndp(struct hal_soc *hal_soc, 1922 struct hal_rx_ppdu_info *ppdu_info) 1923 { 1924 if (ppdu_info->u_sig_info.ppdu_type_comp_mode == 1 && 1925 ppdu_info->u_sig_info.eht_sig_mcs == 0 && 1926 ppdu_info->u_sig_info.num_eht_sig_sym == 0) 1927 return true; 1928 1929 return false; 1930 } 1931 1932 static inline uint32_t 1933 hal_rx_parse_eht_sig_ndp(struct hal_soc *hal_soc, void *tlv, 1934 struct hal_rx_ppdu_info *ppdu_info) 1935 { 1936 struct hal_eht_sig_ndp_cmn_eb *eht_sig_ndp = 1937 (struct hal_eht_sig_ndp_cmn_eb *)tlv; 1938 1939 ppdu_info->rx_status.eht_known |= 1940 QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1941 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1942 QDF_MON_STATUS_EHT_NDP_NSS_KNOWN | 1943 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_KNOWN | 1944 QDF_MON_STATUS_EHT_NDP_DISREGARD_KNOWN | 1945 QDF_MON_STATUS_EHT_CRC1_KNOWN | 1946 QDF_MON_STATUS_EHT_TAIL1_KNOWN; 1947 1948 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->spatial_reuse << 1949 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1950 /* 1951 * GI and LTF size are separately indicated in radiotap header 1952 * and hence will be parsed from other TLV 1953 **/ 1954 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->num_ltf_sym << 1955 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1956 ppdu_info->rx_status.eht_data[0] |= (0xF << 1957 QDF_MON_STATUS_EHT_NDP_DISREGARD_SHIFT); 1958 1959 ppdu_info->rx_status.eht_data[7] |= (eht_sig_ndp->nss << 1960 QDF_MON_STATUS_EHT_NDP_NSS_SHIFT); 1961 ppdu_info->rx_status.eht_data[7] |= (eht_sig_ndp->beamformed << 1962 QDF_MON_STATUS_EHT_NDP_BEAMFORMED_SHIFT); 1963 1964 ppdu_info->rx_status.eht_data[0] |= (eht_sig_ndp->crc << 1965 QDF_MON_STATUS_EHT_CRC1_SHIFT); 1966 1967 return HAL_TLV_STATUS_PPDU_NOT_DONE; 1968 } 1969 1970 #ifdef WLAN_FEATURE_11BE 1971 static inline void 1972 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1973 struct hal_rx_ppdu_info *ppdu_info) 1974 { 1975 ppdu_info->rx_status.punctured_pattern = cmn_usr_info->puncture_bitmap; 1976 } 1977 #else 1978 static inline void 1979 hal_rx_parse_punctured_pattern(struct phyrx_common_user_info *cmn_usr_info, 1980 struct hal_rx_ppdu_info *ppdu_info) 1981 { 1982 } 1983 #endif 1984 static inline uint32_t 1985 hal_rx_parse_cmn_usr_info(struct hal_soc *hal_soc, uint8_t *tlv, 1986 struct hal_rx_ppdu_info *ppdu_info) 1987 { 1988 struct phyrx_common_user_info *cmn_usr_info = 1989 (struct phyrx_common_user_info *)tlv; 1990 1991 ppdu_info->rx_status.eht_known |= 1992 QDF_MON_STATUS_EHT_GUARD_INTERVAL_KNOWN | 1993 QDF_MON_STATUS_EHT_LTF_KNOWN; 1994 1995 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->cp_setting << 1996 QDF_MON_STATUS_EHT_GI_SHIFT); 1997 if (!ppdu_info->rx_status.sgi) 1998 ppdu_info->rx_status.sgi = cmn_usr_info->cp_setting; 1999 2000 ppdu_info->rx_status.eht_data[0] |= (cmn_usr_info->ltf_size << 2001 QDF_MON_STATUS_EHT_LTF_SHIFT); 2002 if (!ppdu_info->rx_status.ltf_size) 2003 ppdu_info->rx_status.ltf_size = cmn_usr_info->ltf_size; 2004 2005 hal_rx_parse_punctured_pattern(cmn_usr_info, ppdu_info); 2006 2007 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2008 } 2009 2010 #ifdef WLAN_FEATURE_11BE 2011 static inline void 2012 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 2013 uint32_t *ru_width) 2014 { 2015 uint32_t width; 2016 2017 width = 0; 2018 switch (ru_size) { 2019 case IEEE80211_EHT_RU_26: 2020 width = RU_26; 2021 break; 2022 case IEEE80211_EHT_RU_52: 2023 width = RU_52; 2024 break; 2025 case IEEE80211_EHT_RU_52_26: 2026 width = RU_52_26; 2027 break; 2028 case IEEE80211_EHT_RU_106: 2029 width = RU_106; 2030 break; 2031 case IEEE80211_EHT_RU_106_26: 2032 width = RU_106_26; 2033 break; 2034 case IEEE80211_EHT_RU_242: 2035 width = RU_242; 2036 break; 2037 case IEEE80211_EHT_RU_484: 2038 width = RU_484; 2039 break; 2040 case IEEE80211_EHT_RU_484_242: 2041 width = RU_484_242; 2042 break; 2043 case IEEE80211_EHT_RU_996: 2044 width = RU_996; 2045 break; 2046 case IEEE80211_EHT_RU_996_484: 2047 width = RU_996_484; 2048 break; 2049 case IEEE80211_EHT_RU_996_484_242: 2050 width = RU_996_484_242; 2051 break; 2052 case IEEE80211_EHT_RU_996x2: 2053 width = RU_2X996; 2054 break; 2055 case IEEE80211_EHT_RU_996x2_484: 2056 width = RU_2X996_484; 2057 break; 2058 case IEEE80211_EHT_RU_996x3: 2059 width = RU_3X996; 2060 break; 2061 case IEEE80211_EHT_RU_996x3_484: 2062 width = RU_3X996_484; 2063 break; 2064 case IEEE80211_EHT_RU_996x4: 2065 width = RU_4X996; 2066 break; 2067 default: 2068 hal_err_rl("RU size(%d) to width convert err", ru_size); 2069 break; 2070 } 2071 *ru_width = width; 2072 } 2073 #else 2074 static inline void 2075 hal_rx_ul_ofdma_ru_size_to_width(uint32_t ru_size, 2076 uint32_t *ru_width) 2077 { 2078 *ru_width = 0; 2079 } 2080 #endif 2081 2082 static inline enum ieee80211_eht_ru_size 2083 hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(struct hal_soc *hal_soc, 2084 uint32_t hal_ru_size) 2085 { 2086 switch (hal_ru_size) { 2087 case HAL_EHT_RU_26: 2088 return IEEE80211_EHT_RU_26; 2089 case HAL_EHT_RU_52: 2090 return IEEE80211_EHT_RU_52; 2091 case HAL_EHT_RU_78: 2092 return IEEE80211_EHT_RU_52_26; 2093 case HAL_EHT_RU_106: 2094 return IEEE80211_EHT_RU_106; 2095 case HAL_EHT_RU_132: 2096 return IEEE80211_EHT_RU_106_26; 2097 case HAL_EHT_RU_242: 2098 return IEEE80211_EHT_RU_242; 2099 case HAL_EHT_RU_484: 2100 return IEEE80211_EHT_RU_484; 2101 case HAL_EHT_RU_726: 2102 return IEEE80211_EHT_RU_484_242; 2103 case HAL_EHT_RU_996: 2104 return IEEE80211_EHT_RU_996; 2105 case HAL_EHT_RU_996x2: 2106 return IEEE80211_EHT_RU_996x2; 2107 case HAL_EHT_RU_996x3: 2108 return IEEE80211_EHT_RU_996x3; 2109 case HAL_EHT_RU_996x4: 2110 return IEEE80211_EHT_RU_996x4; 2111 case HAL_EHT_RU_NONE: 2112 return IEEE80211_EHT_RU_INVALID; 2113 case HAL_EHT_RU_996_484: 2114 return IEEE80211_EHT_RU_996_484; 2115 case HAL_EHT_RU_996x2_484: 2116 return IEEE80211_EHT_RU_996x2_484; 2117 case HAL_EHT_RU_996x3_484: 2118 return IEEE80211_EHT_RU_996x3_484; 2119 case HAL_EHT_RU_996_484_242: 2120 return IEEE80211_EHT_RU_996_484_242; 2121 default: 2122 return IEEE80211_EHT_RU_INVALID; 2123 } 2124 } 2125 2126 #define HAL_SET_RU_PER80(ru_320mhz, ru_per80, ru_idx_per80mhz, num_80mhz) \ 2127 ((ru_320mhz) |= ((uint64_t)(ru_per80) << \ 2128 (((num_80mhz) * NUM_RU_BITS_PER80) + \ 2129 ((ru_idx_per80mhz) * NUM_RU_BITS_PER20)))) 2130 2131 static inline uint32_t 2132 hal_rx_parse_receive_user_info(struct hal_soc *hal_soc, uint8_t *tlv, 2133 struct hal_rx_ppdu_info *ppdu_info, 2134 uint32_t user_id) 2135 { 2136 struct receive_user_info *rx_usr_info = (struct receive_user_info *)tlv; 2137 struct mon_rx_user_status *mon_rx_user_status = NULL; 2138 uint64_t ru_index_320mhz = 0; 2139 uint16_t ru_index_per80mhz; 2140 uint32_t ru_size = 0, num_80mhz_with_ru = 0; 2141 uint32_t ru_index = HAL_EHT_RU_INVALID; 2142 uint32_t rtap_ru_size = IEEE80211_EHT_RU_INVALID; 2143 uint32_t ru_width; 2144 2145 if (ppdu_info->rx_status.user_info_skip) 2146 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2147 2148 switch (rx_usr_info->reception_type) { 2149 case HAL_RECEPTION_TYPE_SU: 2150 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2151 break; 2152 case HAL_RECEPTION_TYPE_DL_MU_MIMO: 2153 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2154 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2155 break; 2156 case HAL_RECEPTION_TYPE_UL_MU_MIMO: 2157 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2158 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2159 break; 2160 case HAL_RECEPTION_TYPE_DL_MU_OFMA: 2161 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2162 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2163 break; 2164 case HAL_RECEPTION_TYPE_UL_MU_OFDMA: 2165 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2166 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 2167 break; 2168 case HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO: 2169 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 2170 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 2171 break; 2172 case HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO: 2173 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2174 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA_MIMO; 2175 break; 2176 } 2177 2178 ppdu_info->start_user_info_cnt++; 2179 2180 ppdu_info->rx_status.is_stbc = rx_usr_info->stbc; 2181 ppdu_info->rx_status.ldpc = rx_usr_info->ldpc; 2182 ppdu_info->rx_status.dcm = rx_usr_info->sta_dcm; 2183 ppdu_info->rx_status.mcs = rx_usr_info->rate_mcs; 2184 ppdu_info->rx_status.nss = rx_usr_info->nss + 1; 2185 2186 if (user_id < HAL_MAX_UL_MU_USERS) { 2187 mon_rx_user_status = 2188 &ppdu_info->rx_user_status[user_id]; 2189 mon_rx_user_status->eht_known |= 2190 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_KNOWN; 2191 mon_rx_user_status->eht_data[0] |= 2192 (rx_usr_info->dl_ofdma_content_channel << 2193 QDF_MON_STATUS_EHT_CONTENT_CH_INDEX_SHIFT); 2194 2195 mon_rx_user_status->is_stbc = 2196 ppdu_info->rx_status.is_stbc; 2197 mon_rx_user_status->ldpc = 2198 ppdu_info->rx_status.ldpc; 2199 mon_rx_user_status->dcm = 2200 ppdu_info->rx_status.dcm; 2201 mon_rx_user_status->mcs = ppdu_info->rx_status.mcs; 2202 mon_rx_user_status->nss = ppdu_info->rx_status.nss; 2203 } 2204 2205 if (!(ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_MIMO || 2206 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA || 2207 ppdu_info->rx_status.reception_type == HAL_RX_TYPE_MU_OFDMA_MIMO)) 2208 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2209 2210 /* RU allocation present only for OFDMA reception */ 2211 if (rx_usr_info->ru_type_80_0 != HAL_EHT_RU_NONE) { 2212 ru_size += rx_usr_info->ru_type_80_0; 2213 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_0; 2214 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_0, 2215 ru_index_per80mhz, 0); 2216 num_80mhz_with_ru++; 2217 } 2218 2219 if (rx_usr_info->ru_type_80_1 != HAL_EHT_RU_NONE) { 2220 ru_size += rx_usr_info->ru_type_80_1; 2221 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_1; 2222 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_1, 2223 ru_index_per80mhz, 1); 2224 num_80mhz_with_ru++; 2225 } 2226 2227 if (rx_usr_info->ru_type_80_2 != HAL_EHT_RU_NONE) { 2228 ru_size += rx_usr_info->ru_type_80_2; 2229 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_2; 2230 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_2, 2231 ru_index_per80mhz, 2); 2232 num_80mhz_with_ru++; 2233 } 2234 2235 if (rx_usr_info->ru_type_80_3 != HAL_EHT_RU_NONE) { 2236 ru_size += rx_usr_info->ru_type_80_3; 2237 ru_index = ru_index_per80mhz = rx_usr_info->ru_start_index_80_3; 2238 HAL_SET_RU_PER80(ru_index_320mhz, rx_usr_info->ru_type_80_3, 2239 ru_index_per80mhz, 3); 2240 num_80mhz_with_ru++; 2241 } 2242 2243 if (num_80mhz_with_ru > 1) { 2244 /* Calculate the MRU index */ 2245 switch (ru_index_320mhz) { 2246 case HAL_EHT_RU_996_484_0: 2247 case HAL_EHT_RU_996x2_484_0: 2248 case HAL_EHT_RU_996x3_484_0: 2249 ru_index = 0; 2250 break; 2251 case HAL_EHT_RU_996_484_1: 2252 case HAL_EHT_RU_996x2_484_1: 2253 case HAL_EHT_RU_996x3_484_1: 2254 ru_index = 1; 2255 break; 2256 case HAL_EHT_RU_996_484_2: 2257 case HAL_EHT_RU_996x2_484_2: 2258 case HAL_EHT_RU_996x3_484_2: 2259 ru_index = 2; 2260 break; 2261 case HAL_EHT_RU_996_484_3: 2262 case HAL_EHT_RU_996x2_484_3: 2263 case HAL_EHT_RU_996x3_484_3: 2264 ru_index = 3; 2265 break; 2266 case HAL_EHT_RU_996_484_4: 2267 case HAL_EHT_RU_996x2_484_4: 2268 case HAL_EHT_RU_996x3_484_4: 2269 ru_index = 4; 2270 break; 2271 case HAL_EHT_RU_996_484_5: 2272 case HAL_EHT_RU_996x2_484_5: 2273 case HAL_EHT_RU_996x3_484_5: 2274 ru_index = 5; 2275 break; 2276 case HAL_EHT_RU_996_484_6: 2277 case HAL_EHT_RU_996x2_484_6: 2278 case HAL_EHT_RU_996x3_484_6: 2279 ru_index = 6; 2280 break; 2281 case HAL_EHT_RU_996_484_7: 2282 case HAL_EHT_RU_996x2_484_7: 2283 case HAL_EHT_RU_996x3_484_7: 2284 ru_index = 7; 2285 break; 2286 case HAL_EHT_RU_996x2_484_8: 2287 ru_index = 8; 2288 break; 2289 case HAL_EHT_RU_996x2_484_9: 2290 ru_index = 9; 2291 break; 2292 case HAL_EHT_RU_996x2_484_10: 2293 ru_index = 10; 2294 break; 2295 case HAL_EHT_RU_996x2_484_11: 2296 ru_index = 11; 2297 break; 2298 default: 2299 ru_index = HAL_EHT_RU_INVALID; 2300 dp_debug("Invalid RU index"); 2301 qdf_assert(0); 2302 break; 2303 } 2304 ru_size += 4; 2305 } 2306 2307 rtap_ru_size = hal_rx_mon_hal_ru_size_to_ieee80211_ru_size(hal_soc, 2308 ru_size); 2309 2310 if (rx_usr_info->pkt_type == HAL_RX_PKT_TYPE_11AX && 2311 mon_rx_user_status) { 2312 if (ru_index != HAL_EHT_RU_INVALID) { 2313 mon_rx_user_status->he_data2 |= 2314 QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN; 2315 mon_rx_user_status->he_data2 |= 2316 ru_index << QDF_MON_STATUS_RU_ALLOCATION_SHIFT; 2317 } 2318 } 2319 2320 if (rx_usr_info->pkt_type == HAL_RX_PKT_TYPE_11BE && 2321 mon_rx_user_status) { 2322 if (rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2323 mon_rx_user_status->eht_known |= 2324 QDF_MON_STATUS_EHT_RU_MRU_SIZE_KNOWN; 2325 mon_rx_user_status->eht_data[1] |= (rtap_ru_size << 2326 QDF_MON_STATUS_EHT_RU_MRU_SIZE_SHIFT); 2327 } 2328 2329 if (ru_index != HAL_EHT_RU_INVALID) { 2330 mon_rx_user_status->eht_known |= 2331 QDF_MON_STATUS_EHT_RU_MRU_INDEX_KNOWN; 2332 mon_rx_user_status->eht_data[1] |= (ru_index << 2333 QDF_MON_STATUS_EHT_RU_MRU_INDEX_SHIFT); 2334 } 2335 } 2336 2337 if (rx_usr_info->pkt_type == HAL_RX_PKT_TYPE_11AX && 2338 mon_rx_user_status) { 2339 if (ppdu_info->rx_status.reception_type == 2340 HAL_RX_TYPE_MU_MIMO) { 2341 ppdu_info->rx_status.he_mu_flags = 1; 2342 2343 /* HE-data1 */ 2344 mon_rx_user_status->he_data1 |= 2345 QDF_MON_STATUS_HE_MCS_KNOWN | 2346 QDF_MON_STATUS_HE_CODING_KNOWN; 2347 2348 /* HE-data2 */ 2349 2350 /* HE-data3 */ 2351 mon_rx_user_status->he_data3 |= 2352 mon_rx_user_status->mcs << 2353 QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2354 2355 mon_rx_user_status->he_data3 |= 2356 ppdu_info->rx_status.ldpc << 2357 QDF_MON_STATUS_CODING_SHIFT; 2358 2359 /* HE-data4 */ 2360 mon_rx_user_status->he_data4 |= 2361 mon_rx_user_status->sta_id << 2362 QDF_MON_STATUS_STA_ID_SHIFT; 2363 /* HE-data5 */ 2364 2365 /* HE-data6 */ 2366 mon_rx_user_status->he_data6 |= 2367 mon_rx_user_status->nss << 2368 QDF_MON_STATUS_HE_DATA_6_NSS_SHIFT; 2369 } 2370 2371 if (ppdu_info->rx_status.reception_type == 2372 HAL_RX_TYPE_MU_OFDMA) { 2373 ppdu_info->rx_status.he_mu_flags = 1; 2374 2375 /* HE-data1 */ 2376 mon_rx_user_status->he_data1 |= 2377 QDF_MON_STATUS_HE_MCS_KNOWN | 2378 QDF_MON_STATUS_HE_DCM_KNOWN | 2379 QDF_MON_STATUS_HE_CODING_KNOWN; 2380 2381 /* HE-data2 */ 2382 2383 /* HE-data3 */ 2384 mon_rx_user_status->he_data3 |= 2385 mon_rx_user_status->mcs << 2386 QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2387 2388 mon_rx_user_status->he_data3 |= 2389 mon_rx_user_status->dcm << 2390 QDF_MON_STATUS_DCM_SHIFT; 2391 2392 mon_rx_user_status->he_data3 |= 2393 mon_rx_user_status->ldpc << 2394 QDF_MON_STATUS_CODING_SHIFT; 2395 2396 /* HE-data4 */ 2397 mon_rx_user_status->he_data4 |= 2398 mon_rx_user_status->sta_id << 2399 QDF_MON_STATUS_STA_ID_SHIFT; 2400 2401 /* HE-data5 */ 2402 //txbf not exist 2403 mon_rx_user_status->he_data5 |= 2404 mon_rx_user_status->beamformed << 2405 QDF_MON_STATUS_TXBF_SHIFT; 2406 2407 /* HE-data6 */ 2408 mon_rx_user_status->he_data6 |= 2409 mon_rx_user_status->nss << 2410 QDF_MON_STATUS_HE_DATA_6_NSS_SHIFT; 2411 2412 mon_rx_user_status->he_flags1 = 2413 ppdu_info->rx_status.he_flags1; 2414 mon_rx_user_status->he_flags2 = 2415 ppdu_info->rx_status.he_flags2; 2416 } 2417 } 2418 2419 if (mon_rx_user_status && ru_index != HAL_EHT_RU_INVALID && 2420 rtap_ru_size != IEEE80211_EHT_RU_INVALID) { 2421 mon_rx_user_status->ofdma_ru_start_index = ru_index; 2422 mon_rx_user_status->ofdma_ru_size = rtap_ru_size; 2423 hal_rx_ul_ofdma_ru_size_to_width(rtap_ru_size, &ru_width); 2424 mon_rx_user_status->ofdma_ru_width = ru_width; 2425 mon_rx_user_status->mu_ul_info_valid = 1; 2426 } 2427 2428 return HAL_TLV_STATUS_PPDU_NOT_DONE; 2429 } 2430 2431 #ifdef WLAN_PKT_CAPTURE_RX_2_0 2432 static inline void 2433 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2434 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2435 { 2436 ppdu_info->rx_status.mpdu_retry_cnt = 2437 rx_ppdu_end_user->retried_mpdu_count; 2438 } 2439 2440 static inline void 2441 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2442 struct hal_rx_ppdu_info *ppdu_info) 2443 { 2444 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)rx_tlv; 2445 2446 ppdu_info->packet_info.sw_cookie = 2447 (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 2448 (addr->buffer_virt_addr_31_0)); 2449 /* HW DMA length is '-1' of actual DMA length*/ 2450 ppdu_info->packet_info.dma_length = addr->dma_length + 1; 2451 ppdu_info->packet_info.msdu_continuation = addr->msdu_continuation; 2452 ppdu_info->packet_info.truncated = addr->truncated; 2453 2454 } 2455 2456 static inline void 2457 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2458 struct hal_rx_ppdu_info *ppdu_info) 2459 { 2460 struct mon_drop *drop_cnt = (struct mon_drop *)rx_tlv; 2461 2462 ppdu_info->drop_cnt.ppdu_drop_cnt = drop_cnt->ppdu_drop_cnt; 2463 ppdu_info->drop_cnt.mpdu_drop_cnt = drop_cnt->mpdu_drop_cnt; 2464 ppdu_info->drop_cnt.end_of_ppdu_drop_cnt = drop_cnt->end_of_ppdu_seen; 2465 ppdu_info->drop_cnt.tlv_drop_cnt = drop_cnt->tlv_drop_cnt; 2466 } 2467 #else 2468 static inline void 2469 hal_rx_status_get_mpdu_retry_cnt(struct hal_rx_ppdu_info *ppdu_info, 2470 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user) 2471 { 2472 ppdu_info->rx_status.mpdu_retry_cnt = 0; 2473 } 2474 static inline void 2475 hal_rx_status_get_mon_buf_addr(uint8_t *rx_tlv, 2476 struct hal_rx_ppdu_info *ppdu_info) 2477 { 2478 } 2479 2480 static inline void 2481 hal_rx_update_ppdu_drop_cnt(uint8_t *rx_tlv, 2482 struct hal_rx_ppdu_info *ppdu_info) 2483 { 2484 } 2485 #endif 2486 2487 #ifdef WLAN_SUPPORT_CTRL_FRAME_STATS 2488 static inline void 2489 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2490 uint32_t user_id) 2491 { 2492 uint16_t fc = ppdu_info->nac_info.frame_control; 2493 2494 if (HAL_RX_GET_FRAME_CTRL_TYPE(fc) == HAL_RX_FRAME_CTRL_TYPE_CTRL) { 2495 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2496 QDF_IEEE80211_FC0_SUBTYPE_VHT_NDP_AN) 2497 ppdu_info->ctrl_frm_info[user_id].ndpa = 1; 2498 if ((fc & QDF_IEEE80211_FC0_SUBTYPE_MASK) == 2499 QDF_IEEE80211_FC0_SUBTYPE_BAR) 2500 ppdu_info->ctrl_frm_info[user_id].bar = 1; 2501 } 2502 } 2503 #else 2504 static inline void 2505 hal_update_rx_ctrl_frame_stats(struct hal_rx_ppdu_info *ppdu_info, 2506 uint32_t user_id) 2507 { 2508 } 2509 #endif /* WLAN_SUPPORT_CTRL_FRAME_STATS */ 2510 2511 #ifdef MONITOR_TLV_RECORDING_ENABLE 2512 /** 2513 * hal_rx_record_tlv_info() - Record received TLV info 2514 * @ppdu_info: pointer to ppdu_info 2515 * @tlv_tag: TLV tag of the TLV to record 2516 * 2517 * Return 2518 */ 2519 static inline void 2520 hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) { 2521 ppdu_info->rx_tlv_info.tlv_tag = tlv_tag; 2522 switch (tlv_tag) { 2523 case WIFIRX_PPDU_START_E: 2524 case WIFIRX_PPDU_START_USER_INFO_E: 2525 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_START; 2526 break; 2527 2528 case WIFIRX_HEADER_E: 2529 case WIFIRX_MPDU_START_E: 2530 case WIFIMON_BUFFER_ADDR_E: 2531 case WIFIRX_MSDU_END_E: 2532 case WIFIRX_MPDU_END_E: 2533 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_MPDU; 2534 break; 2535 2536 case WIFIRX_USER_PPDU_END_E: 2537 case WIFIRX_PPDU_END_E: 2538 case WIFIPHYRX_RSSI_LEGACY_E: 2539 case WIFIPHYRX_L_SIG_B_E: 2540 case WIFIPHYRX_COMMON_USER_INFO_E: 2541 case WIFIPHYRX_DATA_DONE_E: 2542 case WIFIPHYRX_PKT_END_PART1_E: 2543 case WIFIPHYRX_PKT_END_E: 2544 case WIFIRXPCU_PPDU_END_INFO_E: 2545 case WIFIRX_PPDU_END_USER_STATS_E: 2546 case WIFIRX_PPDU_END_STATUS_DONE_E: 2547 ppdu_info->rx_tlv_info.tlv_category = CATEGORY_PPDU_END; 2548 break; 2549 } 2550 } 2551 #else 2552 static inline void 2553 hal_rx_record_tlv_info(struct hal_rx_ppdu_info *ppdu_info, uint32_t tlv_tag) { 2554 } 2555 #endif 2556 2557 #ifdef HE_SIG_A_MU_UL_INFO_FORMAT_INDICATION_OFFSET 2558 /** 2559 * hal_rx_he_sig_a_mu_ul_e_handle() - handle TLV info for he_sig_a_mu_ul_info 2560 * @ppdu_info: pointer to ppdu_info 2561 * @rx_tlv: pointer to tlv 2562 * 2563 * Return 2564 */ 2565 static inline void 2566 hal_rx_he_sig_a_mu_ul_e_handle(struct hal_rx_ppdu_info *ppdu_info, 2567 uint8_t *rx_tlv) { 2568 uint32_t value; 2569 uint8_t *he_sig_a_mu_ul_info = (uint8_t *)rx_tlv; 2570 2571 ppdu_info->rx_status.he_flags = 1; 2572 2573 ppdu_info->rx_status.user_info_skip = 1; 2574 2575 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO, 2576 FORMAT_INDICATION); 2577 if (value == 0) { 2578 ppdu_info->rx_status.he_data1 = 2579 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 2580 } else { 2581 ppdu_info->rx_status.he_data1 = 2582 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 2583 } 2584 2585 /* data1 */ 2586 ppdu_info->rx_status.he_data1 |= 2587 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2588 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 2589 2590 /* data2 */ 2591 ppdu_info->rx_status.he_data2 |= 2592 QDF_MON_STATUS_TXOP_KNOWN; 2593 2594 /* data3 */ 2595 value = HAL_RX_GET(he_sig_a_mu_ul_info, 2596 HE_SIG_A_MU_UL_INFO, BSS_COLOR_ID); 2597 ppdu_info->rx_status.he_data3 = value; 2598 2599 /* data4 */ 2600 2601 /* data5 */ 2602 value = HAL_RX_GET(he_sig_a_mu_ul_info, 2603 HE_SIG_A_MU_UL_INFO, TRANSMIT_BW); 2604 ppdu_info->rx_status.he_data5 = value; 2605 ppdu_info->rx_status.bw = value; 2606 2607 /* data6 */ 2608 value = HAL_RX_GET(he_sig_a_mu_ul_info, HE_SIG_A_MU_UL_INFO, 2609 TXOP_DURATION); 2610 value = value << QDF_MON_STATUS_TXOP_SHIFT; 2611 ppdu_info->rx_status.he_data6 |= value; 2612 2613 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_UL; 2614 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 2615 } 2616 #else 2617 static inline void 2618 hal_rx_he_sig_a_mu_ul_e_handle(struct hal_rx_ppdu_info *ppdu_info, 2619 uint8_t *rx_tlv) { 2620 } 2621 #endif 2622 2623 /** 2624 * hal_rx_status_get_tlv_info_generic_be() - process receive info TLV 2625 * @rx_tlv_hdr: pointer to TLV header 2626 * @ppduinfo: pointer to ppdu_info 2627 * @hal_soc_hdl: HAL version of the SOC pointer 2628 * @nbuf: Network buffer 2629 * 2630 * Return: HAL_TLV_STATUS_PPDU_NOT_DONE or HAL_TLV_STATUS_PPDU_DONE from tlv 2631 */ 2632 static inline uint32_t 2633 hal_rx_status_get_tlv_info_generic_be(void *rx_tlv_hdr, void *ppduinfo, 2634 hal_soc_handle_t hal_soc_hdl, 2635 qdf_nbuf_t nbuf) 2636 { 2637 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 2638 uint32_t tlv_tag, user_id, tlv_len, value; 2639 uint8_t group_id = 0; 2640 uint8_t he_dcm = 0; 2641 uint8_t he_stbc = 0; 2642 uint16_t he_gi = 0; 2643 uint16_t he_ltf = 0; 2644 void *rx_tlv; 2645 struct mon_rx_user_status *mon_rx_user_status; 2646 struct hal_rx_ppdu_info *ppdu_info = 2647 (struct hal_rx_ppdu_info *)ppduinfo; 2648 2649 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 2650 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 2651 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 2652 2653 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV_HDR_SIZE; 2654 2655 ppdu_info->user_id = user_id; 2656 switch (tlv_tag) { 2657 case WIFIRX_PPDU_START_E: 2658 { 2659 if (qdf_unlikely(ppdu_info->com_info.last_ppdu_id == 2660 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, PHY_PPDU_ID))) 2661 hal_err("Matching ppdu_id(%u) detected", 2662 ppdu_info->com_info.last_ppdu_id); 2663 2664 ppdu_info->com_info.last_ppdu_id = 2665 ppdu_info->com_info.ppdu_id = 2666 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2667 PHY_PPDU_ID); 2668 2669 /* channel number is set in PHY meta data */ 2670 ppdu_info->rx_status.chan_num = 2671 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2672 SW_PHY_META_DATA) & 0x0000FFFF); 2673 ppdu_info->rx_status.chan_freq = 2674 (HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2675 SW_PHY_META_DATA) & 0xFFFF0000) >> 16; 2676 if (ppdu_info->rx_status.chan_num && 2677 ppdu_info->rx_status.chan_freq) { 2678 ppdu_info->rx_status.chan_freq = 2679 hal_rx_radiotap_num_to_freq( 2680 ppdu_info->rx_status.chan_num, 2681 ppdu_info->rx_status.chan_freq); 2682 } 2683 2684 ppdu_info->com_info.ppdu_timestamp = 2685 HAL_RX_GET_64(rx_tlv, RX_PPDU_START, 2686 PPDU_START_TIMESTAMP_31_0); 2687 ppdu_info->rx_status.ppdu_timestamp = 2688 ppdu_info->com_info.ppdu_timestamp; 2689 ppdu_info->rx_state = HAL_RX_MON_PPDU_START; 2690 2691 break; 2692 } 2693 2694 case WIFIRX_PPDU_START_USER_INFO_E: 2695 hal_rx_parse_receive_user_info(hal, rx_tlv, ppdu_info, user_id); 2696 break; 2697 2698 case WIFIRX_PPDU_END_E: 2699 /* This is followed by sub-TLVs of PPDU_END */ 2700 ppdu_info->rx_state = HAL_RX_MON_PPDU_END; 2701 break; 2702 2703 case WIFIPHYRX_LOCATION_E: 2704 hal_rx_get_rtt_info(hal_soc_hdl, rx_tlv, ppdu_info); 2705 break; 2706 2707 case WIFIRXPCU_PPDU_END_INFO_E: 2708 ppdu_info->rx_status.rx_antenna = 2709 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, RX_ANTENNA); 2710 ppdu_info->rx_status.tsft = 2711 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2712 WB_TIMESTAMP_UPPER_32); 2713 ppdu_info->rx_status.tsft = (ppdu_info->rx_status.tsft << 32) | 2714 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, 2715 WB_TIMESTAMP_LOWER_32); 2716 ppdu_info->rx_status.duration = 2717 HAL_RX_GET_64(rx_tlv, UNIFIED_RXPCU_PPDU_END_INFO_8, 2718 RX_PPDU_DURATION); 2719 hal_rx_get_bb_info(hal_soc_hdl, rx_tlv, ppdu_info); 2720 break; 2721 2722 /* 2723 * WIFIRX_PPDU_END_USER_STATS_E comes for each user received. 2724 * for MU, based on num users we see this tlv that many times. 2725 */ 2726 case WIFIRX_PPDU_END_USER_STATS_E: 2727 { 2728 hal_rx_mon_ppdu_end_user_t *rx_ppdu_end_user = rx_tlv; 2729 unsigned long tid = 0; 2730 uint16_t seq = 0; 2731 2732 ppdu_info->rx_status.ast_index = 2733 rx_ppdu_end_user->ast_index; 2734 2735 tid = rx_ppdu_end_user->received_qos_data_tid_bitmap; 2736 ppdu_info->rx_status.tid = qdf_find_first_bit(&tid, 2737 sizeof(tid) * 8); 2738 2739 if (ppdu_info->rx_status.tid == (sizeof(tid) * 8)) 2740 ppdu_info->rx_status.tid = HAL_TID_INVALID; 2741 2742 ppdu_info->rx_status.tcp_msdu_count = 2743 rx_ppdu_end_user->tcp_msdu_count + 2744 rx_ppdu_end_user->tcp_ack_msdu_count; 2745 2746 ppdu_info->rx_status.udp_msdu_count = 2747 rx_ppdu_end_user->udp_msdu_count; 2748 2749 ppdu_info->rx_status.other_msdu_count = 2750 rx_ppdu_end_user->other_msdu_count; 2751 2752 hal_rx_status_get_mpdu_retry_cnt(ppdu_info, rx_ppdu_end_user); 2753 2754 if (ppdu_info->sw_frame_group_id 2755 != HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 2756 ppdu_info->rx_status.frame_control_info_valid = 2757 rx_ppdu_end_user->frame_control_info_valid; 2758 2759 if (ppdu_info->rx_status.frame_control_info_valid) 2760 ppdu_info->rx_status.frame_control = 2761 rx_ppdu_end_user->frame_control_field; 2762 2763 hal_get_qos_control(rx_ppdu_end_user, ppdu_info); 2764 } 2765 2766 ppdu_info->rx_status.data_sequence_control_info_valid = 2767 rx_ppdu_end_user->data_sequence_control_info_valid; 2768 2769 seq = rx_ppdu_end_user->first_data_seq_ctrl; 2770 2771 if (ppdu_info->rx_status.data_sequence_control_info_valid) 2772 ppdu_info->rx_status.first_data_seq_ctrl = seq; 2773 2774 ppdu_info->rx_status.preamble_type = 2775 rx_ppdu_end_user->ht_control_field_pkt_type; 2776 2777 ppdu_info->end_user_stats_cnt++; 2778 2779 switch (ppdu_info->rx_status.preamble_type) { 2780 case HAL_RX_PKT_TYPE_11N: 2781 ppdu_info->rx_status.ht_flags = 1; 2782 ppdu_info->rx_status.rtap_flags |= HT_SGI_PRESENT; 2783 break; 2784 case HAL_RX_PKT_TYPE_11AC: 2785 ppdu_info->rx_status.vht_flags = 1; 2786 break; 2787 case HAL_RX_PKT_TYPE_11AX: 2788 ppdu_info->rx_status.he_flags = 1; 2789 break; 2790 case HAL_RX_PKT_TYPE_11BE: 2791 ppdu_info->rx_status.eht_flags = 1; 2792 break; 2793 default: 2794 break; 2795 } 2796 2797 ppdu_info->com_info.mpdu_cnt_fcs_ok = 2798 rx_ppdu_end_user->mpdu_cnt_fcs_ok; 2799 ppdu_info->com_info.mpdu_cnt_fcs_err = 2800 rx_ppdu_end_user->mpdu_cnt_fcs_err; 2801 if ((ppdu_info->com_info.mpdu_cnt_fcs_ok | 2802 ppdu_info->com_info.mpdu_cnt_fcs_err) > 1) 2803 ppdu_info->rx_status.rs_flags |= IEEE80211_AMPDU_FLAG; 2804 else 2805 ppdu_info->rx_status.rs_flags &= 2806 (~IEEE80211_AMPDU_FLAG); 2807 2808 ppdu_info->com_info.mpdu_fcs_ok_bitmap[0] = 2809 rx_ppdu_end_user->fcs_ok_bitmap_31_0; 2810 2811 ppdu_info->com_info.mpdu_fcs_ok_bitmap[1] = 2812 rx_ppdu_end_user->fcs_ok_bitmap_63_32; 2813 2814 if (user_id < HAL_MAX_UL_MU_USERS) { 2815 mon_rx_user_status = 2816 &ppdu_info->rx_user_status[user_id]; 2817 2818 hal_rx_handle_mu_ul_info(rx_ppdu_end_user, 2819 mon_rx_user_status); 2820 2821 ppdu_info->com_info.num_users++; 2822 2823 hal_rx_populate_mu_user_info(rx_ppdu_end_user, ppdu_info, 2824 user_id, 2825 mon_rx_user_status); 2826 } 2827 break; 2828 } 2829 2830 case WIFIRX_PPDU_END_USER_STATS_EXT_E: 2831 ppdu_info->com_info.mpdu_fcs_ok_bitmap[2] = 2832 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2833 FCS_OK_BITMAP_95_64); 2834 2835 ppdu_info->com_info.mpdu_fcs_ok_bitmap[3] = 2836 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2837 FCS_OK_BITMAP_127_96); 2838 2839 ppdu_info->com_info.mpdu_fcs_ok_bitmap[4] = 2840 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2841 FCS_OK_BITMAP_159_128); 2842 2843 ppdu_info->com_info.mpdu_fcs_ok_bitmap[5] = 2844 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2845 FCS_OK_BITMAP_191_160); 2846 2847 ppdu_info->com_info.mpdu_fcs_ok_bitmap[6] = 2848 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2849 FCS_OK_BITMAP_223_192); 2850 2851 ppdu_info->com_info.mpdu_fcs_ok_bitmap[7] = 2852 HAL_RX_GET_64(rx_tlv, RX_PPDU_END_USER_STATS_EXT, 2853 FCS_OK_BITMAP_255_224); 2854 break; 2855 2856 case WIFIRX_PPDU_END_STATUS_DONE_E: 2857 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 2858 return HAL_TLV_STATUS_PPDU_DONE; 2859 2860 case WIFIPHYRX_PKT_END_E: 2861 break; 2862 2863 case WIFIDUMMY_E: 2864 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 2865 return HAL_TLV_STATUS_BUF_DONE; 2866 2867 case WIFIPHYRX_HT_SIG_E: 2868 { 2869 uint8_t *ht_sig_info = (uint8_t *)rx_tlv + 2870 HAL_RX_OFFSET(UNIFIED_PHYRX_HT_SIG_0, 2871 HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS); 2872 value = HAL_RX_GET(ht_sig_info, HT_SIG_INFO, FEC_CODING); 2873 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2874 1 : 0; 2875 ppdu_info->rx_status.mcs = HAL_RX_GET(ht_sig_info, 2876 HT_SIG_INFO, MCS); 2877 ppdu_info->rx_status.ht_mcs = ppdu_info->rx_status.mcs; 2878 ppdu_info->rx_status.bw = HAL_RX_GET(ht_sig_info, 2879 HT_SIG_INFO, CBW); 2880 ppdu_info->rx_status.sgi = HAL_RX_GET(ht_sig_info, 2881 HT_SIG_INFO, SHORT_GI); 2882 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 2883 ppdu_info->rx_status.nss = ((ppdu_info->rx_status.mcs) >> 2884 HT_SIG_SU_NSS_SHIFT) + 1; 2885 ppdu_info->rx_status.mcs &= ((1 << HT_SIG_SU_NSS_SHIFT) - 1); 2886 break; 2887 } 2888 2889 case WIFIPHYRX_L_SIG_B_E: 2890 { 2891 uint8_t *l_sig_b_info = (uint8_t *)rx_tlv + 2892 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_B_0, 2893 L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS); 2894 2895 value = HAL_RX_GET(l_sig_b_info, L_SIG_B_INFO, RATE); 2896 ppdu_info->rx_status.l_sig_b_info = *((uint32_t *)l_sig_b_info); 2897 switch (value) { 2898 case 1: 2899 ppdu_info->rx_status.rate = HAL_11B_RATE_3MCS; 2900 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2901 break; 2902 case 2: 2903 ppdu_info->rx_status.rate = HAL_11B_RATE_2MCS; 2904 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2905 break; 2906 case 3: 2907 ppdu_info->rx_status.rate = HAL_11B_RATE_1MCS; 2908 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2909 break; 2910 case 4: 2911 ppdu_info->rx_status.rate = HAL_11B_RATE_0MCS; 2912 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2913 break; 2914 case 5: 2915 ppdu_info->rx_status.rate = HAL_11B_RATE_6MCS; 2916 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2917 break; 2918 case 6: 2919 ppdu_info->rx_status.rate = HAL_11B_RATE_5MCS; 2920 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2921 break; 2922 case 7: 2923 ppdu_info->rx_status.rate = HAL_11B_RATE_4MCS; 2924 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2925 break; 2926 default: 2927 break; 2928 } 2929 ppdu_info->rx_status.cck_flag = 1; 2930 break; 2931 } 2932 2933 case WIFIPHYRX_L_SIG_A_E: 2934 { 2935 uint8_t *l_sig_a_info = (uint8_t *)rx_tlv + 2936 HAL_RX_OFFSET(UNIFIED_PHYRX_L_SIG_A_0, 2937 L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS); 2938 2939 value = HAL_RX_GET(l_sig_a_info, L_SIG_A_INFO, RATE); 2940 ppdu_info->rx_status.l_sig_a_info = *((uint32_t *)l_sig_a_info); 2941 switch (value) { 2942 case 8: 2943 ppdu_info->rx_status.rate = HAL_11A_RATE_0MCS; 2944 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS0; 2945 break; 2946 case 9: 2947 ppdu_info->rx_status.rate = HAL_11A_RATE_1MCS; 2948 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS1; 2949 break; 2950 case 10: 2951 ppdu_info->rx_status.rate = HAL_11A_RATE_2MCS; 2952 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS2; 2953 break; 2954 case 11: 2955 ppdu_info->rx_status.rate = HAL_11A_RATE_3MCS; 2956 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS3; 2957 break; 2958 case 12: 2959 ppdu_info->rx_status.rate = HAL_11A_RATE_4MCS; 2960 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS4; 2961 break; 2962 case 13: 2963 ppdu_info->rx_status.rate = HAL_11A_RATE_5MCS; 2964 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS5; 2965 break; 2966 case 14: 2967 ppdu_info->rx_status.rate = HAL_11A_RATE_6MCS; 2968 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS6; 2969 break; 2970 case 15: 2971 ppdu_info->rx_status.rate = HAL_11A_RATE_7MCS; 2972 ppdu_info->rx_status.mcs = HAL_LEGACY_MCS7; 2973 break; 2974 default: 2975 break; 2976 } 2977 ppdu_info->rx_status.ofdm_flag = 1; 2978 break; 2979 } 2980 2981 case WIFIPHYRX_VHT_SIG_A_E: 2982 { 2983 uint8_t *vht_sig_a_info = (uint8_t *)rx_tlv + 2984 HAL_RX_OFFSET(UNIFIED_PHYRX_VHT_SIG_A_0, 2985 VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS); 2986 2987 value = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, 2988 SU_MU_CODING); 2989 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 2990 1 : 0; 2991 group_id = HAL_RX_GET(vht_sig_a_info, VHT_SIG_A_INFO, GROUP_ID); 2992 ppdu_info->rx_status.vht_flag_values5 = group_id; 2993 ppdu_info->rx_status.mcs = HAL_RX_GET(vht_sig_a_info, 2994 VHT_SIG_A_INFO, MCS); 2995 ppdu_info->rx_status.sgi = HAL_RX_GET(vht_sig_a_info, 2996 VHT_SIG_A_INFO, 2997 GI_SETTING); 2998 2999 switch (hal->target_type) { 3000 case TARGET_TYPE_QCA8074: 3001 case TARGET_TYPE_QCA8074V2: 3002 case TARGET_TYPE_QCA6018: 3003 case TARGET_TYPE_QCA5018: 3004 case TARGET_TYPE_QCN9000: 3005 case TARGET_TYPE_QCN6122: 3006 case TARGET_TYPE_QCN6432: 3007 #ifdef QCA_WIFI_QCA6390 3008 case TARGET_TYPE_QCA6390: 3009 #endif 3010 ppdu_info->rx_status.is_stbc = 3011 HAL_RX_GET(vht_sig_a_info, 3012 VHT_SIG_A_INFO, STBC); 3013 value = HAL_RX_GET(vht_sig_a_info, 3014 VHT_SIG_A_INFO, N_STS); 3015 value = value & VHT_SIG_SU_NSS_MASK; 3016 if (ppdu_info->rx_status.is_stbc && (value > 0)) 3017 value = ((value + 1) >> 1) - 1; 3018 ppdu_info->rx_status.nss = 3019 ((value & VHT_SIG_SU_NSS_MASK) + 1); 3020 3021 break; 3022 case TARGET_TYPE_QCA6290: 3023 #if !defined(QCA_WIFI_QCA6290_11AX) 3024 ppdu_info->rx_status.is_stbc = 3025 HAL_RX_GET(vht_sig_a_info, 3026 VHT_SIG_A_INFO, STBC); 3027 value = HAL_RX_GET(vht_sig_a_info, 3028 VHT_SIG_A_INFO, N_STS); 3029 value = value & VHT_SIG_SU_NSS_MASK; 3030 if (ppdu_info->rx_status.is_stbc && (value > 0)) 3031 value = ((value + 1) >> 1) - 1; 3032 ppdu_info->rx_status.nss = 3033 ((value & VHT_SIG_SU_NSS_MASK) + 1); 3034 #else 3035 ppdu_info->rx_status.nss = 0; 3036 #endif 3037 break; 3038 case TARGET_TYPE_KIWI: 3039 case TARGET_TYPE_MANGO: 3040 case TARGET_TYPE_PEACH: 3041 ppdu_info->rx_status.is_stbc = 3042 HAL_RX_GET(vht_sig_a_info, 3043 VHT_SIG_A_INFO, STBC); 3044 value = HAL_RX_GET(vht_sig_a_info, 3045 VHT_SIG_A_INFO, N_STS); 3046 value = value & VHT_SIG_SU_NSS_MASK; 3047 if (ppdu_info->rx_status.is_stbc && (value > 0)) 3048 value = ((value + 1) >> 1) - 1; 3049 ppdu_info->rx_status.nss = 3050 ((value & VHT_SIG_SU_NSS_MASK) + 1); 3051 3052 break; 3053 case TARGET_TYPE_QCA6490: 3054 case TARGET_TYPE_QCA6750: 3055 ppdu_info->rx_status.nss = 0; 3056 break; 3057 default: 3058 break; 3059 } 3060 ppdu_info->rx_status.vht_flag_values3[0] = 3061 (((ppdu_info->rx_status.mcs) << 4) 3062 | ppdu_info->rx_status.nss); 3063 ppdu_info->rx_status.bw = HAL_RX_GET(vht_sig_a_info, 3064 VHT_SIG_A_INFO, BANDWIDTH); 3065 ppdu_info->rx_status.vht_flag_values2 = 3066 ppdu_info->rx_status.bw; 3067 ppdu_info->rx_status.vht_flag_values4 = 3068 HAL_RX_GET(vht_sig_a_info, 3069 VHT_SIG_A_INFO, SU_MU_CODING); 3070 3071 ppdu_info->rx_status.beamformed = HAL_RX_GET(vht_sig_a_info, 3072 VHT_SIG_A_INFO, 3073 BEAMFORMED); 3074 if (group_id == 0 || group_id == 63) 3075 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 3076 else 3077 ppdu_info->rx_status.reception_type = 3078 HAL_RX_TYPE_MU_MIMO; 3079 3080 break; 3081 } 3082 case WIFIPHYRX_HE_SIG_A_SU_E: 3083 { 3084 uint8_t *he_sig_a_su_info = (uint8_t *)rx_tlv + 3085 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_SU_0, 3086 HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS); 3087 ppdu_info->rx_status.he_flags = 1; 3088 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3089 FORMAT_INDICATION); 3090 if (value == 0) { 3091 ppdu_info->rx_status.he_data1 = 3092 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 3093 } else { 3094 ppdu_info->rx_status.he_data1 = 3095 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 3096 } 3097 3098 /* data1 */ 3099 ppdu_info->rx_status.he_data1 |= 3100 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 3101 QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN | 3102 QDF_MON_STATUS_HE_DL_UL_KNOWN | 3103 QDF_MON_STATUS_HE_MCS_KNOWN | 3104 QDF_MON_STATUS_HE_DCM_KNOWN | 3105 QDF_MON_STATUS_HE_CODING_KNOWN | 3106 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 3107 QDF_MON_STATUS_HE_STBC_KNOWN | 3108 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 3109 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 3110 3111 /* data2 */ 3112 ppdu_info->rx_status.he_data2 = 3113 QDF_MON_STATUS_HE_GI_KNOWN; 3114 ppdu_info->rx_status.he_data2 |= 3115 QDF_MON_STATUS_TXBF_KNOWN | 3116 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 3117 QDF_MON_STATUS_TXOP_KNOWN | 3118 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 3119 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 3120 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 3121 3122 /* data3 */ 3123 value = HAL_RX_GET(he_sig_a_su_info, 3124 HE_SIG_A_SU_INFO, BSS_COLOR_ID); 3125 ppdu_info->rx_status.he_data3 = value; 3126 value = HAL_RX_GET(he_sig_a_su_info, 3127 HE_SIG_A_SU_INFO, BEAM_CHANGE); 3128 value = value << QDF_MON_STATUS_BEAM_CHANGE_SHIFT; 3129 ppdu_info->rx_status.he_data3 |= value; 3130 value = HAL_RX_GET(he_sig_a_su_info, 3131 HE_SIG_A_SU_INFO, DL_UL_FLAG); 3132 ppdu_info->rx_status.mu_dl_ul = HAL_RX_TYPE_DL; 3133 3134 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 3135 ppdu_info->rx_status.he_data3 |= value; 3136 3137 value = HAL_RX_GET(he_sig_a_su_info, 3138 HE_SIG_A_SU_INFO, TRANSMIT_MCS); 3139 ppdu_info->rx_status.mcs = value; 3140 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3141 ppdu_info->rx_status.he_data3 |= value; 3142 3143 value = HAL_RX_GET(he_sig_a_su_info, 3144 HE_SIG_A_SU_INFO, DCM); 3145 he_dcm = value; 3146 value = value << QDF_MON_STATUS_DCM_SHIFT; 3147 ppdu_info->rx_status.he_data3 |= value; 3148 value = HAL_RX_GET(he_sig_a_su_info, 3149 HE_SIG_A_SU_INFO, CODING); 3150 ppdu_info->rx_status.ldpc = (value == HAL_SU_MU_CODING_LDPC) ? 3151 1 : 0; 3152 value = value << QDF_MON_STATUS_CODING_SHIFT; 3153 ppdu_info->rx_status.he_data3 |= value; 3154 value = HAL_RX_GET(he_sig_a_su_info, 3155 HE_SIG_A_SU_INFO, 3156 LDPC_EXTRA_SYMBOL); 3157 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 3158 ppdu_info->rx_status.he_data3 |= value; 3159 value = HAL_RX_GET(he_sig_a_su_info, 3160 HE_SIG_A_SU_INFO, STBC); 3161 he_stbc = value; 3162 value = value << QDF_MON_STATUS_STBC_SHIFT; 3163 ppdu_info->rx_status.he_data3 |= value; 3164 3165 /* data4 */ 3166 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3167 SPATIAL_REUSE); 3168 ppdu_info->rx_status.he_data4 = value; 3169 3170 /* data5 */ 3171 value = HAL_RX_GET(he_sig_a_su_info, 3172 HE_SIG_A_SU_INFO, TRANSMIT_BW); 3173 ppdu_info->rx_status.he_data5 = value; 3174 ppdu_info->rx_status.bw = value; 3175 value = HAL_RX_GET(he_sig_a_su_info, 3176 HE_SIG_A_SU_INFO, CP_LTF_SIZE); 3177 switch (value) { 3178 case 0: 3179 he_gi = HE_GI_0_8; 3180 he_ltf = HE_LTF_1_X; 3181 break; 3182 case 1: 3183 he_gi = HE_GI_0_8; 3184 he_ltf = HE_LTF_2_X; 3185 break; 3186 case 2: 3187 he_gi = HE_GI_1_6; 3188 he_ltf = HE_LTF_2_X; 3189 break; 3190 case 3: 3191 if (he_dcm && he_stbc) { 3192 he_gi = HE_GI_0_8; 3193 he_ltf = HE_LTF_4_X; 3194 } else { 3195 he_gi = HE_GI_3_2; 3196 he_ltf = HE_LTF_4_X; 3197 } 3198 break; 3199 } 3200 ppdu_info->rx_status.sgi = he_gi; 3201 ppdu_info->rx_status.ltf_size = he_ltf; 3202 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 3203 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 3204 ppdu_info->rx_status.he_data5 |= value; 3205 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 3206 ppdu_info->rx_status.he_data5 |= value; 3207 3208 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 3209 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 3210 ppdu_info->rx_status.he_data5 |= value; 3211 3212 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3213 PACKET_EXTENSION_A_FACTOR); 3214 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 3215 ppdu_info->rx_status.he_data5 |= value; 3216 3217 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, TXBF); 3218 value = value << QDF_MON_STATUS_TXBF_SHIFT; 3219 ppdu_info->rx_status.he_data5 |= value; 3220 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3221 PACKET_EXTENSION_PE_DISAMBIGUITY); 3222 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 3223 ppdu_info->rx_status.he_data5 |= value; 3224 3225 /* data6 */ 3226 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, NSTS); 3227 value++; 3228 ppdu_info->rx_status.nss = value; 3229 ppdu_info->rx_status.he_data6 = value; 3230 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3231 DOPPLER_INDICATION); 3232 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 3233 ppdu_info->rx_status.he_data6 |= value; 3234 value = HAL_RX_GET(he_sig_a_su_info, HE_SIG_A_SU_INFO, 3235 TXOP_DURATION); 3236 value = value << QDF_MON_STATUS_TXOP_SHIFT; 3237 ppdu_info->rx_status.he_data6 |= value; 3238 3239 ppdu_info->rx_status.beamformed = HAL_RX_GET(he_sig_a_su_info, 3240 HE_SIG_A_SU_INFO, 3241 TXBF); 3242 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_SU; 3243 break; 3244 } 3245 case WIFIPHYRX_HE_SIG_A_MU_DL_E: 3246 { 3247 uint8_t *he_sig_a_mu_dl_info = (uint8_t *)rx_tlv + 3248 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_A_MU_DL_0, 3249 HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS); 3250 3251 ppdu_info->rx_status.he_mu_flags = 1; 3252 3253 /* HE Flags */ 3254 /*data1*/ 3255 ppdu_info->rx_status.he_data1 = 3256 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3257 ppdu_info->rx_status.he_data1 |= 3258 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 3259 QDF_MON_STATUS_HE_DL_UL_KNOWN | 3260 QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN | 3261 QDF_MON_STATUS_HE_STBC_KNOWN | 3262 QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN | 3263 QDF_MON_STATUS_HE_DOPPLER_KNOWN; 3264 3265 /* data2 */ 3266 ppdu_info->rx_status.he_data2 = 3267 QDF_MON_STATUS_HE_GI_KNOWN; 3268 ppdu_info->rx_status.he_data2 |= 3269 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN | 3270 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 3271 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 3272 QDF_MON_STATUS_TXOP_KNOWN | 3273 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 3274 3275 /*data3*/ 3276 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3277 HE_SIG_A_MU_DL_INFO, BSS_COLOR_ID); 3278 ppdu_info->rx_status.he_data3 = value; 3279 3280 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3281 HE_SIG_A_MU_DL_INFO, DL_UL_FLAG); 3282 value = value << QDF_MON_STATUS_DL_UL_SHIFT; 3283 ppdu_info->rx_status.he_data3 |= value; 3284 3285 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3286 HE_SIG_A_MU_DL_INFO, 3287 LDPC_EXTRA_SYMBOL); 3288 value = value << QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT; 3289 ppdu_info->rx_status.he_data3 |= value; 3290 3291 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3292 HE_SIG_A_MU_DL_INFO, STBC); 3293 he_stbc = value; 3294 value = value << QDF_MON_STATUS_STBC_SHIFT; 3295 ppdu_info->rx_status.he_data3 |= value; 3296 3297 /*data4*/ 3298 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3299 SPATIAL_REUSE); 3300 ppdu_info->rx_status.he_data4 = value; 3301 3302 /*data5*/ 3303 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3304 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 3305 ppdu_info->rx_status.he_data5 = value; 3306 ppdu_info->rx_status.bw = value; 3307 3308 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3309 HE_SIG_A_MU_DL_INFO, CP_LTF_SIZE); 3310 switch (value) { 3311 case 0: 3312 he_gi = HE_GI_0_8; 3313 he_ltf = HE_LTF_4_X; 3314 break; 3315 case 1: 3316 he_gi = HE_GI_0_8; 3317 he_ltf = HE_LTF_2_X; 3318 break; 3319 case 2: 3320 he_gi = HE_GI_1_6; 3321 he_ltf = HE_LTF_2_X; 3322 break; 3323 case 3: 3324 he_gi = HE_GI_3_2; 3325 he_ltf = HE_LTF_4_X; 3326 break; 3327 } 3328 ppdu_info->rx_status.sgi = he_gi; 3329 ppdu_info->rx_status.ltf_size = he_ltf; 3330 hal_get_radiotap_he_gi_ltf(&he_gi, &he_ltf); 3331 value = he_gi << QDF_MON_STATUS_GI_SHIFT; 3332 ppdu_info->rx_status.he_data5 |= value; 3333 3334 value = he_ltf << QDF_MON_STATUS_HE_LTF_SIZE_SHIFT; 3335 ppdu_info->rx_status.he_data5 |= value; 3336 3337 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3338 HE_SIG_A_MU_DL_INFO, NUM_LTF_SYMBOLS); 3339 value = (value << QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 3340 ppdu_info->rx_status.he_data5 |= value; 3341 3342 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3343 PACKET_EXTENSION_A_FACTOR); 3344 value = value << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT; 3345 ppdu_info->rx_status.he_data5 |= value; 3346 3347 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3348 PACKET_EXTENSION_PE_DISAMBIGUITY); 3349 value = value << QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT; 3350 ppdu_info->rx_status.he_data5 |= value; 3351 3352 /*data6*/ 3353 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3354 DOPPLER_INDICATION); 3355 value = value << QDF_MON_STATUS_DOPPLER_SHIFT; 3356 ppdu_info->rx_status.he_data6 |= value; 3357 3358 value = HAL_RX_GET(he_sig_a_mu_dl_info, HE_SIG_A_MU_DL_INFO, 3359 TXOP_DURATION); 3360 value = value << QDF_MON_STATUS_TXOP_SHIFT; 3361 ppdu_info->rx_status.he_data6 |= value; 3362 3363 /* HE-MU Flags */ 3364 /* HE-MU-flags1 */ 3365 ppdu_info->rx_status.he_flags1 = 3366 QDF_MON_STATUS_SIG_B_MCS_KNOWN | 3367 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 3368 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 3369 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 3370 QDF_MON_STATUS_RU_0_KNOWN; 3371 3372 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3373 HE_SIG_A_MU_DL_INFO, MCS_OF_SIG_B); 3374 ppdu_info->rx_status.he_flags1 |= value; 3375 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3376 HE_SIG_A_MU_DL_INFO, DCM_OF_SIG_B); 3377 value = value << QDF_MON_STATUS_DCM_FLAG_1_SHIFT; 3378 ppdu_info->rx_status.he_flags1 |= value; 3379 3380 /* HE-MU-flags2 */ 3381 ppdu_info->rx_status.he_flags2 = 3382 QDF_MON_STATUS_BW_KNOWN; 3383 3384 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3385 HE_SIG_A_MU_DL_INFO, TRANSMIT_BW); 3386 ppdu_info->rx_status.he_flags2 |= value; 3387 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3388 HE_SIG_A_MU_DL_INFO, COMP_MODE_SIG_B); 3389 value = value << QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 3390 ppdu_info->rx_status.he_flags2 |= value; 3391 value = HAL_RX_GET(he_sig_a_mu_dl_info, 3392 HE_SIG_A_MU_DL_INFO, NUM_SIG_B_SYMBOLS); 3393 value = value - 1; 3394 value = value << QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 3395 ppdu_info->rx_status.he_flags2 |= value; 3396 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 3397 break; 3398 } 3399 case WIFIPHYRX_HE_SIG_A_MU_UL_E: 3400 { 3401 hal_rx_he_sig_a_mu_ul_e_handle(ppdu_info, rx_tlv); 3402 break; 3403 } 3404 case WIFIPHYRX_HE_SIG_B1_MU_E: 3405 { 3406 uint8_t *he_sig_b1_mu_info = (uint8_t *)rx_tlv + 3407 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B1_MU_0, 3408 HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS); 3409 3410 ppdu_info->rx_status.he_sig_b_common_known |= 3411 QDF_MON_STATUS_HE_SIG_B_COMMON_KNOWN_RU0; 3412 /* TODO: Check on the availability of other fields in 3413 * sig_b_common 3414 */ 3415 3416 value = HAL_RX_GET(he_sig_b1_mu_info, 3417 HE_SIG_B1_MU_INFO, RU_ALLOCATION); 3418 ppdu_info->rx_status.he_RU[0] = value; 3419 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_MIMO; 3420 break; 3421 } 3422 case WIFIPHYRX_HE_SIG_B2_MU_E: 3423 { 3424 uint8_t *he_sig_b2_mu_info = (uint8_t *)rx_tlv + 3425 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_MU_0, 3426 HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS); 3427 /* 3428 * Not all "HE" fields can be updated from 3429 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3430 * to populate rest of the "HE" fields for MU scenarios. 3431 */ 3432 3433 /* HE-data1 */ 3434 ppdu_info->rx_status.he_data1 |= 3435 QDF_MON_STATUS_HE_MCS_KNOWN | 3436 QDF_MON_STATUS_HE_CODING_KNOWN; 3437 3438 /* HE-data2 */ 3439 3440 /* HE-data3 */ 3441 value = HAL_RX_GET(he_sig_b2_mu_info, 3442 HE_SIG_B2_MU_INFO, STA_MCS); 3443 ppdu_info->rx_status.mcs = value; 3444 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3445 ppdu_info->rx_status.he_data3 |= value; 3446 3447 value = HAL_RX_GET(he_sig_b2_mu_info, 3448 HE_SIG_B2_MU_INFO, STA_CODING); 3449 value = value << QDF_MON_STATUS_CODING_SHIFT; 3450 ppdu_info->rx_status.he_data3 |= value; 3451 3452 /* HE-data4 */ 3453 value = HAL_RX_GET(he_sig_b2_mu_info, 3454 HE_SIG_B2_MU_INFO, STA_ID); 3455 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3456 ppdu_info->rx_status.he_data4 |= value; 3457 3458 /* HE-data5 */ 3459 3460 /* HE-data6 */ 3461 value = HAL_RX_GET(he_sig_b2_mu_info, 3462 HE_SIG_B2_MU_INFO, NSTS); 3463 /* value n indicates n+1 spatial streams */ 3464 value++; 3465 ppdu_info->rx_status.nss = value; 3466 ppdu_info->rx_status.he_data6 |= value; 3467 3468 break; 3469 } 3470 case WIFIPHYRX_HE_SIG_B2_OFDMA_E: 3471 { 3472 uint8_t *he_sig_b2_ofdma_info = 3473 (uint8_t *)rx_tlv + 3474 HAL_RX_OFFSET(UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0, 3475 HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS); 3476 3477 /* 3478 * Not all "HE" fields can be updated from 3479 * WIFIPHYRX_HE_SIG_A_MU_DL_E TLV. Use WIFIPHYRX_HE_SIG_B2_MU_E 3480 * to populate rest of "HE" fields for MU OFDMA scenarios. 3481 */ 3482 3483 /* HE-data1 */ 3484 ppdu_info->rx_status.he_data1 |= 3485 QDF_MON_STATUS_HE_MCS_KNOWN | 3486 QDF_MON_STATUS_HE_DCM_KNOWN | 3487 QDF_MON_STATUS_HE_CODING_KNOWN; 3488 3489 /* HE-data2 */ 3490 ppdu_info->rx_status.he_data2 |= 3491 QDF_MON_STATUS_TXBF_KNOWN; 3492 3493 /* HE-data3 */ 3494 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3495 HE_SIG_B2_OFDMA_INFO, STA_MCS); 3496 ppdu_info->rx_status.mcs = value; 3497 value = value << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 3498 ppdu_info->rx_status.he_data3 |= value; 3499 3500 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3501 HE_SIG_B2_OFDMA_INFO, STA_DCM); 3502 he_dcm = value; 3503 value = value << QDF_MON_STATUS_DCM_SHIFT; 3504 ppdu_info->rx_status.he_data3 |= value; 3505 3506 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3507 HE_SIG_B2_OFDMA_INFO, STA_CODING); 3508 value = value << QDF_MON_STATUS_CODING_SHIFT; 3509 ppdu_info->rx_status.he_data3 |= value; 3510 3511 /* HE-data4 */ 3512 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3513 HE_SIG_B2_OFDMA_INFO, STA_ID); 3514 value = value << QDF_MON_STATUS_STA_ID_SHIFT; 3515 ppdu_info->rx_status.he_data4 |= value; 3516 3517 /* HE-data5 */ 3518 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3519 HE_SIG_B2_OFDMA_INFO, TXBF); 3520 value = value << QDF_MON_STATUS_TXBF_SHIFT; 3521 ppdu_info->rx_status.he_data5 |= value; 3522 3523 /* HE-data6 */ 3524 value = HAL_RX_GET(he_sig_b2_ofdma_info, 3525 HE_SIG_B2_OFDMA_INFO, NSTS); 3526 /* value n indicates n+1 spatial streams */ 3527 value++; 3528 ppdu_info->rx_status.nss = value; 3529 ppdu_info->rx_status.he_data6 |= value; 3530 ppdu_info->rx_status.reception_type = HAL_RX_TYPE_MU_OFDMA; 3531 break; 3532 } 3533 case WIFIPHYRX_RSSI_LEGACY_E: 3534 { 3535 uint8_t reception_type; 3536 int8_t rssi_value; 3537 uint8_t *rssi_info_tlv = (uint8_t *)rx_tlv + 3538 HAL_RX_OFFSET(UNIFIED_PHYRX_RSSI_LEGACY_19, 3539 RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS); 3540 3541 ppdu_info->rx_status.rssi_comb = 3542 hal_rx_phy_legacy_get_rssi(hal_soc_hdl, rx_tlv); 3543 3544 ppdu_info->rx_status.bw = hal->ops->hal_rx_get_tlv(rx_tlv); 3545 ppdu_info->rx_status.he_re = 0; 3546 3547 reception_type = HAL_RX_GET_64(rx_tlv, 3548 PHYRX_RSSI_LEGACY, 3549 RECEPTION_TYPE); 3550 switch (reception_type) { 3551 case QDF_RECEPTION_TYPE_ULOFMDA: 3552 ppdu_info->rx_status.ulofdma_flag = 1; 3553 ppdu_info->rx_status.he_data1 = 3554 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 3555 break; 3556 case QDF_RECEPTION_TYPE_ULMIMO: 3557 ppdu_info->rx_status.he_data1 = 3558 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3559 break; 3560 default: 3561 break; 3562 } 3563 3564 ppdu_info->rx_status.ul_mu_type = reception_type; 3565 3566 hal_rx_update_rssi_chain(ppdu_info, rssi_info_tlv); 3567 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3568 RECEIVE_RSSI_INFO, 3569 RSSI_PRI20_CHAIN0); 3570 ppdu_info->rx_status.rssi[0] = rssi_value; 3571 3572 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3573 RECEIVE_RSSI_INFO, 3574 RSSI_PRI20_CHAIN1); 3575 ppdu_info->rx_status.rssi[1] = rssi_value; 3576 3577 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3578 RECEIVE_RSSI_INFO, 3579 RSSI_PRI20_CHAIN2); 3580 ppdu_info->rx_status.rssi[2] = rssi_value; 3581 3582 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3583 RECEIVE_RSSI_INFO, 3584 RSSI_PRI20_CHAIN3); 3585 ppdu_info->rx_status.rssi[3] = rssi_value; 3586 3587 #ifdef DP_BE_NOTYET_WAR 3588 // TODO - this is not preset for kiwi 3589 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3590 RECEIVE_RSSI_INFO, 3591 RSSI_PRI20_CHAIN4); 3592 ppdu_info->rx_status.rssi[4] = rssi_value; 3593 3594 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3595 RECEIVE_RSSI_INFO, 3596 RSSI_PRI20_CHAIN5); 3597 ppdu_info->rx_status.rssi[5] = rssi_value; 3598 3599 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3600 RECEIVE_RSSI_INFO, 3601 RSSI_PRI20_CHAIN6); 3602 ppdu_info->rx_status.rssi[6] = rssi_value; 3603 3604 rssi_value = HAL_RX_GET_64(rssi_info_tlv, 3605 RECEIVE_RSSI_INFO, 3606 RSSI_PRI20_CHAIN7); 3607 ppdu_info->rx_status.rssi[7] = rssi_value; 3608 #endif 3609 break; 3610 } 3611 case WIFIPHYRX_OTHER_RECEIVE_INFO_E: 3612 hal_rx_proc_phyrx_other_receive_info_tlv(hal, rx_tlv_hdr, 3613 ppdu_info); 3614 break; 3615 case WIFIPHYRX_GENERIC_U_SIG_E: 3616 hal_rx_parse_u_sig_hdr(hal, rx_tlv, ppdu_info); 3617 break; 3618 case WIFIPHYRX_COMMON_USER_INFO_E: 3619 hal_rx_parse_cmn_usr_info(hal, rx_tlv, ppdu_info); 3620 break; 3621 case WIFIRX_HEADER_E: 3622 { 3623 struct hal_rx_ppdu_common_info *com_info = &ppdu_info->com_info; 3624 3625 if (ppdu_info->fcs_ok_cnt >= 3626 HAL_RX_MAX_MPDU_H_PER_STATUS_BUFFER) { 3627 hal_err("Number of MPDUs(%d) per status buff exceeded", 3628 ppdu_info->fcs_ok_cnt); 3629 break; 3630 } 3631 3632 /* Update first_msdu_payload for every mpdu and increment 3633 * com_info->mpdu_cnt for every WIFIRX_HEADER_E TLV 3634 */ 3635 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].first_msdu_payload = 3636 rx_tlv; 3637 ppdu_info->ppdu_msdu_info[ppdu_info->fcs_ok_cnt].payload_len = tlv_len; 3638 ppdu_info->msdu_info.first_msdu_payload = rx_tlv; 3639 ppdu_info->msdu_info.payload_len = tlv_len; 3640 ppdu_info->user_id = user_id; 3641 ppdu_info->hdr_len = tlv_len; 3642 ppdu_info->data = rx_tlv; 3643 ppdu_info->data += 4; 3644 3645 /* for every RX_HEADER TLV increment mpdu_cnt */ 3646 com_info->mpdu_cnt++; 3647 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3648 return HAL_TLV_STATUS_HEADER; 3649 } 3650 case WIFIRX_MPDU_START_E: 3651 { 3652 hal_rx_mon_mpdu_start_t *rx_mpdu_start = rx_tlv; 3653 uint32_t ppdu_id = rx_mpdu_start->rx_mpdu_info_details.phy_ppdu_id; 3654 uint8_t filter_category = 0; 3655 3656 ppdu_info->nac_info.fc_valid = 3657 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_valid; 3658 3659 ppdu_info->nac_info.to_ds_flag = 3660 rx_mpdu_start->rx_mpdu_info_details.to_ds; 3661 3662 ppdu_info->nac_info.frame_control = 3663 rx_mpdu_start->rx_mpdu_info_details.mpdu_frame_control_field; 3664 3665 ppdu_info->sw_frame_group_id = 3666 rx_mpdu_start->rx_mpdu_info_details.sw_frame_group_id; 3667 3668 ppdu_info->rx_user_status[user_id].sw_peer_id = 3669 rx_mpdu_start->rx_mpdu_info_details.sw_peer_id; 3670 3671 hal_update_rx_ctrl_frame_stats(ppdu_info, user_id); 3672 3673 if (ppdu_info->sw_frame_group_id == 3674 HAL_MPDU_SW_FRAME_GROUP_NULL_DATA) { 3675 ppdu_info->rx_status.frame_control_info_valid = 3676 ppdu_info->nac_info.fc_valid; 3677 ppdu_info->rx_status.frame_control = 3678 ppdu_info->nac_info.frame_control; 3679 } 3680 3681 hal_get_mac_addr1(rx_mpdu_start, 3682 ppdu_info); 3683 3684 ppdu_info->nac_info.mac_addr2_valid = 3685 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_valid; 3686 3687 *(uint16_t *)&ppdu_info->nac_info.mac_addr2[0] = 3688 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_15_0; 3689 3690 *(uint32_t *)&ppdu_info->nac_info.mac_addr2[2] = 3691 rx_mpdu_start->rx_mpdu_info_details.mac_addr_ad2_47_16; 3692 3693 if (ppdu_info->rx_status.prev_ppdu_id != ppdu_id) { 3694 ppdu_info->rx_status.prev_ppdu_id = ppdu_id; 3695 ppdu_info->rx_status.ppdu_len = 3696 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3697 } else { 3698 ppdu_info->rx_status.ppdu_len += 3699 rx_mpdu_start->rx_mpdu_info_details.mpdu_length; 3700 } 3701 3702 filter_category = 3703 rx_mpdu_start->rx_mpdu_info_details.rxpcu_mpdu_filter_in_category; 3704 3705 if (filter_category == 0) 3706 ppdu_info->rx_status.rxpcu_filter_pass = 1; 3707 else if (filter_category == 1) 3708 ppdu_info->rx_status.monitor_direct_used = 1; 3709 3710 ppdu_info->rx_user_status[user_id].filter_category = filter_category; 3711 3712 ppdu_info->nac_info.mcast_bcast = 3713 rx_mpdu_start->rx_mpdu_info_details.mcast_bcast; 3714 ppdu_info->mpdu_info[user_id].decap_type = 3715 rx_mpdu_start->rx_mpdu_info_details.decap_type; 3716 3717 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3718 return HAL_TLV_STATUS_MPDU_START; 3719 } 3720 case WIFIRX_MPDU_END_E: 3721 ppdu_info->user_id = user_id; 3722 ppdu_info->fcs_err = 3723 HAL_RX_GET_64(rx_tlv, RX_MPDU_END, 3724 FCS_ERR); 3725 3726 ppdu_info->mpdu_info[user_id].fcs_err = ppdu_info->fcs_err; 3727 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3728 return HAL_TLV_STATUS_MPDU_END; 3729 case WIFIRX_MSDU_END_E: { 3730 hal_rx_mon_msdu_end_t *rx_msdu_end = rx_tlv; 3731 3732 if (user_id < HAL_MAX_UL_MU_USERS) { 3733 ppdu_info->rx_msdu_info[user_id].cce_metadata = 3734 rx_msdu_end->cce_metadata; 3735 ppdu_info->rx_msdu_info[user_id].fse_metadata = 3736 rx_msdu_end->fse_metadata; 3737 ppdu_info->rx_msdu_info[user_id].is_flow_idx_timeout = 3738 rx_msdu_end->flow_idx_timeout; 3739 ppdu_info->rx_msdu_info[user_id].is_flow_idx_invalid = 3740 rx_msdu_end->flow_idx_invalid; 3741 ppdu_info->rx_msdu_info[user_id].flow_idx = 3742 rx_msdu_end->flow_idx; 3743 ppdu_info->msdu[user_id].first_msdu = 3744 rx_msdu_end->first_msdu; 3745 ppdu_info->msdu[user_id].last_msdu = 3746 rx_msdu_end->last_msdu; 3747 ppdu_info->msdu[user_id].msdu_len = 3748 rx_msdu_end->msdu_length; 3749 ppdu_info->msdu[user_id].user_rssi = 3750 rx_msdu_end->user_rssi; 3751 ppdu_info->msdu[user_id].reception_type = 3752 rx_msdu_end->reception_type; 3753 } 3754 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3755 return HAL_TLV_STATUS_MSDU_END; 3756 } 3757 case WIFIMON_BUFFER_ADDR_E: 3758 hal_rx_status_get_mon_buf_addr(rx_tlv, ppdu_info); 3759 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3760 return HAL_TLV_STATUS_MON_BUF_ADDR; 3761 case WIFIMON_DROP_E: 3762 hal_rx_update_ppdu_drop_cnt(rx_tlv, ppdu_info); 3763 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3764 return HAL_TLV_STATUS_MON_DROP; 3765 case 0: 3766 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3767 return HAL_TLV_STATUS_PPDU_DONE; 3768 case WIFIRX_STATUS_BUFFER_DONE_E: 3769 case WIFIPHYRX_DATA_DONE_E: 3770 case WIFIPHYRX_PKT_END_PART1_E: 3771 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3772 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3773 3774 default: 3775 hal_debug("unhandled tlv tag %d", tlv_tag); 3776 } 3777 3778 hal_rx_record_tlv_info(ppdu_info, tlv_tag); 3779 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3780 } 3781 3782 static uint32_t 3783 hal_rx_status_process_aggr_tlv(struct hal_soc *hal_soc, 3784 struct hal_rx_ppdu_info *ppdu_info) 3785 { 3786 uint32_t aggr_tlv_tag = ppdu_info->tlv_aggr.tlv_tag; 3787 3788 switch (aggr_tlv_tag) { 3789 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3790 hal_rx_parse_eht_sig_hdr(hal_soc, ppdu_info->tlv_aggr.buf, 3791 ppdu_info); 3792 break; 3793 default: 3794 /* Aggregated TLV cannot be handled */ 3795 qdf_assert(0); 3796 break; 3797 } 3798 3799 ppdu_info->tlv_aggr.in_progress = 0; 3800 ppdu_info->tlv_aggr.cur_len = 0; 3801 3802 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3803 } 3804 3805 static inline bool 3806 hal_rx_status_tlv_should_aggregate(struct hal_soc *hal_soc, uint32_t tlv_tag) 3807 { 3808 switch (tlv_tag) { 3809 case WIFIPHYRX_GENERIC_EHT_SIG_E: 3810 return true; 3811 } 3812 3813 return false; 3814 } 3815 3816 static inline uint32_t 3817 hal_rx_status_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3818 struct hal_rx_ppdu_info *ppdu_info, 3819 qdf_nbuf_t nbuf) 3820 { 3821 uint32_t tlv_tag, user_id, tlv_len; 3822 void *rx_tlv; 3823 3824 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3825 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3826 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3827 3828 rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV_HDR_SIZE; 3829 3830 if (tlv_len <= HAL_RX_MON_MAX_AGGR_SIZE - ppdu_info->tlv_aggr.cur_len) { 3831 qdf_mem_copy(ppdu_info->tlv_aggr.buf + 3832 ppdu_info->tlv_aggr.cur_len, 3833 rx_tlv, tlv_len); 3834 ppdu_info->tlv_aggr.cur_len += tlv_len; 3835 } else { 3836 dp_err("Length of TLV exceeds max aggregation length"); 3837 qdf_assert(0); 3838 } 3839 3840 return HAL_TLV_STATUS_PPDU_NOT_DONE; 3841 } 3842 3843 static inline uint32_t 3844 hal_rx_status_start_new_aggr_tlv(struct hal_soc *hal_soc, void *rx_tlv_hdr, 3845 struct hal_rx_ppdu_info *ppdu_info, 3846 qdf_nbuf_t nbuf) 3847 { 3848 uint32_t tlv_tag, user_id, tlv_len; 3849 3850 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3851 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3852 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3853 3854 ppdu_info->tlv_aggr.in_progress = 1; 3855 ppdu_info->tlv_aggr.tlv_tag = tlv_tag; 3856 ppdu_info->tlv_aggr.cur_len = 0; 3857 ppdu_info->tlv_aggr.rd_idx = 0; 3858 3859 return hal_rx_status_aggr_tlv(hal_soc, rx_tlv_hdr, ppdu_info, nbuf); 3860 } 3861 3862 static inline uint32_t 3863 hal_rx_status_get_tlv_info_wrapper_be(void *rx_tlv_hdr, void *ppduinfo, 3864 hal_soc_handle_t hal_soc_hdl, 3865 qdf_nbuf_t nbuf) 3866 { 3867 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3868 uint32_t tlv_tag, user_id, tlv_len; 3869 struct hal_rx_ppdu_info *ppdu_info = 3870 (struct hal_rx_ppdu_info *)ppduinfo; 3871 3872 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr); 3873 user_id = HAL_RX_GET_USER_TLV32_USERID(rx_tlv_hdr); 3874 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr); 3875 3876 /* 3877 * Handle the case where aggregation is in progress 3878 * or the current TLV is one of the TLVs which should be 3879 * aggregated 3880 */ 3881 if (ppdu_info->tlv_aggr.in_progress) { 3882 if (ppdu_info->tlv_aggr.tlv_tag == tlv_tag) { 3883 return hal_rx_status_aggr_tlv(hal, rx_tlv_hdr, 3884 ppdu_info, nbuf); 3885 } else { 3886 /* Finish aggregation of current TLV */ 3887 hal_rx_status_process_aggr_tlv(hal, ppdu_info); 3888 } 3889 } 3890 3891 if (hal_rx_status_tlv_should_aggregate(hal, tlv_tag)) { 3892 return hal_rx_status_start_new_aggr_tlv(hal, rx_tlv_hdr, 3893 ppduinfo, nbuf); 3894 } 3895 3896 return hal_rx_status_get_tlv_info_generic_be(rx_tlv_hdr, ppduinfo, 3897 hal_soc_hdl, nbuf); 3898 } 3899 #endif /* _HAL_BE_API_MON_H_ */ 3900