1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include <linux/pci.h>
28 #include <linux/i2c.h>
29 #include "amdgpu.h"
30 #include "amdgpu_dpm.h"
31 #include "amdgpu_smu.h"
32 #include "atomfirmware.h"
33 #include "amdgpu_atomfirmware.h"
34 #include "amdgpu_atombios.h"
35 #include "soc15_common.h"
36 #include "smu_v11_0.h"
37 #include "smu11_driver_if_navi10.h"
38 #include "atom.h"
39 #include "navi10_ppt.h"
40 #include "smu_v11_0_pptable.h"
41 #include "smu_v11_0_ppsmc.h"
42 #include "nbio/nbio_2_3_offset.h"
43 #include "nbio/nbio_2_3_sh_mask.h"
44 #include "thm/thm_11_0_2_offset.h"
45 #include "thm/thm_11_0_2_sh_mask.h"
46
47 #include "asic_reg/mp/mp_11_0_sh_mask.h"
48 #include "smu_cmn.h"
49 #include "smu_11_0_cdr_table.h"
50
51 /*
52 * DO NOT use these for err/warn/info/debug messages.
53 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
54 * They are more MGPU friendly.
55 */
56 #undef pr_err
57 #undef pr_warn
58 #undef pr_info
59 #undef pr_debug
60
61 #define FEATURE_MASK(feature) (1ULL << feature)
62 #define SMC_DPM_FEATURE ( \
63 FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) | \
64 FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT) | \
65 FEATURE_MASK(FEATURE_DPM_GFX_PACE_BIT) | \
66 FEATURE_MASK(FEATURE_DPM_UCLK_BIT) | \
67 FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT) | \
68 FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT) | \
69 FEATURE_MASK(FEATURE_DPM_LINK_BIT) | \
70 FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT))
71
72 #define SMU_11_0_GFX_BUSY_THRESHOLD 15
73
74 static struct cmn2asic_msg_mapping navi10_message_map[SMU_MSG_MAX_COUNT] = {
75 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 1),
76 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
77 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
78 MSG_MAP(SetAllowedFeaturesMaskLow, PPSMC_MSG_SetAllowedFeaturesMaskLow, 0),
79 MSG_MAP(SetAllowedFeaturesMaskHigh, PPSMC_MSG_SetAllowedFeaturesMaskHigh, 0),
80 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
81 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
82 MSG_MAP(EnableSmuFeaturesLow, PPSMC_MSG_EnableSmuFeaturesLow, 0),
83 MSG_MAP(EnableSmuFeaturesHigh, PPSMC_MSG_EnableSmuFeaturesHigh, 0),
84 MSG_MAP(DisableSmuFeaturesLow, PPSMC_MSG_DisableSmuFeaturesLow, 0),
85 MSG_MAP(DisableSmuFeaturesHigh, PPSMC_MSG_DisableSmuFeaturesHigh, 0),
86 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
87 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
88 MSG_MAP(SetWorkloadMask, PPSMC_MSG_SetWorkloadMask, 0),
89 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 0),
90 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
91 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
92 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
93 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
94 MSG_MAP(TransferTableSmu2Dram, PPSMC_MSG_TransferTableSmu2Dram, 1),
95 MSG_MAP(TransferTableDram2Smu, PPSMC_MSG_TransferTableDram2Smu, 0),
96 MSG_MAP(UseDefaultPPTable, PPSMC_MSG_UseDefaultPPTable, 0),
97 MSG_MAP(UseBackupPPTable, PPSMC_MSG_UseBackupPPTable, 0),
98 MSG_MAP(RunBtc, PPSMC_MSG_RunBtc, 0),
99 MSG_MAP(EnterBaco, PPSMC_MSG_EnterBaco, 0),
100 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 1),
101 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
102 MSG_MAP(SetHardMinByFreq, PPSMC_MSG_SetHardMinByFreq, 0),
103 MSG_MAP(SetHardMaxByFreq, PPSMC_MSG_SetHardMaxByFreq, 0),
104 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
105 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
106 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
107 MSG_MAP(SetMemoryChannelConfig, PPSMC_MSG_SetMemoryChannelConfig, 0),
108 MSG_MAP(SetGeminiMode, PPSMC_MSG_SetGeminiMode, 0),
109 MSG_MAP(SetGeminiApertureHigh, PPSMC_MSG_SetGeminiApertureHigh, 0),
110 MSG_MAP(SetGeminiApertureLow, PPSMC_MSG_SetGeminiApertureLow, 0),
111 MSG_MAP(OverridePcieParameters, PPSMC_MSG_OverridePcieParameters, 0),
112 MSG_MAP(SetMinDeepSleepDcefclk, PPSMC_MSG_SetMinDeepSleepDcefclk, 0),
113 MSG_MAP(ReenableAcDcInterrupt, PPSMC_MSG_ReenableAcDcInterrupt, 0),
114 MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
115 MSG_MAP(SetUclkFastSwitch, PPSMC_MSG_SetUclkFastSwitch, 0),
116 MSG_MAP(SetVideoFps, PPSMC_MSG_SetVideoFps, 0),
117 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 1),
118 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
119 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
120 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
121 MSG_MAP(ConfigureGfxDidt, PPSMC_MSG_ConfigureGfxDidt, 0),
122 MSG_MAP(NumOfDisplays, PPSMC_MSG_NumOfDisplays, 0),
123 MSG_MAP(SetSystemVirtualDramAddrHigh, PPSMC_MSG_SetSystemVirtualDramAddrHigh, 0),
124 MSG_MAP(SetSystemVirtualDramAddrLow, PPSMC_MSG_SetSystemVirtualDramAddrLow, 0),
125 MSG_MAP(AllowGfxOff, PPSMC_MSG_AllowGfxOff, 0),
126 MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
127 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
128 MSG_MAP(GetDcModeMaxDpmFreq, PPSMC_MSG_GetDcModeMaxDpmFreq, 1),
129 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
130 MSG_MAP(ExitBaco, PPSMC_MSG_ExitBaco, 0),
131 MSG_MAP(PrepareMp1ForReset, PPSMC_MSG_PrepareMp1ForReset, 0),
132 MSG_MAP(PrepareMp1ForShutdown, PPSMC_MSG_PrepareMp1ForShutdown, 0),
133 MSG_MAP(PowerUpVcn, PPSMC_MSG_PowerUpVcn, 0),
134 MSG_MAP(PowerDownVcn, PPSMC_MSG_PowerDownVcn, 0),
135 MSG_MAP(PowerUpJpeg, PPSMC_MSG_PowerUpJpeg, 0),
136 MSG_MAP(PowerDownJpeg, PPSMC_MSG_PowerDownJpeg, 0),
137 MSG_MAP(BacoAudioD3PME, PPSMC_MSG_BacoAudioD3PME, 0),
138 MSG_MAP(ArmD3, PPSMC_MSG_ArmD3, 0),
139 MSG_MAP(DAL_DISABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALDisableDummyPstateChange, 0),
140 MSG_MAP(DAL_ENABLE_DUMMY_PSTATE_CHANGE, PPSMC_MSG_DALEnableDummyPstateChange, 0),
141 MSG_MAP(GetVoltageByDpm, PPSMC_MSG_GetVoltageByDpm, 0),
142 MSG_MAP(GetVoltageByDpmOverdrive, PPSMC_MSG_GetVoltageByDpmOverdrive, 0),
143 MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
144 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH, PPSMC_MSG_SetDriverDummyTableDramAddrHigh, 0),
145 MSG_MAP(SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW, PPSMC_MSG_SetDriverDummyTableDramAddrLow, 0),
146 MSG_MAP(GET_UMC_FW_WA, PPSMC_MSG_GetUMCFWWA, 0),
147 };
148
149 static struct cmn2asic_mapping navi10_clk_map[SMU_CLK_COUNT] = {
150 CLK_MAP(GFXCLK, PPCLK_GFXCLK),
151 CLK_MAP(SCLK, PPCLK_GFXCLK),
152 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
153 CLK_MAP(FCLK, PPCLK_SOCCLK),
154 CLK_MAP(UCLK, PPCLK_UCLK),
155 CLK_MAP(MCLK, PPCLK_UCLK),
156 CLK_MAP(DCLK, PPCLK_DCLK),
157 CLK_MAP(VCLK, PPCLK_VCLK),
158 CLK_MAP(DCEFCLK, PPCLK_DCEFCLK),
159 CLK_MAP(DISPCLK, PPCLK_DISPCLK),
160 CLK_MAP(PIXCLK, PPCLK_PIXCLK),
161 CLK_MAP(PHYCLK, PPCLK_PHYCLK),
162 };
163
164 static struct cmn2asic_mapping navi10_feature_mask_map[SMU_FEATURE_COUNT] = {
165 FEA_MAP(DPM_PREFETCHER),
166 FEA_MAP(DPM_GFXCLK),
167 FEA_MAP(DPM_GFX_PACE),
168 FEA_MAP(DPM_UCLK),
169 FEA_MAP(DPM_SOCCLK),
170 FEA_MAP(DPM_MP0CLK),
171 FEA_MAP(DPM_LINK),
172 FEA_MAP(DPM_DCEFCLK),
173 FEA_MAP(MEM_VDDCI_SCALING),
174 FEA_MAP(MEM_MVDD_SCALING),
175 FEA_MAP(DS_GFXCLK),
176 FEA_MAP(DS_SOCCLK),
177 FEA_MAP(DS_LCLK),
178 FEA_MAP(DS_DCEFCLK),
179 FEA_MAP(DS_UCLK),
180 FEA_MAP(GFX_ULV),
181 FEA_MAP(FW_DSTATE),
182 FEA_MAP(GFXOFF),
183 FEA_MAP(BACO),
184 FEA_MAP(VCN_PG),
185 FEA_MAP(JPEG_PG),
186 FEA_MAP(USB_PG),
187 FEA_MAP(RSMU_SMN_CG),
188 FEA_MAP(PPT),
189 FEA_MAP(TDC),
190 FEA_MAP(GFX_EDC),
191 FEA_MAP(APCC_PLUS),
192 FEA_MAP(GTHR),
193 FEA_MAP(ACDC),
194 FEA_MAP(VR0HOT),
195 FEA_MAP(VR1HOT),
196 FEA_MAP(FW_CTF),
197 FEA_MAP(FAN_CONTROL),
198 FEA_MAP(THERMAL),
199 FEA_MAP(GFX_DCS),
200 FEA_MAP(RM),
201 FEA_MAP(LED_DISPLAY),
202 FEA_MAP(GFX_SS),
203 FEA_MAP(OUT_OF_BAND_MONITOR),
204 FEA_MAP(TEMP_DEPENDENT_VMIN),
205 FEA_MAP(MMHUB_PG),
206 FEA_MAP(ATHUB_PG),
207 FEA_MAP(APCC_DFLL),
208 };
209
210 static struct cmn2asic_mapping navi10_table_map[SMU_TABLE_COUNT] = {
211 TAB_MAP(PPTABLE),
212 TAB_MAP(WATERMARKS),
213 TAB_MAP(AVFS),
214 TAB_MAP(AVFS_PSM_DEBUG),
215 TAB_MAP(AVFS_FUSE_OVERRIDE),
216 TAB_MAP(PMSTATUSLOG),
217 TAB_MAP(SMU_METRICS),
218 TAB_MAP(DRIVER_SMU_CONFIG),
219 TAB_MAP(ACTIVITY_MONITOR_COEFF),
220 TAB_MAP(OVERDRIVE),
221 TAB_MAP(I2C_COMMANDS),
222 TAB_MAP(PACE),
223 };
224
225 static struct cmn2asic_mapping navi10_pwr_src_map[SMU_POWER_SOURCE_COUNT] = {
226 PWR_MAP(AC),
227 PWR_MAP(DC),
228 };
229
230 static struct cmn2asic_mapping navi10_workload_map[PP_SMC_POWER_PROFILE_COUNT] = {
231 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT, WORKLOAD_PPLIB_DEFAULT_BIT),
232 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_FULLSCREEN3D, WORKLOAD_PPLIB_FULL_SCREEN_3D_BIT),
233 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_POWERSAVING, WORKLOAD_PPLIB_POWER_SAVING_BIT),
234 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VIDEO, WORKLOAD_PPLIB_VIDEO_BIT),
235 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_VR, WORKLOAD_PPLIB_VR_BIT),
236 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_COMPUTE, WORKLOAD_PPLIB_COMPUTE_BIT),
237 WORKLOAD_MAP(PP_SMC_POWER_PROFILE_CUSTOM, WORKLOAD_PPLIB_CUSTOM_BIT),
238 };
239
240 static const uint8_t navi1x_throttler_map[] = {
241 [THROTTLER_TEMP_EDGE_BIT] = (SMU_THROTTLER_TEMP_EDGE_BIT),
242 [THROTTLER_TEMP_HOTSPOT_BIT] = (SMU_THROTTLER_TEMP_HOTSPOT_BIT),
243 [THROTTLER_TEMP_MEM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
244 [THROTTLER_TEMP_VR_GFX_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
245 [THROTTLER_TEMP_VR_MEM0_BIT] = (SMU_THROTTLER_TEMP_VR_MEM0_BIT),
246 [THROTTLER_TEMP_VR_MEM1_BIT] = (SMU_THROTTLER_TEMP_VR_MEM1_BIT),
247 [THROTTLER_TEMP_VR_SOC_BIT] = (SMU_THROTTLER_TEMP_VR_SOC_BIT),
248 [THROTTLER_TEMP_LIQUID0_BIT] = (SMU_THROTTLER_TEMP_LIQUID0_BIT),
249 [THROTTLER_TEMP_LIQUID1_BIT] = (SMU_THROTTLER_TEMP_LIQUID1_BIT),
250 [THROTTLER_TDC_GFX_BIT] = (SMU_THROTTLER_TDC_GFX_BIT),
251 [THROTTLER_TDC_SOC_BIT] = (SMU_THROTTLER_TDC_SOC_BIT),
252 [THROTTLER_PPT0_BIT] = (SMU_THROTTLER_PPT0_BIT),
253 [THROTTLER_PPT1_BIT] = (SMU_THROTTLER_PPT1_BIT),
254 [THROTTLER_PPT2_BIT] = (SMU_THROTTLER_PPT2_BIT),
255 [THROTTLER_PPT3_BIT] = (SMU_THROTTLER_PPT3_BIT),
256 [THROTTLER_FIT_BIT] = (SMU_THROTTLER_FIT_BIT),
257 [THROTTLER_PPM_BIT] = (SMU_THROTTLER_PPM_BIT),
258 [THROTTLER_APCC_BIT] = (SMU_THROTTLER_APCC_BIT),
259 };
260
261
is_asic_secure(struct smu_context * smu)262 static bool is_asic_secure(struct smu_context *smu)
263 {
264 struct amdgpu_device *adev = smu->adev;
265 bool is_secure = true;
266 uint32_t mp0_fw_intf;
267
268 mp0_fw_intf = RREG32_PCIE(MP0_Public |
269 (smnMP0_FW_INTF & 0xffffffff));
270
271 if (!(mp0_fw_intf & (1 << 19)))
272 is_secure = false;
273
274 return is_secure;
275 }
276
277 static int
navi10_get_allowed_feature_mask(struct smu_context * smu,uint32_t * feature_mask,uint32_t num)278 navi10_get_allowed_feature_mask(struct smu_context *smu,
279 uint32_t *feature_mask, uint32_t num)
280 {
281 struct amdgpu_device *adev = smu->adev;
282
283 if (num > 2)
284 return -EINVAL;
285
286 memset(feature_mask, 0, sizeof(uint32_t) * num);
287
288 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT)
289 | FEATURE_MASK(FEATURE_DPM_MP0CLK_BIT)
290 | FEATURE_MASK(FEATURE_RSMU_SMN_CG_BIT)
291 | FEATURE_MASK(FEATURE_DS_SOCCLK_BIT)
292 | FEATURE_MASK(FEATURE_PPT_BIT)
293 | FEATURE_MASK(FEATURE_TDC_BIT)
294 | FEATURE_MASK(FEATURE_GFX_EDC_BIT)
295 | FEATURE_MASK(FEATURE_APCC_PLUS_BIT)
296 | FEATURE_MASK(FEATURE_VR0HOT_BIT)
297 | FEATURE_MASK(FEATURE_FAN_CONTROL_BIT)
298 | FEATURE_MASK(FEATURE_THERMAL_BIT)
299 | FEATURE_MASK(FEATURE_LED_DISPLAY_BIT)
300 | FEATURE_MASK(FEATURE_DS_LCLK_BIT)
301 | FEATURE_MASK(FEATURE_DS_DCEFCLK_BIT)
302 | FEATURE_MASK(FEATURE_FW_DSTATE_BIT)
303 | FEATURE_MASK(FEATURE_BACO_BIT)
304 | FEATURE_MASK(FEATURE_GFX_SS_BIT)
305 | FEATURE_MASK(FEATURE_APCC_DFLL_BIT)
306 | FEATURE_MASK(FEATURE_FW_CTF_BIT)
307 | FEATURE_MASK(FEATURE_OUT_OF_BAND_MONITOR_BIT)
308 | FEATURE_MASK(FEATURE_TEMP_DEPENDENT_VMIN_BIT);
309
310 if (adev->pm.pp_feature & PP_SCLK_DPM_MASK)
311 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT);
312
313 if (adev->pm.pp_feature & PP_PCIE_DPM_MASK)
314 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT);
315
316 if (adev->pm.pp_feature & PP_DCEFCLK_DPM_MASK)
317 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT);
318
319 if (adev->pm.pp_feature & PP_ULV_MASK)
320 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT);
321
322 if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
323 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
324
325 if (adev->pm.pp_feature & PP_GFXOFF_MASK)
326 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT);
327
328 if (smu->adev->pg_flags & AMD_PG_SUPPORT_MMHUB)
329 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MMHUB_PG_BIT);
330
331 if (smu->adev->pg_flags & AMD_PG_SUPPORT_ATHUB)
332 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ATHUB_PG_BIT);
333
334 if (smu->adev->pg_flags & AMD_PG_SUPPORT_VCN)
335 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VCN_PG_BIT);
336
337 if (smu->adev->pg_flags & AMD_PG_SUPPORT_JPEG)
338 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_JPEG_PG_BIT);
339
340 if (smu->dc_controlled_by_gpio)
341 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_ACDC_BIT);
342
343 if (adev->pm.pp_feature & PP_SOCCLK_DPM_MASK)
344 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_SOCCLK_BIT);
345
346 /* DPM UCLK enablement should be skipped for navi10 A0 secure board */
347 if (!(is_asic_secure(smu) &&
348 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
349 (adev->rev_id == 0)) &&
350 (adev->pm.pp_feature & PP_MCLK_DPM_MASK))
351 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT)
352 | FEATURE_MASK(FEATURE_MEM_VDDCI_SCALING_BIT)
353 | FEATURE_MASK(FEATURE_MEM_MVDD_SCALING_BIT);
354
355 /* DS SOCCLK enablement should be skipped for navi10 A0 secure board */
356 if (is_asic_secure(smu) &&
357 (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
358 (adev->rev_id == 0))
359 *(uint64_t *)feature_mask &=
360 ~FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
361
362 return 0;
363 }
364
navi10_check_bxco_support(struct smu_context * smu)365 static void navi10_check_bxco_support(struct smu_context *smu)
366 {
367 struct smu_table_context *table_context = &smu->smu_table;
368 struct smu_11_0_powerplay_table *powerplay_table =
369 table_context->power_play_table;
370 struct smu_baco_context *smu_baco = &smu->smu_baco;
371 struct amdgpu_device *adev = smu->adev;
372 uint32_t val;
373
374 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_BACO ||
375 powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_MACO) {
376 val = RREG32_SOC15(NBIO, 0, mmRCC_BIF_STRAP0);
377 smu_baco->platform_support =
378 (val & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) ? true :
379 false;
380 }
381 }
382
navi10_check_powerplay_table(struct smu_context * smu)383 static int navi10_check_powerplay_table(struct smu_context *smu)
384 {
385 struct smu_table_context *table_context = &smu->smu_table;
386 struct smu_11_0_powerplay_table *powerplay_table =
387 table_context->power_play_table;
388
389 if (powerplay_table->platform_caps & SMU_11_0_PP_PLATFORM_CAP_HARDWAREDC)
390 smu->dc_controlled_by_gpio = true;
391
392 navi10_check_bxco_support(smu);
393
394 table_context->thermal_controller_type =
395 powerplay_table->thermal_controller_type;
396
397 /*
398 * Instead of having its own buffer space and get overdrive_table copied,
399 * smu->od_settings just points to the actual overdrive_table
400 */
401 smu->od_settings = &powerplay_table->overdrive_table;
402
403 return 0;
404 }
405
navi10_append_powerplay_table(struct smu_context * smu)406 static int navi10_append_powerplay_table(struct smu_context *smu)
407 {
408 struct amdgpu_device *adev = smu->adev;
409 struct smu_table_context *table_context = &smu->smu_table;
410 PPTable_t *smc_pptable = table_context->driver_pptable;
411 struct atom_smc_dpm_info_v4_5 *smc_dpm_table;
412 struct atom_smc_dpm_info_v4_7 *smc_dpm_table_v4_7;
413 int index, ret;
414
415 index = get_index_into_master_table(atom_master_list_of_data_tables_v2_1,
416 smc_dpm_info);
417
418 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
419 (uint8_t **)&smc_dpm_table);
420 if (ret)
421 return ret;
422
423 dev_info(adev->dev, "smc_dpm_info table revision(format.content): %d.%d\n",
424 smc_dpm_table->table_header.format_revision,
425 smc_dpm_table->table_header.content_revision);
426
427 if (smc_dpm_table->table_header.format_revision != 4) {
428 dev_err(adev->dev, "smc_dpm_info table format revision is not 4!\n");
429 return -EINVAL;
430 }
431
432 switch (smc_dpm_table->table_header.content_revision) {
433 case 5: /* nv10 and nv14 */
434 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
435 smc_dpm_table, I2cControllers);
436 break;
437 case 7: /* nv12 */
438 ret = amdgpu_atombios_get_data_table(adev, index, NULL, NULL, NULL,
439 (uint8_t **)&smc_dpm_table_v4_7);
440 if (ret)
441 return ret;
442 smu_memcpy_trailing(smc_pptable, I2cControllers, BoardReserved,
443 smc_dpm_table_v4_7, I2cControllers);
444 break;
445 default:
446 dev_err(smu->adev->dev, "smc_dpm_info with unsupported content revision %d!\n",
447 smc_dpm_table->table_header.content_revision);
448 return -EINVAL;
449 }
450
451 if (adev->pm.pp_feature & PP_GFXOFF_MASK) {
452 /* TODO: remove it once SMU fw fix it */
453 smc_pptable->DebugOverrides |= DPM_OVERRIDE_DISABLE_DFLL_PLL_SHUTDOWN;
454 }
455
456 return 0;
457 }
458
navi10_store_powerplay_table(struct smu_context * smu)459 static int navi10_store_powerplay_table(struct smu_context *smu)
460 {
461 struct smu_table_context *table_context = &smu->smu_table;
462 struct smu_11_0_powerplay_table *powerplay_table =
463 table_context->power_play_table;
464
465 memcpy(table_context->driver_pptable, &powerplay_table->smc_pptable,
466 sizeof(PPTable_t));
467
468 return 0;
469 }
470
navi10_setup_pptable(struct smu_context * smu)471 static int navi10_setup_pptable(struct smu_context *smu)
472 {
473 int ret = 0;
474
475 ret = smu_v11_0_setup_pptable(smu);
476 if (ret)
477 return ret;
478
479 ret = navi10_store_powerplay_table(smu);
480 if (ret)
481 return ret;
482
483 ret = navi10_append_powerplay_table(smu);
484 if (ret)
485 return ret;
486
487 ret = navi10_check_powerplay_table(smu);
488 if (ret)
489 return ret;
490
491 return ret;
492 }
493
navi10_tables_init(struct smu_context * smu)494 static int navi10_tables_init(struct smu_context *smu)
495 {
496 struct smu_table_context *smu_table = &smu->smu_table;
497 struct smu_table *tables = smu_table->tables;
498 struct smu_table *dummy_read_1_table =
499 &smu_table->dummy_read_1_table;
500
501 SMU_TABLE_INIT(tables, SMU_TABLE_PPTABLE, sizeof(PPTable_t),
502 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
503 SMU_TABLE_INIT(tables, SMU_TABLE_WATERMARKS, sizeof(Watermarks_t),
504 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
505 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS, sizeof(SmuMetrics_NV1X_t),
506 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
507 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
508 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
509 SMU_TABLE_INIT(tables, SMU_TABLE_OVERDRIVE, sizeof(OverDriveTable_t),
510 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
511 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU11_TOOL_SIZE,
512 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
513 SMU_TABLE_INIT(tables, SMU_TABLE_ACTIVITY_MONITOR_COEFF,
514 sizeof(DpmActivityMonitorCoeffInt_t), PAGE_SIZE,
515 AMDGPU_GEM_DOMAIN_VRAM);
516 SMU_TABLE_INIT(tables, SMU_TABLE_DRIVER_SMU_CONFIG, sizeof(DriverSmuConfig_t),
517 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
518
519 dummy_read_1_table->size = 0x40000;
520 dummy_read_1_table->align = PAGE_SIZE;
521 dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
522
523 smu_table->metrics_table = kzalloc(sizeof(SmuMetrics_NV1X_t),
524 GFP_KERNEL);
525 if (!smu_table->metrics_table)
526 goto err0_out;
527 smu_table->metrics_time = 0;
528
529 smu_table->gpu_metrics_table_size = sizeof(struct gpu_metrics_v1_3);
530 smu_table->gpu_metrics_table = kzalloc(smu_table->gpu_metrics_table_size, GFP_KERNEL);
531 if (!smu_table->gpu_metrics_table)
532 goto err1_out;
533
534 smu_table->watermarks_table = kzalloc(sizeof(Watermarks_t), GFP_KERNEL);
535 if (!smu_table->watermarks_table)
536 goto err2_out;
537
538 smu_table->driver_smu_config_table =
539 kzalloc(tables[SMU_TABLE_DRIVER_SMU_CONFIG].size, GFP_KERNEL);
540 if (!smu_table->driver_smu_config_table)
541 goto err3_out;
542
543 return 0;
544
545 err3_out:
546 kfree(smu_table->watermarks_table);
547 err2_out:
548 kfree(smu_table->gpu_metrics_table);
549 err1_out:
550 kfree(smu_table->metrics_table);
551 err0_out:
552 return -ENOMEM;
553 }
554
navi10_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)555 static int navi10_get_legacy_smu_metrics_data(struct smu_context *smu,
556 MetricsMember_t member,
557 uint32_t *value)
558 {
559 struct smu_table_context *smu_table = &smu->smu_table;
560 SmuMetrics_legacy_t *metrics =
561 (SmuMetrics_legacy_t *)smu_table->metrics_table;
562 int ret = 0;
563
564 ret = smu_cmn_get_metrics_table(smu,
565 NULL,
566 false);
567 if (ret)
568 return ret;
569
570 switch (member) {
571 case METRICS_CURR_GFXCLK:
572 *value = metrics->CurrClock[PPCLK_GFXCLK];
573 break;
574 case METRICS_CURR_SOCCLK:
575 *value = metrics->CurrClock[PPCLK_SOCCLK];
576 break;
577 case METRICS_CURR_UCLK:
578 *value = metrics->CurrClock[PPCLK_UCLK];
579 break;
580 case METRICS_CURR_VCLK:
581 *value = metrics->CurrClock[PPCLK_VCLK];
582 break;
583 case METRICS_CURR_DCLK:
584 *value = metrics->CurrClock[PPCLK_DCLK];
585 break;
586 case METRICS_CURR_DCEFCLK:
587 *value = metrics->CurrClock[PPCLK_DCEFCLK];
588 break;
589 case METRICS_AVERAGE_GFXCLK:
590 *value = metrics->AverageGfxclkFrequency;
591 break;
592 case METRICS_AVERAGE_SOCCLK:
593 *value = metrics->AverageSocclkFrequency;
594 break;
595 case METRICS_AVERAGE_UCLK:
596 *value = metrics->AverageUclkFrequency;
597 break;
598 case METRICS_AVERAGE_GFXACTIVITY:
599 *value = metrics->AverageGfxActivity;
600 break;
601 case METRICS_AVERAGE_MEMACTIVITY:
602 *value = metrics->AverageUclkActivity;
603 break;
604 case METRICS_AVERAGE_SOCKETPOWER:
605 *value = metrics->AverageSocketPower << 8;
606 break;
607 case METRICS_TEMPERATURE_EDGE:
608 *value = metrics->TemperatureEdge *
609 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
610 break;
611 case METRICS_TEMPERATURE_HOTSPOT:
612 *value = metrics->TemperatureHotspot *
613 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
614 break;
615 case METRICS_TEMPERATURE_MEM:
616 *value = metrics->TemperatureMem *
617 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
618 break;
619 case METRICS_TEMPERATURE_VRGFX:
620 *value = metrics->TemperatureVrGfx *
621 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
622 break;
623 case METRICS_TEMPERATURE_VRSOC:
624 *value = metrics->TemperatureVrSoc *
625 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
626 break;
627 case METRICS_THROTTLER_STATUS:
628 *value = metrics->ThrottlerStatus;
629 break;
630 case METRICS_CURR_FANSPEED:
631 *value = metrics->CurrFanSpeed;
632 break;
633 default:
634 *value = UINT_MAX;
635 break;
636 }
637
638 return ret;
639 }
640
navi10_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)641 static int navi10_get_smu_metrics_data(struct smu_context *smu,
642 MetricsMember_t member,
643 uint32_t *value)
644 {
645 struct smu_table_context *smu_table = &smu->smu_table;
646 SmuMetrics_t *metrics =
647 (SmuMetrics_t *)smu_table->metrics_table;
648 int ret = 0;
649
650 ret = smu_cmn_get_metrics_table(smu,
651 NULL,
652 false);
653 if (ret)
654 return ret;
655
656 switch (member) {
657 case METRICS_CURR_GFXCLK:
658 *value = metrics->CurrClock[PPCLK_GFXCLK];
659 break;
660 case METRICS_CURR_SOCCLK:
661 *value = metrics->CurrClock[PPCLK_SOCCLK];
662 break;
663 case METRICS_CURR_UCLK:
664 *value = metrics->CurrClock[PPCLK_UCLK];
665 break;
666 case METRICS_CURR_VCLK:
667 *value = metrics->CurrClock[PPCLK_VCLK];
668 break;
669 case METRICS_CURR_DCLK:
670 *value = metrics->CurrClock[PPCLK_DCLK];
671 break;
672 case METRICS_CURR_DCEFCLK:
673 *value = metrics->CurrClock[PPCLK_DCEFCLK];
674 break;
675 case METRICS_AVERAGE_GFXCLK:
676 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
677 *value = metrics->AverageGfxclkFrequencyPreDs;
678 else
679 *value = metrics->AverageGfxclkFrequencyPostDs;
680 break;
681 case METRICS_AVERAGE_SOCCLK:
682 *value = metrics->AverageSocclkFrequency;
683 break;
684 case METRICS_AVERAGE_UCLK:
685 *value = metrics->AverageUclkFrequencyPostDs;
686 break;
687 case METRICS_AVERAGE_GFXACTIVITY:
688 *value = metrics->AverageGfxActivity;
689 break;
690 case METRICS_AVERAGE_MEMACTIVITY:
691 *value = metrics->AverageUclkActivity;
692 break;
693 case METRICS_AVERAGE_SOCKETPOWER:
694 *value = metrics->AverageSocketPower << 8;
695 break;
696 case METRICS_TEMPERATURE_EDGE:
697 *value = metrics->TemperatureEdge *
698 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
699 break;
700 case METRICS_TEMPERATURE_HOTSPOT:
701 *value = metrics->TemperatureHotspot *
702 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
703 break;
704 case METRICS_TEMPERATURE_MEM:
705 *value = metrics->TemperatureMem *
706 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
707 break;
708 case METRICS_TEMPERATURE_VRGFX:
709 *value = metrics->TemperatureVrGfx *
710 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
711 break;
712 case METRICS_TEMPERATURE_VRSOC:
713 *value = metrics->TemperatureVrSoc *
714 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
715 break;
716 case METRICS_THROTTLER_STATUS:
717 *value = metrics->ThrottlerStatus;
718 break;
719 case METRICS_CURR_FANSPEED:
720 *value = metrics->CurrFanSpeed;
721 break;
722 default:
723 *value = UINT_MAX;
724 break;
725 }
726
727 return ret;
728 }
729
navi12_get_legacy_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)730 static int navi12_get_legacy_smu_metrics_data(struct smu_context *smu,
731 MetricsMember_t member,
732 uint32_t *value)
733 {
734 struct smu_table_context *smu_table = &smu->smu_table;
735 SmuMetrics_NV12_legacy_t *metrics =
736 (SmuMetrics_NV12_legacy_t *)smu_table->metrics_table;
737 int ret = 0;
738
739 ret = smu_cmn_get_metrics_table(smu,
740 NULL,
741 false);
742 if (ret)
743 return ret;
744
745 switch (member) {
746 case METRICS_CURR_GFXCLK:
747 *value = metrics->CurrClock[PPCLK_GFXCLK];
748 break;
749 case METRICS_CURR_SOCCLK:
750 *value = metrics->CurrClock[PPCLK_SOCCLK];
751 break;
752 case METRICS_CURR_UCLK:
753 *value = metrics->CurrClock[PPCLK_UCLK];
754 break;
755 case METRICS_CURR_VCLK:
756 *value = metrics->CurrClock[PPCLK_VCLK];
757 break;
758 case METRICS_CURR_DCLK:
759 *value = metrics->CurrClock[PPCLK_DCLK];
760 break;
761 case METRICS_CURR_DCEFCLK:
762 *value = metrics->CurrClock[PPCLK_DCEFCLK];
763 break;
764 case METRICS_AVERAGE_GFXCLK:
765 *value = metrics->AverageGfxclkFrequency;
766 break;
767 case METRICS_AVERAGE_SOCCLK:
768 *value = metrics->AverageSocclkFrequency;
769 break;
770 case METRICS_AVERAGE_UCLK:
771 *value = metrics->AverageUclkFrequency;
772 break;
773 case METRICS_AVERAGE_GFXACTIVITY:
774 *value = metrics->AverageGfxActivity;
775 break;
776 case METRICS_AVERAGE_MEMACTIVITY:
777 *value = metrics->AverageUclkActivity;
778 break;
779 case METRICS_AVERAGE_SOCKETPOWER:
780 *value = metrics->AverageSocketPower << 8;
781 break;
782 case METRICS_TEMPERATURE_EDGE:
783 *value = metrics->TemperatureEdge *
784 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
785 break;
786 case METRICS_TEMPERATURE_HOTSPOT:
787 *value = metrics->TemperatureHotspot *
788 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
789 break;
790 case METRICS_TEMPERATURE_MEM:
791 *value = metrics->TemperatureMem *
792 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
793 break;
794 case METRICS_TEMPERATURE_VRGFX:
795 *value = metrics->TemperatureVrGfx *
796 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
797 break;
798 case METRICS_TEMPERATURE_VRSOC:
799 *value = metrics->TemperatureVrSoc *
800 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
801 break;
802 case METRICS_THROTTLER_STATUS:
803 *value = metrics->ThrottlerStatus;
804 break;
805 case METRICS_CURR_FANSPEED:
806 *value = metrics->CurrFanSpeed;
807 break;
808 default:
809 *value = UINT_MAX;
810 break;
811 }
812
813 return ret;
814 }
815
navi12_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)816 static int navi12_get_smu_metrics_data(struct smu_context *smu,
817 MetricsMember_t member,
818 uint32_t *value)
819 {
820 struct smu_table_context *smu_table = &smu->smu_table;
821 SmuMetrics_NV12_t *metrics =
822 (SmuMetrics_NV12_t *)smu_table->metrics_table;
823 int ret = 0;
824
825 ret = smu_cmn_get_metrics_table(smu,
826 NULL,
827 false);
828 if (ret)
829 return ret;
830
831 switch (member) {
832 case METRICS_CURR_GFXCLK:
833 *value = metrics->CurrClock[PPCLK_GFXCLK];
834 break;
835 case METRICS_CURR_SOCCLK:
836 *value = metrics->CurrClock[PPCLK_SOCCLK];
837 break;
838 case METRICS_CURR_UCLK:
839 *value = metrics->CurrClock[PPCLK_UCLK];
840 break;
841 case METRICS_CURR_VCLK:
842 *value = metrics->CurrClock[PPCLK_VCLK];
843 break;
844 case METRICS_CURR_DCLK:
845 *value = metrics->CurrClock[PPCLK_DCLK];
846 break;
847 case METRICS_CURR_DCEFCLK:
848 *value = metrics->CurrClock[PPCLK_DCEFCLK];
849 break;
850 case METRICS_AVERAGE_GFXCLK:
851 if (metrics->AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
852 *value = metrics->AverageGfxclkFrequencyPreDs;
853 else
854 *value = metrics->AverageGfxclkFrequencyPostDs;
855 break;
856 case METRICS_AVERAGE_SOCCLK:
857 *value = metrics->AverageSocclkFrequency;
858 break;
859 case METRICS_AVERAGE_UCLK:
860 *value = metrics->AverageUclkFrequencyPostDs;
861 break;
862 case METRICS_AVERAGE_GFXACTIVITY:
863 *value = metrics->AverageGfxActivity;
864 break;
865 case METRICS_AVERAGE_MEMACTIVITY:
866 *value = metrics->AverageUclkActivity;
867 break;
868 case METRICS_AVERAGE_SOCKETPOWER:
869 *value = metrics->AverageSocketPower << 8;
870 break;
871 case METRICS_TEMPERATURE_EDGE:
872 *value = metrics->TemperatureEdge *
873 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
874 break;
875 case METRICS_TEMPERATURE_HOTSPOT:
876 *value = metrics->TemperatureHotspot *
877 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
878 break;
879 case METRICS_TEMPERATURE_MEM:
880 *value = metrics->TemperatureMem *
881 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
882 break;
883 case METRICS_TEMPERATURE_VRGFX:
884 *value = metrics->TemperatureVrGfx *
885 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
886 break;
887 case METRICS_TEMPERATURE_VRSOC:
888 *value = metrics->TemperatureVrSoc *
889 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
890 break;
891 case METRICS_THROTTLER_STATUS:
892 *value = metrics->ThrottlerStatus;
893 break;
894 case METRICS_CURR_FANSPEED:
895 *value = metrics->CurrFanSpeed;
896 break;
897 default:
898 *value = UINT_MAX;
899 break;
900 }
901
902 return ret;
903 }
904
navi1x_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)905 static int navi1x_get_smu_metrics_data(struct smu_context *smu,
906 MetricsMember_t member,
907 uint32_t *value)
908 {
909 struct amdgpu_device *adev = smu->adev;
910 int ret = 0;
911
912 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
913 case IP_VERSION(11, 0, 9):
914 if (smu->smc_fw_version > 0x00341C00)
915 ret = navi12_get_smu_metrics_data(smu, member, value);
916 else
917 ret = navi12_get_legacy_smu_metrics_data(smu, member, value);
918 break;
919 case IP_VERSION(11, 0, 0):
920 case IP_VERSION(11, 0, 5):
921 default:
922 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
923 IP_VERSION(11, 0, 5)) &&
924 smu->smc_fw_version > 0x00351F00) ||
925 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
926 IP_VERSION(11, 0, 0)) &&
927 smu->smc_fw_version > 0x002A3B00))
928 ret = navi10_get_smu_metrics_data(smu, member, value);
929 else
930 ret = navi10_get_legacy_smu_metrics_data(smu, member, value);
931 break;
932 }
933
934 return ret;
935 }
936
navi10_allocate_dpm_context(struct smu_context * smu)937 static int navi10_allocate_dpm_context(struct smu_context *smu)
938 {
939 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
940
941 smu_dpm->dpm_context = kzalloc(sizeof(struct smu_11_0_dpm_context),
942 GFP_KERNEL);
943 if (!smu_dpm->dpm_context)
944 return -ENOMEM;
945
946 smu_dpm->dpm_context_size = sizeof(struct smu_11_0_dpm_context);
947
948 return 0;
949 }
950
navi10_init_smc_tables(struct smu_context * smu)951 static int navi10_init_smc_tables(struct smu_context *smu)
952 {
953 int ret = 0;
954
955 ret = navi10_tables_init(smu);
956 if (ret)
957 return ret;
958
959 ret = navi10_allocate_dpm_context(smu);
960 if (ret)
961 return ret;
962
963 return smu_v11_0_init_smc_tables(smu);
964 }
965
navi10_set_default_dpm_table(struct smu_context * smu)966 static int navi10_set_default_dpm_table(struct smu_context *smu)
967 {
968 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
969 PPTable_t *driver_ppt = smu->smu_table.driver_pptable;
970 struct smu_11_0_dpm_table *dpm_table;
971 int ret = 0;
972
973 /* socclk dpm table setup */
974 dpm_table = &dpm_context->dpm_tables.soc_table;
975 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
976 ret = smu_v11_0_set_single_dpm_table(smu,
977 SMU_SOCCLK,
978 dpm_table);
979 if (ret)
980 return ret;
981 dpm_table->is_fine_grained =
982 !driver_ppt->DpmDescriptor[PPCLK_SOCCLK].SnapToDiscrete;
983 } else {
984 dpm_table->count = 1;
985 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.socclk / 100;
986 dpm_table->dpm_levels[0].enabled = true;
987 dpm_table->min = dpm_table->dpm_levels[0].value;
988 dpm_table->max = dpm_table->dpm_levels[0].value;
989 }
990
991 /* gfxclk dpm table setup */
992 dpm_table = &dpm_context->dpm_tables.gfx_table;
993 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
994 ret = smu_v11_0_set_single_dpm_table(smu,
995 SMU_GFXCLK,
996 dpm_table);
997 if (ret)
998 return ret;
999 dpm_table->is_fine_grained =
1000 !driver_ppt->DpmDescriptor[PPCLK_GFXCLK].SnapToDiscrete;
1001 } else {
1002 dpm_table->count = 1;
1003 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
1004 dpm_table->dpm_levels[0].enabled = true;
1005 dpm_table->min = dpm_table->dpm_levels[0].value;
1006 dpm_table->max = dpm_table->dpm_levels[0].value;
1007 }
1008
1009 /* uclk dpm table setup */
1010 dpm_table = &dpm_context->dpm_tables.uclk_table;
1011 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1012 ret = smu_v11_0_set_single_dpm_table(smu,
1013 SMU_UCLK,
1014 dpm_table);
1015 if (ret)
1016 return ret;
1017 dpm_table->is_fine_grained =
1018 !driver_ppt->DpmDescriptor[PPCLK_UCLK].SnapToDiscrete;
1019 } else {
1020 dpm_table->count = 1;
1021 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.uclk / 100;
1022 dpm_table->dpm_levels[0].enabled = true;
1023 dpm_table->min = dpm_table->dpm_levels[0].value;
1024 dpm_table->max = dpm_table->dpm_levels[0].value;
1025 }
1026
1027 /* vclk dpm table setup */
1028 dpm_table = &dpm_context->dpm_tables.vclk_table;
1029 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1030 ret = smu_v11_0_set_single_dpm_table(smu,
1031 SMU_VCLK,
1032 dpm_table);
1033 if (ret)
1034 return ret;
1035 dpm_table->is_fine_grained =
1036 !driver_ppt->DpmDescriptor[PPCLK_VCLK].SnapToDiscrete;
1037 } else {
1038 dpm_table->count = 1;
1039 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.vclk / 100;
1040 dpm_table->dpm_levels[0].enabled = true;
1041 dpm_table->min = dpm_table->dpm_levels[0].value;
1042 dpm_table->max = dpm_table->dpm_levels[0].value;
1043 }
1044
1045 /* dclk dpm table setup */
1046 dpm_table = &dpm_context->dpm_tables.dclk_table;
1047 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1048 ret = smu_v11_0_set_single_dpm_table(smu,
1049 SMU_DCLK,
1050 dpm_table);
1051 if (ret)
1052 return ret;
1053 dpm_table->is_fine_grained =
1054 !driver_ppt->DpmDescriptor[PPCLK_DCLK].SnapToDiscrete;
1055 } else {
1056 dpm_table->count = 1;
1057 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dclk / 100;
1058 dpm_table->dpm_levels[0].enabled = true;
1059 dpm_table->min = dpm_table->dpm_levels[0].value;
1060 dpm_table->max = dpm_table->dpm_levels[0].value;
1061 }
1062
1063 /* dcefclk dpm table setup */
1064 dpm_table = &dpm_context->dpm_tables.dcef_table;
1065 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1066 ret = smu_v11_0_set_single_dpm_table(smu,
1067 SMU_DCEFCLK,
1068 dpm_table);
1069 if (ret)
1070 return ret;
1071 dpm_table->is_fine_grained =
1072 !driver_ppt->DpmDescriptor[PPCLK_DCEFCLK].SnapToDiscrete;
1073 } else {
1074 dpm_table->count = 1;
1075 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1076 dpm_table->dpm_levels[0].enabled = true;
1077 dpm_table->min = dpm_table->dpm_levels[0].value;
1078 dpm_table->max = dpm_table->dpm_levels[0].value;
1079 }
1080
1081 /* pixelclk dpm table setup */
1082 dpm_table = &dpm_context->dpm_tables.pixel_table;
1083 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1084 ret = smu_v11_0_set_single_dpm_table(smu,
1085 SMU_PIXCLK,
1086 dpm_table);
1087 if (ret)
1088 return ret;
1089 dpm_table->is_fine_grained =
1090 !driver_ppt->DpmDescriptor[PPCLK_PIXCLK].SnapToDiscrete;
1091 } else {
1092 dpm_table->count = 1;
1093 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1094 dpm_table->dpm_levels[0].enabled = true;
1095 dpm_table->min = dpm_table->dpm_levels[0].value;
1096 dpm_table->max = dpm_table->dpm_levels[0].value;
1097 }
1098
1099 /* displayclk dpm table setup */
1100 dpm_table = &dpm_context->dpm_tables.display_table;
1101 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1102 ret = smu_v11_0_set_single_dpm_table(smu,
1103 SMU_DISPCLK,
1104 dpm_table);
1105 if (ret)
1106 return ret;
1107 dpm_table->is_fine_grained =
1108 !driver_ppt->DpmDescriptor[PPCLK_DISPCLK].SnapToDiscrete;
1109 } else {
1110 dpm_table->count = 1;
1111 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1112 dpm_table->dpm_levels[0].enabled = true;
1113 dpm_table->min = dpm_table->dpm_levels[0].value;
1114 dpm_table->max = dpm_table->dpm_levels[0].value;
1115 }
1116
1117 /* phyclk dpm table setup */
1118 dpm_table = &dpm_context->dpm_tables.phy_table;
1119 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
1120 ret = smu_v11_0_set_single_dpm_table(smu,
1121 SMU_PHYCLK,
1122 dpm_table);
1123 if (ret)
1124 return ret;
1125 dpm_table->is_fine_grained =
1126 !driver_ppt->DpmDescriptor[PPCLK_PHYCLK].SnapToDiscrete;
1127 } else {
1128 dpm_table->count = 1;
1129 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100;
1130 dpm_table->dpm_levels[0].enabled = true;
1131 dpm_table->min = dpm_table->dpm_levels[0].value;
1132 dpm_table->max = dpm_table->dpm_levels[0].value;
1133 }
1134
1135 return 0;
1136 }
1137
navi10_dpm_set_vcn_enable(struct smu_context * smu,bool enable)1138 static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
1139 {
1140 int ret = 0;
1141
1142 if (enable) {
1143 /* vcn dpm on is a prerequisite for vcn power gate messages */
1144 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1145 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_PowerUpVcn, 1, NULL);
1146 if (ret)
1147 return ret;
1148 }
1149 } else {
1150 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_VCN_PG_BIT)) {
1151 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownVcn, NULL);
1152 if (ret)
1153 return ret;
1154 }
1155 }
1156
1157 return ret;
1158 }
1159
navi10_dpm_set_jpeg_enable(struct smu_context * smu,bool enable)1160 static int navi10_dpm_set_jpeg_enable(struct smu_context *smu, bool enable)
1161 {
1162 int ret = 0;
1163
1164 if (enable) {
1165 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1166 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerUpJpeg, NULL);
1167 if (ret)
1168 return ret;
1169 }
1170 } else {
1171 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_JPEG_PG_BIT)) {
1172 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PowerDownJpeg, NULL);
1173 if (ret)
1174 return ret;
1175 }
1176 }
1177
1178 return ret;
1179 }
1180
navi10_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1181 static int navi10_get_current_clk_freq_by_table(struct smu_context *smu,
1182 enum smu_clk_type clk_type,
1183 uint32_t *value)
1184 {
1185 MetricsMember_t member_type;
1186 int clk_id = 0;
1187
1188 clk_id = smu_cmn_to_asic_specific_index(smu,
1189 CMN2ASIC_MAPPING_CLK,
1190 clk_type);
1191 if (clk_id < 0)
1192 return clk_id;
1193
1194 switch (clk_id) {
1195 case PPCLK_GFXCLK:
1196 member_type = METRICS_CURR_GFXCLK;
1197 break;
1198 case PPCLK_UCLK:
1199 member_type = METRICS_CURR_UCLK;
1200 break;
1201 case PPCLK_SOCCLK:
1202 member_type = METRICS_CURR_SOCCLK;
1203 break;
1204 case PPCLK_VCLK:
1205 member_type = METRICS_CURR_VCLK;
1206 break;
1207 case PPCLK_DCLK:
1208 member_type = METRICS_CURR_DCLK;
1209 break;
1210 case PPCLK_DCEFCLK:
1211 member_type = METRICS_CURR_DCEFCLK;
1212 break;
1213 default:
1214 return -EINVAL;
1215 }
1216
1217 return navi1x_get_smu_metrics_data(smu,
1218 member_type,
1219 value);
1220 }
1221
navi10_is_support_fine_grained_dpm(struct smu_context * smu,enum smu_clk_type clk_type)1222 static int navi10_is_support_fine_grained_dpm(struct smu_context *smu, enum smu_clk_type clk_type)
1223 {
1224 PPTable_t *pptable = smu->smu_table.driver_pptable;
1225 DpmDescriptor_t *dpm_desc = NULL;
1226 int clk_index = 0;
1227
1228 clk_index = smu_cmn_to_asic_specific_index(smu,
1229 CMN2ASIC_MAPPING_CLK,
1230 clk_type);
1231 if (clk_index < 0)
1232 return clk_index;
1233
1234 dpm_desc = &pptable->DpmDescriptor[clk_index];
1235
1236 /* 0 - Fine grained DPM, 1 - Discrete DPM */
1237 return dpm_desc->SnapToDiscrete == 0 ? 1 : 0;
1238 }
1239
navi10_od_feature_is_supported(struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODFEATURE_CAP cap)1240 static inline bool navi10_od_feature_is_supported(struct smu_11_0_overdrive_table *od_table, enum SMU_11_0_ODFEATURE_CAP cap)
1241 {
1242 return od_table->cap[cap];
1243 }
1244
navi10_od_setting_get_range(struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODSETTING_ID setting,uint32_t * min,uint32_t * max)1245 static void navi10_od_setting_get_range(struct smu_11_0_overdrive_table *od_table,
1246 enum SMU_11_0_ODSETTING_ID setting,
1247 uint32_t *min, uint32_t *max)
1248 {
1249 if (min)
1250 *min = od_table->min[setting];
1251 if (max)
1252 *max = od_table->max[setting];
1253 }
1254
navi10_emit_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf,int * offset)1255 static int navi10_emit_clk_levels(struct smu_context *smu,
1256 enum smu_clk_type clk_type,
1257 char *buf,
1258 int *offset)
1259 {
1260 uint16_t *curve_settings;
1261 int ret = 0;
1262 uint32_t cur_value = 0, value = 0;
1263 uint32_t freq_values[3] = {0};
1264 uint32_t i, levels, mark_index = 0, count = 0;
1265 struct smu_table_context *table_context = &smu->smu_table;
1266 uint32_t gen_speed, lane_width;
1267 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1268 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1269 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1270 OverDriveTable_t *od_table =
1271 (OverDriveTable_t *)table_context->overdrive_table;
1272 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1273 uint32_t min_value, max_value;
1274
1275 switch (clk_type) {
1276 case SMU_GFXCLK:
1277 case SMU_SCLK:
1278 case SMU_SOCCLK:
1279 case SMU_MCLK:
1280 case SMU_UCLK:
1281 case SMU_FCLK:
1282 case SMU_VCLK:
1283 case SMU_DCLK:
1284 case SMU_DCEFCLK:
1285 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1286 if (ret)
1287 return ret;
1288
1289 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1290 if (ret)
1291 return ret;
1292
1293 ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
1294 if (ret < 0)
1295 return ret;
1296
1297 if (!ret) {
1298 for (i = 0; i < count; i++) {
1299 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1300 clk_type, i, &value);
1301 if (ret)
1302 return ret;
1303
1304 *offset += sysfs_emit_at(buf, *offset,
1305 "%d: %uMhz %s\n",
1306 i, value,
1307 cur_value == value ? "*" : "");
1308 }
1309 } else {
1310 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1311 clk_type, 0, &freq_values[0]);
1312 if (ret)
1313 return ret;
1314 ret = smu_v11_0_get_dpm_freq_by_index(smu,
1315 clk_type,
1316 count - 1,
1317 &freq_values[2]);
1318 if (ret)
1319 return ret;
1320
1321 freq_values[1] = cur_value;
1322 mark_index = cur_value == freq_values[0] ? 0 :
1323 cur_value == freq_values[2] ? 2 : 1;
1324
1325 levels = 3;
1326 if (mark_index != 1) {
1327 levels = 2;
1328 freq_values[1] = freq_values[2];
1329 }
1330
1331 for (i = 0; i < levels; i++) {
1332 *offset += sysfs_emit_at(buf, *offset,
1333 "%d: %uMhz %s\n",
1334 i, freq_values[i],
1335 i == mark_index ? "*" : "");
1336 }
1337 }
1338 break;
1339 case SMU_PCIE:
1340 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1341 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1342 for (i = 0; i < NUM_LINK_LEVELS; i++) {
1343 *offset += sysfs_emit_at(buf, *offset, "%d: %s %s %dMhz %s\n", i,
1344 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1345 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1346 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1347 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1348 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1349 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1350 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1351 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1352 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1353 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1354 pptable->LclkFreq[i],
1355 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1356 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1357 "*" : "");
1358 }
1359 break;
1360 case SMU_OD_SCLK:
1361 if (!smu->od_enabled || !od_table || !od_settings)
1362 return -EOPNOTSUPP;
1363 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1364 break;
1365 *offset += sysfs_emit_at(buf, *offset, "OD_SCLK:\n0: %uMhz\n1: %uMhz\n",
1366 od_table->GfxclkFmin, od_table->GfxclkFmax);
1367 break;
1368 case SMU_OD_MCLK:
1369 if (!smu->od_enabled || !od_table || !od_settings)
1370 return -EOPNOTSUPP;
1371 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1372 break;
1373 *offset += sysfs_emit_at(buf, *offset, "OD_MCLK:\n1: %uMHz\n", od_table->UclkFmax);
1374 break;
1375 case SMU_OD_VDDC_CURVE:
1376 if (!smu->od_enabled || !od_table || !od_settings)
1377 return -EOPNOTSUPP;
1378 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1379 break;
1380 *offset += sysfs_emit_at(buf, *offset, "OD_VDDC_CURVE:\n");
1381 for (i = 0; i < 3; i++) {
1382 switch (i) {
1383 case 0:
1384 curve_settings = &od_table->GfxclkFreq1;
1385 break;
1386 case 1:
1387 curve_settings = &od_table->GfxclkFreq2;
1388 break;
1389 case 2:
1390 curve_settings = &od_table->GfxclkFreq3;
1391 break;
1392 }
1393 *offset += sysfs_emit_at(buf, *offset, "%d: %uMHz %umV\n",
1394 i, curve_settings[0],
1395 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1396 }
1397 break;
1398 case SMU_OD_RANGE:
1399 if (!smu->od_enabled || !od_table || !od_settings)
1400 return -EOPNOTSUPP;
1401 *offset += sysfs_emit_at(buf, *offset, "%s:\n", "OD_RANGE");
1402
1403 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1404 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1405 &min_value, NULL);
1406 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1407 NULL, &max_value);
1408 *offset += sysfs_emit_at(buf, *offset, "SCLK: %7uMhz %10uMhz\n",
1409 min_value, max_value);
1410 }
1411
1412 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1413 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1414 &min_value, &max_value);
1415 *offset += sysfs_emit_at(buf, *offset, "MCLK: %7uMhz %10uMhz\n",
1416 min_value, max_value);
1417 }
1418
1419 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1420 navi10_od_setting_get_range(od_settings,
1421 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1422 &min_value, &max_value);
1423 *offset += sysfs_emit_at(buf, *offset,
1424 "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1425 min_value, max_value);
1426 navi10_od_setting_get_range(od_settings,
1427 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1428 &min_value, &max_value);
1429 *offset += sysfs_emit_at(buf, *offset,
1430 "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1431 min_value, max_value);
1432 navi10_od_setting_get_range(od_settings,
1433 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1434 &min_value, &max_value);
1435 *offset += sysfs_emit_at(buf, *offset,
1436 "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1437 min_value, max_value);
1438 navi10_od_setting_get_range(od_settings,
1439 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1440 &min_value, &max_value);
1441 *offset += sysfs_emit_at(buf, *offset,
1442 "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1443 min_value, max_value);
1444 navi10_od_setting_get_range(od_settings,
1445 SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1446 &min_value, &max_value);
1447 *offset += sysfs_emit_at(buf, *offset,
1448 "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1449 min_value, max_value);
1450 navi10_od_setting_get_range(od_settings,
1451 SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1452 &min_value, &max_value);
1453 *offset += sysfs_emit_at(buf, *offset,
1454 "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1455 min_value, max_value);
1456 }
1457
1458 break;
1459 default:
1460 break;
1461 }
1462
1463 return 0;
1464 }
1465
navi10_print_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,char * buf)1466 static int navi10_print_clk_levels(struct smu_context *smu,
1467 enum smu_clk_type clk_type, char *buf)
1468 {
1469 uint16_t *curve_settings;
1470 int i, levels, size = 0, ret = 0;
1471 uint32_t cur_value = 0, value = 0, count = 0;
1472 uint32_t freq_values[3] = {0};
1473 uint32_t mark_index = 0;
1474 struct smu_table_context *table_context = &smu->smu_table;
1475 uint32_t gen_speed, lane_width;
1476 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1477 struct smu_11_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1478 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable;
1479 OverDriveTable_t *od_table =
1480 (OverDriveTable_t *)table_context->overdrive_table;
1481 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
1482 uint32_t min_value, max_value;
1483
1484 smu_cmn_get_sysfs_buf(&buf, &size);
1485
1486 switch (clk_type) {
1487 case SMU_GFXCLK:
1488 case SMU_SCLK:
1489 case SMU_SOCCLK:
1490 case SMU_MCLK:
1491 case SMU_UCLK:
1492 case SMU_FCLK:
1493 case SMU_VCLK:
1494 case SMU_DCLK:
1495 case SMU_DCEFCLK:
1496 ret = navi10_get_current_clk_freq_by_table(smu, clk_type, &cur_value);
1497 if (ret)
1498 return size;
1499
1500 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &count);
1501 if (ret)
1502 return size;
1503
1504 ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
1505 if (ret < 0)
1506 return ret;
1507
1508 if (!ret) {
1509 for (i = 0; i < count; i++) {
1510 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &value);
1511 if (ret)
1512 return size;
1513
1514 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, value,
1515 cur_value == value ? "*" : "");
1516 }
1517 } else {
1518 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, 0, &freq_values[0]);
1519 if (ret)
1520 return size;
1521 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, count - 1, &freq_values[2]);
1522 if (ret)
1523 return size;
1524
1525 freq_values[1] = cur_value;
1526 mark_index = cur_value == freq_values[0] ? 0 :
1527 cur_value == freq_values[2] ? 2 : 1;
1528
1529 levels = 3;
1530 if (mark_index != 1) {
1531 levels = 2;
1532 freq_values[1] = freq_values[2];
1533 }
1534
1535 for (i = 0; i < levels; i++) {
1536 size += sysfs_emit_at(buf, size, "%d: %uMhz %s\n", i, freq_values[i],
1537 i == mark_index ? "*" : "");
1538 }
1539 }
1540 break;
1541 case SMU_PCIE:
1542 gen_speed = smu_v11_0_get_current_pcie_link_speed_level(smu);
1543 lane_width = smu_v11_0_get_current_pcie_link_width_level(smu);
1544 for (i = 0; i < NUM_LINK_LEVELS; i++)
1545 size += sysfs_emit_at(buf, size, "%d: %s %s %dMhz %s\n", i,
1546 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 0) ? "2.5GT/s," :
1547 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 1) ? "5.0GT/s," :
1548 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 2) ? "8.0GT/s," :
1549 (dpm_context->dpm_tables.pcie_table.pcie_gen[i] == 3) ? "16.0GT/s," : "",
1550 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 1) ? "x1" :
1551 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 2) ? "x2" :
1552 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 3) ? "x4" :
1553 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 4) ? "x8" :
1554 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 5) ? "x12" :
1555 (dpm_context->dpm_tables.pcie_table.pcie_lane[i] == 6) ? "x16" : "",
1556 pptable->LclkFreq[i],
1557 (gen_speed == dpm_context->dpm_tables.pcie_table.pcie_gen[i]) &&
1558 (lane_width == dpm_context->dpm_tables.pcie_table.pcie_lane[i]) ?
1559 "*" : "");
1560 break;
1561 case SMU_OD_SCLK:
1562 if (!smu->od_enabled || !od_table || !od_settings)
1563 break;
1564 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS))
1565 break;
1566 size += sysfs_emit_at(buf, size, "OD_SCLK:\n");
1567 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1568 od_table->GfxclkFmin, od_table->GfxclkFmax);
1569 break;
1570 case SMU_OD_MCLK:
1571 if (!smu->od_enabled || !od_table || !od_settings)
1572 break;
1573 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX))
1574 break;
1575 size += sysfs_emit_at(buf, size, "OD_MCLK:\n");
1576 size += sysfs_emit_at(buf, size, "1: %uMHz\n", od_table->UclkFmax);
1577 break;
1578 case SMU_OD_VDDC_CURVE:
1579 if (!smu->od_enabled || !od_table || !od_settings)
1580 break;
1581 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE))
1582 break;
1583 size += sysfs_emit_at(buf, size, "OD_VDDC_CURVE:\n");
1584 for (i = 0; i < 3; i++) {
1585 switch (i) {
1586 case 0:
1587 curve_settings = &od_table->GfxclkFreq1;
1588 break;
1589 case 1:
1590 curve_settings = &od_table->GfxclkFreq2;
1591 break;
1592 case 2:
1593 curve_settings = &od_table->GfxclkFreq3;
1594 break;
1595 }
1596 size += sysfs_emit_at(buf, size, "%d: %uMHz %umV\n",
1597 i, curve_settings[0],
1598 curve_settings[1] / NAVI10_VOLTAGE_SCALE);
1599 }
1600 break;
1601 case SMU_OD_RANGE:
1602 if (!smu->od_enabled || !od_table || !od_settings)
1603 break;
1604 size += sysfs_emit_at(buf, size, "%s:\n", "OD_RANGE");
1605
1606 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
1607 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMIN,
1608 &min_value, NULL);
1609 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_GFXCLKFMAX,
1610 NULL, &max_value);
1611 size += sysfs_emit_at(buf, size, "SCLK: %7uMhz %10uMhz\n",
1612 min_value, max_value);
1613 }
1614
1615 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
1616 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_UCLKFMAX,
1617 &min_value, &max_value);
1618 size += sysfs_emit_at(buf, size, "MCLK: %7uMhz %10uMhz\n",
1619 min_value, max_value);
1620 }
1621
1622 if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
1623 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1,
1624 &min_value, &max_value);
1625 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[0]: %7uMhz %10uMhz\n",
1626 min_value, max_value);
1627 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1,
1628 &min_value, &max_value);
1629 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[0]: %7dmV %11dmV\n",
1630 min_value, max_value);
1631 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2,
1632 &min_value, &max_value);
1633 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[1]: %7uMhz %10uMhz\n",
1634 min_value, max_value);
1635 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2,
1636 &min_value, &max_value);
1637 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[1]: %7dmV %11dmV\n",
1638 min_value, max_value);
1639 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3,
1640 &min_value, &max_value);
1641 size += sysfs_emit_at(buf, size, "VDDC_CURVE_SCLK[2]: %7uMhz %10uMhz\n",
1642 min_value, max_value);
1643 navi10_od_setting_get_range(od_settings, SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3,
1644 &min_value, &max_value);
1645 size += sysfs_emit_at(buf, size, "VDDC_CURVE_VOLT[2]: %7dmV %11dmV\n",
1646 min_value, max_value);
1647 }
1648
1649 break;
1650 default:
1651 break;
1652 }
1653
1654 return size;
1655 }
1656
navi10_force_clk_levels(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t mask)1657 static int navi10_force_clk_levels(struct smu_context *smu,
1658 enum smu_clk_type clk_type, uint32_t mask)
1659 {
1660
1661 int ret = 0;
1662 uint32_t soft_min_level = 0, soft_max_level = 0, min_freq = 0, max_freq = 0;
1663
1664 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1665 soft_max_level = mask ? (fls(mask) - 1) : 0;
1666
1667 switch (clk_type) {
1668 case SMU_GFXCLK:
1669 case SMU_SCLK:
1670 case SMU_SOCCLK:
1671 case SMU_MCLK:
1672 case SMU_UCLK:
1673 case SMU_FCLK:
1674 /* There is only 2 levels for fine grained DPM */
1675 ret = navi10_is_support_fine_grained_dpm(smu, clk_type);
1676 if (ret < 0)
1677 return ret;
1678
1679 if (ret) {
1680 soft_max_level = (soft_max_level >= 1 ? 1 : 0);
1681 soft_min_level = (soft_min_level >= 1 ? 1 : 0);
1682 }
1683
1684 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
1685 if (ret)
1686 return 0;
1687
1688 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, soft_max_level, &max_freq);
1689 if (ret)
1690 return 0;
1691
1692 ret = smu_v11_0_set_soft_freq_limited_range(smu, clk_type, min_freq, max_freq);
1693 if (ret)
1694 return 0;
1695 break;
1696 case SMU_DCEFCLK:
1697 dev_info(smu->adev->dev, "Setting DCEFCLK min/max dpm level is not supported!\n");
1698 break;
1699
1700 default:
1701 break;
1702 }
1703
1704 return 0;
1705 }
1706
navi10_populate_umd_state_clk(struct smu_context * smu)1707 static int navi10_populate_umd_state_clk(struct smu_context *smu)
1708 {
1709 struct smu_11_0_dpm_context *dpm_context =
1710 smu->smu_dpm.dpm_context;
1711 struct smu_11_0_dpm_table *gfx_table =
1712 &dpm_context->dpm_tables.gfx_table;
1713 struct smu_11_0_dpm_table *mem_table =
1714 &dpm_context->dpm_tables.uclk_table;
1715 struct smu_11_0_dpm_table *soc_table =
1716 &dpm_context->dpm_tables.soc_table;
1717 struct smu_umd_pstate_table *pstate_table =
1718 &smu->pstate_table;
1719 struct amdgpu_device *adev = smu->adev;
1720 uint32_t sclk_freq;
1721
1722 pstate_table->gfxclk_pstate.min = gfx_table->min;
1723 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
1724 case IP_VERSION(11, 0, 0):
1725 switch (adev->pdev->revision) {
1726 case 0xf0: /* XTX */
1727 case 0xc0:
1728 sclk_freq = NAVI10_PEAK_SCLK_XTX;
1729 break;
1730 case 0xf1: /* XT */
1731 case 0xc1:
1732 sclk_freq = NAVI10_PEAK_SCLK_XT;
1733 break;
1734 default: /* XL */
1735 sclk_freq = NAVI10_PEAK_SCLK_XL;
1736 break;
1737 }
1738 break;
1739 case IP_VERSION(11, 0, 5):
1740 switch (adev->pdev->revision) {
1741 case 0xc7: /* XT */
1742 case 0xf4:
1743 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
1744 break;
1745 case 0xc1: /* XTM */
1746 case 0xf2:
1747 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
1748 break;
1749 case 0xc3: /* XLM */
1750 case 0xf3:
1751 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1752 break;
1753 case 0xc5: /* XTX */
1754 case 0xf6:
1755 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
1756 break;
1757 default: /* XL */
1758 sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
1759 break;
1760 }
1761 break;
1762 case IP_VERSION(11, 0, 9):
1763 sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
1764 break;
1765 default:
1766 sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
1767 break;
1768 }
1769 pstate_table->gfxclk_pstate.peak = sclk_freq;
1770
1771 pstate_table->uclk_pstate.min = mem_table->min;
1772 pstate_table->uclk_pstate.peak = mem_table->max;
1773
1774 pstate_table->socclk_pstate.min = soc_table->min;
1775 pstate_table->socclk_pstate.peak = soc_table->max;
1776
1777 if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
1778 mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
1779 soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
1780 pstate_table->gfxclk_pstate.standard =
1781 NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
1782 pstate_table->uclk_pstate.standard =
1783 NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
1784 pstate_table->socclk_pstate.standard =
1785 NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
1786 } else {
1787 pstate_table->gfxclk_pstate.standard =
1788 pstate_table->gfxclk_pstate.min;
1789 pstate_table->uclk_pstate.standard =
1790 pstate_table->uclk_pstate.min;
1791 pstate_table->socclk_pstate.standard =
1792 pstate_table->socclk_pstate.min;
1793 }
1794
1795 return 0;
1796 }
1797
navi10_get_clock_by_type_with_latency(struct smu_context * smu,enum smu_clk_type clk_type,struct pp_clock_levels_with_latency * clocks)1798 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,
1799 enum smu_clk_type clk_type,
1800 struct pp_clock_levels_with_latency *clocks)
1801 {
1802 int ret = 0, i = 0;
1803 uint32_t level_count = 0, freq = 0;
1804
1805 switch (clk_type) {
1806 case SMU_GFXCLK:
1807 case SMU_DCEFCLK:
1808 case SMU_SOCCLK:
1809 case SMU_MCLK:
1810 case SMU_UCLK:
1811 ret = smu_v11_0_get_dpm_level_count(smu, clk_type, &level_count);
1812 if (ret)
1813 return ret;
1814
1815 level_count = min(level_count, (uint32_t)MAX_NUM_CLOCKS);
1816 clocks->num_levels = level_count;
1817
1818 for (i = 0; i < level_count; i++) {
1819 ret = smu_v11_0_get_dpm_freq_by_index(smu, clk_type, i, &freq);
1820 if (ret)
1821 return ret;
1822
1823 clocks->data[i].clocks_in_khz = freq * 1000;
1824 clocks->data[i].latency_in_us = 0;
1825 }
1826 break;
1827 default:
1828 break;
1829 }
1830
1831 return ret;
1832 }
1833
navi10_pre_display_config_changed(struct smu_context * smu)1834 static int navi10_pre_display_config_changed(struct smu_context *smu)
1835 {
1836 int ret = 0;
1837 uint32_t max_freq = 0;
1838
1839 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays, 0, NULL);
1840 if (ret)
1841 return ret;
1842
1843 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
1844 ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_UCLK, NULL, &max_freq);
1845 if (ret)
1846 return ret;
1847 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, max_freq);
1848 if (ret)
1849 return ret;
1850 }
1851
1852 return ret;
1853 }
1854
navi10_display_config_changed(struct smu_context * smu)1855 static int navi10_display_config_changed(struct smu_context *smu)
1856 {
1857 int ret = 0;
1858
1859 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
1860 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
1861 smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
1862 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
1863 smu->display_config->num_display,
1864 NULL);
1865 if (ret)
1866 return ret;
1867 }
1868
1869 return ret;
1870 }
1871
navi10_is_dpm_running(struct smu_context * smu)1872 static bool navi10_is_dpm_running(struct smu_context *smu)
1873 {
1874 int ret = 0;
1875 uint64_t feature_enabled;
1876
1877 ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
1878 if (ret)
1879 return false;
1880
1881 return !!(feature_enabled & SMC_DPM_FEATURE);
1882 }
1883
navi10_get_fan_speed_rpm(struct smu_context * smu,uint32_t * speed)1884 static int navi10_get_fan_speed_rpm(struct smu_context *smu,
1885 uint32_t *speed)
1886 {
1887 int ret = 0;
1888
1889 if (!speed)
1890 return -EINVAL;
1891
1892 switch (smu_v11_0_get_fan_control_mode(smu)) {
1893 case AMD_FAN_CTRL_AUTO:
1894 ret = navi10_get_smu_metrics_data(smu,
1895 METRICS_CURR_FANSPEED,
1896 speed);
1897 break;
1898 default:
1899 ret = smu_v11_0_get_fan_speed_rpm(smu,
1900 speed);
1901 break;
1902 }
1903
1904 return ret;
1905 }
1906
navi10_get_fan_parameters(struct smu_context * smu)1907 static int navi10_get_fan_parameters(struct smu_context *smu)
1908 {
1909 PPTable_t *pptable = smu->smu_table.driver_pptable;
1910
1911 smu->fan_max_rpm = pptable->FanMaximumRpm;
1912
1913 return 0;
1914 }
1915
navi10_get_power_profile_mode(struct smu_context * smu,char * buf)1916 static int navi10_get_power_profile_mode(struct smu_context *smu, char *buf)
1917 {
1918 DpmActivityMonitorCoeffInt_t activity_monitor;
1919 uint32_t i, size = 0;
1920 int16_t workload_type = 0;
1921 static const char *title[] = {
1922 "PROFILE_INDEX(NAME)",
1923 "CLOCK_TYPE(NAME)",
1924 "FPS",
1925 "MinFreqType",
1926 "MinActiveFreqType",
1927 "MinActiveFreq",
1928 "BoosterFreqType",
1929 "BoosterFreq",
1930 "PD_Data_limit_c",
1931 "PD_Data_error_coeff",
1932 "PD_Data_error_rate_coeff"};
1933 int result = 0;
1934
1935 if (!buf)
1936 return -EINVAL;
1937
1938 size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s %s\n",
1939 title[0], title[1], title[2], title[3], title[4], title[5],
1940 title[6], title[7], title[8], title[9], title[10]);
1941
1942 for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
1943 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
1944 workload_type = smu_cmn_to_asic_specific_index(smu,
1945 CMN2ASIC_MAPPING_WORKLOAD,
1946 i);
1947 if (workload_type < 0)
1948 return -EINVAL;
1949
1950 result = smu_cmn_update_table(smu,
1951 SMU_TABLE_ACTIVITY_MONITOR_COEFF, workload_type,
1952 (void *)(&activity_monitor), false);
1953 if (result) {
1954 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
1955 return result;
1956 }
1957
1958 size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
1959 i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
1960
1961 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1962 " ",
1963 0,
1964 "GFXCLK",
1965 activity_monitor.Gfx_FPS,
1966 activity_monitor.Gfx_MinFreqStep,
1967 activity_monitor.Gfx_MinActiveFreqType,
1968 activity_monitor.Gfx_MinActiveFreq,
1969 activity_monitor.Gfx_BoosterFreqType,
1970 activity_monitor.Gfx_BoosterFreq,
1971 activity_monitor.Gfx_PD_Data_limit_c,
1972 activity_monitor.Gfx_PD_Data_error_coeff,
1973 activity_monitor.Gfx_PD_Data_error_rate_coeff);
1974
1975 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1976 " ",
1977 1,
1978 "SOCCLK",
1979 activity_monitor.Soc_FPS,
1980 activity_monitor.Soc_MinFreqStep,
1981 activity_monitor.Soc_MinActiveFreqType,
1982 activity_monitor.Soc_MinActiveFreq,
1983 activity_monitor.Soc_BoosterFreqType,
1984 activity_monitor.Soc_BoosterFreq,
1985 activity_monitor.Soc_PD_Data_limit_c,
1986 activity_monitor.Soc_PD_Data_error_coeff,
1987 activity_monitor.Soc_PD_Data_error_rate_coeff);
1988
1989 size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d %7d\n",
1990 " ",
1991 2,
1992 "MEMCLK",
1993 activity_monitor.Mem_FPS,
1994 activity_monitor.Mem_MinFreqStep,
1995 activity_monitor.Mem_MinActiveFreqType,
1996 activity_monitor.Mem_MinActiveFreq,
1997 activity_monitor.Mem_BoosterFreqType,
1998 activity_monitor.Mem_BoosterFreq,
1999 activity_monitor.Mem_PD_Data_limit_c,
2000 activity_monitor.Mem_PD_Data_error_coeff,
2001 activity_monitor.Mem_PD_Data_error_rate_coeff);
2002 }
2003
2004 return size;
2005 }
2006
navi10_set_power_profile_mode(struct smu_context * smu,long * input,uint32_t size)2007 static int navi10_set_power_profile_mode(struct smu_context *smu, long *input, uint32_t size)
2008 {
2009 DpmActivityMonitorCoeffInt_t activity_monitor;
2010 int workload_type, ret = 0;
2011
2012 smu->power_profile_mode = input[size];
2013
2014 if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
2015 dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
2016 return -EINVAL;
2017 }
2018
2019 if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
2020 if (size != 10)
2021 return -EINVAL;
2022
2023 ret = smu_cmn_update_table(smu,
2024 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2025 (void *)(&activity_monitor), false);
2026 if (ret) {
2027 dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
2028 return ret;
2029 }
2030
2031 switch (input[0]) {
2032 case 0: /* Gfxclk */
2033 activity_monitor.Gfx_FPS = input[1];
2034 activity_monitor.Gfx_MinFreqStep = input[2];
2035 activity_monitor.Gfx_MinActiveFreqType = input[3];
2036 activity_monitor.Gfx_MinActiveFreq = input[4];
2037 activity_monitor.Gfx_BoosterFreqType = input[5];
2038 activity_monitor.Gfx_BoosterFreq = input[6];
2039 activity_monitor.Gfx_PD_Data_limit_c = input[7];
2040 activity_monitor.Gfx_PD_Data_error_coeff = input[8];
2041 activity_monitor.Gfx_PD_Data_error_rate_coeff = input[9];
2042 break;
2043 case 1: /* Socclk */
2044 activity_monitor.Soc_FPS = input[1];
2045 activity_monitor.Soc_MinFreqStep = input[2];
2046 activity_monitor.Soc_MinActiveFreqType = input[3];
2047 activity_monitor.Soc_MinActiveFreq = input[4];
2048 activity_monitor.Soc_BoosterFreqType = input[5];
2049 activity_monitor.Soc_BoosterFreq = input[6];
2050 activity_monitor.Soc_PD_Data_limit_c = input[7];
2051 activity_monitor.Soc_PD_Data_error_coeff = input[8];
2052 activity_monitor.Soc_PD_Data_error_rate_coeff = input[9];
2053 break;
2054 case 2: /* Memclk */
2055 activity_monitor.Mem_FPS = input[1];
2056 activity_monitor.Mem_MinFreqStep = input[2];
2057 activity_monitor.Mem_MinActiveFreqType = input[3];
2058 activity_monitor.Mem_MinActiveFreq = input[4];
2059 activity_monitor.Mem_BoosterFreqType = input[5];
2060 activity_monitor.Mem_BoosterFreq = input[6];
2061 activity_monitor.Mem_PD_Data_limit_c = input[7];
2062 activity_monitor.Mem_PD_Data_error_coeff = input[8];
2063 activity_monitor.Mem_PD_Data_error_rate_coeff = input[9];
2064 break;
2065 default:
2066 return -EINVAL;
2067 }
2068
2069 ret = smu_cmn_update_table(smu,
2070 SMU_TABLE_ACTIVITY_MONITOR_COEFF, WORKLOAD_PPLIB_CUSTOM_BIT,
2071 (void *)(&activity_monitor), true);
2072 if (ret) {
2073 dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
2074 return ret;
2075 }
2076 }
2077
2078 /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
2079 workload_type = smu_cmn_to_asic_specific_index(smu,
2080 CMN2ASIC_MAPPING_WORKLOAD,
2081 smu->power_profile_mode);
2082 if (workload_type < 0)
2083 return -EINVAL;
2084 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetWorkloadMask,
2085 1 << workload_type, NULL);
2086 if (ret)
2087 dev_err(smu->adev->dev, "[%s] Failed to set work load mask!", __func__);
2088
2089 return ret;
2090 }
2091
navi10_notify_smc_display_config(struct smu_context * smu)2092 static int navi10_notify_smc_display_config(struct smu_context *smu)
2093 {
2094 struct smu_clocks min_clocks = {0};
2095 struct pp_display_clock_request clock_req;
2096 int ret = 0;
2097
2098 min_clocks.dcef_clock = smu->display_config->min_dcef_set_clk;
2099 min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
2100 min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
2101
2102 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
2103 clock_req.clock_type = amd_pp_dcef_clock;
2104 clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
2105
2106 ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
2107 if (!ret) {
2108 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
2109 ret = smu_cmn_send_smc_msg_with_param(smu,
2110 SMU_MSG_SetMinDeepSleepDcefclk,
2111 min_clocks.dcef_clock_in_sr/100,
2112 NULL);
2113 if (ret) {
2114 dev_err(smu->adev->dev, "Attempt to set divider for DCEFCLK Failed!");
2115 return ret;
2116 }
2117 }
2118 } else {
2119 dev_info(smu->adev->dev, "Attempt to set Hard Min for DCEFCLK Failed!");
2120 }
2121 }
2122
2123 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT)) {
2124 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_clocks.memory_clock/100, 0);
2125 if (ret) {
2126 dev_err(smu->adev->dev, "[%s] Set hard min uclk failed!", __func__);
2127 return ret;
2128 }
2129 }
2130
2131 return 0;
2132 }
2133
navi10_set_watermarks_table(struct smu_context * smu,struct pp_smu_wm_range_sets * clock_ranges)2134 static int navi10_set_watermarks_table(struct smu_context *smu,
2135 struct pp_smu_wm_range_sets *clock_ranges)
2136 {
2137 Watermarks_t *table = smu->smu_table.watermarks_table;
2138 int ret = 0;
2139 int i;
2140
2141 if (clock_ranges) {
2142 if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||
2143 clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)
2144 return -EINVAL;
2145
2146 for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {
2147 table->WatermarkRow[WM_DCEFCLK][i].MinClock =
2148 clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;
2149 table->WatermarkRow[WM_DCEFCLK][i].MaxClock =
2150 clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;
2151 table->WatermarkRow[WM_DCEFCLK][i].MinUclk =
2152 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;
2153 table->WatermarkRow[WM_DCEFCLK][i].MaxUclk =
2154 clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;
2155
2156 table->WatermarkRow[WM_DCEFCLK][i].WmSetting =
2157 clock_ranges->reader_wm_sets[i].wm_inst;
2158 }
2159
2160 for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {
2161 table->WatermarkRow[WM_SOCCLK][i].MinClock =
2162 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;
2163 table->WatermarkRow[WM_SOCCLK][i].MaxClock =
2164 clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;
2165 table->WatermarkRow[WM_SOCCLK][i].MinUclk =
2166 clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;
2167 table->WatermarkRow[WM_SOCCLK][i].MaxUclk =
2168 clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;
2169
2170 table->WatermarkRow[WM_SOCCLK][i].WmSetting =
2171 clock_ranges->writer_wm_sets[i].wm_inst;
2172 }
2173
2174 smu->watermarks_bitmap |= WATERMARKS_EXIST;
2175 }
2176
2177 /* pass data to smu controller */
2178 if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
2179 !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {
2180 ret = smu_cmn_write_watermarks_table(smu);
2181 if (ret) {
2182 dev_err(smu->adev->dev, "Failed to update WMTABLE!");
2183 return ret;
2184 }
2185 smu->watermarks_bitmap |= WATERMARKS_LOADED;
2186 }
2187
2188 return 0;
2189 }
2190
navi10_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)2191 static int navi10_read_sensor(struct smu_context *smu,
2192 enum amd_pp_sensors sensor,
2193 void *data, uint32_t *size)
2194 {
2195 int ret = 0;
2196 struct smu_table_context *table_context = &smu->smu_table;
2197 PPTable_t *pptable = table_context->driver_pptable;
2198
2199 if (!data || !size)
2200 return -EINVAL;
2201
2202 switch (sensor) {
2203 case AMDGPU_PP_SENSOR_MAX_FAN_RPM:
2204 *(uint32_t *)data = pptable->FanMaximumRpm;
2205 *size = 4;
2206 break;
2207 case AMDGPU_PP_SENSOR_MEM_LOAD:
2208 ret = navi1x_get_smu_metrics_data(smu,
2209 METRICS_AVERAGE_MEMACTIVITY,
2210 (uint32_t *)data);
2211 *size = 4;
2212 break;
2213 case AMDGPU_PP_SENSOR_GPU_LOAD:
2214 ret = navi1x_get_smu_metrics_data(smu,
2215 METRICS_AVERAGE_GFXACTIVITY,
2216 (uint32_t *)data);
2217 *size = 4;
2218 break;
2219 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
2220 ret = navi1x_get_smu_metrics_data(smu,
2221 METRICS_AVERAGE_SOCKETPOWER,
2222 (uint32_t *)data);
2223 *size = 4;
2224 break;
2225 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
2226 ret = navi1x_get_smu_metrics_data(smu,
2227 METRICS_TEMPERATURE_HOTSPOT,
2228 (uint32_t *)data);
2229 *size = 4;
2230 break;
2231 case AMDGPU_PP_SENSOR_EDGE_TEMP:
2232 ret = navi1x_get_smu_metrics_data(smu,
2233 METRICS_TEMPERATURE_EDGE,
2234 (uint32_t *)data);
2235 *size = 4;
2236 break;
2237 case AMDGPU_PP_SENSOR_MEM_TEMP:
2238 ret = navi1x_get_smu_metrics_data(smu,
2239 METRICS_TEMPERATURE_MEM,
2240 (uint32_t *)data);
2241 *size = 4;
2242 break;
2243 case AMDGPU_PP_SENSOR_GFX_MCLK:
2244 ret = navi10_get_current_clk_freq_by_table(smu, SMU_UCLK, (uint32_t *)data);
2245 *(uint32_t *)data *= 100;
2246 *size = 4;
2247 break;
2248 case AMDGPU_PP_SENSOR_GFX_SCLK:
2249 ret = navi1x_get_smu_metrics_data(smu, METRICS_AVERAGE_GFXCLK, (uint32_t *)data);
2250 *(uint32_t *)data *= 100;
2251 *size = 4;
2252 break;
2253 case AMDGPU_PP_SENSOR_VDDGFX:
2254 ret = smu_v11_0_get_gfx_vdd(smu, (uint32_t *)data);
2255 *size = 4;
2256 break;
2257 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
2258 default:
2259 ret = -EOPNOTSUPP;
2260 break;
2261 }
2262
2263 return ret;
2264 }
2265
navi10_get_uclk_dpm_states(struct smu_context * smu,uint32_t * clocks_in_khz,uint32_t * num_states)2266 static int navi10_get_uclk_dpm_states(struct smu_context *smu, uint32_t *clocks_in_khz, uint32_t *num_states)
2267 {
2268 uint32_t num_discrete_levels = 0;
2269 uint16_t *dpm_levels = NULL;
2270 uint16_t i = 0;
2271 struct smu_table_context *table_context = &smu->smu_table;
2272 PPTable_t *driver_ppt = NULL;
2273
2274 if (!clocks_in_khz || !num_states || !table_context->driver_pptable)
2275 return -EINVAL;
2276
2277 driver_ppt = table_context->driver_pptable;
2278 num_discrete_levels = driver_ppt->DpmDescriptor[PPCLK_UCLK].NumDiscreteLevels;
2279 dpm_levels = driver_ppt->FreqTableUclk;
2280
2281 if (num_discrete_levels == 0 || dpm_levels == NULL)
2282 return -EINVAL;
2283
2284 *num_states = num_discrete_levels;
2285 for (i = 0; i < num_discrete_levels; i++) {
2286 /* convert to khz */
2287 *clocks_in_khz = (*dpm_levels) * 1000;
2288 clocks_in_khz++;
2289 dpm_levels++;
2290 }
2291
2292 return 0;
2293 }
2294
navi10_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)2295 static int navi10_get_thermal_temperature_range(struct smu_context *smu,
2296 struct smu_temperature_range *range)
2297 {
2298 struct smu_table_context *table_context = &smu->smu_table;
2299 struct smu_11_0_powerplay_table *powerplay_table =
2300 table_context->power_play_table;
2301 PPTable_t *pptable = smu->smu_table.driver_pptable;
2302
2303 if (!range)
2304 return -EINVAL;
2305
2306 memcpy(range, &smu11_thermal_policy[0], sizeof(struct smu_temperature_range));
2307
2308 range->max = pptable->TedgeLimit *
2309 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2310 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) *
2311 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2312 range->hotspot_crit_max = pptable->ThotspotLimit *
2313 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2314 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) *
2315 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2316 range->mem_crit_max = pptable->TmemLimit *
2317 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2318 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_MEM)*
2319 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
2320 range->software_shutdown_temp = powerplay_table->software_shutdown_temp;
2321
2322 return 0;
2323 }
2324
navi10_display_disable_memory_clock_switch(struct smu_context * smu,bool disable_memory_clock_switch)2325 static int navi10_display_disable_memory_clock_switch(struct smu_context *smu,
2326 bool disable_memory_clock_switch)
2327 {
2328 int ret = 0;
2329 struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks =
2330 (struct smu_11_0_max_sustainable_clocks *)
2331 smu->smu_table.max_sustainable_clocks;
2332 uint32_t min_memory_clock = smu->hard_min_uclk_req_from_dal;
2333 uint32_t max_memory_clock = max_sustainable_clocks->uclock;
2334
2335 if (smu->disable_uclk_switch == disable_memory_clock_switch)
2336 return 0;
2337
2338 if (disable_memory_clock_switch)
2339 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, max_memory_clock, 0);
2340 else
2341 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, min_memory_clock, 0);
2342
2343 if (!ret)
2344 smu->disable_uclk_switch = disable_memory_clock_switch;
2345
2346 return ret;
2347 }
2348
navi10_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)2349 static int navi10_get_power_limit(struct smu_context *smu,
2350 uint32_t *current_power_limit,
2351 uint32_t *default_power_limit,
2352 uint32_t *max_power_limit,
2353 uint32_t *min_power_limit)
2354 {
2355 struct smu_11_0_powerplay_table *powerplay_table =
2356 (struct smu_11_0_powerplay_table *)smu->smu_table.power_play_table;
2357 struct smu_11_0_overdrive_table *od_settings = smu->od_settings;
2358 PPTable_t *pptable = smu->smu_table.driver_pptable;
2359 uint32_t power_limit, od_percent_upper = 0, od_percent_lower = 0;
2360
2361 if (smu_v11_0_get_current_power_limit(smu, &power_limit)) {
2362 /* the last hope to figure out the ppt limit */
2363 if (!pptable) {
2364 dev_err(smu->adev->dev, "Cannot get PPT limit due to pptable missing!");
2365 return -EINVAL;
2366 }
2367 power_limit =
2368 pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0];
2369 }
2370
2371 if (current_power_limit)
2372 *current_power_limit = power_limit;
2373 if (default_power_limit)
2374 *default_power_limit = power_limit;
2375
2376 if (powerplay_table) {
2377 if (smu->od_enabled &&
2378 navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2379 od_percent_upper = le32_to_cpu(powerplay_table->overdrive_table.max[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2380 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2381 } else if (navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_POWER_LIMIT)) {
2382 od_percent_upper = 0;
2383 od_percent_lower = le32_to_cpu(powerplay_table->overdrive_table.min[SMU_11_0_ODSETTING_POWERPERCENTAGE]);
2384 }
2385 }
2386
2387 dev_dbg(smu->adev->dev, "od percent upper:%d, od percent lower:%d (default power: %d)\n",
2388 od_percent_upper, od_percent_lower, power_limit);
2389
2390 if (max_power_limit) {
2391 *max_power_limit = power_limit * (100 + od_percent_upper);
2392 *max_power_limit /= 100;
2393 }
2394
2395 if (min_power_limit) {
2396 *min_power_limit = power_limit * (100 - od_percent_lower);
2397 *min_power_limit /= 100;
2398 }
2399
2400 return 0;
2401 }
2402
navi10_update_pcie_parameters(struct smu_context * smu,uint8_t pcie_gen_cap,uint8_t pcie_width_cap)2403 static int navi10_update_pcie_parameters(struct smu_context *smu,
2404 uint8_t pcie_gen_cap,
2405 uint8_t pcie_width_cap)
2406 {
2407 struct smu_11_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
2408 PPTable_t *pptable = smu->smu_table.driver_pptable;
2409 uint32_t smu_pcie_arg;
2410 int ret, i;
2411
2412 /* lclk dpm table setup */
2413 for (i = 0; i < MAX_PCIE_CONF; i++) {
2414 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pptable->PcieGenSpeed[i];
2415 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pptable->PcieLaneCount[i];
2416 }
2417
2418 for (i = 0; i < NUM_LINK_LEVELS; i++) {
2419 smu_pcie_arg = (i << 16) |
2420 ((pptable->PcieGenSpeed[i] <= pcie_gen_cap) ? (pptable->PcieGenSpeed[i] << 8) :
2421 (pcie_gen_cap << 8)) | ((pptable->PcieLaneCount[i] <= pcie_width_cap) ?
2422 pptable->PcieLaneCount[i] : pcie_width_cap);
2423 ret = smu_cmn_send_smc_msg_with_param(smu,
2424 SMU_MSG_OverridePcieParameters,
2425 smu_pcie_arg,
2426 NULL);
2427
2428 if (ret)
2429 return ret;
2430
2431 if (pptable->PcieGenSpeed[i] > pcie_gen_cap)
2432 dpm_context->dpm_tables.pcie_table.pcie_gen[i] = pcie_gen_cap;
2433 if (pptable->PcieLaneCount[i] > pcie_width_cap)
2434 dpm_context->dpm_tables.pcie_table.pcie_lane[i] = pcie_width_cap;
2435 }
2436
2437 return 0;
2438 }
2439
navi10_dump_od_table(struct smu_context * smu,OverDriveTable_t * od_table)2440 static inline void navi10_dump_od_table(struct smu_context *smu,
2441 OverDriveTable_t *od_table)
2442 {
2443 dev_dbg(smu->adev->dev, "OD: Gfxclk: (%d, %d)\n", od_table->GfxclkFmin, od_table->GfxclkFmax);
2444 dev_dbg(smu->adev->dev, "OD: Gfx1: (%d, %d)\n", od_table->GfxclkFreq1, od_table->GfxclkVolt1);
2445 dev_dbg(smu->adev->dev, "OD: Gfx2: (%d, %d)\n", od_table->GfxclkFreq2, od_table->GfxclkVolt2);
2446 dev_dbg(smu->adev->dev, "OD: Gfx3: (%d, %d)\n", od_table->GfxclkFreq3, od_table->GfxclkVolt3);
2447 dev_dbg(smu->adev->dev, "OD: UclkFmax: %d\n", od_table->UclkFmax);
2448 dev_dbg(smu->adev->dev, "OD: OverDrivePct: %d\n", od_table->OverDrivePct);
2449 }
2450
navi10_od_setting_check_range(struct smu_context * smu,struct smu_11_0_overdrive_table * od_table,enum SMU_11_0_ODSETTING_ID setting,uint32_t value)2451 static int navi10_od_setting_check_range(struct smu_context *smu,
2452 struct smu_11_0_overdrive_table *od_table,
2453 enum SMU_11_0_ODSETTING_ID setting,
2454 uint32_t value)
2455 {
2456 if (value < od_table->min[setting]) {
2457 dev_warn(smu->adev->dev, "OD setting (%d, %d) is less than the minimum allowed (%d)\n", setting, value, od_table->min[setting]);
2458 return -EINVAL;
2459 }
2460 if (value > od_table->max[setting]) {
2461 dev_warn(smu->adev->dev, "OD setting (%d, %d) is greater than the maximum allowed (%d)\n", setting, value, od_table->max[setting]);
2462 return -EINVAL;
2463 }
2464 return 0;
2465 }
2466
navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context * smu,uint16_t * voltage,uint32_t freq)2467 static int navi10_overdrive_get_gfx_clk_base_voltage(struct smu_context *smu,
2468 uint16_t *voltage,
2469 uint32_t freq)
2470 {
2471 uint32_t param = (freq & 0xFFFF) | (PPCLK_GFXCLK << 16);
2472 uint32_t value = 0;
2473 int ret;
2474
2475 ret = smu_cmn_send_smc_msg_with_param(smu,
2476 SMU_MSG_GetVoltageByDpm,
2477 param,
2478 &value);
2479 if (ret) {
2480 dev_err(smu->adev->dev, "[GetBaseVoltage] failed to get GFXCLK AVFS voltage from SMU!");
2481 return ret;
2482 }
2483
2484 *voltage = (uint16_t)value;
2485
2486 return 0;
2487 }
2488
navi10_baco_enter(struct smu_context * smu)2489 static int navi10_baco_enter(struct smu_context *smu)
2490 {
2491 struct amdgpu_device *adev = smu->adev;
2492
2493 /*
2494 * This aims the case below:
2495 * amdgpu driver loaded -> runpm suspend kicked -> sound driver loaded
2496 *
2497 * For NAVI10 and later ASICs, we rely on PMFW to handle the runpm. To
2498 * make that possible, PMFW needs to acknowledge the dstate transition
2499 * process for both gfx(function 0) and audio(function 1) function of
2500 * the ASIC.
2501 *
2502 * The PCI device's initial runpm status is RUNPM_SUSPENDED. So as the
2503 * device representing the audio function of the ASIC. And that means
2504 * even if the sound driver(snd_hda_intel) was not loaded yet, it's still
2505 * possible runpm suspend kicked on the ASIC. However without the dstate
2506 * transition notification from audio function, pmfw cannot handle the
2507 * BACO in/exit correctly. And that will cause driver hang on runpm
2508 * resuming.
2509 *
2510 * To address this, we revert to legacy message way(driver masters the
2511 * timing for BACO in/exit) on sound driver missing.
2512 */
2513 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev))
2514 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_BACO);
2515 else
2516 return smu_v11_0_baco_enter(smu);
2517 }
2518
navi10_baco_exit(struct smu_context * smu)2519 static int navi10_baco_exit(struct smu_context *smu)
2520 {
2521 struct amdgpu_device *adev = smu->adev;
2522
2523 if (adev->in_runpm && smu_cmn_is_audio_func_enabled(adev)) {
2524 /* Wait for PMFW handling for the Dstate change */
2525 msleep(10);
2526 return smu_v11_0_baco_set_armd3_sequence(smu, BACO_SEQ_ULPS);
2527 } else {
2528 return smu_v11_0_baco_exit(smu);
2529 }
2530 }
2531
navi10_set_default_od_settings(struct smu_context * smu)2532 static int navi10_set_default_od_settings(struct smu_context *smu)
2533 {
2534 OverDriveTable_t *od_table =
2535 (OverDriveTable_t *)smu->smu_table.overdrive_table;
2536 OverDriveTable_t *boot_od_table =
2537 (OverDriveTable_t *)smu->smu_table.boot_overdrive_table;
2538 OverDriveTable_t *user_od_table =
2539 (OverDriveTable_t *)smu->smu_table.user_overdrive_table;
2540 int ret = 0;
2541
2542 /*
2543 * For S3/S4/Runpm resume, no need to setup those overdrive tables again as
2544 * - either they already have the default OD settings got during cold bootup
2545 * - or they have some user customized OD settings which cannot be overwritten
2546 */
2547 if (smu->adev->in_suspend)
2548 return 0;
2549
2550 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)boot_od_table, false);
2551 if (ret) {
2552 dev_err(smu->adev->dev, "Failed to get overdrive table!\n");
2553 return ret;
2554 }
2555
2556 if (!boot_od_table->GfxclkVolt1) {
2557 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2558 &boot_od_table->GfxclkVolt1,
2559 boot_od_table->GfxclkFreq1);
2560 if (ret)
2561 return ret;
2562 }
2563
2564 if (!boot_od_table->GfxclkVolt2) {
2565 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2566 &boot_od_table->GfxclkVolt2,
2567 boot_od_table->GfxclkFreq2);
2568 if (ret)
2569 return ret;
2570 }
2571
2572 if (!boot_od_table->GfxclkVolt3) {
2573 ret = navi10_overdrive_get_gfx_clk_base_voltage(smu,
2574 &boot_od_table->GfxclkVolt3,
2575 boot_od_table->GfxclkFreq3);
2576 if (ret)
2577 return ret;
2578 }
2579
2580 navi10_dump_od_table(smu, boot_od_table);
2581
2582 memcpy(od_table, boot_od_table, sizeof(OverDriveTable_t));
2583 memcpy(user_od_table, boot_od_table, sizeof(OverDriveTable_t));
2584
2585 return 0;
2586 }
2587
navi10_od_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2588 static int navi10_od_edit_dpm_table(struct smu_context *smu, enum PP_OD_DPM_TABLE_COMMAND type, long input[], uint32_t size)
2589 {
2590 int i;
2591 int ret = 0;
2592 struct smu_table_context *table_context = &smu->smu_table;
2593 OverDriveTable_t *od_table;
2594 struct smu_11_0_overdrive_table *od_settings;
2595 enum SMU_11_0_ODSETTING_ID freq_setting, voltage_setting;
2596 uint16_t *freq_ptr, *voltage_ptr;
2597 od_table = (OverDriveTable_t *)table_context->overdrive_table;
2598
2599 if (!smu->od_enabled) {
2600 dev_warn(smu->adev->dev, "OverDrive is not enabled!\n");
2601 return -EINVAL;
2602 }
2603
2604 if (!smu->od_settings) {
2605 dev_err(smu->adev->dev, "OD board limits are not set!\n");
2606 return -ENOENT;
2607 }
2608
2609 od_settings = smu->od_settings;
2610
2611 switch (type) {
2612 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2613 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_LIMITS)) {
2614 dev_warn(smu->adev->dev, "GFXCLK_LIMITS not supported!\n");
2615 return -ENOTSUPP;
2616 }
2617 if (!table_context->overdrive_table) {
2618 dev_err(smu->adev->dev, "Overdrive is not initialized\n");
2619 return -EINVAL;
2620 }
2621 for (i = 0; i < size; i += 2) {
2622 if (i + 2 > size) {
2623 dev_info(smu->adev->dev, "invalid number of input parameters %d\n", size);
2624 return -EINVAL;
2625 }
2626 switch (input[i]) {
2627 case 0:
2628 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMIN;
2629 freq_ptr = &od_table->GfxclkFmin;
2630 if (input[i + 1] > od_table->GfxclkFmax) {
2631 dev_info(smu->adev->dev, "GfxclkFmin (%ld) must be <= GfxclkFmax (%u)!\n",
2632 input[i + 1],
2633 od_table->GfxclkFmin);
2634 return -EINVAL;
2635 }
2636 break;
2637 case 1:
2638 freq_setting = SMU_11_0_ODSETTING_GFXCLKFMAX;
2639 freq_ptr = &od_table->GfxclkFmax;
2640 if (input[i + 1] < od_table->GfxclkFmin) {
2641 dev_info(smu->adev->dev, "GfxclkFmax (%ld) must be >= GfxclkFmin (%u)!\n",
2642 input[i + 1],
2643 od_table->GfxclkFmax);
2644 return -EINVAL;
2645 }
2646 break;
2647 default:
2648 dev_info(smu->adev->dev, "Invalid SCLK_VDDC_TABLE index: %ld\n", input[i]);
2649 dev_info(smu->adev->dev, "Supported indices: [0:min,1:max]\n");
2650 return -EINVAL;
2651 }
2652 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[i + 1]);
2653 if (ret)
2654 return ret;
2655 *freq_ptr = input[i + 1];
2656 }
2657 break;
2658 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2659 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_UCLK_MAX)) {
2660 dev_warn(smu->adev->dev, "UCLK_MAX not supported!\n");
2661 return -ENOTSUPP;
2662 }
2663 if (size < 2) {
2664 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2665 return -EINVAL;
2666 }
2667 if (input[0] != 1) {
2668 dev_info(smu->adev->dev, "Invalid MCLK_VDDC_TABLE index: %ld\n", input[0]);
2669 dev_info(smu->adev->dev, "Supported indices: [1:max]\n");
2670 return -EINVAL;
2671 }
2672 ret = navi10_od_setting_check_range(smu, od_settings, SMU_11_0_ODSETTING_UCLKFMAX, input[1]);
2673 if (ret)
2674 return ret;
2675 od_table->UclkFmax = input[1];
2676 break;
2677 case PP_OD_RESTORE_DEFAULT_TABLE:
2678 if (!(table_context->overdrive_table && table_context->boot_overdrive_table)) {
2679 dev_err(smu->adev->dev, "Overdrive table was not initialized!\n");
2680 return -EINVAL;
2681 }
2682 memcpy(table_context->overdrive_table, table_context->boot_overdrive_table, sizeof(OverDriveTable_t));
2683 break;
2684 case PP_OD_COMMIT_DPM_TABLE:
2685 if (memcmp(od_table, table_context->user_overdrive_table, sizeof(OverDriveTable_t))) {
2686 navi10_dump_od_table(smu, od_table);
2687 ret = smu_cmn_update_table(smu, SMU_TABLE_OVERDRIVE, 0, (void *)od_table, true);
2688 if (ret) {
2689 dev_err(smu->adev->dev, "Failed to import overdrive table!\n");
2690 return ret;
2691 }
2692 memcpy(table_context->user_overdrive_table, od_table, sizeof(OverDriveTable_t));
2693 smu->user_dpm_profile.user_od = true;
2694
2695 if (!memcmp(table_context->user_overdrive_table,
2696 table_context->boot_overdrive_table,
2697 sizeof(OverDriveTable_t)))
2698 smu->user_dpm_profile.user_od = false;
2699 }
2700 break;
2701 case PP_OD_EDIT_VDDC_CURVE:
2702 if (!navi10_od_feature_is_supported(od_settings, SMU_11_0_ODCAP_GFXCLK_CURVE)) {
2703 dev_warn(smu->adev->dev, "GFXCLK_CURVE not supported!\n");
2704 return -ENOTSUPP;
2705 }
2706 if (size < 3) {
2707 dev_info(smu->adev->dev, "invalid number of parameters: %d\n", size);
2708 return -EINVAL;
2709 }
2710 if (!od_table) {
2711 dev_info(smu->adev->dev, "Overdrive is not initialized\n");
2712 return -EINVAL;
2713 }
2714
2715 switch (input[0]) {
2716 case 0:
2717 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P1;
2718 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P1;
2719 freq_ptr = &od_table->GfxclkFreq1;
2720 voltage_ptr = &od_table->GfxclkVolt1;
2721 break;
2722 case 1:
2723 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P2;
2724 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P2;
2725 freq_ptr = &od_table->GfxclkFreq2;
2726 voltage_ptr = &od_table->GfxclkVolt2;
2727 break;
2728 case 2:
2729 freq_setting = SMU_11_0_ODSETTING_VDDGFXCURVEFREQ_P3;
2730 voltage_setting = SMU_11_0_ODSETTING_VDDGFXCURVEVOLTAGE_P3;
2731 freq_ptr = &od_table->GfxclkFreq3;
2732 voltage_ptr = &od_table->GfxclkVolt3;
2733 break;
2734 default:
2735 dev_info(smu->adev->dev, "Invalid VDDC_CURVE index: %ld\n", input[0]);
2736 dev_info(smu->adev->dev, "Supported indices: [0, 1, 2]\n");
2737 return -EINVAL;
2738 }
2739 ret = navi10_od_setting_check_range(smu, od_settings, freq_setting, input[1]);
2740 if (ret)
2741 return ret;
2742 // Allow setting zero to disable the OverDrive VDDC curve
2743 if (input[2] != 0) {
2744 ret = navi10_od_setting_check_range(smu, od_settings, voltage_setting, input[2]);
2745 if (ret)
2746 return ret;
2747 *freq_ptr = input[1];
2748 *voltage_ptr = ((uint16_t)input[2]) * NAVI10_VOLTAGE_SCALE;
2749 dev_dbg(smu->adev->dev, "OD: set curve %ld: (%d, %d)\n", input[0], *freq_ptr, *voltage_ptr);
2750 } else {
2751 // If setting 0, disable all voltage curve settings
2752 od_table->GfxclkVolt1 = 0;
2753 od_table->GfxclkVolt2 = 0;
2754 od_table->GfxclkVolt3 = 0;
2755 }
2756 navi10_dump_od_table(smu, od_table);
2757 break;
2758 default:
2759 return -ENOSYS;
2760 }
2761 return ret;
2762 }
2763
navi10_run_btc(struct smu_context * smu)2764 static int navi10_run_btc(struct smu_context *smu)
2765 {
2766 int ret = 0;
2767
2768 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RunBtc, NULL);
2769 if (ret)
2770 dev_err(smu->adev->dev, "RunBtc failed!\n");
2771
2772 return ret;
2773 }
2774
navi10_need_umc_cdr_workaround(struct smu_context * smu)2775 static bool navi10_need_umc_cdr_workaround(struct smu_context *smu)
2776 {
2777 struct amdgpu_device *adev = smu->adev;
2778
2779 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2780 return false;
2781
2782 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0) ||
2783 amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5))
2784 return true;
2785
2786 return false;
2787 }
2788
navi10_umc_hybrid_cdr_workaround(struct smu_context * smu)2789 static int navi10_umc_hybrid_cdr_workaround(struct smu_context *smu)
2790 {
2791 uint32_t uclk_count, uclk_min, uclk_max;
2792 int ret = 0;
2793
2794 /* This workaround can be applied only with uclk dpm enabled */
2795 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT))
2796 return 0;
2797
2798 ret = smu_v11_0_get_dpm_level_count(smu, SMU_UCLK, &uclk_count);
2799 if (ret)
2800 return ret;
2801
2802 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)(uclk_count - 1), &uclk_max);
2803 if (ret)
2804 return ret;
2805
2806 /*
2807 * The NAVI10_UMC_HYBRID_CDR_WORKAROUND_UCLK_THRESHOLD is 750Mhz.
2808 * This workaround is needed only when the max uclk frequency
2809 * not greater than that.
2810 */
2811 if (uclk_max > 0x2EE)
2812 return 0;
2813
2814 ret = smu_v11_0_get_dpm_freq_by_index(smu, SMU_UCLK, (uint16_t)0, &uclk_min);
2815 if (ret)
2816 return ret;
2817
2818 /* Force UCLK out of the highest DPM */
2819 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_min);
2820 if (ret)
2821 return ret;
2822
2823 /* Revert the UCLK Hardmax */
2824 ret = smu_v11_0_set_hard_freq_limited_range(smu, SMU_UCLK, 0, uclk_max);
2825 if (ret)
2826 return ret;
2827
2828 /*
2829 * In this case, SMU already disabled dummy pstate during enablement
2830 * of UCLK DPM, we have to re-enabled it.
2831 */
2832 return smu_cmn_send_smc_msg(smu, SMU_MSG_DAL_ENABLE_DUMMY_PSTATE_CHANGE, NULL);
2833 }
2834
navi10_set_dummy_pstates_table_location(struct smu_context * smu)2835 static int navi10_set_dummy_pstates_table_location(struct smu_context *smu)
2836 {
2837 struct smu_table_context *smu_table = &smu->smu_table;
2838 struct smu_table *dummy_read_table =
2839 &smu_table->dummy_read_1_table;
2840 char *dummy_table = dummy_read_table->cpu_addr;
2841 int ret = 0;
2842 uint32_t i;
2843
2844 for (i = 0; i < 0x40000; i += 0x1000 * 2) {
2845 memcpy(dummy_table, &NoDbiPrbs7[0], 0x1000);
2846 dummy_table += 0x1000;
2847 memcpy(dummy_table, &DbiPrbs7[0], 0x1000);
2848 dummy_table += 0x1000;
2849 }
2850
2851 amdgpu_asic_flush_hdp(smu->adev, NULL);
2852
2853 ret = smu_cmn_send_smc_msg_with_param(smu,
2854 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_HIGH,
2855 upper_32_bits(dummy_read_table->mc_address),
2856 NULL);
2857 if (ret)
2858 return ret;
2859
2860 return smu_cmn_send_smc_msg_with_param(smu,
2861 SMU_MSG_SET_DRIVER_DUMMY_TABLE_DRAM_ADDR_LOW,
2862 lower_32_bits(dummy_read_table->mc_address),
2863 NULL);
2864 }
2865
navi10_run_umc_cdr_workaround(struct smu_context * smu)2866 static int navi10_run_umc_cdr_workaround(struct smu_context *smu)
2867 {
2868 struct amdgpu_device *adev = smu->adev;
2869 uint8_t umc_fw_greater_than_v136 = false;
2870 uint8_t umc_fw_disable_cdr = false;
2871 uint32_t param;
2872 int ret = 0;
2873
2874 if (!navi10_need_umc_cdr_workaround(smu))
2875 return 0;
2876
2877 /*
2878 * The messages below are only supported by Navi10 42.53.0 and later
2879 * PMFWs and Navi14 53.29.0 and later PMFWs.
2880 * - PPSMC_MSG_SetDriverDummyTableDramAddrHigh
2881 * - PPSMC_MSG_SetDriverDummyTableDramAddrLow
2882 * - PPSMC_MSG_GetUMCFWWA
2883 */
2884 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 0)) &&
2885 (smu->smc_fw_version >= 0x2a3500)) ||
2886 ((amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 5)) &&
2887 (smu->smc_fw_version >= 0x351D00))) {
2888 ret = smu_cmn_send_smc_msg_with_param(smu,
2889 SMU_MSG_GET_UMC_FW_WA,
2890 0,
2891 ¶m);
2892 if (ret)
2893 return ret;
2894
2895 /* First bit indicates if the UMC f/w is above v137 */
2896 umc_fw_greater_than_v136 = param & 0x1;
2897
2898 /* Second bit indicates if hybrid-cdr is disabled */
2899 umc_fw_disable_cdr = param & 0x2;
2900
2901 /* w/a only allowed if UMC f/w is <= 136 */
2902 if (umc_fw_greater_than_v136)
2903 return 0;
2904
2905 if (umc_fw_disable_cdr) {
2906 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2907 IP_VERSION(11, 0, 0))
2908 return navi10_umc_hybrid_cdr_workaround(smu);
2909 } else {
2910 return navi10_set_dummy_pstates_table_location(smu);
2911 }
2912 } else {
2913 if (amdgpu_ip_version(adev, MP1_HWIP, 0) ==
2914 IP_VERSION(11, 0, 0))
2915 return navi10_umc_hybrid_cdr_workaround(smu);
2916 }
2917
2918 return 0;
2919 }
2920
navi10_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)2921 static ssize_t navi10_get_legacy_gpu_metrics(struct smu_context *smu,
2922 void **table)
2923 {
2924 struct smu_table_context *smu_table = &smu->smu_table;
2925 struct gpu_metrics_v1_3 *gpu_metrics =
2926 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
2927 SmuMetrics_legacy_t metrics;
2928 int ret = 0;
2929
2930 ret = smu_cmn_get_metrics_table(smu,
2931 NULL,
2932 true);
2933 if (ret)
2934 return ret;
2935
2936 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_legacy_t));
2937
2938 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
2939
2940 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
2941 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
2942 gpu_metrics->temperature_mem = metrics.TemperatureMem;
2943 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
2944 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
2945 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
2946
2947 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
2948 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
2949
2950 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
2951
2952 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
2953 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
2954 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
2955
2956 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
2957 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
2958 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
2959 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
2960 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
2961
2962 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
2963 gpu_metrics->indep_throttle_status =
2964 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
2965 navi1x_throttler_map);
2966
2967 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
2968
2969 gpu_metrics->pcie_link_width =
2970 smu_v11_0_get_current_pcie_link_width(smu);
2971 gpu_metrics->pcie_link_speed =
2972 smu_v11_0_get_current_pcie_link_speed(smu);
2973
2974 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2975
2976 if (metrics.CurrGfxVoltageOffset)
2977 gpu_metrics->voltage_gfx =
2978 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
2979 if (metrics.CurrMemVidOffset)
2980 gpu_metrics->voltage_mem =
2981 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
2982 if (metrics.CurrSocVoltageOffset)
2983 gpu_metrics->voltage_soc =
2984 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
2985
2986 *table = (void *)gpu_metrics;
2987
2988 return sizeof(struct gpu_metrics_v1_3);
2989 }
2990
navi10_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2991 static int navi10_i2c_xfer(struct i2c_adapter *i2c_adap,
2992 struct i2c_msg *msg, int num_msgs)
2993 {
2994 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2995 struct amdgpu_device *adev = smu_i2c->adev;
2996 struct smu_context *smu = adev->powerplay.pp_handle;
2997 struct smu_table_context *smu_table = &smu->smu_table;
2998 struct smu_table *table = &smu_table->driver_table;
2999 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
3000 int i, j, r, c;
3001 u16 dir;
3002
3003 if (!adev->pm.dpm_enabled)
3004 return -EBUSY;
3005
3006 req = kzalloc(sizeof(*req), GFP_KERNEL);
3007 if (!req)
3008 return -ENOMEM;
3009
3010 req->I2CcontrollerPort = smu_i2c->port;
3011 req->I2CSpeed = I2C_SPEED_FAST_400K;
3012 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
3013 dir = msg[0].flags & I2C_M_RD;
3014
3015 for (c = i = 0; i < num_msgs; i++) {
3016 for (j = 0; j < msg[i].len; j++, c++) {
3017 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
3018
3019 if (!(msg[i].flags & I2C_M_RD)) {
3020 /* write */
3021 cmd->Cmd = I2C_CMD_WRITE;
3022 cmd->RegisterAddr = msg[i].buf[j];
3023 }
3024
3025 if ((dir ^ msg[i].flags) & I2C_M_RD) {
3026 /* The direction changes.
3027 */
3028 dir = msg[i].flags & I2C_M_RD;
3029 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
3030 }
3031
3032 req->NumCmds++;
3033
3034 /*
3035 * Insert STOP if we are at the last byte of either last
3036 * message for the transaction or the client explicitly
3037 * requires a STOP at this particular message.
3038 */
3039 if ((j == msg[i].len - 1) &&
3040 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
3041 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
3042 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
3043 }
3044 }
3045 }
3046 mutex_lock(&adev->pm.mutex);
3047 r = smu_cmn_update_table(smu, SMU_TABLE_I2C_COMMANDS, 0, req, true);
3048 if (r)
3049 goto fail;
3050
3051 for (c = i = 0; i < num_msgs; i++) {
3052 if (!(msg[i].flags & I2C_M_RD)) {
3053 c += msg[i].len;
3054 continue;
3055 }
3056 for (j = 0; j < msg[i].len; j++, c++) {
3057 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
3058
3059 msg[i].buf[j] = cmd->Data;
3060 }
3061 }
3062 r = num_msgs;
3063 fail:
3064 mutex_unlock(&adev->pm.mutex);
3065 kfree(req);
3066 return r;
3067 }
3068
navi10_i2c_func(struct i2c_adapter * adap)3069 static u32 navi10_i2c_func(struct i2c_adapter *adap)
3070 {
3071 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
3072 }
3073
3074
3075 static const struct i2c_algorithm navi10_i2c_algo = {
3076 .master_xfer = navi10_i2c_xfer,
3077 .functionality = navi10_i2c_func,
3078 };
3079
3080 static const struct i2c_adapter_quirks navi10_i2c_control_quirks = {
3081 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
3082 .max_read_len = MAX_SW_I2C_COMMANDS,
3083 .max_write_len = MAX_SW_I2C_COMMANDS,
3084 .max_comb_1st_msg_len = 2,
3085 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
3086 };
3087
navi10_i2c_control_init(struct smu_context * smu)3088 static int navi10_i2c_control_init(struct smu_context *smu)
3089 {
3090 struct amdgpu_device *adev = smu->adev;
3091 int res, i;
3092
3093 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3094 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3095 struct i2c_adapter *control = &smu_i2c->adapter;
3096
3097 smu_i2c->adev = adev;
3098 smu_i2c->port = i;
3099 mutex_init(&smu_i2c->mutex);
3100 control->owner = THIS_MODULE;
3101 control->class = I2C_CLASS_HWMON;
3102 control->dev.parent = &adev->pdev->dev;
3103 control->algo = &navi10_i2c_algo;
3104 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
3105 control->quirks = &navi10_i2c_control_quirks;
3106 i2c_set_adapdata(control, smu_i2c);
3107
3108 res = i2c_add_adapter(control);
3109 if (res) {
3110 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
3111 goto Out_err;
3112 }
3113 }
3114
3115 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
3116 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[1].adapter;
3117
3118 return 0;
3119 Out_err:
3120 for ( ; i >= 0; i--) {
3121 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3122 struct i2c_adapter *control = &smu_i2c->adapter;
3123
3124 i2c_del_adapter(control);
3125 }
3126 return res;
3127 }
3128
navi10_i2c_control_fini(struct smu_context * smu)3129 static void navi10_i2c_control_fini(struct smu_context *smu)
3130 {
3131 struct amdgpu_device *adev = smu->adev;
3132 int i;
3133
3134 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
3135 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
3136 struct i2c_adapter *control = &smu_i2c->adapter;
3137
3138 i2c_del_adapter(control);
3139 }
3140 adev->pm.ras_eeprom_i2c_bus = NULL;
3141 adev->pm.fru_eeprom_i2c_bus = NULL;
3142 }
3143
navi10_get_gpu_metrics(struct smu_context * smu,void ** table)3144 static ssize_t navi10_get_gpu_metrics(struct smu_context *smu,
3145 void **table)
3146 {
3147 struct smu_table_context *smu_table = &smu->smu_table;
3148 struct gpu_metrics_v1_3 *gpu_metrics =
3149 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3150 SmuMetrics_t metrics;
3151 int ret = 0;
3152
3153 ret = smu_cmn_get_metrics_table(smu,
3154 NULL,
3155 true);
3156 if (ret)
3157 return ret;
3158
3159 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_t));
3160
3161 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3162
3163 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3164 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3165 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3166 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3167 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3168 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3169
3170 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3171 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3172
3173 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3174
3175 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3176 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3177 else
3178 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3179
3180 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3181 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3182
3183 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3184 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3185 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3186 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3187 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3188
3189 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3190 gpu_metrics->indep_throttle_status =
3191 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3192 navi1x_throttler_map);
3193
3194 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3195
3196 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3197 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3198
3199 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3200
3201 if (metrics.CurrGfxVoltageOffset)
3202 gpu_metrics->voltage_gfx =
3203 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3204 if (metrics.CurrMemVidOffset)
3205 gpu_metrics->voltage_mem =
3206 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3207 if (metrics.CurrSocVoltageOffset)
3208 gpu_metrics->voltage_soc =
3209 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3210
3211 *table = (void *)gpu_metrics;
3212
3213 return sizeof(struct gpu_metrics_v1_3);
3214 }
3215
navi12_get_legacy_gpu_metrics(struct smu_context * smu,void ** table)3216 static ssize_t navi12_get_legacy_gpu_metrics(struct smu_context *smu,
3217 void **table)
3218 {
3219 struct smu_table_context *smu_table = &smu->smu_table;
3220 struct gpu_metrics_v1_3 *gpu_metrics =
3221 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3222 SmuMetrics_NV12_legacy_t metrics;
3223 int ret = 0;
3224
3225 ret = smu_cmn_get_metrics_table(smu,
3226 NULL,
3227 true);
3228 if (ret)
3229 return ret;
3230
3231 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_legacy_t));
3232
3233 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3234
3235 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3236 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3237 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3238 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3239 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3240 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3241
3242 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3243 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3244
3245 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3246
3247 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequency;
3248 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3249 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequency;
3250
3251 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3252 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3253 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3254 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3255
3256 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3257 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3258 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3259 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3260 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3261
3262 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3263 gpu_metrics->indep_throttle_status =
3264 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3265 navi1x_throttler_map);
3266
3267 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3268
3269 gpu_metrics->pcie_link_width =
3270 smu_v11_0_get_current_pcie_link_width(smu);
3271 gpu_metrics->pcie_link_speed =
3272 smu_v11_0_get_current_pcie_link_speed(smu);
3273
3274 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3275
3276 if (metrics.CurrGfxVoltageOffset)
3277 gpu_metrics->voltage_gfx =
3278 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3279 if (metrics.CurrMemVidOffset)
3280 gpu_metrics->voltage_mem =
3281 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3282 if (metrics.CurrSocVoltageOffset)
3283 gpu_metrics->voltage_soc =
3284 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3285
3286 *table = (void *)gpu_metrics;
3287
3288 return sizeof(struct gpu_metrics_v1_3);
3289 }
3290
navi12_get_gpu_metrics(struct smu_context * smu,void ** table)3291 static ssize_t navi12_get_gpu_metrics(struct smu_context *smu,
3292 void **table)
3293 {
3294 struct smu_table_context *smu_table = &smu->smu_table;
3295 struct gpu_metrics_v1_3 *gpu_metrics =
3296 (struct gpu_metrics_v1_3 *)smu_table->gpu_metrics_table;
3297 SmuMetrics_NV12_t metrics;
3298 int ret = 0;
3299
3300 ret = smu_cmn_get_metrics_table(smu,
3301 NULL,
3302 true);
3303 if (ret)
3304 return ret;
3305
3306 memcpy(&metrics, smu_table->metrics_table, sizeof(SmuMetrics_NV12_t));
3307
3308 smu_cmn_init_soft_gpu_metrics(gpu_metrics, 1, 3);
3309
3310 gpu_metrics->temperature_edge = metrics.TemperatureEdge;
3311 gpu_metrics->temperature_hotspot = metrics.TemperatureHotspot;
3312 gpu_metrics->temperature_mem = metrics.TemperatureMem;
3313 gpu_metrics->temperature_vrgfx = metrics.TemperatureVrGfx;
3314 gpu_metrics->temperature_vrsoc = metrics.TemperatureVrSoc;
3315 gpu_metrics->temperature_vrmem = metrics.TemperatureVrMem0;
3316
3317 gpu_metrics->average_gfx_activity = metrics.AverageGfxActivity;
3318 gpu_metrics->average_umc_activity = metrics.AverageUclkActivity;
3319
3320 gpu_metrics->average_socket_power = metrics.AverageSocketPower;
3321
3322 if (metrics.AverageGfxActivity > SMU_11_0_GFX_BUSY_THRESHOLD)
3323 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPreDs;
3324 else
3325 gpu_metrics->average_gfxclk_frequency = metrics.AverageGfxclkFrequencyPostDs;
3326
3327 gpu_metrics->average_socclk_frequency = metrics.AverageSocclkFrequency;
3328 gpu_metrics->average_uclk_frequency = metrics.AverageUclkFrequencyPostDs;
3329
3330 gpu_metrics->energy_accumulator = metrics.EnergyAccumulator;
3331 gpu_metrics->average_vclk0_frequency = metrics.AverageVclkFrequency;
3332 gpu_metrics->average_dclk0_frequency = metrics.AverageDclkFrequency;
3333 gpu_metrics->average_mm_activity = metrics.VcnActivityPercentage;
3334
3335 gpu_metrics->current_gfxclk = metrics.CurrClock[PPCLK_GFXCLK];
3336 gpu_metrics->current_socclk = metrics.CurrClock[PPCLK_SOCCLK];
3337 gpu_metrics->current_uclk = metrics.CurrClock[PPCLK_UCLK];
3338 gpu_metrics->current_vclk0 = metrics.CurrClock[PPCLK_VCLK];
3339 gpu_metrics->current_dclk0 = metrics.CurrClock[PPCLK_DCLK];
3340
3341 gpu_metrics->throttle_status = metrics.ThrottlerStatus;
3342 gpu_metrics->indep_throttle_status =
3343 smu_cmn_get_indep_throttler_status(metrics.ThrottlerStatus,
3344 navi1x_throttler_map);
3345
3346 gpu_metrics->current_fan_speed = metrics.CurrFanSpeed;
3347
3348 gpu_metrics->pcie_link_width = metrics.PcieWidth;
3349 gpu_metrics->pcie_link_speed = link_speed[metrics.PcieRate];
3350
3351 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
3352
3353 if (metrics.CurrGfxVoltageOffset)
3354 gpu_metrics->voltage_gfx =
3355 (155000 - 625 * metrics.CurrGfxVoltageOffset) / 100;
3356 if (metrics.CurrMemVidOffset)
3357 gpu_metrics->voltage_mem =
3358 (155000 - 625 * metrics.CurrMemVidOffset) / 100;
3359 if (metrics.CurrSocVoltageOffset)
3360 gpu_metrics->voltage_soc =
3361 (155000 - 625 * metrics.CurrSocVoltageOffset) / 100;
3362
3363 *table = (void *)gpu_metrics;
3364
3365 return sizeof(struct gpu_metrics_v1_3);
3366 }
3367
navi1x_get_gpu_metrics(struct smu_context * smu,void ** table)3368 static ssize_t navi1x_get_gpu_metrics(struct smu_context *smu,
3369 void **table)
3370 {
3371 struct amdgpu_device *adev = smu->adev;
3372 int ret = 0;
3373
3374 switch (amdgpu_ip_version(adev, MP1_HWIP, 0)) {
3375 case IP_VERSION(11, 0, 9):
3376 if (smu->smc_fw_version > 0x00341C00)
3377 ret = navi12_get_gpu_metrics(smu, table);
3378 else
3379 ret = navi12_get_legacy_gpu_metrics(smu, table);
3380 break;
3381 case IP_VERSION(11, 0, 0):
3382 case IP_VERSION(11, 0, 5):
3383 default:
3384 if (((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3385 IP_VERSION(11, 0, 5)) &&
3386 smu->smc_fw_version > 0x00351F00) ||
3387 ((amdgpu_ip_version(adev, MP1_HWIP, 0) ==
3388 IP_VERSION(11, 0, 0)) &&
3389 smu->smc_fw_version > 0x002A3B00))
3390 ret = navi10_get_gpu_metrics(smu, table);
3391 else
3392 ret = navi10_get_legacy_gpu_metrics(smu, table);
3393 break;
3394 }
3395
3396 return ret;
3397 }
3398
navi10_enable_mgpu_fan_boost(struct smu_context * smu)3399 static int navi10_enable_mgpu_fan_boost(struct smu_context *smu)
3400 {
3401 struct smu_table_context *table_context = &smu->smu_table;
3402 PPTable_t *smc_pptable = table_context->driver_pptable;
3403 struct amdgpu_device *adev = smu->adev;
3404 uint32_t param = 0;
3405
3406 /* Navi12 does not support this */
3407 if (amdgpu_ip_version(adev, MP1_HWIP, 0) == IP_VERSION(11, 0, 9))
3408 return 0;
3409
3410 /*
3411 * Skip the MGpuFanBoost setting for those ASICs
3412 * which do not support it
3413 */
3414 if (!smc_pptable->MGpuFanBoostLimitRpm)
3415 return 0;
3416
3417 /* Workaround for WS SKU */
3418 if (adev->pdev->device == 0x7312 &&
3419 adev->pdev->revision == 0)
3420 param = 0xD188;
3421
3422 return smu_cmn_send_smc_msg_with_param(smu,
3423 SMU_MSG_SetMGpuFanBoostLimitRpm,
3424 param,
3425 NULL);
3426 }
3427
navi10_post_smu_init(struct smu_context * smu)3428 static int navi10_post_smu_init(struct smu_context *smu)
3429 {
3430 struct amdgpu_device *adev = smu->adev;
3431 int ret = 0;
3432
3433 if (amdgpu_sriov_vf(adev))
3434 return 0;
3435
3436 ret = navi10_run_umc_cdr_workaround(smu);
3437 if (ret)
3438 dev_err(adev->dev, "Failed to apply umc cdr workaround!\n");
3439
3440 return ret;
3441 }
3442
navi10_get_default_config_table_settings(struct smu_context * smu,struct config_table_setting * table)3443 static int navi10_get_default_config_table_settings(struct smu_context *smu,
3444 struct config_table_setting *table)
3445 {
3446 if (!table)
3447 return -EINVAL;
3448
3449 table->gfxclk_average_tau = 10;
3450 table->socclk_average_tau = 10;
3451 table->uclk_average_tau = 10;
3452 table->gfx_activity_average_tau = 10;
3453 table->mem_activity_average_tau = 10;
3454 table->socket_power_average_tau = 10;
3455
3456 return 0;
3457 }
3458
navi10_set_config_table(struct smu_context * smu,struct config_table_setting * table)3459 static int navi10_set_config_table(struct smu_context *smu,
3460 struct config_table_setting *table)
3461 {
3462 DriverSmuConfig_t driver_smu_config_table;
3463
3464 if (!table)
3465 return -EINVAL;
3466
3467 memset(&driver_smu_config_table,
3468 0,
3469 sizeof(driver_smu_config_table));
3470
3471 driver_smu_config_table.GfxclkAverageLpfTau =
3472 table->gfxclk_average_tau;
3473 driver_smu_config_table.SocclkAverageLpfTau =
3474 table->socclk_average_tau;
3475 driver_smu_config_table.UclkAverageLpfTau =
3476 table->uclk_average_tau;
3477 driver_smu_config_table.GfxActivityLpfTau =
3478 table->gfx_activity_average_tau;
3479 driver_smu_config_table.UclkActivityLpfTau =
3480 table->mem_activity_average_tau;
3481 driver_smu_config_table.SocketPowerLpfTau =
3482 table->socket_power_average_tau;
3483
3484 return smu_cmn_update_table(smu,
3485 SMU_TABLE_DRIVER_SMU_CONFIG,
3486 0,
3487 (void *)&driver_smu_config_table,
3488 true);
3489 }
3490
3491 static const struct pptable_funcs navi10_ppt_funcs = {
3492 .get_allowed_feature_mask = navi10_get_allowed_feature_mask,
3493 .set_default_dpm_table = navi10_set_default_dpm_table,
3494 .dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
3495 .dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
3496 .i2c_init = navi10_i2c_control_init,
3497 .i2c_fini = navi10_i2c_control_fini,
3498 .print_clk_levels = navi10_print_clk_levels,
3499 .emit_clk_levels = navi10_emit_clk_levels,
3500 .force_clk_levels = navi10_force_clk_levels,
3501 .populate_umd_state_clk = navi10_populate_umd_state_clk,
3502 .get_clock_by_type_with_latency = navi10_get_clock_by_type_with_latency,
3503 .pre_display_config_changed = navi10_pre_display_config_changed,
3504 .display_config_changed = navi10_display_config_changed,
3505 .notify_smc_display_config = navi10_notify_smc_display_config,
3506 .is_dpm_running = navi10_is_dpm_running,
3507 .get_fan_speed_pwm = smu_v11_0_get_fan_speed_pwm,
3508 .get_fan_speed_rpm = navi10_get_fan_speed_rpm,
3509 .get_power_profile_mode = navi10_get_power_profile_mode,
3510 .set_power_profile_mode = navi10_set_power_profile_mode,
3511 .set_watermarks_table = navi10_set_watermarks_table,
3512 .read_sensor = navi10_read_sensor,
3513 .get_uclk_dpm_states = navi10_get_uclk_dpm_states,
3514 .set_performance_level = smu_v11_0_set_performance_level,
3515 .get_thermal_temperature_range = navi10_get_thermal_temperature_range,
3516 .display_disable_memory_clock_switch = navi10_display_disable_memory_clock_switch,
3517 .get_power_limit = navi10_get_power_limit,
3518 .update_pcie_parameters = navi10_update_pcie_parameters,
3519 .init_microcode = smu_v11_0_init_microcode,
3520 .load_microcode = smu_v11_0_load_microcode,
3521 .fini_microcode = smu_v11_0_fini_microcode,
3522 .init_smc_tables = navi10_init_smc_tables,
3523 .fini_smc_tables = smu_v11_0_fini_smc_tables,
3524 .init_power = smu_v11_0_init_power,
3525 .fini_power = smu_v11_0_fini_power,
3526 .check_fw_status = smu_v11_0_check_fw_status,
3527 .setup_pptable = navi10_setup_pptable,
3528 .get_vbios_bootup_values = smu_v11_0_get_vbios_bootup_values,
3529 .check_fw_version = smu_v11_0_check_fw_version,
3530 .write_pptable = smu_cmn_write_pptable,
3531 .set_driver_table_location = smu_v11_0_set_driver_table_location,
3532 .set_tool_table_location = smu_v11_0_set_tool_table_location,
3533 .notify_memory_pool_location = smu_v11_0_notify_memory_pool_location,
3534 .system_features_control = smu_v11_0_system_features_control,
3535 .send_smc_msg_with_param = smu_cmn_send_smc_msg_with_param,
3536 .send_smc_msg = smu_cmn_send_smc_msg,
3537 .init_display_count = smu_v11_0_init_display_count,
3538 .set_allowed_mask = smu_v11_0_set_allowed_mask,
3539 .get_enabled_mask = smu_cmn_get_enabled_mask,
3540 .feature_is_enabled = smu_cmn_feature_is_enabled,
3541 .disable_all_features_with_exception = smu_cmn_disable_all_features_with_exception,
3542 .notify_display_change = smu_v11_0_notify_display_change,
3543 .set_power_limit = smu_v11_0_set_power_limit,
3544 .init_max_sustainable_clocks = smu_v11_0_init_max_sustainable_clocks,
3545 .enable_thermal_alert = smu_v11_0_enable_thermal_alert,
3546 .disable_thermal_alert = smu_v11_0_disable_thermal_alert,
3547 .set_min_dcef_deep_sleep = smu_v11_0_set_min_deep_sleep_dcefclk,
3548 .display_clock_voltage_request = smu_v11_0_display_clock_voltage_request,
3549 .get_fan_control_mode = smu_v11_0_get_fan_control_mode,
3550 .set_fan_control_mode = smu_v11_0_set_fan_control_mode,
3551 .set_fan_speed_pwm = smu_v11_0_set_fan_speed_pwm,
3552 .set_fan_speed_rpm = smu_v11_0_set_fan_speed_rpm,
3553 .set_xgmi_pstate = smu_v11_0_set_xgmi_pstate,
3554 .gfx_off_control = smu_v11_0_gfx_off_control,
3555 .register_irq_handler = smu_v11_0_register_irq_handler,
3556 .set_azalia_d3_pme = smu_v11_0_set_azalia_d3_pme,
3557 .get_max_sustainable_clocks_by_dc = smu_v11_0_get_max_sustainable_clocks_by_dc,
3558 .get_bamaco_support = smu_v11_0_get_bamaco_support,
3559 .baco_enter = navi10_baco_enter,
3560 .baco_exit = navi10_baco_exit,
3561 .get_dpm_ultimate_freq = smu_v11_0_get_dpm_ultimate_freq,
3562 .set_soft_freq_limited_range = smu_v11_0_set_soft_freq_limited_range,
3563 .set_default_od_settings = navi10_set_default_od_settings,
3564 .od_edit_dpm_table = navi10_od_edit_dpm_table,
3565 .restore_user_od_settings = smu_v11_0_restore_user_od_settings,
3566 .run_btc = navi10_run_btc,
3567 .set_power_source = smu_v11_0_set_power_source,
3568 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3569 .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
3570 .get_gpu_metrics = navi1x_get_gpu_metrics,
3571 .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
3572 .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
3573 .deep_sleep_control = smu_v11_0_deep_sleep_control,
3574 .get_fan_parameters = navi10_get_fan_parameters,
3575 .post_init = navi10_post_smu_init,
3576 .interrupt_work = smu_v11_0_interrupt_work,
3577 .set_mp1_state = smu_cmn_set_mp1_state,
3578 .get_default_config_table_settings = navi10_get_default_config_table_settings,
3579 .set_config_table = navi10_set_config_table,
3580 };
3581
navi10_set_ppt_funcs(struct smu_context * smu)3582 void navi10_set_ppt_funcs(struct smu_context *smu)
3583 {
3584 smu->ppt_funcs = &navi10_ppt_funcs;
3585 smu->message_map = navi10_message_map;
3586 smu->clock_map = navi10_clk_map;
3587 smu->feature_map = navi10_feature_mask_map;
3588 smu->table_map = navi10_table_map;
3589 smu->pwr_src_map = navi10_pwr_src_map;
3590 smu->workload_map = navi10_workload_map;
3591 smu_v11_0_set_smu_mailbox_registers(smu);
3592 }
3593