1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the r8a73a4 SoC 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Magnus Damm 7 */ 8 9#include <dt-bindings/clock/r8a73a4-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12 13/ { 14 compatible = "renesas,r8a73a4"; 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 23 cpu0: cpu@0 { 24 device_type = "cpu"; 25 compatible = "arm,cortex-a15"; 26 reg = <0>; 27 clocks = <&cpg_clocks R8A73A4_CLK_Z>; 28 clock-frequency = <1500000000>; 29 power-domains = <&pd_a2sl>; 30 next-level-cache = <&L2_CA15>; 31 }; 32 33 L2_CA15: cache-controller-0 { 34 compatible = "cache"; 35 clocks = <&cpg_clocks R8A73A4_CLK_Z>; 36 power-domains = <&pd_a3sm>; 37 cache-unified; 38 cache-level = <2>; 39 }; 40 41 L2_CA7: cache-controller-1 { 42 compatible = "cache"; 43 clocks = <&cpg_clocks R8A73A4_CLK_Z2>; 44 power-domains = <&pd_a3km>; 45 cache-unified; 46 cache-level = <2>; 47 }; 48 }; 49 50 ptm { 51 compatible = "arm,coresight-etm3x"; 52 power-domains = <&pd_d4>; 53 }; 54 55 timer { 56 compatible = "arm,armv7-timer"; 57 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 58 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 59 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>, 60 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>; 61 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys"; 62 }; 63 64 tmu0: timer@e61e0000 { 65 compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 66 reg = <0 0xe61e0000 0 0x30>; 67 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 68 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 69 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; 70 interrupt-names = "tuni0", "tuni1", "tuni2"; 71 clocks = <&mstp1_clks R8A73A4_CLK_TMU0>; 72 clock-names = "fck"; 73 power-domains = <&pd_c5>; 74 status = "disabled"; 75 }; 76 77 tmu3: timer@fff80000 { 78 compatible = "renesas,tmu-r8a73a4", "renesas,tmu"; 79 reg = <0 0xfff80000 0 0x30>; 80 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 81 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 82 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 83 interrupt-names = "tuni0", "tuni1", "tuni2"; 84 clocks = <&mstp1_clks R8A73A4_CLK_TMU3>; 85 clock-names = "fck"; 86 power-domains = <&pd_a3r>; 87 status = "disabled"; 88 }; 89 90 dbsc1: memory-controller@e6790000 { 91 compatible = "renesas,dbsc-r8a73a4"; 92 reg = <0 0xe6790000 0 0x10000>; 93 power-domains = <&pd_a3bc>; 94 }; 95 96 dbsc2: memory-controller@e67a0000 { 97 compatible = "renesas,dbsc-r8a73a4"; 98 reg = <0 0xe67a0000 0 0x10000>; 99 power-domains = <&pd_a3bc>; 100 }; 101 102 i2c5: i2c@e60b0000 { 103 #address-cells = <1>; 104 #size-cells = <0>; 105 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 106 reg = <0 0xe60b0000 0 0x428>; 107 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 108 clocks = <&mstp4_clks R8A73A4_CLK_IIC5>; 109 power-domains = <&pd_a3sp>; 110 111 status = "disabled"; 112 }; 113 114 cmt1: timer@e6130000 { 115 compatible = "renesas,r8a73a4-cmt1", "renesas,rcar-gen2-cmt1"; 116 reg = <0 0xe6130000 0 0x1004>; 117 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 118 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 119 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 120 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 121 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 122 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 123 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 124 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 125 clocks = <&mstp3_clks R8A73A4_CLK_CMT1>; 126 clock-names = "fck"; 127 power-domains = <&pd_c5>; 128 status = "disabled"; 129 }; 130 131 irqc0: interrupt-controller@e61c0000 { 132 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 133 #interrupt-cells = <2>; 134 interrupt-controller; 135 reg = <0 0xe61c0000 0 0x200>; 136 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, 137 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 138 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, 139 <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 140 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 141 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>, 142 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 144 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 145 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 146 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 147 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 151 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, 152 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, 153 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>, 154 <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, 155 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, 156 <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 158 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, 159 <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>, 161 <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>, 162 <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, 163 <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>, 164 <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>, 165 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>, 166 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 167 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 168 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 169 power-domains = <&pd_c4>; 170 }; 171 172 irqc1: interrupt-controller@e61c0200 { 173 compatible = "renesas,irqc-r8a73a4", "renesas,irqc"; 174 #interrupt-cells = <2>; 175 interrupt-controller; 176 reg = <0 0xe61c0200 0 0x200>; 177 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 178 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 179 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 180 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 181 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 182 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 183 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 184 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 186 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 187 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 188 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 189 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 190 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 191 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 192 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 193 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 194 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 195 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 196 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 197 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 198 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 200 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 201 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, 202 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 203 clocks = <&mstp4_clks R8A73A4_CLK_IRQC>; 204 power-domains = <&pd_c4>; 205 }; 206 207 pfc: pinctrl@e6050000 { 208 compatible = "renesas,pfc-r8a73a4"; 209 reg = <0 0xe6050000 0 0x9000>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 gpio-ranges = 213 <&pfc 0 0 31>, <&pfc 32 32 9>, 214 <&pfc 64 64 22>, <&pfc 96 96 31>, 215 <&pfc 128 128 7>, <&pfc 160 160 19>, 216 <&pfc 192 192 31>, <&pfc 224 224 27>, 217 <&pfc 256 256 28>, <&pfc 288 288 21>, 218 <&pfc 320 320 10>; 219 interrupts-extended = 220 <&irqc0 0 0>, <&irqc0 1 0>, <&irqc0 2 0>, <&irqc0 3 0>, 221 <&irqc0 4 0>, <&irqc0 5 0>, <&irqc0 6 0>, <&irqc0 7 0>, 222 <&irqc0 8 0>, <&irqc0 9 0>, <&irqc0 10 0>, <&irqc0 11 0>, 223 <&irqc0 12 0>, <&irqc0 13 0>, <&irqc0 14 0>, <&irqc0 15 0>, 224 <&irqc0 16 0>, <&irqc0 17 0>, <&irqc0 18 0>, <&irqc0 19 0>, 225 <&irqc0 20 0>, <&irqc0 21 0>, <&irqc0 22 0>, <&irqc0 23 0>, 226 <&irqc0 24 0>, <&irqc0 25 0>, <&irqc0 26 0>, <&irqc0 27 0>, 227 <&irqc0 28 0>, <&irqc0 29 0>, <&irqc0 30 0>, <&irqc0 31 0>, 228 <&irqc1 0 0>, <&irqc1 1 0>, <&irqc1 2 0>, <&irqc1 3 0>, 229 <&irqc1 4 0>, <&irqc1 5 0>, <&irqc1 6 0>, <&irqc1 7 0>, 230 <&irqc1 8 0>, <&irqc1 9 0>, <&irqc1 10 0>, <&irqc1 11 0>, 231 <&irqc1 12 0>, <&irqc1 13 0>, <&irqc1 14 0>, <&irqc1 15 0>, 232 <&irqc1 16 0>, <&irqc1 17 0>, <&irqc1 18 0>, <&irqc1 19 0>, 233 <&irqc1 20 0>, <&irqc1 21 0>, <&irqc1 22 0>, <&irqc1 23 0>, 234 <&irqc1 24 0>, <&irqc1 25 0>; 235 power-domains = <&pd_c5>; 236 }; 237 238 thermal@e61f0000 { 239 compatible = "renesas,thermal-r8a73a4", "renesas,rcar-thermal"; 240 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>, 241 <0 0xe61f0200 0 0x38>, <0 0xe61f0300 0 0x38>; 242 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&mstp5_clks R8A73A4_CLK_THERMAL>; 244 power-domains = <&pd_c5>; 245 }; 246 247 i2c0: i2c@e6500000 { 248 #address-cells = <1>; 249 #size-cells = <0>; 250 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 251 reg = <0 0xe6500000 0 0x428>; 252 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 253 clocks = <&mstp3_clks R8A73A4_CLK_IIC0>; 254 power-domains = <&pd_a3sp>; 255 status = "disabled"; 256 }; 257 258 i2c1: i2c@e6510000 { 259 #address-cells = <1>; 260 #size-cells = <0>; 261 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 262 reg = <0 0xe6510000 0 0x428>; 263 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&mstp3_clks R8A73A4_CLK_IIC1>; 265 power-domains = <&pd_a3sp>; 266 status = "disabled"; 267 }; 268 269 i2c2: i2c@e6520000 { 270 #address-cells = <1>; 271 #size-cells = <0>; 272 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 273 reg = <0 0xe6520000 0 0x428>; 274 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; 275 clocks = <&mstp3_clks R8A73A4_CLK_IIC2>; 276 power-domains = <&pd_a3sp>; 277 status = "disabled"; 278 }; 279 280 i2c3: i2c@e6530000 { 281 #address-cells = <1>; 282 #size-cells = <0>; 283 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 284 reg = <0 0xe6530000 0 0x428>; 285 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 286 clocks = <&mstp4_clks R8A73A4_CLK_IIC3>; 287 power-domains = <&pd_a3sp>; 288 status = "disabled"; 289 }; 290 291 i2c4: i2c@e6540000 { 292 #address-cells = <1>; 293 #size-cells = <0>; 294 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 295 reg = <0 0xe6540000 0 0x428>; 296 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 297 clocks = <&mstp4_clks R8A73A4_CLK_IIC4>; 298 power-domains = <&pd_a3sp>; 299 status = "disabled"; 300 }; 301 302 i2c6: i2c@e6550000 { 303 #address-cells = <1>; 304 #size-cells = <0>; 305 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 306 reg = <0 0xe6550000 0 0x428>; 307 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 308 clocks = <&mstp3_clks R8A73A4_CLK_IIC6>; 309 power-domains = <&pd_a3sp>; 310 status = "disabled"; 311 }; 312 313 i2c7: i2c@e6560000 { 314 #address-cells = <1>; 315 #size-cells = <0>; 316 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 317 reg = <0 0xe6560000 0 0x428>; 318 interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 319 clocks = <&mstp3_clks R8A73A4_CLK_IIC7>; 320 power-domains = <&pd_a3sp>; 321 status = "disabled"; 322 }; 323 324 i2c8: i2c@e6570000 { 325 #address-cells = <1>; 326 #size-cells = <0>; 327 compatible = "renesas,iic-r8a73a4", "renesas,rmobile-iic"; 328 reg = <0 0xe6570000 0 0x428>; 329 interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 330 clocks = <&mstp5_clks R8A73A4_CLK_IIC8>; 331 power-domains = <&pd_a3sp>; 332 status = "disabled"; 333 }; 334 335 scifb0: serial@e6c20000 { 336 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 337 reg = <0 0xe6c20000 0 0x100>; 338 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 339 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB0>; 340 clock-names = "fck"; 341 power-domains = <&pd_a3sp>; 342 status = "disabled"; 343 }; 344 345 scifb1: serial@e6c30000 { 346 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 347 reg = <0 0xe6c30000 0 0x100>; 348 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB1>; 350 clock-names = "fck"; 351 power-domains = <&pd_a3sp>; 352 status = "disabled"; 353 }; 354 355 scifa0: serial@e6c40000 { 356 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 357 reg = <0 0xe6c40000 0 0x100>; 358 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 359 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA0>; 360 clock-names = "fck"; 361 power-domains = <&pd_a3sp>; 362 status = "disabled"; 363 }; 364 365 scifa1: serial@e6c50000 { 366 compatible = "renesas,scifa-r8a73a4", "renesas,scifa"; 367 reg = <0 0xe6c50000 0 0x100>; 368 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 369 clocks = <&mstp2_clks R8A73A4_CLK_SCIFA1>; 370 clock-names = "fck"; 371 power-domains = <&pd_a3sp>; 372 status = "disabled"; 373 }; 374 375 scifb2: serial@e6ce0000 { 376 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 377 reg = <0 0xe6ce0000 0 0x100>; 378 interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB2>; 380 clock-names = "fck"; 381 power-domains = <&pd_a3sp>; 382 status = "disabled"; 383 }; 384 385 scifb3: serial@e6cf0000 { 386 compatible = "renesas,scifb-r8a73a4", "renesas,scifb"; 387 reg = <0 0xe6cf0000 0 0x100>; 388 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>; 389 clocks = <&mstp2_clks R8A73A4_CLK_SCIFB3>; 390 clock-names = "fck"; 391 power-domains = <&pd_c4>; 392 status = "disabled"; 393 }; 394 395 sdhi0: mmc@ee100000 { 396 compatible = "renesas,sdhi-r8a73a4"; 397 reg = <0 0xee100000 0 0x100>; 398 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>; 399 clocks = <&mstp3_clks R8A73A4_CLK_SDHI0>; 400 power-domains = <&pd_a3sp>; 401 cap-sd-highspeed; 402 status = "disabled"; 403 }; 404 405 sdhi1: mmc@ee120000 { 406 compatible = "renesas,sdhi-r8a73a4"; 407 reg = <0 0xee120000 0 0x100>; 408 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; 409 clocks = <&mstp3_clks R8A73A4_CLK_SDHI1>; 410 power-domains = <&pd_a3sp>; 411 cap-sd-highspeed; 412 status = "disabled"; 413 }; 414 415 sdhi2: mmc@ee140000 { 416 compatible = "renesas,sdhi-r8a73a4"; 417 reg = <0 0xee140000 0 0x100>; 418 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>; 419 clocks = <&mstp3_clks R8A73A4_CLK_SDHI2>; 420 power-domains = <&pd_a3sp>; 421 cap-sd-highspeed; 422 status = "disabled"; 423 }; 424 425 mmcif0: mmc@ee200000 { 426 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 427 reg = <0 0xee200000 0 0x80>; 428 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF0>; 430 power-domains = <&pd_a3sp>; 431 reg-io-width = <4>; 432 status = "disabled"; 433 }; 434 435 mmcif1: mmc@ee220000 { 436 compatible = "renesas,mmcif-r8a73a4", "renesas,sh-mmcif"; 437 reg = <0 0xee220000 0 0x80>; 438 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&mstp3_clks R8A73A4_CLK_MMCIF1>; 440 power-domains = <&pd_a3sp>; 441 reg-io-width = <4>; 442 status = "disabled"; 443 }; 444 445 gic: interrupt-controller@f1001000 { 446 compatible = "arm,gic-400"; 447 #interrupt-cells = <3>; 448 #address-cells = <0>; 449 interrupt-controller; 450 reg = <0 0xf1001000 0 0x1000>, 451 <0 0xf1002000 0 0x2000>, 452 <0 0xf1004000 0 0x2000>, 453 <0 0xf1006000 0 0x2000>; 454 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>; 455 clocks = <&mstp4_clks R8A73A4_CLK_INTC_SYS>; 456 clock-names = "clk"; 457 power-domains = <&pd_c4>; 458 }; 459 460 bsc: bus@fec10000 { 461 compatible = "renesas,bsc-r8a73a4", "renesas,bsc", 462 "simple-pm-bus"; 463 #address-cells = <1>; 464 #size-cells = <1>; 465 ranges = <0 0 0 0x20000000>; 466 reg = <0 0xfec10000 0 0x400>; 467 clocks = <&zb_clk>; 468 power-domains = <&pd_c4>; 469 }; 470 471 clocks { 472 #address-cells = <2>; 473 #size-cells = <2>; 474 ranges; 475 476 /* External root clocks */ 477 extalr_clk: extalr { 478 compatible = "fixed-clock"; 479 #clock-cells = <0>; 480 /* This value must be overridden by the board. */ 481 clock-frequency = <0>; 482 }; 483 extal1_clk: extal1 { 484 compatible = "fixed-clock"; 485 #clock-cells = <0>; 486 /* This value must be overridden by the board. */ 487 clock-frequency = <0>; 488 }; 489 extal2_clk: extal2 { 490 compatible = "fixed-clock"; 491 #clock-cells = <0>; 492 /* This value must be overridden by the board. */ 493 clock-frequency = <0>; 494 }; 495 fsiack_clk: fsiack { 496 compatible = "fixed-clock"; 497 #clock-cells = <0>; 498 /* This value must be overridden by the board. */ 499 clock-frequency = <0>; 500 }; 501 fsibck_clk: fsibck { 502 compatible = "fixed-clock"; 503 #clock-cells = <0>; 504 /* This value must be overridden by the board. */ 505 clock-frequency = <0>; 506 }; 507 508 /* Special CPG clocks */ 509 cpg_clocks: cpg_clocks@e6150000 { 510 compatible = "renesas,r8a73a4-cpg-clocks"; 511 reg = <0 0xe6150000 0 0x10000>; 512 clocks = <&extal1_clk>, <&extal2_clk>; 513 #clock-cells = <1>; 514 clock-output-names = "main", "pll0", "pll1", "pll2", 515 "pll2s", "pll2h", "z", "z2", 516 "i", "m3", "b", "m1", "m2", 517 "zx", "zs", "hp"; 518 }; 519 520 /* Variable factor clocks (DIV6) */ 521 zb_clk: zb_clk@e6150010 { 522 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 523 reg = <0 0xe6150010 0 4>; 524 clocks = <&pll1_div2_clk>, <0>, 525 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 526 #clock-cells = <0>; 527 clock-output-names = "zb"; 528 }; 529 sdhi0_clk: sdhi0ck@e6150074 { 530 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 531 reg = <0 0xe6150074 0 4>; 532 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 533 <0>, <&extal2_clk>; 534 #clock-cells = <0>; 535 }; 536 sdhi1_clk: sdhi1ck@e6150078 { 537 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 538 reg = <0 0xe6150078 0 4>; 539 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 540 <0>, <&extal2_clk>; 541 #clock-cells = <0>; 542 }; 543 sdhi2_clk: sdhi2ck@e615007c { 544 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 545 reg = <0 0xe615007c 0 4>; 546 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 547 <0>, <&extal2_clk>; 548 #clock-cells = <0>; 549 }; 550 mmc0_clk: mmc0@e6150240 { 551 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 552 reg = <0 0xe6150240 0 4>; 553 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 554 <0>, <&extal2_clk>; 555 #clock-cells = <0>; 556 }; 557 mmc1_clk: mmc1@e6150244 { 558 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 559 reg = <0 0xe6150244 0 4>; 560 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 561 <0>, <&extal2_clk>; 562 #clock-cells = <0>; 563 }; 564 vclk1_clk: vclk1@e6150008 { 565 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 566 reg = <0 0xe6150008 0 4>; 567 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 568 <0>, <&extal2_clk>, <&main_div2_clk>, 569 <&extalr_clk>, <0>, <0>; 570 #clock-cells = <0>; 571 }; 572 vclk2_clk: vclk2@e615000c { 573 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 574 reg = <0 0xe615000c 0 4>; 575 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 576 <0>, <&extal2_clk>, <&main_div2_clk>, 577 <&extalr_clk>, <0>, <0>; 578 #clock-cells = <0>; 579 }; 580 vclk3_clk: vclk3@e615001c { 581 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 582 reg = <0 0xe615001c 0 4>; 583 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 584 <0>, <&extal2_clk>, <&main_div2_clk>, 585 <&extalr_clk>, <0>, <0>; 586 #clock-cells = <0>; 587 }; 588 vclk4_clk: vclk4@e6150014 { 589 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 590 reg = <0 0xe6150014 0 4>; 591 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 592 <0>, <&extal2_clk>, <&main_div2_clk>, 593 <&extalr_clk>, <0>, <0>; 594 #clock-cells = <0>; 595 }; 596 vclk5_clk: vclk5@e6150034 { 597 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 598 reg = <0 0xe6150034 0 4>; 599 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 600 <0>, <&extal2_clk>, <&main_div2_clk>, 601 <&extalr_clk>, <0>, <0>; 602 #clock-cells = <0>; 603 }; 604 fsia_clk: fsia@e6150018 { 605 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 606 reg = <0 0xe6150018 0 4>; 607 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 608 <&fsiack_clk>, <0>; 609 #clock-cells = <0>; 610 }; 611 fsib_clk: fsib@e6150090 { 612 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 613 reg = <0 0xe6150090 0 4>; 614 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 615 <&fsibck_clk>, <0>; 616 #clock-cells = <0>; 617 }; 618 mp_clk: mp@e6150080 { 619 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 620 reg = <0 0xe6150080 0 4>; 621 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 622 <&extal2_clk>, <&extal2_clk>; 623 #clock-cells = <0>; 624 }; 625 m4_clk: m4@e6150098 { 626 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 627 reg = <0 0xe6150098 0 4>; 628 clocks = <&cpg_clocks R8A73A4_CLK_PLL2S>; 629 #clock-cells = <0>; 630 }; 631 hsi_clk: hsi@e615026c { 632 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 633 reg = <0 0xe615026c 0 4>; 634 clocks = <&cpg_clocks R8A73A4_CLK_PLL2H>, <&pll1_div2_clk>, 635 <&cpg_clocks R8A73A4_CLK_PLL2S>, <0>; 636 #clock-cells = <0>; 637 }; 638 spuv_clk: spuv@e6150094 { 639 compatible = "renesas,r8a73a4-div6-clock", "renesas,cpg-div6-clock"; 640 reg = <0 0xe6150094 0 4>; 641 clocks = <&pll1_div2_clk>, <&cpg_clocks R8A73A4_CLK_PLL2S>, 642 <&extal2_clk>, <&extal2_clk>; 643 #clock-cells = <0>; 644 }; 645 646 /* Fixed factor clocks */ 647 main_div2_clk: main_div2 { 648 compatible = "fixed-factor-clock"; 649 clocks = <&cpg_clocks R8A73A4_CLK_MAIN>; 650 #clock-cells = <0>; 651 clock-div = <2>; 652 clock-mult = <1>; 653 }; 654 cp_clk: cp { 655 compatible = "fixed-factor-clock"; 656 clocks = <&main_div2_clk>; 657 #clock-cells = <0>; 658 clock-div = <1>; 659 clock-mult = <1>; 660 }; 661 pll0_div2_clk: pll0_div2 { 662 compatible = "fixed-factor-clock"; 663 clocks = <&cpg_clocks R8A73A4_CLK_PLL0>; 664 #clock-cells = <0>; 665 clock-div = <2>; 666 clock-mult = <1>; 667 }; 668 pll1_div2_clk: pll1_div2 { 669 compatible = "fixed-factor-clock"; 670 clocks = <&cpg_clocks R8A73A4_CLK_PLL1>; 671 #clock-cells = <0>; 672 clock-div = <2>; 673 clock-mult = <1>; 674 }; 675 extal1_div2_clk: extal1_div2 { 676 compatible = "fixed-factor-clock"; 677 clocks = <&extal1_clk>; 678 #clock-cells = <0>; 679 clock-div = <2>; 680 clock-mult = <1>; 681 }; 682 683 /* Gate clocks */ 684 mstp1_clks: mstp1_clks@e6150134 { 685 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 686 reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; 687 clocks = <&cp_clk>, <&mp_clk>; 688 #clock-cells = <1>; 689 clock-indices = < 690 R8A73A4_CLK_TMU0 R8A73A4_CLK_TMU3 691 >; 692 clock-output-names = 693 "tmu0", "tmu3"; 694 }; 695 mstp2_clks: mstp2_clks@e6150138 { 696 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 697 reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; 698 clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, 699 <&mp_clk>, <&mp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 700 #clock-cells = <1>; 701 clock-indices = < 702 R8A73A4_CLK_SCIFA0 R8A73A4_CLK_SCIFA1 703 R8A73A4_CLK_SCIFB0 R8A73A4_CLK_SCIFB1 704 R8A73A4_CLK_SCIFB2 R8A73A4_CLK_SCIFB3 705 R8A73A4_CLK_DMAC 706 >; 707 clock-output-names = 708 "scifa0", "scifa1", "scifb0", "scifb1", 709 "scifb2", "scifb3", "dmac"; 710 }; 711 mstp3_clks: mstp3_clks@e615013c { 712 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 713 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 714 clocks = <&cpg_clocks R8A73A4_CLK_HP>, <&mmc1_clk>, 715 <&sdhi2_clk>, <&sdhi1_clk>, <&sdhi0_clk>, 716 <&mmc0_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 717 <&cpg_clocks R8A73A4_CLK_HP>, <&cpg_clocks 718 R8A73A4_CLK_HP>, <&cpg_clocks 719 R8A73A4_CLK_HP>, <&extalr_clk>; 720 #clock-cells = <1>; 721 clock-indices = < 722 R8A73A4_CLK_IIC2 R8A73A4_CLK_MMCIF1 723 R8A73A4_CLK_SDHI2 R8A73A4_CLK_SDHI1 724 R8A73A4_CLK_SDHI0 R8A73A4_CLK_MMCIF0 725 R8A73A4_CLK_IIC6 R8A73A4_CLK_IIC7 726 R8A73A4_CLK_IIC0 R8A73A4_CLK_IIC1 727 R8A73A4_CLK_CMT1 728 >; 729 clock-output-names = 730 "iic2", "mmcif1", "sdhi2", "sdhi1", "sdhi0", 731 "mmcif0", "iic6", "iic7", "iic0", "iic1", 732 "cmt1"; 733 }; 734 mstp4_clks: mstp4_clks@e6150140 { 735 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 736 reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; 737 clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_ZS>, 738 <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>, 739 <&cpg_clocks R8A73A4_CLK_HP>; 740 #clock-cells = <1>; 741 clock-indices = < 742 R8A73A4_CLK_IRQC R8A73A4_CLK_INTC_SYS 743 R8A73A4_CLK_IIC5 R8A73A4_CLK_IIC4 744 R8A73A4_CLK_IIC3 745 >; 746 clock-output-names = 747 "irqc", "intc-sys", "iic5", "iic4", "iic3"; 748 }; 749 mstp5_clks: mstp5_clks@e6150144 { 750 compatible = "renesas,r8a73a4-mstp-clocks", "renesas,cpg-mstp-clocks"; 751 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 752 clocks = <&cp_clk>, <&cpg_clocks R8A73A4_CLK_HP>; 753 #clock-cells = <1>; 754 clock-indices = < 755 R8A73A4_CLK_THERMAL R8A73A4_CLK_IIC8 756 >; 757 clock-output-names = 758 "thermal", "iic8"; 759 }; 760 }; 761 762 prr: chipid@ff000044 { 763 compatible = "renesas,prr"; 764 reg = <0 0xff000044 0 4>; 765 }; 766 767 sysc: system-controller@e6180000 { 768 compatible = "renesas,sysc-r8a73a4", "renesas,sysc-rmobile"; 769 reg = <0 0xe6180000 0 0x8000>, <0 0xe6188000 0 0x8000>; 770 771 pm-domains { 772 pd_c5: c5 { 773 #address-cells = <1>; 774 #size-cells = <0>; 775 #power-domain-cells = <0>; 776 777 pd_c4: c4@0 { 778 reg = <0>; 779 #address-cells = <1>; 780 #size-cells = <0>; 781 #power-domain-cells = <0>; 782 783 pd_a3sg: a3sg@16 { 784 reg = <16>; 785 #power-domain-cells = <0>; 786 }; 787 788 pd_a3ex: a3ex@17 { 789 reg = <17>; 790 #power-domain-cells = <0>; 791 }; 792 793 pd_a3sp: a3sp@18 { 794 reg = <18>; 795 #address-cells = <1>; 796 #size-cells = <0>; 797 #power-domain-cells = <0>; 798 799 pd_a2us: a2us@19 { 800 reg = <19>; 801 #power-domain-cells = <0>; 802 }; 803 }; 804 805 pd_a3sm: a3sm@20 { 806 reg = <20>; 807 #address-cells = <1>; 808 #size-cells = <0>; 809 #power-domain-cells = <0>; 810 811 pd_a2sl: a2sl@21 { 812 reg = <21>; 813 #power-domain-cells = <0>; 814 }; 815 }; 816 817 pd_a3km: a3km@22 { 818 reg = <22>; 819 #address-cells = <1>; 820 #size-cells = <0>; 821 #power-domain-cells = <0>; 822 823 pd_a2kl: a2kl@23 { 824 reg = <23>; 825 #power-domain-cells = <0>; 826 }; 827 }; 828 }; 829 830 pd_c4ma: c4ma@1 { 831 reg = <1>; 832 #power-domain-cells = <0>; 833 }; 834 835 pd_c4cl: c4cl@2 { 836 reg = <2>; 837 #power-domain-cells = <0>; 838 }; 839 840 pd_d4: d4@3 { 841 reg = <3>; 842 #power-domain-cells = <0>; 843 }; 844 845 pd_a4bc: a4bc@4 { 846 reg = <4>; 847 #address-cells = <1>; 848 #size-cells = <0>; 849 #power-domain-cells = <0>; 850 851 pd_a3bc: a3bc@5 { 852 reg = <5>; 853 #power-domain-cells = <0>; 854 }; 855 }; 856 857 pd_a4l: a4l@6 { 858 reg = <6>; 859 #power-domain-cells = <0>; 860 }; 861 862 pd_a4lc: a4lc@7 { 863 reg = <7>; 864 #power-domain-cells = <0>; 865 }; 866 867 pd_a4mp: a4mp@8 { 868 reg = <8>; 869 #address-cells = <1>; 870 #size-cells = <0>; 871 #power-domain-cells = <0>; 872 873 pd_a3mp: a3mp@9 { 874 reg = <9>; 875 #power-domain-cells = <0>; 876 }; 877 878 pd_a3vc: a3vc@10 { 879 reg = <10>; 880 #power-domain-cells = <0>; 881 }; 882 }; 883 884 pd_a4sf: a4sf@11 { 885 reg = <11>; 886 #power-domain-cells = <0>; 887 }; 888 889 pd_a3r: a3r@12 { 890 reg = <12>; 891 #address-cells = <1>; 892 #size-cells = <0>; 893 #power-domain-cells = <0>; 894 895 pd_a2rv: a2rv@13 { 896 reg = <13>; 897 #power-domain-cells = <0>; 898 }; 899 900 pd_a2is: a2is@14 { 901 reg = <14>; 902 #power-domain-cells = <0>; 903 }; 904 }; 905 }; 906 }; 907 }; 908}; 909