1 /*
2  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
3  *
4  * This software is available to you under a choice of one of two
5  * licenses.  You may choose to be licensed under the terms of the GNU
6  * General Public License (GPL) Version 2, available from the file
7  * COPYING in the main directory of this source tree, or the
8  * OpenIB.org BSD license below:
9  *
10  *     Redistribution and use in source and binary forms, with or
11  *     without modification, are permitted provided that the following
12  *     conditions are met:
13  *
14  *      - Redistributions of source code must retain the above
15  *        copyright notice, this list of conditions and the following
16  *        disclaimer.
17  *
18  *      - Redistributions in binary form must reproduce the above
19  *        copyright notice, this list of conditions and the following
20  *        disclaimer in the documentation and/or other materials
21  *        provided with the distribution.
22  *
23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30  * SOFTWARE.
31  */
32 
33 #include <net/flow_dissector.h>
34 #include <net/flow_offload.h>
35 #include <net/sch_generic.h>
36 #include <net/pkt_cls.h>
37 #include <linux/mlx5/fs.h>
38 #include <linux/mlx5/device.h>
39 #include <linux/rhashtable.h>
40 #include <linux/refcount.h>
41 #include <linux/completion.h>
42 #include <net/arp.h>
43 #include <net/ipv6_stubs.h>
44 #include <net/bareudp.h>
45 #include <net/bonding.h>
46 #include <net/dst_metadata.h>
47 #include "devlink.h"
48 #include "en.h"
49 #include "en/tc/post_act.h"
50 #include "en/tc/act_stats.h"
51 #include "en_rep.h"
52 #include "en/rep/tc.h"
53 #include "en/rep/neigh.h"
54 #include "en_tc.h"
55 #include "eswitch.h"
56 #include "fs_core.h"
57 #include "en/port.h"
58 #include "en/tc_tun.h"
59 #include "en/mapping.h"
60 #include "en/tc_ct.h"
61 #include "en/mod_hdr.h"
62 #include "en/tc_tun_encap.h"
63 #include "en/tc/sample.h"
64 #include "en/tc/act/act.h"
65 #include "en/tc/post_meter.h"
66 #include "lib/devcom.h"
67 #include "lib/geneve.h"
68 #include "lib/fs_chains.h"
69 #include "diag/en_tc_tracepoint.h"
70 #include <asm/div64.h>
71 #include "lag/lag.h"
72 #include "lag/mp.h"
73 
74 #define MLX5E_TC_TABLE_NUM_GROUPS 4
75 #define MLX5E_TC_TABLE_MAX_GROUP_SIZE BIT(18)
76 
77 struct mlx5e_tc_table {
78 	/* Protects the dynamic assignment of the t parameter
79 	 * which is the nic tc root table.
80 	 */
81 	struct mutex			t_lock;
82 	struct mlx5e_priv		*priv;
83 	struct mlx5_flow_table		*t;
84 	struct mlx5_flow_table		*miss_t;
85 	struct mlx5_fs_chains           *chains;
86 	struct mlx5e_post_act		*post_act;
87 
88 	struct rhashtable               ht;
89 
90 	struct mod_hdr_tbl mod_hdr;
91 	struct mutex hairpin_tbl_lock; /* protects hairpin_tbl */
92 	DECLARE_HASHTABLE(hairpin_tbl, 8);
93 
94 	struct notifier_block     netdevice_nb;
95 	struct netdev_net_notifier	netdevice_nn;
96 
97 	struct mlx5_tc_ct_priv         *ct;
98 	struct mapping_ctx             *mapping;
99 	struct dentry                  *dfs_root;
100 
101 	/* tc action stats */
102 	struct mlx5e_tc_act_stats_handle *action_stats_handle;
103 };
104 
105 struct mlx5e_tc_attr_to_reg_mapping mlx5e_tc_attr_to_reg_mappings[] = {
106 	[MAPPED_OBJ_TO_REG] = {
107 		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
108 		.moffset = 0,
109 		.mlen = 16,
110 	},
111 	[VPORT_TO_REG] = {
112 		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_0,
113 		.moffset = 16,
114 		.mlen = 16,
115 	},
116 	[TUNNEL_TO_REG] = {
117 		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_C_1,
118 		.moffset = 8,
119 		.mlen = ESW_TUN_OPTS_BITS + ESW_TUN_ID_BITS,
120 		.soffset = MLX5_BYTE_OFF(fte_match_param,
121 					 misc_parameters_2.metadata_reg_c_1),
122 	},
123 	[ZONE_TO_REG] = zone_to_reg_ct,
124 	[ZONE_RESTORE_TO_REG] = zone_restore_to_reg_ct,
125 	[CTSTATE_TO_REG] = ctstate_to_reg_ct,
126 	[MARK_TO_REG] = mark_to_reg_ct,
127 	[LABELS_TO_REG] = labels_to_reg_ct,
128 	[FTEID_TO_REG] = fteid_to_reg_ct,
129 	/* For NIC rules we store the restore metadata directly
130 	 * into reg_b that is passed to SW since we don't
131 	 * jump between steering domains.
132 	 */
133 	[NIC_MAPPED_OBJ_TO_REG] = {
134 		.mfield = MLX5_ACTION_IN_FIELD_METADATA_REG_B,
135 		.moffset = 0,
136 		.mlen = 16,
137 	},
138 	[NIC_ZONE_RESTORE_TO_REG] = nic_zone_restore_to_reg_ct,
139 	[PACKET_COLOR_TO_REG] = packet_color_to_reg,
140 };
141 
142 struct mlx5e_tc_jump_state {
143 	u32 jump_count;
144 	bool jump_target;
145 	struct mlx5_flow_attr *jumping_attr;
146 
147 	enum flow_action_id last_id;
148 	u32 last_index;
149 };
150 
mlx5e_tc_table_alloc(void)151 struct mlx5e_tc_table *mlx5e_tc_table_alloc(void)
152 {
153 	struct mlx5e_tc_table *tc;
154 
155 	tc = kvzalloc(sizeof(*tc), GFP_KERNEL);
156 	return tc ? tc : ERR_PTR(-ENOMEM);
157 }
158 
mlx5e_tc_table_free(struct mlx5e_tc_table * tc)159 void mlx5e_tc_table_free(struct mlx5e_tc_table *tc)
160 {
161 	kvfree(tc);
162 }
163 
mlx5e_nic_chains(struct mlx5e_tc_table * tc)164 struct mlx5_fs_chains *mlx5e_nic_chains(struct mlx5e_tc_table *tc)
165 {
166 	return tc->chains;
167 }
168 
169 /* To avoid false lock dependency warning set the tc_ht lock
170  * class different than the lock class of the ht being used when deleting
171  * last flow from a group and then deleting a group, we get into del_sw_flow_group()
172  * which call rhashtable_destroy on fg->ftes_hash which will take ht->mutex but
173  * it's different than the ht->mutex here.
174  */
175 static struct lock_class_key tc_ht_lock_key;
176 static struct lock_class_key tc_ht_wq_key;
177 
178 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow);
179 static void free_flow_post_acts(struct mlx5e_tc_flow *flow);
180 static void mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow,
181 					struct mlx5_flow_attr *attr);
182 
183 void
mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec * spec,enum mlx5e_tc_attr_to_reg type,u32 val,u32 mask)184 mlx5e_tc_match_to_reg_match(struct mlx5_flow_spec *spec,
185 			    enum mlx5e_tc_attr_to_reg type,
186 			    u32 val,
187 			    u32 mask)
188 {
189 	void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
190 	int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
191 	int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
192 	int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
193 	u32 max_mask = GENMASK(match_len - 1, 0);
194 	__be32 curr_mask_be, curr_val_be;
195 	u32 curr_mask, curr_val;
196 
197 	fmask = headers_c + soffset;
198 	fval = headers_v + soffset;
199 
200 	memcpy(&curr_mask_be, fmask, 4);
201 	memcpy(&curr_val_be, fval, 4);
202 
203 	curr_mask = be32_to_cpu(curr_mask_be);
204 	curr_val = be32_to_cpu(curr_val_be);
205 
206 	//move to correct offset
207 	WARN_ON(mask > max_mask);
208 	mask <<= moffset;
209 	val <<= moffset;
210 	max_mask <<= moffset;
211 
212 	//zero val and mask
213 	curr_mask &= ~max_mask;
214 	curr_val &= ~max_mask;
215 
216 	//add current to mask
217 	curr_mask |= mask;
218 	curr_val |= val;
219 
220 	//back to be32 and write
221 	curr_mask_be = cpu_to_be32(curr_mask);
222 	curr_val_be = cpu_to_be32(curr_val);
223 
224 	memcpy(fmask, &curr_mask_be, 4);
225 	memcpy(fval, &curr_val_be, 4);
226 
227 	spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_2;
228 }
229 
230 void
mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec * spec,enum mlx5e_tc_attr_to_reg type,u32 * val,u32 * mask)231 mlx5e_tc_match_to_reg_get_match(struct mlx5_flow_spec *spec,
232 				enum mlx5e_tc_attr_to_reg type,
233 				u32 *val,
234 				u32 *mask)
235 {
236 	void *headers_c = spec->match_criteria, *headers_v = spec->match_value, *fmask, *fval;
237 	int soffset = mlx5e_tc_attr_to_reg_mappings[type].soffset;
238 	int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
239 	int match_len = mlx5e_tc_attr_to_reg_mappings[type].mlen;
240 	u32 max_mask = GENMASK(match_len - 1, 0);
241 	__be32 curr_mask_be, curr_val_be;
242 	u32 curr_mask, curr_val;
243 
244 	fmask = headers_c + soffset;
245 	fval = headers_v + soffset;
246 
247 	memcpy(&curr_mask_be, fmask, 4);
248 	memcpy(&curr_val_be, fval, 4);
249 
250 	curr_mask = be32_to_cpu(curr_mask_be);
251 	curr_val = be32_to_cpu(curr_val_be);
252 
253 	*mask = (curr_mask >> moffset) & max_mask;
254 	*val = (curr_val >> moffset) & max_mask;
255 }
256 
257 int
mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5_flow_namespace_type ns,enum mlx5e_tc_attr_to_reg type,u32 data)258 mlx5e_tc_match_to_reg_set_and_get_id(struct mlx5_core_dev *mdev,
259 				     struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
260 				     enum mlx5_flow_namespace_type ns,
261 				     enum mlx5e_tc_attr_to_reg type,
262 				     u32 data)
263 {
264 	int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
265 	int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
266 	int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
267 	char *modact;
268 	int err;
269 
270 	modact = mlx5e_mod_hdr_alloc(mdev, ns, mod_hdr_acts);
271 	if (IS_ERR(modact))
272 		return PTR_ERR(modact);
273 
274 	/* Firmware has 5bit length field and 0 means 32bits */
275 	if (mlen == 32)
276 		mlen = 0;
277 
278 	MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
279 	MLX5_SET(set_action_in, modact, field, mfield);
280 	MLX5_SET(set_action_in, modact, offset, moffset);
281 	MLX5_SET(set_action_in, modact, length, mlen);
282 	MLX5_SET(set_action_in, modact, data, data);
283 	err = mod_hdr_acts->num_actions;
284 	mod_hdr_acts->num_actions++;
285 
286 	return err;
287 }
288 
289 static struct mlx5e_tc_act_stats_handle  *
get_act_stats_handle(struct mlx5e_priv * priv)290 get_act_stats_handle(struct mlx5e_priv *priv)
291 {
292 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
293 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
294 	struct mlx5_rep_uplink_priv *uplink_priv;
295 	struct mlx5e_rep_priv *uplink_rpriv;
296 
297 	if (is_mdev_switchdev_mode(priv->mdev)) {
298 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
299 		uplink_priv = &uplink_rpriv->uplink_priv;
300 
301 		return uplink_priv->action_stats_handle;
302 	}
303 
304 	return tc->action_stats_handle;
305 }
306 
307 struct mlx5e_tc_int_port_priv *
mlx5e_get_int_port_priv(struct mlx5e_priv * priv)308 mlx5e_get_int_port_priv(struct mlx5e_priv *priv)
309 {
310 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
311 	struct mlx5_rep_uplink_priv *uplink_priv;
312 	struct mlx5e_rep_priv *uplink_rpriv;
313 
314 	if (is_mdev_switchdev_mode(priv->mdev)) {
315 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
316 		uplink_priv = &uplink_rpriv->uplink_priv;
317 
318 		return uplink_priv->int_port_priv;
319 	}
320 
321 	return NULL;
322 }
323 
324 struct mlx5e_flow_meters *
mlx5e_get_flow_meters(struct mlx5_core_dev * dev)325 mlx5e_get_flow_meters(struct mlx5_core_dev *dev)
326 {
327 	struct mlx5_eswitch *esw = dev->priv.eswitch;
328 	struct mlx5_rep_uplink_priv *uplink_priv;
329 	struct mlx5e_rep_priv *uplink_rpriv;
330 	struct mlx5e_priv *priv;
331 
332 	if (is_mdev_switchdev_mode(dev)) {
333 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
334 		uplink_priv = &uplink_rpriv->uplink_priv;
335 		priv = netdev_priv(uplink_rpriv->netdev);
336 		if (!uplink_priv->flow_meters)
337 			uplink_priv->flow_meters =
338 				mlx5e_flow_meters_init(priv,
339 						       MLX5_FLOW_NAMESPACE_FDB,
340 						       uplink_priv->post_act);
341 		if (!IS_ERR(uplink_priv->flow_meters))
342 			return uplink_priv->flow_meters;
343 	}
344 
345 	return NULL;
346 }
347 
348 static struct mlx5_tc_ct_priv *
get_ct_priv(struct mlx5e_priv * priv)349 get_ct_priv(struct mlx5e_priv *priv)
350 {
351 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
352 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
353 	struct mlx5_rep_uplink_priv *uplink_priv;
354 	struct mlx5e_rep_priv *uplink_rpriv;
355 
356 	if (is_mdev_switchdev_mode(priv->mdev)) {
357 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
358 		uplink_priv = &uplink_rpriv->uplink_priv;
359 
360 		return uplink_priv->ct_priv;
361 	}
362 
363 	return tc->ct;
364 }
365 
366 static struct mlx5e_tc_psample *
get_sample_priv(struct mlx5e_priv * priv)367 get_sample_priv(struct mlx5e_priv *priv)
368 {
369 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
370 	struct mlx5_rep_uplink_priv *uplink_priv;
371 	struct mlx5e_rep_priv *uplink_rpriv;
372 
373 	if (is_mdev_switchdev_mode(priv->mdev)) {
374 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
375 		uplink_priv = &uplink_rpriv->uplink_priv;
376 
377 		return uplink_priv->tc_psample;
378 	}
379 
380 	return NULL;
381 }
382 
383 static struct mlx5e_post_act *
get_post_action(struct mlx5e_priv * priv)384 get_post_action(struct mlx5e_priv *priv)
385 {
386 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
387 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
388 	struct mlx5_rep_uplink_priv *uplink_priv;
389 	struct mlx5e_rep_priv *uplink_rpriv;
390 
391 	if (is_mdev_switchdev_mode(priv->mdev)) {
392 		uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
393 		uplink_priv = &uplink_rpriv->uplink_priv;
394 
395 		return uplink_priv->post_act;
396 	}
397 
398 	return tc->post_act;
399 }
400 
401 struct mlx5_flow_handle *
mlx5_tc_rule_insert(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)402 mlx5_tc_rule_insert(struct mlx5e_priv *priv,
403 		    struct mlx5_flow_spec *spec,
404 		    struct mlx5_flow_attr *attr)
405 {
406 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
407 
408 	if (is_mdev_switchdev_mode(priv->mdev))
409 		return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
410 
411 	return	mlx5e_add_offloaded_nic_rule(priv, spec, attr);
412 }
413 
414 void
mlx5_tc_rule_delete(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)415 mlx5_tc_rule_delete(struct mlx5e_priv *priv,
416 		    struct mlx5_flow_handle *rule,
417 		    struct mlx5_flow_attr *attr)
418 {
419 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
420 
421 	if (is_mdev_switchdev_mode(priv->mdev)) {
422 		mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
423 		return;
424 	}
425 
426 	mlx5e_del_offloaded_nic_rule(priv, rule, attr);
427 }
428 
429 static bool
is_flow_meter_action(struct mlx5_flow_attr * attr)430 is_flow_meter_action(struct mlx5_flow_attr *attr)
431 {
432 	return (((attr->action & MLX5_FLOW_CONTEXT_ACTION_EXECUTE_ASO) &&
433 		 (attr->exe_aso_type == MLX5_EXE_ASO_FLOW_METER)) ||
434 		attr->flags & MLX5_ATTR_FLAG_MTU);
435 }
436 
437 static int
mlx5e_tc_add_flow_meter(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr)438 mlx5e_tc_add_flow_meter(struct mlx5e_priv *priv,
439 			struct mlx5_flow_attr *attr)
440 {
441 	struct mlx5e_post_act *post_act = get_post_action(priv);
442 	struct mlx5e_post_meter_priv *post_meter;
443 	enum mlx5_flow_namespace_type ns_type;
444 	struct mlx5e_flow_meter_handle *meter;
445 	enum mlx5e_post_meter_type type;
446 
447 	if (IS_ERR(post_act))
448 		return PTR_ERR(post_act);
449 
450 	meter = mlx5e_tc_meter_replace(priv->mdev, &attr->meter_attr.params);
451 	if (IS_ERR(meter)) {
452 		mlx5_core_err(priv->mdev, "Failed to get flow meter\n");
453 		return PTR_ERR(meter);
454 	}
455 
456 	ns_type = mlx5e_tc_meter_get_namespace(meter->flow_meters);
457 	type = meter->params.mtu ? MLX5E_POST_METER_MTU : MLX5E_POST_METER_RATE;
458 	post_meter = mlx5e_post_meter_init(priv, ns_type, post_act,
459 					   type,
460 					   meter->act_counter, meter->drop_counter,
461 					   attr->branch_true, attr->branch_false);
462 	if (IS_ERR(post_meter)) {
463 		mlx5_core_err(priv->mdev, "Failed to init post meter\n");
464 		goto err_meter_init;
465 	}
466 
467 	attr->meter_attr.meter = meter;
468 	attr->meter_attr.post_meter = post_meter;
469 	attr->dest_ft = mlx5e_post_meter_get_ft(post_meter);
470 	attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
471 
472 	return 0;
473 
474 err_meter_init:
475 	mlx5e_tc_meter_put(meter);
476 	return PTR_ERR(post_meter);
477 }
478 
479 static void
mlx5e_tc_del_flow_meter(struct mlx5_eswitch * esw,struct mlx5_flow_attr * attr)480 mlx5e_tc_del_flow_meter(struct mlx5_eswitch *esw, struct mlx5_flow_attr *attr)
481 {
482 	mlx5e_post_meter_cleanup(esw, attr->meter_attr.post_meter);
483 	mlx5e_tc_meter_put(attr->meter_attr.meter);
484 }
485 
486 struct mlx5_flow_handle *
mlx5e_tc_rule_offload(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)487 mlx5e_tc_rule_offload(struct mlx5e_priv *priv,
488 		      struct mlx5_flow_spec *spec,
489 		      struct mlx5_flow_attr *attr)
490 {
491 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
492 	int err;
493 
494 	if (!is_mdev_switchdev_mode(priv->mdev))
495 		return mlx5e_add_offloaded_nic_rule(priv, spec, attr);
496 
497 	if (attr->flags & MLX5_ATTR_FLAG_SAMPLE)
498 		return mlx5e_tc_sample_offload(get_sample_priv(priv), spec, attr);
499 
500 	if (is_flow_meter_action(attr)) {
501 		err = mlx5e_tc_add_flow_meter(priv, attr);
502 		if (err)
503 			return ERR_PTR(err);
504 	}
505 
506 	return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
507 }
508 
509 void
mlx5e_tc_rule_unoffload(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)510 mlx5e_tc_rule_unoffload(struct mlx5e_priv *priv,
511 			struct mlx5_flow_handle *rule,
512 			struct mlx5_flow_attr *attr)
513 {
514 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
515 
516 	if (!is_mdev_switchdev_mode(priv->mdev)) {
517 		mlx5e_del_offloaded_nic_rule(priv, rule, attr);
518 		return;
519 	}
520 
521 	if (attr->flags & MLX5_ATTR_FLAG_SAMPLE) {
522 		mlx5e_tc_sample_unoffload(get_sample_priv(priv), rule, attr);
523 		return;
524 	}
525 
526 	mlx5_eswitch_del_offloaded_rule(esw, rule, attr);
527 
528 	if (attr->meter_attr.meter)
529 		mlx5e_tc_del_flow_meter(esw, attr);
530 }
531 
532 int
mlx5e_tc_match_to_reg_set(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5_flow_namespace_type ns,enum mlx5e_tc_attr_to_reg type,u32 data)533 mlx5e_tc_match_to_reg_set(struct mlx5_core_dev *mdev,
534 			  struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
535 			  enum mlx5_flow_namespace_type ns,
536 			  enum mlx5e_tc_attr_to_reg type,
537 			  u32 data)
538 {
539 	int ret = mlx5e_tc_match_to_reg_set_and_get_id(mdev, mod_hdr_acts, ns, type, data);
540 
541 	return ret < 0 ? ret : 0;
542 }
543 
mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev * mdev,struct mlx5e_tc_mod_hdr_acts * mod_hdr_acts,enum mlx5e_tc_attr_to_reg type,int act_id,u32 data)544 void mlx5e_tc_match_to_reg_mod_hdr_change(struct mlx5_core_dev *mdev,
545 					  struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts,
546 					  enum mlx5e_tc_attr_to_reg type,
547 					  int act_id, u32 data)
548 {
549 	int moffset = mlx5e_tc_attr_to_reg_mappings[type].moffset;
550 	int mfield = mlx5e_tc_attr_to_reg_mappings[type].mfield;
551 	int mlen = mlx5e_tc_attr_to_reg_mappings[type].mlen;
552 	char *modact;
553 
554 	modact = mlx5e_mod_hdr_get_item(mod_hdr_acts, act_id);
555 
556 	/* Firmware has 5bit length field and 0 means 32bits */
557 	if (mlen == 32)
558 		mlen = 0;
559 
560 	MLX5_SET(set_action_in, modact, action_type, MLX5_ACTION_TYPE_SET);
561 	MLX5_SET(set_action_in, modact, field, mfield);
562 	MLX5_SET(set_action_in, modact, offset, moffset);
563 	MLX5_SET(set_action_in, modact, length, mlen);
564 	MLX5_SET(set_action_in, modact, data, data);
565 }
566 
567 struct mlx5e_hairpin {
568 	struct mlx5_hairpin *pair;
569 
570 	struct mlx5_core_dev *func_mdev;
571 	struct mlx5e_priv *func_priv;
572 	u32 tdn;
573 	struct mlx5e_tir direct_tir;
574 
575 	int num_channels;
576 	u8 log_num_packets;
577 	struct mlx5e_rqt indir_rqt;
578 	struct mlx5e_tir indir_tir[MLX5E_NUM_INDIR_TIRS];
579 	struct mlx5_ttc_table *ttc;
580 };
581 
582 struct mlx5e_hairpin_entry {
583 	/* a node of a hash table which keeps all the  hairpin entries */
584 	struct hlist_node hairpin_hlist;
585 
586 	/* protects flows list */
587 	spinlock_t flows_lock;
588 	/* flows sharing the same hairpin */
589 	struct list_head flows;
590 	/* hpe's that were not fully initialized when dead peer update event
591 	 * function traversed them.
592 	 */
593 	struct list_head dead_peer_wait_list;
594 
595 	u16 peer_vhca_id;
596 	u8 prio;
597 	struct mlx5e_hairpin *hp;
598 	refcount_t refcnt;
599 	struct completion res_ready;
600 };
601 
602 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
603 			      struct mlx5e_tc_flow *flow);
604 
mlx5e_flow_get(struct mlx5e_tc_flow * flow)605 struct mlx5e_tc_flow *mlx5e_flow_get(struct mlx5e_tc_flow *flow)
606 {
607 	if (!flow || !refcount_inc_not_zero(&flow->refcnt))
608 		return ERR_PTR(-EINVAL);
609 	return flow;
610 }
611 
mlx5e_flow_put(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)612 void mlx5e_flow_put(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
613 {
614 	if (refcount_dec_and_test(&flow->refcnt)) {
615 		mlx5e_tc_del_flow(priv, flow);
616 		kfree_rcu(flow, rcu_head);
617 	}
618 }
619 
mlx5e_is_eswitch_flow(struct mlx5e_tc_flow * flow)620 bool mlx5e_is_eswitch_flow(struct mlx5e_tc_flow *flow)
621 {
622 	return flow_flag_test(flow, ESWITCH);
623 }
624 
mlx5e_is_ft_flow(struct mlx5e_tc_flow * flow)625 bool mlx5e_is_ft_flow(struct mlx5e_tc_flow *flow)
626 {
627 	return flow_flag_test(flow, FT);
628 }
629 
mlx5e_is_offloaded_flow(struct mlx5e_tc_flow * flow)630 bool mlx5e_is_offloaded_flow(struct mlx5e_tc_flow *flow)
631 {
632 	return flow_flag_test(flow, OFFLOADED);
633 }
634 
mlx5e_get_flow_namespace(struct mlx5e_tc_flow * flow)635 int mlx5e_get_flow_namespace(struct mlx5e_tc_flow *flow)
636 {
637 	return mlx5e_is_eswitch_flow(flow) ?
638 		MLX5_FLOW_NAMESPACE_FDB : MLX5_FLOW_NAMESPACE_KERNEL;
639 }
640 
641 static struct mlx5_core_dev *
get_flow_counter_dev(struct mlx5e_tc_flow * flow)642 get_flow_counter_dev(struct mlx5e_tc_flow *flow)
643 {
644 	return mlx5e_is_eswitch_flow(flow) ? flow->attr->esw_attr->counter_dev : flow->priv->mdev;
645 }
646 
647 static struct mod_hdr_tbl *
get_mod_hdr_table(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)648 get_mod_hdr_table(struct mlx5e_priv *priv, struct mlx5e_tc_flow *flow)
649 {
650 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
651 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
652 
653 	return mlx5e_get_flow_namespace(flow) == MLX5_FLOW_NAMESPACE_FDB ?
654 		&esw->offloads.mod_hdr :
655 		&tc->mod_hdr;
656 }
657 
mlx5e_tc_attach_mod_hdr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)658 int mlx5e_tc_attach_mod_hdr(struct mlx5e_priv *priv,
659 			    struct mlx5e_tc_flow *flow,
660 			    struct mlx5_flow_attr *attr)
661 {
662 	struct mlx5e_mod_hdr_handle *mh;
663 
664 	mh = mlx5e_mod_hdr_attach(priv->mdev, get_mod_hdr_table(priv, flow),
665 				  mlx5e_get_flow_namespace(flow),
666 				  &attr->parse_attr->mod_hdr_acts);
667 	if (IS_ERR(mh))
668 		return PTR_ERR(mh);
669 
670 	WARN_ON(attr->modify_hdr);
671 	attr->modify_hdr = mlx5e_mod_hdr_get(mh);
672 	attr->mh = mh;
673 
674 	return 0;
675 }
676 
mlx5e_tc_detach_mod_hdr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)677 void mlx5e_tc_detach_mod_hdr(struct mlx5e_priv *priv,
678 			     struct mlx5e_tc_flow *flow,
679 			     struct mlx5_flow_attr *attr)
680 {
681 	/* flow wasn't fully initialized */
682 	if (!attr->mh)
683 		return;
684 
685 	mlx5e_mod_hdr_detach(priv->mdev, get_mod_hdr_table(priv, flow),
686 			     attr->mh);
687 	attr->mh = NULL;
688 }
689 
690 static
mlx5e_hairpin_get_mdev(struct net * net,int ifindex)691 struct mlx5_core_dev *mlx5e_hairpin_get_mdev(struct net *net, int ifindex)
692 {
693 	struct mlx5_core_dev *mdev;
694 	struct net_device *netdev;
695 	struct mlx5e_priv *priv;
696 
697 	netdev = dev_get_by_index(net, ifindex);
698 	if (!netdev)
699 		return ERR_PTR(-ENODEV);
700 
701 	priv = netdev_priv(netdev);
702 	mdev = priv->mdev;
703 	dev_put(netdev);
704 
705 	/* Mirred tc action holds a refcount on the ifindex net_device (see
706 	 * net/sched/act_mirred.c:tcf_mirred_get_dev). So, it's okay to continue using mdev
707 	 * after dev_put(netdev), while we're in the context of adding a tc flow.
708 	 *
709 	 * The mdev pointer corresponds to the peer/out net_device of a hairpin. It is then
710 	 * stored in a hairpin object, which exists until all flows, that refer to it, get
711 	 * removed.
712 	 *
713 	 * On the other hand, after a hairpin object has been created, the peer net_device may
714 	 * be removed/unbound while there are still some hairpin flows that are using it. This
715 	 * case is handled by mlx5e_tc_hairpin_update_dead_peer, which is hooked to
716 	 * NETDEV_UNREGISTER event of the peer net_device.
717 	 */
718 	return mdev;
719 }
720 
mlx5e_hairpin_create_transport(struct mlx5e_hairpin * hp)721 static int mlx5e_hairpin_create_transport(struct mlx5e_hairpin *hp)
722 {
723 	struct mlx5e_tir_builder *builder;
724 	int err;
725 
726 	builder = mlx5e_tir_builder_alloc(false);
727 	if (!builder)
728 		return -ENOMEM;
729 
730 	err = mlx5_core_alloc_transport_domain(hp->func_mdev, &hp->tdn);
731 	if (err)
732 		goto out;
733 
734 	mlx5e_tir_builder_build_inline(builder, hp->tdn, hp->pair->rqn[0]);
735 	err = mlx5e_tir_init(&hp->direct_tir, builder, hp->func_mdev, false);
736 	if (err)
737 		goto create_tir_err;
738 
739 out:
740 	mlx5e_tir_builder_free(builder);
741 	return err;
742 
743 create_tir_err:
744 	mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
745 
746 	goto out;
747 }
748 
mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin * hp)749 static void mlx5e_hairpin_destroy_transport(struct mlx5e_hairpin *hp)
750 {
751 	mlx5e_tir_destroy(&hp->direct_tir);
752 	mlx5_core_dealloc_transport_domain(hp->func_mdev, hp->tdn);
753 }
754 
mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin * hp)755 static int mlx5e_hairpin_create_indirect_rqt(struct mlx5e_hairpin *hp)
756 {
757 	struct mlx5e_priv *priv = hp->func_priv;
758 	struct mlx5_core_dev *mdev = priv->mdev;
759 	struct mlx5e_rss_params_indir indir;
760 	int err;
761 
762 	err = mlx5e_rss_params_indir_init(&indir, mdev,
763 					  mlx5e_rqt_size(mdev, hp->num_channels),
764 					  mlx5e_rqt_size(mdev, hp->num_channels));
765 	if (err)
766 		return err;
767 
768 	mlx5e_rss_params_indir_init_uniform(&indir, hp->num_channels);
769 	err = mlx5e_rqt_init_indir(&hp->indir_rqt, mdev, hp->pair->rqn, NULL, hp->num_channels,
770 				   mlx5e_rx_res_get_current_hash(priv->rx_res).hfunc,
771 				   &indir);
772 
773 	mlx5e_rss_params_indir_cleanup(&indir);
774 	return err;
775 }
776 
mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin * hp)777 static int mlx5e_hairpin_create_indirect_tirs(struct mlx5e_hairpin *hp)
778 {
779 	struct mlx5e_priv *priv = hp->func_priv;
780 	struct mlx5e_rss_params_hash rss_hash;
781 	enum mlx5_traffic_types tt, max_tt;
782 	struct mlx5e_tir_builder *builder;
783 	int err = 0;
784 
785 	builder = mlx5e_tir_builder_alloc(false);
786 	if (!builder)
787 		return -ENOMEM;
788 
789 	rss_hash = mlx5e_rx_res_get_current_hash(priv->rx_res);
790 
791 	for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
792 		struct mlx5e_rss_params_traffic_type rss_tt;
793 
794 		rss_tt = mlx5e_rss_get_default_tt_config(tt);
795 
796 		mlx5e_tir_builder_build_rqt(builder, hp->tdn,
797 					    mlx5e_rqt_get_rqtn(&hp->indir_rqt),
798 					    false);
799 		mlx5e_tir_builder_build_rss(builder, &rss_hash, &rss_tt, false);
800 
801 		err = mlx5e_tir_init(&hp->indir_tir[tt], builder, hp->func_mdev, false);
802 		if (err) {
803 			mlx5_core_warn(hp->func_mdev, "create indirect tirs failed, %d\n", err);
804 			goto err_destroy_tirs;
805 		}
806 
807 		mlx5e_tir_builder_clear(builder);
808 	}
809 
810 out:
811 	mlx5e_tir_builder_free(builder);
812 	return err;
813 
814 err_destroy_tirs:
815 	max_tt = tt;
816 	for (tt = 0; tt < max_tt; tt++)
817 		mlx5e_tir_destroy(&hp->indir_tir[tt]);
818 
819 	goto out;
820 }
821 
mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin * hp)822 static void mlx5e_hairpin_destroy_indirect_tirs(struct mlx5e_hairpin *hp)
823 {
824 	int tt;
825 
826 	for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++)
827 		mlx5e_tir_destroy(&hp->indir_tir[tt]);
828 }
829 
mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin * hp,struct ttc_params * ttc_params)830 static void mlx5e_hairpin_set_ttc_params(struct mlx5e_hairpin *hp,
831 					 struct ttc_params *ttc_params)
832 {
833 	struct mlx5_flow_table_attr *ft_attr = &ttc_params->ft_attr;
834 	int tt;
835 
836 	memset(ttc_params, 0, sizeof(*ttc_params));
837 
838 	ttc_params->ns_type = MLX5_FLOW_NAMESPACE_KERNEL;
839 	for (tt = 0; tt < MLX5_NUM_TT; tt++) {
840 		ttc_params->dests[tt].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
841 		ttc_params->dests[tt].tir_num =
842 			tt == MLX5_TT_ANY ?
843 				mlx5e_tir_get_tirn(&hp->direct_tir) :
844 				mlx5e_tir_get_tirn(&hp->indir_tir[tt]);
845 	}
846 
847 	ft_attr->level = MLX5E_TC_TTC_FT_LEVEL;
848 	ft_attr->prio = MLX5E_TC_PRIO;
849 }
850 
mlx5e_hairpin_rss_init(struct mlx5e_hairpin * hp)851 static int mlx5e_hairpin_rss_init(struct mlx5e_hairpin *hp)
852 {
853 	struct mlx5e_priv *priv = hp->func_priv;
854 	struct ttc_params ttc_params;
855 	struct mlx5_ttc_table *ttc;
856 	int err;
857 
858 	err = mlx5e_hairpin_create_indirect_rqt(hp);
859 	if (err)
860 		return err;
861 
862 	err = mlx5e_hairpin_create_indirect_tirs(hp);
863 	if (err)
864 		goto err_create_indirect_tirs;
865 
866 	mlx5e_hairpin_set_ttc_params(hp, &ttc_params);
867 	hp->ttc = mlx5_create_ttc_table(priv->mdev, &ttc_params);
868 	if (IS_ERR(hp->ttc)) {
869 		err = PTR_ERR(hp->ttc);
870 		goto err_create_ttc_table;
871 	}
872 
873 	ttc = mlx5e_fs_get_ttc(priv->fs, false);
874 	netdev_dbg(priv->netdev, "add hairpin: using %d channels rss ttc table id %x\n",
875 		   hp->num_channels,
876 		   mlx5_get_ttc_flow_table(ttc)->id);
877 
878 	return 0;
879 
880 err_create_ttc_table:
881 	mlx5e_hairpin_destroy_indirect_tirs(hp);
882 err_create_indirect_tirs:
883 	mlx5e_rqt_destroy(&hp->indir_rqt);
884 
885 	return err;
886 }
887 
mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin * hp)888 static void mlx5e_hairpin_rss_cleanup(struct mlx5e_hairpin *hp)
889 {
890 	mlx5_destroy_ttc_table(hp->ttc);
891 	mlx5e_hairpin_destroy_indirect_tirs(hp);
892 	mlx5e_rqt_destroy(&hp->indir_rqt);
893 }
894 
895 static struct mlx5e_hairpin *
mlx5e_hairpin_create(struct mlx5e_priv * priv,struct mlx5_hairpin_params * params,int peer_ifindex)896 mlx5e_hairpin_create(struct mlx5e_priv *priv, struct mlx5_hairpin_params *params,
897 		     int peer_ifindex)
898 {
899 	struct mlx5_core_dev *func_mdev, *peer_mdev;
900 	struct mlx5e_hairpin *hp;
901 	struct mlx5_hairpin *pair;
902 	int err;
903 
904 	hp = kzalloc(sizeof(*hp), GFP_KERNEL);
905 	if (!hp)
906 		return ERR_PTR(-ENOMEM);
907 
908 	func_mdev = priv->mdev;
909 	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
910 	if (IS_ERR(peer_mdev)) {
911 		err = PTR_ERR(peer_mdev);
912 		goto create_pair_err;
913 	}
914 
915 	pair = mlx5_core_hairpin_create(func_mdev, peer_mdev, params);
916 	if (IS_ERR(pair)) {
917 		err = PTR_ERR(pair);
918 		goto create_pair_err;
919 	}
920 	hp->pair = pair;
921 	hp->func_mdev = func_mdev;
922 	hp->func_priv = priv;
923 	hp->num_channels = params->num_channels;
924 	hp->log_num_packets = params->log_num_packets;
925 
926 	err = mlx5e_hairpin_create_transport(hp);
927 	if (err)
928 		goto create_transport_err;
929 
930 	if (hp->num_channels > 1) {
931 		err = mlx5e_hairpin_rss_init(hp);
932 		if (err)
933 			goto rss_init_err;
934 	}
935 
936 	return hp;
937 
938 rss_init_err:
939 	mlx5e_hairpin_destroy_transport(hp);
940 create_transport_err:
941 	mlx5_core_hairpin_destroy(hp->pair);
942 create_pair_err:
943 	kfree(hp);
944 	return ERR_PTR(err);
945 }
946 
mlx5e_hairpin_destroy(struct mlx5e_hairpin * hp)947 static void mlx5e_hairpin_destroy(struct mlx5e_hairpin *hp)
948 {
949 	if (hp->num_channels > 1)
950 		mlx5e_hairpin_rss_cleanup(hp);
951 	mlx5e_hairpin_destroy_transport(hp);
952 	mlx5_core_hairpin_destroy(hp->pair);
953 	kvfree(hp);
954 }
955 
hash_hairpin_info(u16 peer_vhca_id,u8 prio)956 static inline u32 hash_hairpin_info(u16 peer_vhca_id, u8 prio)
957 {
958 	return (peer_vhca_id << 16 | prio);
959 }
960 
mlx5e_hairpin_get(struct mlx5e_priv * priv,u16 peer_vhca_id,u8 prio)961 static struct mlx5e_hairpin_entry *mlx5e_hairpin_get(struct mlx5e_priv *priv,
962 						     u16 peer_vhca_id, u8 prio)
963 {
964 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
965 	struct mlx5e_hairpin_entry *hpe;
966 	u32 hash_key = hash_hairpin_info(peer_vhca_id, prio);
967 
968 	hash_for_each_possible(tc->hairpin_tbl, hpe,
969 			       hairpin_hlist, hash_key) {
970 		if (hpe->peer_vhca_id == peer_vhca_id && hpe->prio == prio) {
971 			refcount_inc(&hpe->refcnt);
972 			return hpe;
973 		}
974 	}
975 
976 	return NULL;
977 }
978 
mlx5e_hairpin_put(struct mlx5e_priv * priv,struct mlx5e_hairpin_entry * hpe)979 static void mlx5e_hairpin_put(struct mlx5e_priv *priv,
980 			      struct mlx5e_hairpin_entry *hpe)
981 {
982 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
983 	/* no more hairpin flows for us, release the hairpin pair */
984 	if (!refcount_dec_and_mutex_lock(&hpe->refcnt, &tc->hairpin_tbl_lock))
985 		return;
986 	hash_del(&hpe->hairpin_hlist);
987 	mutex_unlock(&tc->hairpin_tbl_lock);
988 
989 	if (!IS_ERR_OR_NULL(hpe->hp)) {
990 		netdev_dbg(priv->netdev, "del hairpin: peer %s\n",
991 			   dev_name(hpe->hp->pair->peer_mdev->device));
992 
993 		mlx5e_hairpin_destroy(hpe->hp);
994 	}
995 
996 	WARN_ON(!list_empty(&hpe->flows));
997 	kfree(hpe);
998 }
999 
1000 #define UNKNOWN_MATCH_PRIO 8
1001 
mlx5e_hairpin_get_prio(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,u8 * match_prio,struct netlink_ext_ack * extack)1002 static int mlx5e_hairpin_get_prio(struct mlx5e_priv *priv,
1003 				  struct mlx5_flow_spec *spec, u8 *match_prio,
1004 				  struct netlink_ext_ack *extack)
1005 {
1006 	void *headers_c, *headers_v;
1007 	u8 prio_val, prio_mask = 0;
1008 	bool vlan_present;
1009 
1010 #ifdef CONFIG_MLX5_CORE_EN_DCB
1011 	if (priv->dcbx_dp.trust_state != MLX5_QPTS_TRUST_PCP) {
1012 		NL_SET_ERR_MSG_MOD(extack,
1013 				   "only PCP trust state supported for hairpin");
1014 		return -EOPNOTSUPP;
1015 	}
1016 #endif
1017 	headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria, outer_headers);
1018 	headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
1019 
1020 	vlan_present = MLX5_GET(fte_match_set_lyr_2_4, headers_v, cvlan_tag);
1021 	if (vlan_present) {
1022 		prio_mask = MLX5_GET(fte_match_set_lyr_2_4, headers_c, first_prio);
1023 		prio_val = MLX5_GET(fte_match_set_lyr_2_4, headers_v, first_prio);
1024 	}
1025 
1026 	if (!vlan_present || !prio_mask) {
1027 		prio_val = UNKNOWN_MATCH_PRIO;
1028 	} else if (prio_mask != 0x7) {
1029 		NL_SET_ERR_MSG_MOD(extack,
1030 				   "masked priority match not supported for hairpin");
1031 		return -EOPNOTSUPP;
1032 	}
1033 
1034 	*match_prio = prio_val;
1035 	return 0;
1036 }
1037 
debugfs_hairpin_num_active_get(void * data,u64 * val)1038 static int debugfs_hairpin_num_active_get(void *data, u64 *val)
1039 {
1040 	struct mlx5e_tc_table *tc = data;
1041 	struct mlx5e_hairpin_entry *hpe;
1042 	u32 cnt = 0;
1043 	u32 bkt;
1044 
1045 	mutex_lock(&tc->hairpin_tbl_lock);
1046 	hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1047 		cnt++;
1048 	mutex_unlock(&tc->hairpin_tbl_lock);
1049 
1050 	*val = cnt;
1051 
1052 	return 0;
1053 }
1054 DEFINE_DEBUGFS_ATTRIBUTE(fops_hairpin_num_active,
1055 			 debugfs_hairpin_num_active_get, NULL, "%llu\n");
1056 
debugfs_hairpin_table_dump_show(struct seq_file * file,void * priv)1057 static int debugfs_hairpin_table_dump_show(struct seq_file *file, void *priv)
1058 
1059 {
1060 	struct mlx5e_tc_table *tc = file->private;
1061 	struct mlx5e_hairpin_entry *hpe;
1062 	u32 bkt;
1063 
1064 	mutex_lock(&tc->hairpin_tbl_lock);
1065 	hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
1066 		seq_printf(file,
1067 			   "Hairpin peer_vhca_id %u prio %u refcnt %u num_channels %u num_packets %lu\n",
1068 			   hpe->peer_vhca_id, hpe->prio,
1069 			   refcount_read(&hpe->refcnt), hpe->hp->num_channels,
1070 			   BIT(hpe->hp->log_num_packets));
1071 	mutex_unlock(&tc->hairpin_tbl_lock);
1072 
1073 	return 0;
1074 }
1075 DEFINE_SHOW_ATTRIBUTE(debugfs_hairpin_table_dump);
1076 
mlx5e_tc_debugfs_init(struct mlx5e_tc_table * tc,struct dentry * dfs_root)1077 static void mlx5e_tc_debugfs_init(struct mlx5e_tc_table *tc,
1078 				  struct dentry *dfs_root)
1079 {
1080 	if (IS_ERR_OR_NULL(dfs_root))
1081 		return;
1082 
1083 	tc->dfs_root = debugfs_create_dir("tc", dfs_root);
1084 
1085 	debugfs_create_file("hairpin_num_active", 0444, tc->dfs_root, tc,
1086 			    &fops_hairpin_num_active);
1087 	debugfs_create_file("hairpin_table_dump", 0444, tc->dfs_root, tc,
1088 			    &debugfs_hairpin_table_dump_fops);
1089 }
1090 
mlx5e_hairpin_flow_add(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5e_tc_flow_parse_attr * parse_attr,struct netlink_ext_ack * extack)1091 static int mlx5e_hairpin_flow_add(struct mlx5e_priv *priv,
1092 				  struct mlx5e_tc_flow *flow,
1093 				  struct mlx5e_tc_flow_parse_attr *parse_attr,
1094 				  struct netlink_ext_ack *extack)
1095 {
1096 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1097 	struct devlink *devlink = priv_to_devlink(priv->mdev);
1098 	int peer_ifindex = parse_attr->mirred_ifindex[0];
1099 	union devlink_param_value val = {};
1100 	struct mlx5_hairpin_params params;
1101 	struct mlx5_core_dev *peer_mdev;
1102 	struct mlx5e_hairpin_entry *hpe;
1103 	struct mlx5e_hairpin *hp;
1104 	u8 match_prio;
1105 	u16 peer_id;
1106 	int err;
1107 
1108 	peer_mdev = mlx5e_hairpin_get_mdev(dev_net(priv->netdev), peer_ifindex);
1109 	if (IS_ERR(peer_mdev)) {
1110 		NL_SET_ERR_MSG_MOD(extack, "invalid ifindex of mirred device");
1111 		return PTR_ERR(peer_mdev);
1112 	}
1113 
1114 	if (!MLX5_CAP_GEN(priv->mdev, hairpin) || !MLX5_CAP_GEN(peer_mdev, hairpin)) {
1115 		NL_SET_ERR_MSG_MOD(extack, "hairpin is not supported");
1116 		return -EOPNOTSUPP;
1117 	}
1118 
1119 	peer_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
1120 	err = mlx5e_hairpin_get_prio(priv, &parse_attr->spec, &match_prio,
1121 				     extack);
1122 	if (err)
1123 		return err;
1124 
1125 	mutex_lock(&tc->hairpin_tbl_lock);
1126 	hpe = mlx5e_hairpin_get(priv, peer_id, match_prio);
1127 	if (hpe) {
1128 		mutex_unlock(&tc->hairpin_tbl_lock);
1129 		wait_for_completion(&hpe->res_ready);
1130 
1131 		if (IS_ERR(hpe->hp)) {
1132 			err = -EREMOTEIO;
1133 			goto out_err;
1134 		}
1135 		goto attach_flow;
1136 	}
1137 
1138 	hpe = kzalloc(sizeof(*hpe), GFP_KERNEL);
1139 	if (!hpe) {
1140 		mutex_unlock(&tc->hairpin_tbl_lock);
1141 		return -ENOMEM;
1142 	}
1143 
1144 	spin_lock_init(&hpe->flows_lock);
1145 	INIT_LIST_HEAD(&hpe->flows);
1146 	INIT_LIST_HEAD(&hpe->dead_peer_wait_list);
1147 	hpe->peer_vhca_id = peer_id;
1148 	hpe->prio = match_prio;
1149 	refcount_set(&hpe->refcnt, 1);
1150 	init_completion(&hpe->res_ready);
1151 
1152 	hash_add(tc->hairpin_tbl, &hpe->hairpin_hlist,
1153 		 hash_hairpin_info(peer_id, match_prio));
1154 	mutex_unlock(&tc->hairpin_tbl_lock);
1155 
1156 	err = devl_param_driverinit_value_get(
1157 		devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_QUEUE_SIZE, &val);
1158 	if (err) {
1159 		err = -ENOMEM;
1160 		goto out_err;
1161 	}
1162 
1163 	params.log_num_packets = ilog2(val.vu32);
1164 	params.log_data_size =
1165 		clamp_t(u32,
1166 			params.log_num_packets +
1167 				MLX5_MPWRQ_MIN_LOG_STRIDE_SZ(priv->mdev),
1168 			MLX5_CAP_GEN(priv->mdev, log_min_hairpin_wq_data_sz),
1169 			MLX5_CAP_GEN(priv->mdev, log_max_hairpin_wq_data_sz));
1170 
1171 	params.q_counter = priv->q_counter[0];
1172 	err = devl_param_driverinit_value_get(
1173 		devlink, MLX5_DEVLINK_PARAM_ID_HAIRPIN_NUM_QUEUES, &val);
1174 	if (err) {
1175 		err = -ENOMEM;
1176 		goto out_err;
1177 	}
1178 
1179 	params.num_channels = val.vu32;
1180 
1181 	hp = mlx5e_hairpin_create(priv, &params, peer_ifindex);
1182 	hpe->hp = hp;
1183 	complete_all(&hpe->res_ready);
1184 	if (IS_ERR(hp)) {
1185 		err = PTR_ERR(hp);
1186 		goto out_err;
1187 	}
1188 
1189 	netdev_dbg(priv->netdev, "add hairpin: tirn %x rqn %x peer %s sqn %x prio %d (log) data %d packets %d\n",
1190 		   mlx5e_tir_get_tirn(&hp->direct_tir), hp->pair->rqn[0],
1191 		   dev_name(hp->pair->peer_mdev->device),
1192 		   hp->pair->sqn[0], match_prio, params.log_data_size, params.log_num_packets);
1193 
1194 attach_flow:
1195 	if (hpe->hp->num_channels > 1) {
1196 		flow_flag_set(flow, HAIRPIN_RSS);
1197 		flow->attr->nic_attr->hairpin_ft =
1198 			mlx5_get_ttc_flow_table(hpe->hp->ttc);
1199 	} else {
1200 		flow->attr->nic_attr->hairpin_tirn = mlx5e_tir_get_tirn(&hpe->hp->direct_tir);
1201 	}
1202 
1203 	flow->hpe = hpe;
1204 	spin_lock(&hpe->flows_lock);
1205 	list_add(&flow->hairpin, &hpe->flows);
1206 	spin_unlock(&hpe->flows_lock);
1207 
1208 	return 0;
1209 
1210 out_err:
1211 	mlx5e_hairpin_put(priv, hpe);
1212 	return err;
1213 }
1214 
mlx5e_hairpin_flow_del(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)1215 static void mlx5e_hairpin_flow_del(struct mlx5e_priv *priv,
1216 				   struct mlx5e_tc_flow *flow)
1217 {
1218 	/* flow wasn't fully initialized */
1219 	if (!flow->hpe)
1220 		return;
1221 
1222 	spin_lock(&flow->hpe->flows_lock);
1223 	list_del(&flow->hairpin);
1224 	spin_unlock(&flow->hpe->flows_lock);
1225 
1226 	mlx5e_hairpin_put(priv, flow->hpe);
1227 	flow->hpe = NULL;
1228 }
1229 
1230 struct mlx5_flow_handle *
mlx5e_add_offloaded_nic_rule(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)1231 mlx5e_add_offloaded_nic_rule(struct mlx5e_priv *priv,
1232 			     struct mlx5_flow_spec *spec,
1233 			     struct mlx5_flow_attr *attr)
1234 {
1235 	struct mlx5_flow_context *flow_context = &spec->flow_context;
1236 	struct mlx5e_vlan_table *vlan = mlx5e_fs_get_vlan(priv->fs);
1237 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1238 	struct mlx5_nic_flow_attr *nic_attr = attr->nic_attr;
1239 	struct mlx5_flow_destination dest[2] = {};
1240 	struct mlx5_fs_chains *nic_chains;
1241 	struct mlx5_flow_act flow_act = {
1242 		.action = attr->action,
1243 		.flags    = FLOW_ACT_NO_APPEND,
1244 	};
1245 	struct mlx5_flow_handle *rule;
1246 	struct mlx5_flow_table *ft;
1247 	int dest_ix = 0;
1248 
1249 	nic_chains = mlx5e_nic_chains(tc);
1250 	flow_context->flags |= FLOW_CONTEXT_HAS_TAG;
1251 	flow_context->flow_tag = nic_attr->flow_tag;
1252 
1253 	if (attr->dest_ft) {
1254 		dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1255 		dest[dest_ix].ft = attr->dest_ft;
1256 		dest_ix++;
1257 	} else if (nic_attr->hairpin_ft) {
1258 		dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1259 		dest[dest_ix].ft = nic_attr->hairpin_ft;
1260 		dest_ix++;
1261 	} else if (nic_attr->hairpin_tirn) {
1262 		dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_TIR;
1263 		dest[dest_ix].tir_num = nic_attr->hairpin_tirn;
1264 		dest_ix++;
1265 	} else if (attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1266 		dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE;
1267 		if (attr->dest_chain) {
1268 			dest[dest_ix].ft = mlx5_chains_get_table(nic_chains,
1269 								 attr->dest_chain, 1,
1270 								 MLX5E_TC_FT_LEVEL);
1271 			if (IS_ERR(dest[dest_ix].ft))
1272 				return ERR_CAST(dest[dest_ix].ft);
1273 		} else {
1274 			dest[dest_ix].ft = mlx5e_vlan_get_flowtable(vlan);
1275 		}
1276 		dest_ix++;
1277 	}
1278 
1279 	if (dest[0].type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE &&
1280 	    MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
1281 		flow_act.flags |= FLOW_ACT_IGNORE_FLOW_LEVEL;
1282 
1283 	if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1284 		dest[dest_ix].type = MLX5_FLOW_DESTINATION_TYPE_COUNTER;
1285 		dest[dest_ix].counter_id = mlx5_fc_id(attr->counter);
1286 		dest_ix++;
1287 	}
1288 
1289 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
1290 		flow_act.modify_hdr = attr->modify_hdr;
1291 
1292 	mutex_lock(&tc->t_lock);
1293 	if (IS_ERR_OR_NULL(tc->t)) {
1294 		/* Create the root table here if doesn't exist yet */
1295 		tc->t =
1296 			mlx5_chains_get_table(nic_chains, 0, 1, MLX5E_TC_FT_LEVEL);
1297 
1298 		if (IS_ERR(tc->t)) {
1299 			mutex_unlock(&tc->t_lock);
1300 			netdev_err(priv->netdev,
1301 				   "Failed to create tc offload table\n");
1302 			rule = ERR_CAST(tc->t);
1303 			goto err_ft_get;
1304 		}
1305 	}
1306 	mutex_unlock(&tc->t_lock);
1307 
1308 	if (attr->chain || attr->prio)
1309 		ft = mlx5_chains_get_table(nic_chains,
1310 					   attr->chain, attr->prio,
1311 					   MLX5E_TC_FT_LEVEL);
1312 	else
1313 		ft = attr->ft;
1314 
1315 	if (IS_ERR(ft)) {
1316 		rule = ERR_CAST(ft);
1317 		goto err_ft_get;
1318 	}
1319 
1320 	if (attr->outer_match_level != MLX5_MATCH_NONE)
1321 		spec->match_criteria_enable |= MLX5_MATCH_OUTER_HEADERS;
1322 
1323 	rule = mlx5_add_flow_rules(ft, spec,
1324 				   &flow_act, dest, dest_ix);
1325 	if (IS_ERR(rule))
1326 		goto err_rule;
1327 
1328 	return rule;
1329 
1330 err_rule:
1331 	if (attr->chain || attr->prio)
1332 		mlx5_chains_put_table(nic_chains,
1333 				      attr->chain, attr->prio,
1334 				      MLX5E_TC_FT_LEVEL);
1335 err_ft_get:
1336 	if (attr->dest_chain)
1337 		mlx5_chains_put_table(nic_chains,
1338 				      attr->dest_chain, 1,
1339 				      MLX5E_TC_FT_LEVEL);
1340 
1341 	return ERR_CAST(rule);
1342 }
1343 
1344 static int
alloc_flow_attr_counter(struct mlx5_core_dev * counter_dev,struct mlx5_flow_attr * attr)1345 alloc_flow_attr_counter(struct mlx5_core_dev *counter_dev,
1346 			struct mlx5_flow_attr *attr)
1347 
1348 {
1349 	struct mlx5_fc *counter;
1350 
1351 	counter = mlx5_fc_create(counter_dev, true);
1352 	if (IS_ERR(counter))
1353 		return PTR_ERR(counter);
1354 
1355 	attr->counter = counter;
1356 	return 0;
1357 }
1358 
1359 static int
mlx5e_tc_add_nic_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)1360 mlx5e_tc_add_nic_flow(struct mlx5e_priv *priv,
1361 		      struct mlx5e_tc_flow *flow,
1362 		      struct netlink_ext_ack *extack)
1363 {
1364 	struct mlx5e_tc_flow_parse_attr *parse_attr;
1365 	struct mlx5_flow_attr *attr = flow->attr;
1366 	struct mlx5_core_dev *dev = priv->mdev;
1367 	int err;
1368 
1369 	parse_attr = attr->parse_attr;
1370 
1371 	if (flow_flag_test(flow, HAIRPIN)) {
1372 		err = mlx5e_hairpin_flow_add(priv, flow, parse_attr, extack);
1373 		if (err)
1374 			return err;
1375 	}
1376 
1377 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1378 		err = alloc_flow_attr_counter(dev, attr);
1379 		if (err)
1380 			return err;
1381 	}
1382 
1383 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1384 		err = mlx5e_tc_attach_mod_hdr(priv, flow, attr);
1385 		if (err)
1386 			return err;
1387 	}
1388 
1389 	flow->rule[0] = mlx5e_add_offloaded_nic_rule(priv, &parse_attr->spec, attr);
1390 	return PTR_ERR_OR_ZERO(flow->rule[0]);
1391 }
1392 
mlx5e_del_offloaded_nic_rule(struct mlx5e_priv * priv,struct mlx5_flow_handle * rule,struct mlx5_flow_attr * attr)1393 void mlx5e_del_offloaded_nic_rule(struct mlx5e_priv *priv,
1394 				  struct mlx5_flow_handle *rule,
1395 				  struct mlx5_flow_attr *attr)
1396 {
1397 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1398 	struct mlx5_fs_chains *nic_chains;
1399 
1400 	nic_chains = mlx5e_nic_chains(tc);
1401 	mlx5_del_flow_rules(rule);
1402 
1403 	if (attr->chain || attr->prio)
1404 		mlx5_chains_put_table(nic_chains, attr->chain, attr->prio,
1405 				      MLX5E_TC_FT_LEVEL);
1406 
1407 	if (attr->dest_chain)
1408 		mlx5_chains_put_table(nic_chains, attr->dest_chain, 1,
1409 				      MLX5E_TC_FT_LEVEL);
1410 }
1411 
mlx5e_tc_del_nic_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)1412 static void mlx5e_tc_del_nic_flow(struct mlx5e_priv *priv,
1413 				  struct mlx5e_tc_flow *flow)
1414 {
1415 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
1416 	struct mlx5_flow_attr *attr = flow->attr;
1417 
1418 	flow_flag_clear(flow, OFFLOADED);
1419 
1420 	if (!IS_ERR_OR_NULL(flow->rule[0]))
1421 		mlx5e_del_offloaded_nic_rule(priv, flow->rule[0], attr);
1422 
1423 	/* Remove root table if no rules are left to avoid
1424 	 * extra steering hops.
1425 	 */
1426 	mutex_lock(&tc->t_lock);
1427 	if (!mlx5e_tc_num_filters(priv, MLX5_TC_FLAG(NIC_OFFLOAD)) &&
1428 	    !IS_ERR_OR_NULL(tc->t)) {
1429 		mlx5_chains_put_table(mlx5e_nic_chains(tc), 0, 1, MLX5E_TC_FT_LEVEL);
1430 		tc->t = NULL;
1431 	}
1432 	mutex_unlock(&tc->t_lock);
1433 
1434 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1435 		mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
1436 		mlx5e_tc_detach_mod_hdr(priv, flow, attr);
1437 	}
1438 
1439 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
1440 		mlx5_fc_destroy(priv->mdev, attr->counter);
1441 
1442 	if (flow_flag_test(flow, HAIRPIN))
1443 		mlx5e_hairpin_flow_del(priv, flow);
1444 
1445 	free_flow_post_acts(flow);
1446 	mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
1447 
1448 	kvfree(attr->parse_attr);
1449 	kfree(flow->attr);
1450 }
1451 
1452 struct mlx5_flow_handle *
mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct mlx5_flow_attr * attr)1453 mlx5e_tc_offload_fdb_rules(struct mlx5_eswitch *esw,
1454 			   struct mlx5e_tc_flow *flow,
1455 			   struct mlx5_flow_spec *spec,
1456 			   struct mlx5_flow_attr *attr)
1457 {
1458 	struct mlx5_flow_handle *rule;
1459 
1460 	if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1461 		return mlx5_eswitch_add_offloaded_rule(esw, spec, attr);
1462 
1463 	rule = mlx5e_tc_rule_offload(flow->priv, spec, attr);
1464 
1465 	if (IS_ERR(rule))
1466 		return rule;
1467 
1468 	if (attr->esw_attr->split_count) {
1469 		flow->rule[1] = mlx5_eswitch_add_fwd_rule(esw, spec, attr);
1470 		if (IS_ERR(flow->rule[1]))
1471 			goto err_rule1;
1472 	}
1473 
1474 	return rule;
1475 
1476 err_rule1:
1477 	mlx5e_tc_rule_unoffload(flow->priv, rule, attr);
1478 	return flow->rule[1];
1479 }
1480 
mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)1481 void mlx5e_tc_unoffload_fdb_rules(struct mlx5_eswitch *esw,
1482 				  struct mlx5e_tc_flow *flow,
1483 				  struct mlx5_flow_attr *attr)
1484 {
1485 	flow_flag_clear(flow, OFFLOADED);
1486 
1487 	if (attr->flags & MLX5_ATTR_FLAG_SLOW_PATH)
1488 		return mlx5_eswitch_del_offloaded_rule(esw, flow->rule[0], attr);
1489 
1490 	if (attr->esw_attr->split_count)
1491 		mlx5_eswitch_del_fwd_rule(esw, flow->rule[1], attr);
1492 
1493 	mlx5e_tc_rule_unoffload(flow->priv, flow->rule[0], attr);
1494 }
1495 
1496 struct mlx5_flow_handle *
mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec)1497 mlx5e_tc_offload_to_slow_path(struct mlx5_eswitch *esw,
1498 			      struct mlx5e_tc_flow *flow,
1499 			      struct mlx5_flow_spec *spec)
1500 {
1501 	struct mlx5e_tc_mod_hdr_acts mod_acts = {};
1502 	struct mlx5e_mod_hdr_handle *mh = NULL;
1503 	struct mlx5_flow_attr *slow_attr;
1504 	struct mlx5_flow_handle *rule;
1505 	bool fwd_and_modify_cap;
1506 	u32 chain_mapping = 0;
1507 	int err;
1508 
1509 	slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1510 	if (!slow_attr)
1511 		return ERR_PTR(-ENOMEM);
1512 
1513 	memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1514 	slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1515 	slow_attr->esw_attr->split_count = 0;
1516 	slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1517 
1518 	fwd_and_modify_cap = MLX5_CAP_ESW_FLOWTABLE((esw)->dev, fdb_modify_header_fwd_to_table);
1519 	if (!fwd_and_modify_cap)
1520 		goto skip_restore;
1521 
1522 	err = mlx5_chains_get_chain_mapping(esw_chains(esw), flow->attr->chain, &chain_mapping);
1523 	if (err)
1524 		goto err_get_chain;
1525 
1526 	err = mlx5e_tc_match_to_reg_set(esw->dev, &mod_acts, MLX5_FLOW_NAMESPACE_FDB,
1527 					MAPPED_OBJ_TO_REG, chain_mapping);
1528 	if (err)
1529 		goto err_reg_set;
1530 
1531 	mh = mlx5e_mod_hdr_attach(esw->dev, get_mod_hdr_table(flow->priv, flow),
1532 				  MLX5_FLOW_NAMESPACE_FDB, &mod_acts);
1533 	if (IS_ERR(mh)) {
1534 		err = PTR_ERR(mh);
1535 		goto err_attach;
1536 	}
1537 
1538 	slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1539 	slow_attr->modify_hdr = mlx5e_mod_hdr_get(mh);
1540 
1541 skip_restore:
1542 	rule = mlx5e_tc_offload_fdb_rules(esw, flow, spec, slow_attr);
1543 	if (IS_ERR(rule)) {
1544 		err = PTR_ERR(rule);
1545 		goto err_offload;
1546 	}
1547 
1548 	flow->attr->slow_mh = mh;
1549 	flow->chain_mapping = chain_mapping;
1550 	flow_flag_set(flow, SLOW);
1551 
1552 	mlx5e_mod_hdr_dealloc(&mod_acts);
1553 	kfree(slow_attr);
1554 
1555 	return rule;
1556 
1557 err_offload:
1558 	if (fwd_and_modify_cap)
1559 		mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), mh);
1560 err_attach:
1561 err_reg_set:
1562 	if (fwd_and_modify_cap)
1563 		mlx5_chains_put_chain_mapping(esw_chains(esw), chain_mapping);
1564 err_get_chain:
1565 	mlx5e_mod_hdr_dealloc(&mod_acts);
1566 	kfree(slow_attr);
1567 	return ERR_PTR(err);
1568 }
1569 
mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch * esw,struct mlx5e_tc_flow * flow)1570 void mlx5e_tc_unoffload_from_slow_path(struct mlx5_eswitch *esw,
1571 				       struct mlx5e_tc_flow *flow)
1572 {
1573 	struct mlx5e_mod_hdr_handle *slow_mh = flow->attr->slow_mh;
1574 	struct mlx5_flow_attr *slow_attr;
1575 
1576 	slow_attr = mlx5_alloc_flow_attr(MLX5_FLOW_NAMESPACE_FDB);
1577 	if (!slow_attr) {
1578 		mlx5_core_warn(flow->priv->mdev, "Unable to alloc attr to unoffload slow path rule\n");
1579 		return;
1580 	}
1581 
1582 	memcpy(slow_attr, flow->attr, ESW_FLOW_ATTR_SZ);
1583 	slow_attr->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1584 	slow_attr->esw_attr->split_count = 0;
1585 	slow_attr->flags |= MLX5_ATTR_FLAG_SLOW_PATH;
1586 	if (slow_mh) {
1587 		slow_attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1588 		slow_attr->modify_hdr = mlx5e_mod_hdr_get(slow_mh);
1589 	}
1590 	mlx5e_tc_unoffload_fdb_rules(esw, flow, slow_attr);
1591 	if (slow_mh) {
1592 		mlx5e_mod_hdr_detach(esw->dev, get_mod_hdr_table(flow->priv, flow), slow_mh);
1593 		mlx5_chains_put_chain_mapping(esw_chains(esw), flow->chain_mapping);
1594 		flow->chain_mapping = 0;
1595 		flow->attr->slow_mh = NULL;
1596 	}
1597 	flow_flag_clear(flow, SLOW);
1598 	kfree(slow_attr);
1599 }
1600 
1601 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1602  * function.
1603  */
unready_flow_add(struct mlx5e_tc_flow * flow,struct list_head * unready_flows)1604 static void unready_flow_add(struct mlx5e_tc_flow *flow,
1605 			     struct list_head *unready_flows)
1606 {
1607 	flow_flag_set(flow, NOT_READY);
1608 	list_add_tail(&flow->unready, unready_flows);
1609 }
1610 
1611 /* Caller must obtain uplink_priv->unready_flows_lock mutex before calling this
1612  * function.
1613  */
unready_flow_del(struct mlx5e_tc_flow * flow)1614 static void unready_flow_del(struct mlx5e_tc_flow *flow)
1615 {
1616 	list_del(&flow->unready);
1617 	flow_flag_clear(flow, NOT_READY);
1618 }
1619 
add_unready_flow(struct mlx5e_tc_flow * flow)1620 static void add_unready_flow(struct mlx5e_tc_flow *flow)
1621 {
1622 	struct mlx5_rep_uplink_priv *uplink_priv;
1623 	struct mlx5e_rep_priv *rpriv;
1624 	struct mlx5_eswitch *esw;
1625 
1626 	esw = flow->priv->mdev->priv.eswitch;
1627 	rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1628 	uplink_priv = &rpriv->uplink_priv;
1629 
1630 	mutex_lock(&uplink_priv->unready_flows_lock);
1631 	unready_flow_add(flow, &uplink_priv->unready_flows);
1632 	mutex_unlock(&uplink_priv->unready_flows_lock);
1633 }
1634 
remove_unready_flow(struct mlx5e_tc_flow * flow)1635 static void remove_unready_flow(struct mlx5e_tc_flow *flow)
1636 {
1637 	struct mlx5_rep_uplink_priv *uplink_priv;
1638 	struct mlx5e_rep_priv *rpriv;
1639 	struct mlx5_eswitch *esw;
1640 
1641 	esw = flow->priv->mdev->priv.eswitch;
1642 	rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
1643 	uplink_priv = &rpriv->uplink_priv;
1644 
1645 	mutex_lock(&uplink_priv->unready_flows_lock);
1646 	if (flow_flag_test(flow, NOT_READY))
1647 		unready_flow_del(flow);
1648 	mutex_unlock(&uplink_priv->unready_flows_lock);
1649 }
1650 
mlx5e_tc_is_vf_tunnel(struct net_device * out_dev,struct net_device * route_dev)1651 bool mlx5e_tc_is_vf_tunnel(struct net_device *out_dev, struct net_device *route_dev)
1652 {
1653 	struct mlx5_core_dev *out_mdev, *route_mdev;
1654 	struct mlx5e_priv *out_priv, *route_priv;
1655 
1656 	out_priv = netdev_priv(out_dev);
1657 	out_mdev = out_priv->mdev;
1658 	route_priv = netdev_priv(route_dev);
1659 	route_mdev = route_priv->mdev;
1660 
1661 	if (out_mdev->coredev_type != MLX5_COREDEV_PF)
1662 		return false;
1663 
1664 	if (route_mdev->coredev_type != MLX5_COREDEV_VF &&
1665 	    route_mdev->coredev_type != MLX5_COREDEV_SF)
1666 		return false;
1667 
1668 	return mlx5e_same_hw_devs(out_priv, route_priv);
1669 }
1670 
mlx5e_tc_query_route_vport(struct net_device * out_dev,struct net_device * route_dev,u16 * vport)1671 int mlx5e_tc_query_route_vport(struct net_device *out_dev, struct net_device *route_dev, u16 *vport)
1672 {
1673 	struct mlx5e_priv *out_priv, *route_priv;
1674 	struct mlx5_core_dev *route_mdev;
1675 	struct mlx5_devcom_comp_dev *pos;
1676 	struct mlx5_eswitch *esw;
1677 	u16 vhca_id;
1678 	int err;
1679 
1680 	out_priv = netdev_priv(out_dev);
1681 	esw = out_priv->mdev->priv.eswitch;
1682 	route_priv = netdev_priv(route_dev);
1683 	route_mdev = route_priv->mdev;
1684 
1685 	vhca_id = MLX5_CAP_GEN(route_mdev, vhca_id);
1686 	err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1687 	if (!err)
1688 		return err;
1689 
1690 	if (!mlx5_lag_is_active(out_priv->mdev))
1691 		return err;
1692 
1693 	rcu_read_lock();
1694 	err = -ENODEV;
1695 	mlx5_devcom_for_each_peer_entry_rcu(esw->devcom, esw, pos) {
1696 		err = mlx5_eswitch_vhca_id_to_vport(esw, vhca_id, vport);
1697 		if (!err)
1698 			break;
1699 	}
1700 	rcu_read_unlock();
1701 
1702 	return err;
1703 }
1704 
1705 static int
verify_attr_actions(u32 actions,struct netlink_ext_ack * extack)1706 verify_attr_actions(u32 actions, struct netlink_ext_ack *extack)
1707 {
1708 	if (!(actions &
1709 	      (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1710 		NL_SET_ERR_MSG_MOD(extack, "Rule must have at least one forward/drop action");
1711 		return -EOPNOTSUPP;
1712 	}
1713 
1714 	if (!(~actions &
1715 	      (MLX5_FLOW_CONTEXT_ACTION_FWD_DEST | MLX5_FLOW_CONTEXT_ACTION_DROP))) {
1716 		NL_SET_ERR_MSG_MOD(extack, "Rule cannot support forward+drop action");
1717 		return -EOPNOTSUPP;
1718 	}
1719 
1720 	if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
1721 	    actions & MLX5_FLOW_CONTEXT_ACTION_DROP) {
1722 		NL_SET_ERR_MSG_MOD(extack, "Drop with modify header action is not supported");
1723 		return -EOPNOTSUPP;
1724 	}
1725 
1726 	return 0;
1727 }
1728 
1729 static bool
has_encap_dests(struct mlx5_flow_attr * attr)1730 has_encap_dests(struct mlx5_flow_attr *attr)
1731 {
1732 	struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
1733 	int out_index;
1734 
1735 	for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
1736 		if (esw_attr->dests[out_index].flags & MLX5_ESW_DEST_ENCAP)
1737 			return true;
1738 
1739 	return false;
1740 }
1741 
1742 static int
extra_split_attr_dests_needed(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)1743 extra_split_attr_dests_needed(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
1744 {
1745 	bool int_dest = false, ext_dest = false;
1746 	struct mlx5_esw_flow_attr *esw_attr;
1747 	int i;
1748 
1749 	if (flow->attr != attr ||
1750 	    !list_is_first(&attr->list, &flow->attrs))
1751 		return 0;
1752 
1753 	if (flow_flag_test(flow, SLOW))
1754 		return 0;
1755 
1756 	esw_attr = attr->esw_attr;
1757 	if (!esw_attr->split_count ||
1758 	    esw_attr->split_count == esw_attr->out_count - 1)
1759 		return 0;
1760 
1761 	if (esw_attr->dest_int_port &&
1762 	    (esw_attr->dests[esw_attr->split_count].flags &
1763 	     MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE))
1764 		return esw_attr->split_count + 1;
1765 
1766 	for (i = esw_attr->split_count; i < esw_attr->out_count; i++) {
1767 		/* external dest with encap is considered as internal by firmware */
1768 		if (esw_attr->dests[i].vport == MLX5_VPORT_UPLINK &&
1769 		    !(esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP_VALID))
1770 			ext_dest = true;
1771 		else
1772 			int_dest = true;
1773 
1774 		if (ext_dest && int_dest)
1775 			return esw_attr->split_count;
1776 	}
1777 
1778 	return 0;
1779 }
1780 
1781 static int
extra_split_attr_dests(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,int split_count)1782 extra_split_attr_dests(struct mlx5e_tc_flow *flow,
1783 		       struct mlx5_flow_attr *attr, int split_count)
1784 {
1785 	struct mlx5e_post_act *post_act = get_post_action(flow->priv);
1786 	struct mlx5e_tc_flow_parse_attr *parse_attr, *parse_attr2;
1787 	struct mlx5_esw_flow_attr *esw_attr, *esw_attr2;
1788 	struct mlx5e_post_act_handle *handle;
1789 	struct mlx5_flow_attr *attr2;
1790 	int i, j, err;
1791 
1792 	if (IS_ERR(post_act))
1793 		return PTR_ERR(post_act);
1794 
1795 	attr2 = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
1796 	parse_attr2 = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
1797 	if (!attr2 || !parse_attr2) {
1798 		err = -ENOMEM;
1799 		goto err_free;
1800 	}
1801 	attr2->parse_attr = parse_attr2;
1802 
1803 	handle = mlx5e_tc_post_act_add(post_act, attr2);
1804 	if (IS_ERR(handle)) {
1805 		err = PTR_ERR(handle);
1806 		goto err_free;
1807 	}
1808 
1809 	esw_attr = attr->esw_attr;
1810 	esw_attr2 = attr2->esw_attr;
1811 	esw_attr2->in_rep = esw_attr->in_rep;
1812 
1813 	parse_attr = attr->parse_attr;
1814 	parse_attr2->filter_dev = parse_attr->filter_dev;
1815 
1816 	for (i = split_count, j = 0; i < esw_attr->out_count; i++, j++)
1817 		esw_attr2->dests[j] = esw_attr->dests[i];
1818 
1819 	esw_attr2->out_count = j;
1820 	attr2->action = MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
1821 
1822 	err = mlx5e_tc_post_act_offload(post_act, handle);
1823 	if (err)
1824 		goto err_post_act_offload;
1825 
1826 	err = mlx5e_tc_post_act_set_handle(flow->priv->mdev, handle,
1827 					   &parse_attr->mod_hdr_acts);
1828 	if (err)
1829 		goto err_post_act_set_handle;
1830 
1831 	esw_attr->out_count = split_count;
1832 	attr->extra_split_ft = mlx5e_tc_post_act_get_ft(post_act);
1833 	flow->extra_split_attr = attr2;
1834 
1835 	attr2->post_act_handle = handle;
1836 
1837 	return 0;
1838 
1839 err_post_act_set_handle:
1840 	mlx5e_tc_post_act_unoffload(post_act, handle);
1841 err_post_act_offload:
1842 	mlx5e_tc_post_act_del(post_act, handle);
1843 err_free:
1844 	kvfree(parse_attr2);
1845 	kfree(attr2);
1846 	return err;
1847 }
1848 
1849 static int
post_process_attr(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct netlink_ext_ack * extack)1850 post_process_attr(struct mlx5e_tc_flow *flow,
1851 		  struct mlx5_flow_attr *attr,
1852 		  struct netlink_ext_ack *extack)
1853 {
1854 	int extra_split;
1855 	bool vf_tun;
1856 	int err = 0;
1857 
1858 	err = verify_attr_actions(attr->action, extack);
1859 	if (err)
1860 		goto err_out;
1861 
1862 	if (mlx5e_is_eswitch_flow(flow) && has_encap_dests(attr)) {
1863 		err = mlx5e_tc_tun_encap_dests_set(flow->priv, flow, attr, extack, &vf_tun);
1864 		if (err)
1865 			goto err_out;
1866 	}
1867 
1868 	extra_split = extra_split_attr_dests_needed(flow, attr);
1869 	if (extra_split > 0) {
1870 		err = extra_split_attr_dests(flow, attr, extra_split);
1871 		if (err)
1872 			goto err_out;
1873 	}
1874 
1875 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1876 		err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr);
1877 		if (err)
1878 			goto err_out;
1879 	}
1880 
1881 	if (attr->branch_true &&
1882 	    attr->branch_true->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1883 		err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_true);
1884 		if (err)
1885 			goto err_out;
1886 	}
1887 
1888 	if (attr->branch_false &&
1889 	    attr->branch_false->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
1890 		err = mlx5e_tc_attach_mod_hdr(flow->priv, flow, attr->branch_false);
1891 		if (err)
1892 			goto err_out;
1893 	}
1894 
1895 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
1896 		err = alloc_flow_attr_counter(get_flow_counter_dev(flow), attr);
1897 		if (err)
1898 			goto err_out;
1899 	}
1900 
1901 err_out:
1902 	return err;
1903 }
1904 
1905 static int
mlx5e_tc_add_fdb_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)1906 mlx5e_tc_add_fdb_flow(struct mlx5e_priv *priv,
1907 		      struct mlx5e_tc_flow *flow,
1908 		      struct netlink_ext_ack *extack)
1909 {
1910 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
1911 	struct mlx5e_tc_flow_parse_attr *parse_attr;
1912 	struct mlx5_flow_attr *attr = flow->attr;
1913 	struct mlx5_esw_flow_attr *esw_attr;
1914 	u32 max_prio, max_chain;
1915 	int err = 0;
1916 
1917 	parse_attr = attr->parse_attr;
1918 	esw_attr = attr->esw_attr;
1919 
1920 	/* We check chain range only for tc flows.
1921 	 * For ft flows, we checked attr->chain was originally 0 and set it to
1922 	 * FDB_FT_CHAIN which is outside tc range.
1923 	 * See mlx5e_rep_setup_ft_cb().
1924 	 */
1925 	max_chain = mlx5_chains_get_chain_range(esw_chains(esw));
1926 	if (!mlx5e_is_ft_flow(flow) && attr->chain > max_chain) {
1927 		NL_SET_ERR_MSG_MOD(extack,
1928 				   "Requested chain is out of supported range");
1929 		err = -EOPNOTSUPP;
1930 		goto err_out;
1931 	}
1932 
1933 	max_prio = mlx5_chains_get_prio_range(esw_chains(esw));
1934 	if (attr->prio > max_prio) {
1935 		NL_SET_ERR_MSG_MOD(extack,
1936 				   "Requested priority is out of supported range");
1937 		err = -EOPNOTSUPP;
1938 		goto err_out;
1939 	}
1940 
1941 	if (flow_flag_test(flow, TUN_RX)) {
1942 		err = mlx5e_attach_decap_route(priv, flow);
1943 		if (err)
1944 			goto err_out;
1945 
1946 		if (!attr->chain && esw_attr->int_port &&
1947 		    attr->action & MLX5_FLOW_CONTEXT_ACTION_FWD_DEST) {
1948 			/* If decap route device is internal port, change the
1949 			 * source vport value in reg_c0 back to uplink just in
1950 			 * case the rule performs goto chain > 0. If we have a miss
1951 			 * on chain > 0 we want the metadata regs to hold the
1952 			 * chain id so SW will resume handling of this packet
1953 			 * from the proper chain.
1954 			 */
1955 			u32 metadata = mlx5_eswitch_get_vport_metadata_for_set(esw,
1956 									esw_attr->in_rep->vport);
1957 
1958 			err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
1959 							MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
1960 							metadata);
1961 			if (err)
1962 				goto err_out;
1963 
1964 			attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
1965 		}
1966 	}
1967 
1968 	if (flow_flag_test(flow, L3_TO_L2_DECAP)) {
1969 		err = mlx5e_attach_decap(priv, flow, extack);
1970 		if (err)
1971 			goto err_out;
1972 	}
1973 
1974 	if (netif_is_ovs_master(parse_attr->filter_dev)) {
1975 		struct mlx5e_tc_int_port *int_port;
1976 
1977 		if (attr->chain) {
1978 			NL_SET_ERR_MSG_MOD(extack,
1979 					   "Internal port rule is only supported on chain 0");
1980 			err = -EOPNOTSUPP;
1981 			goto err_out;
1982 		}
1983 
1984 		if (attr->dest_chain) {
1985 			NL_SET_ERR_MSG_MOD(extack,
1986 					   "Internal port rule offload doesn't support goto action");
1987 			err = -EOPNOTSUPP;
1988 			goto err_out;
1989 		}
1990 
1991 		int_port = mlx5e_tc_int_port_get(mlx5e_get_int_port_priv(priv),
1992 						 parse_attr->filter_dev->ifindex,
1993 						 flow_flag_test(flow, EGRESS) ?
1994 						 MLX5E_TC_INT_PORT_EGRESS :
1995 						 MLX5E_TC_INT_PORT_INGRESS);
1996 		if (IS_ERR(int_port)) {
1997 			err = PTR_ERR(int_port);
1998 			goto err_out;
1999 		}
2000 
2001 		esw_attr->int_port = int_port;
2002 	}
2003 
2004 	err = post_process_attr(flow, attr, extack);
2005 	if (err)
2006 		goto err_out;
2007 
2008 	err = mlx5e_tc_act_stats_add_flow(get_act_stats_handle(priv), flow);
2009 	if (err)
2010 		goto err_out;
2011 
2012 	/* we get here if one of the following takes place:
2013 	 * (1) there's no error
2014 	 * (2) there's an encap action and we don't have valid neigh
2015 	 */
2016 	if (flow_flag_test(flow, SLOW))
2017 		flow->rule[0] = mlx5e_tc_offload_to_slow_path(esw, flow, &parse_attr->spec);
2018 	else
2019 		flow->rule[0] = mlx5e_tc_offload_fdb_rules(esw, flow, &parse_attr->spec, attr);
2020 
2021 	if (IS_ERR(flow->rule[0])) {
2022 		err = PTR_ERR(flow->rule[0]);
2023 		goto err_out;
2024 	}
2025 	flow_flag_set(flow, OFFLOADED);
2026 
2027 	return 0;
2028 
2029 err_out:
2030 	flow_flag_set(flow, FAILED);
2031 	return err;
2032 }
2033 
mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow * flow)2034 static bool mlx5_flow_has_geneve_opt(struct mlx5e_tc_flow *flow)
2035 {
2036 	struct mlx5_flow_spec *spec = &flow->attr->parse_attr->spec;
2037 	void *headers_v = MLX5_ADDR_OF(fte_match_param,
2038 				       spec->match_value,
2039 				       misc_parameters_3);
2040 	u32 geneve_tlv_opt_0_data = MLX5_GET(fte_match_set_misc3,
2041 					     headers_v,
2042 					     geneve_tlv_option_0_data);
2043 
2044 	return !!geneve_tlv_opt_0_data;
2045 }
2046 
free_branch_attr(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)2047 static void free_branch_attr(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
2048 {
2049 	if (!attr)
2050 		return;
2051 
2052 	mlx5_free_flow_attr_actions(flow, attr);
2053 	kvfree(attr->parse_attr);
2054 	kfree(attr);
2055 }
2056 
mlx5e_tc_del_fdb_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)2057 static void mlx5e_tc_del_fdb_flow(struct mlx5e_priv *priv,
2058 				  struct mlx5e_tc_flow *flow)
2059 {
2060 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2061 	struct mlx5_flow_attr *attr = flow->attr;
2062 
2063 	mlx5e_put_flow_tunnel_id(flow);
2064 
2065 	remove_unready_flow(flow);
2066 
2067 	if (mlx5e_is_offloaded_flow(flow)) {
2068 		if (flow_flag_test(flow, SLOW))
2069 			mlx5e_tc_unoffload_from_slow_path(esw, flow);
2070 		else
2071 			mlx5e_tc_unoffload_fdb_rules(esw, flow, attr);
2072 	}
2073 	complete_all(&flow->del_hw_done);
2074 
2075 	if (mlx5_flow_has_geneve_opt(flow))
2076 		mlx5_geneve_tlv_option_del(priv->mdev->geneve);
2077 
2078 	if (flow->decap_route)
2079 		mlx5e_detach_decap_route(priv, flow);
2080 
2081 	mlx5_tc_ct_match_del(get_ct_priv(priv), &flow->attr->ct_attr);
2082 
2083 	if (flow_flag_test(flow, L3_TO_L2_DECAP))
2084 		mlx5e_detach_decap(priv, flow);
2085 
2086 	mlx5e_tc_act_stats_del_flow(get_act_stats_handle(priv), flow);
2087 
2088 	free_flow_post_acts(flow);
2089 	if (flow->extra_split_attr) {
2090 		mlx5_free_flow_attr_actions(flow, flow->extra_split_attr);
2091 		kvfree(flow->extra_split_attr->parse_attr);
2092 		kfree(flow->extra_split_attr);
2093 	}
2094 	mlx5_free_flow_attr_actions(flow, attr);
2095 
2096 	kvfree(attr->esw_attr->rx_tun_attr);
2097 	kvfree(attr->parse_attr);
2098 	kfree(flow->attr);
2099 }
2100 
mlx5e_tc_get_counter(struct mlx5e_tc_flow * flow)2101 struct mlx5_fc *mlx5e_tc_get_counter(struct mlx5e_tc_flow *flow)
2102 {
2103 	struct mlx5_flow_attr *attr;
2104 
2105 	attr = list_first_entry(&flow->attrs, struct mlx5_flow_attr, list);
2106 	return attr->counter;
2107 }
2108 
2109 /* Iterate over tmp_list of flows attached to flow_list head. */
mlx5e_put_flow_list(struct mlx5e_priv * priv,struct list_head * flow_list)2110 void mlx5e_put_flow_list(struct mlx5e_priv *priv, struct list_head *flow_list)
2111 {
2112 	struct mlx5e_tc_flow *flow, *tmp;
2113 
2114 	list_for_each_entry_safe(flow, tmp, flow_list, tmp_list)
2115 		mlx5e_flow_put(priv, flow);
2116 }
2117 
mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow * flow,int peer_index)2118 static void mlx5e_tc_del_fdb_peer_flow(struct mlx5e_tc_flow *flow,
2119 				       int peer_index)
2120 {
2121 	struct mlx5_eswitch *esw = flow->priv->mdev->priv.eswitch;
2122 	struct mlx5e_tc_flow *peer_flow;
2123 	struct mlx5e_tc_flow *tmp;
2124 
2125 	if (!flow_flag_test(flow, ESWITCH) ||
2126 	    !flow_flag_test(flow, DUP))
2127 		return;
2128 
2129 	mutex_lock(&esw->offloads.peer_mutex);
2130 	list_del(&flow->peer[peer_index]);
2131 	mutex_unlock(&esw->offloads.peer_mutex);
2132 
2133 	list_for_each_entry_safe(peer_flow, tmp, &flow->peer_flows, peer_flows) {
2134 		if (peer_index != mlx5_get_dev_index(peer_flow->priv->mdev))
2135 			continue;
2136 
2137 		list_del(&peer_flow->peer_flows);
2138 		if (refcount_dec_and_test(&peer_flow->refcnt)) {
2139 			mlx5e_tc_del_fdb_flow(peer_flow->priv, peer_flow);
2140 			kfree(peer_flow);
2141 		}
2142 	}
2143 
2144 	if (list_empty(&flow->peer_flows))
2145 		flow_flag_clear(flow, DUP);
2146 }
2147 
mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow * flow)2148 static void mlx5e_tc_del_fdb_peers_flow(struct mlx5e_tc_flow *flow)
2149 {
2150 	int i;
2151 
2152 	for (i = 0; i < MLX5_MAX_PORTS; i++) {
2153 		if (i == mlx5_get_dev_index(flow->priv->mdev))
2154 			continue;
2155 		mlx5e_tc_del_fdb_peer_flow(flow, i);
2156 	}
2157 }
2158 
mlx5e_tc_del_flow(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow)2159 static void mlx5e_tc_del_flow(struct mlx5e_priv *priv,
2160 			      struct mlx5e_tc_flow *flow)
2161 {
2162 	if (mlx5e_is_eswitch_flow(flow)) {
2163 		struct mlx5_devcom_comp_dev *devcom = flow->priv->mdev->priv.eswitch->devcom;
2164 
2165 		if (!mlx5_devcom_for_each_peer_begin(devcom)) {
2166 			mlx5e_tc_del_fdb_flow(priv, flow);
2167 			return;
2168 		}
2169 
2170 		mlx5e_tc_del_fdb_peers_flow(flow);
2171 		mlx5_devcom_for_each_peer_end(devcom);
2172 		mlx5e_tc_del_fdb_flow(priv, flow);
2173 	} else {
2174 		mlx5e_tc_del_nic_flow(priv, flow);
2175 	}
2176 }
2177 
flow_requires_tunnel_mapping(u32 chain,struct flow_cls_offload * f)2178 static bool flow_requires_tunnel_mapping(u32 chain, struct flow_cls_offload *f)
2179 {
2180 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2181 	struct flow_action *flow_action = &rule->action;
2182 	const struct flow_action_entry *act;
2183 	int i;
2184 
2185 	if (chain)
2186 		return false;
2187 
2188 	flow_action_for_each(i, act, flow_action) {
2189 		switch (act->id) {
2190 		case FLOW_ACTION_GOTO:
2191 			return true;
2192 		case FLOW_ACTION_SAMPLE:
2193 			return true;
2194 		default:
2195 			continue;
2196 		}
2197 	}
2198 
2199 	return false;
2200 }
2201 
2202 static int
enc_opts_is_dont_care_or_full_match(struct mlx5e_priv * priv,struct flow_dissector_key_enc_opts * opts,struct netlink_ext_ack * extack,bool * dont_care)2203 enc_opts_is_dont_care_or_full_match(struct mlx5e_priv *priv,
2204 				    struct flow_dissector_key_enc_opts *opts,
2205 				    struct netlink_ext_ack *extack,
2206 				    bool *dont_care)
2207 {
2208 	struct geneve_opt *opt;
2209 	int off = 0;
2210 
2211 	*dont_care = true;
2212 
2213 	while (opts->len > off) {
2214 		opt = (struct geneve_opt *)&opts->data[off];
2215 
2216 		if (!(*dont_care) || opt->opt_class || opt->type ||
2217 		    memchr_inv(opt->opt_data, 0, opt->length * 4)) {
2218 			*dont_care = false;
2219 
2220 			if (opt->opt_class != htons(U16_MAX) ||
2221 			    opt->type != U8_MAX) {
2222 				NL_SET_ERR_MSG_MOD(extack,
2223 						   "Partial match of tunnel options in chain > 0 isn't supported");
2224 				netdev_warn(priv->netdev,
2225 					    "Partial match of tunnel options in chain > 0 isn't supported");
2226 				return -EOPNOTSUPP;
2227 			}
2228 		}
2229 
2230 		off += sizeof(struct geneve_opt) + opt->length * 4;
2231 	}
2232 
2233 	return 0;
2234 }
2235 
2236 #define COPY_DISSECTOR(rule, diss_key, dst)\
2237 ({ \
2238 	struct flow_rule *__rule = (rule);\
2239 	typeof(dst) __dst = dst;\
2240 \
2241 	memcpy(__dst,\
2242 	       skb_flow_dissector_target(__rule->match.dissector,\
2243 					 diss_key,\
2244 					 __rule->match.key),\
2245 	       sizeof(*__dst));\
2246 })
2247 
mlx5e_get_flow_tunnel_id(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct flow_cls_offload * f,struct net_device * filter_dev)2248 static int mlx5e_get_flow_tunnel_id(struct mlx5e_priv *priv,
2249 				    struct mlx5e_tc_flow *flow,
2250 				    struct flow_cls_offload *f,
2251 				    struct net_device *filter_dev)
2252 {
2253 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2254 	struct netlink_ext_ack *extack = f->common.extack;
2255 	struct mlx5e_tc_mod_hdr_acts *mod_hdr_acts;
2256 	struct flow_match_enc_opts enc_opts_match;
2257 	struct tunnel_match_enc_opts tun_enc_opts;
2258 	struct mlx5_rep_uplink_priv *uplink_priv;
2259 	struct mlx5_flow_attr *attr = flow->attr;
2260 	struct mlx5e_rep_priv *uplink_rpriv;
2261 	struct tunnel_match_key tunnel_key;
2262 	bool enc_opts_is_dont_care = true;
2263 	u32 tun_id, enc_opts_id = 0;
2264 	struct mlx5_eswitch *esw;
2265 	u32 value, mask;
2266 	int err;
2267 
2268 	esw = priv->mdev->priv.eswitch;
2269 	uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2270 	uplink_priv = &uplink_rpriv->uplink_priv;
2271 
2272 	memset(&tunnel_key, 0, sizeof(tunnel_key));
2273 	COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_CONTROL,
2274 		       &tunnel_key.enc_control);
2275 	if (tunnel_key.enc_control.addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS)
2276 		COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS,
2277 			       &tunnel_key.enc_ipv4);
2278 	else
2279 		COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS,
2280 			       &tunnel_key.enc_ipv6);
2281 	COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_IP, &tunnel_key.enc_ip);
2282 	COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_PORTS,
2283 		       &tunnel_key.enc_tp);
2284 	COPY_DISSECTOR(rule, FLOW_DISSECTOR_KEY_ENC_KEYID,
2285 		       &tunnel_key.enc_key_id);
2286 	tunnel_key.filter_ifindex = filter_dev->ifindex;
2287 
2288 	err = mapping_add(uplink_priv->tunnel_mapping, &tunnel_key, &tun_id);
2289 	if (err)
2290 		return err;
2291 
2292 	flow_rule_match_enc_opts(rule, &enc_opts_match);
2293 	err = enc_opts_is_dont_care_or_full_match(priv,
2294 						  enc_opts_match.mask,
2295 						  extack,
2296 						  &enc_opts_is_dont_care);
2297 	if (err)
2298 		goto err_enc_opts;
2299 
2300 	if (!enc_opts_is_dont_care) {
2301 		memset(&tun_enc_opts, 0, sizeof(tun_enc_opts));
2302 		memcpy(&tun_enc_opts.key, enc_opts_match.key,
2303 		       sizeof(*enc_opts_match.key));
2304 		memcpy(&tun_enc_opts.mask, enc_opts_match.mask,
2305 		       sizeof(*enc_opts_match.mask));
2306 
2307 		err = mapping_add(uplink_priv->tunnel_enc_opts_mapping,
2308 				  &tun_enc_opts, &enc_opts_id);
2309 		if (err)
2310 			goto err_enc_opts;
2311 	}
2312 
2313 	value = tun_id << ENC_OPTS_BITS | enc_opts_id;
2314 	mask = enc_opts_id ? TUNNEL_ID_MASK :
2315 			     (TUNNEL_ID_MASK & ~ENC_OPTS_BITS_MASK);
2316 
2317 	if (attr->chain) {
2318 		mlx5e_tc_match_to_reg_match(&attr->parse_attr->spec,
2319 					    TUNNEL_TO_REG, value, mask);
2320 	} else {
2321 		mod_hdr_acts = &attr->parse_attr->mod_hdr_acts;
2322 		err = mlx5e_tc_match_to_reg_set(priv->mdev,
2323 						mod_hdr_acts, MLX5_FLOW_NAMESPACE_FDB,
2324 						TUNNEL_TO_REG, value);
2325 		if (err)
2326 			goto err_set;
2327 
2328 		attr->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2329 	}
2330 
2331 	flow->attr->tunnel_id = value;
2332 	return 0;
2333 
2334 err_set:
2335 	if (enc_opts_id)
2336 		mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2337 			       enc_opts_id);
2338 err_enc_opts:
2339 	mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2340 	return err;
2341 }
2342 
mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow * flow)2343 static void mlx5e_put_flow_tunnel_id(struct mlx5e_tc_flow *flow)
2344 {
2345 	u32 enc_opts_id = flow->attr->tunnel_id & ENC_OPTS_BITS_MASK;
2346 	u32 tun_id = flow->attr->tunnel_id >> ENC_OPTS_BITS;
2347 	struct mlx5_rep_uplink_priv *uplink_priv;
2348 	struct mlx5e_rep_priv *uplink_rpriv;
2349 	struct mlx5_eswitch *esw;
2350 
2351 	esw = flow->priv->mdev->priv.eswitch;
2352 	uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
2353 	uplink_priv = &uplink_rpriv->uplink_priv;
2354 
2355 	if (tun_id)
2356 		mapping_remove(uplink_priv->tunnel_mapping, tun_id);
2357 	if (enc_opts_id)
2358 		mapping_remove(uplink_priv->tunnel_enc_opts_mapping,
2359 			       enc_opts_id);
2360 }
2361 
mlx5e_tc_set_ethertype(struct mlx5_core_dev * mdev,struct flow_match_basic * match,bool outer,void * headers_c,void * headers_v)2362 void mlx5e_tc_set_ethertype(struct mlx5_core_dev *mdev,
2363 			    struct flow_match_basic *match, bool outer,
2364 			    void *headers_c, void *headers_v)
2365 {
2366 	bool ip_version_cap;
2367 
2368 	ip_version_cap = outer ?
2369 		MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2370 					  ft_field_support.outer_ip_version) :
2371 		MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2372 					  ft_field_support.inner_ip_version);
2373 
2374 	if (ip_version_cap && match->mask->n_proto == htons(0xFFFF) &&
2375 	    (match->key->n_proto == htons(ETH_P_IP) ||
2376 	     match->key->n_proto == htons(ETH_P_IPV6))) {
2377 		MLX5_SET_TO_ONES(fte_match_set_lyr_2_4, headers_c, ip_version);
2378 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_version,
2379 			 match->key->n_proto == htons(ETH_P_IP) ? 4 : 6);
2380 	} else {
2381 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, ethertype,
2382 			 ntohs(match->mask->n_proto));
2383 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ethertype,
2384 			 ntohs(match->key->n_proto));
2385 	}
2386 }
2387 
mlx5e_tc_get_ip_version(struct mlx5_flow_spec * spec,bool outer)2388 u8 mlx5e_tc_get_ip_version(struct mlx5_flow_spec *spec, bool outer)
2389 {
2390 	void *headers_v;
2391 	u16 ethertype;
2392 	u8 ip_version;
2393 
2394 	if (outer)
2395 		headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, outer_headers);
2396 	else
2397 		headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value, inner_headers);
2398 
2399 	ip_version = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_version);
2400 	/* Return ip_version converted from ethertype anyway */
2401 	if (!ip_version) {
2402 		ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
2403 		if (ethertype == ETH_P_IP || ethertype == ETH_P_ARP)
2404 			ip_version = 4;
2405 		else if (ethertype == ETH_P_IPV6)
2406 			ip_version = 6;
2407 	}
2408 	return ip_version;
2409 }
2410 
2411 /* Tunnel device follows RFC 6040, see include/net/inet_ecn.h.
2412  * And changes inner ip_ecn depending on inner and outer ip_ecn as follows:
2413  *      +---------+----------------------------------------+
2414  *      |Arriving |         Arriving Outer Header          |
2415  *      |   Inner +---------+---------+---------+----------+
2416  *      |  Header | Not-ECT | ECT(0)  | ECT(1)  |   CE     |
2417  *      +---------+---------+---------+---------+----------+
2418  *      | Not-ECT | Not-ECT | Not-ECT | Not-ECT | <drop>   |
2419  *      |  ECT(0) |  ECT(0) | ECT(0)  | ECT(1)  |   CE*    |
2420  *      |  ECT(1) |  ECT(1) | ECT(1)  | ECT(1)* |   CE*    |
2421  *      |    CE   |   CE    |  CE     | CE      |   CE     |
2422  *      +---------+---------+---------+---------+----------+
2423  *
2424  * Tc matches on inner after decapsulation on tunnel device, but hw offload matches
2425  * the inner ip_ecn value before hardware decap action.
2426  *
2427  * Cells marked are changed from original inner packet ip_ecn value during decap, and
2428  * so matching those values on inner ip_ecn before decap will fail.
2429  *
2430  * The following helper allows offload when inner ip_ecn won't be changed by outer ip_ecn,
2431  * except for the outer ip_ecn = CE, where in all cases inner ip_ecn will be changed to CE,
2432  * and such we can drop the inner ip_ecn=CE match.
2433  */
2434 
mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv * priv,struct flow_cls_offload * f,bool * match_inner_ecn)2435 static int mlx5e_tc_verify_tunnel_ecn(struct mlx5e_priv *priv,
2436 				      struct flow_cls_offload *f,
2437 				      bool *match_inner_ecn)
2438 {
2439 	u8 outer_ecn_mask = 0, outer_ecn_key = 0, inner_ecn_mask = 0, inner_ecn_key = 0;
2440 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2441 	struct netlink_ext_ack *extack = f->common.extack;
2442 	struct flow_match_ip match;
2443 
2444 	*match_inner_ecn = true;
2445 
2446 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ENC_IP)) {
2447 		flow_rule_match_enc_ip(rule, &match);
2448 		outer_ecn_key = match.key->tos & INET_ECN_MASK;
2449 		outer_ecn_mask = match.mask->tos & INET_ECN_MASK;
2450 	}
2451 
2452 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
2453 		flow_rule_match_ip(rule, &match);
2454 		inner_ecn_key = match.key->tos & INET_ECN_MASK;
2455 		inner_ecn_mask = match.mask->tos & INET_ECN_MASK;
2456 	}
2457 
2458 	if (outer_ecn_mask != 0 && outer_ecn_mask != INET_ECN_MASK) {
2459 		NL_SET_ERR_MSG_MOD(extack, "Partial match on enc_tos ecn bits isn't supported");
2460 		netdev_warn(priv->netdev, "Partial match on enc_tos ecn bits isn't supported");
2461 		return -EOPNOTSUPP;
2462 	}
2463 
2464 	if (!outer_ecn_mask) {
2465 		if (!inner_ecn_mask)
2466 			return 0;
2467 
2468 		NL_SET_ERR_MSG_MOD(extack,
2469 				   "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2470 		netdev_warn(priv->netdev,
2471 			    "Matching on tos ecn bits without also matching enc_tos ecn bits isn't supported");
2472 		return -EOPNOTSUPP;
2473 	}
2474 
2475 	if (inner_ecn_mask && inner_ecn_mask != INET_ECN_MASK) {
2476 		NL_SET_ERR_MSG_MOD(extack,
2477 				   "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2478 		netdev_warn(priv->netdev,
2479 			    "Partial match on tos ecn bits with match on enc_tos ecn bits isn't supported");
2480 		return -EOPNOTSUPP;
2481 	}
2482 
2483 	if (!inner_ecn_mask)
2484 		return 0;
2485 
2486 	/* Both inner and outer have full mask on ecn */
2487 
2488 	if (outer_ecn_key == INET_ECN_ECT_1) {
2489 		/* inner ecn might change by DECAP action */
2490 
2491 		NL_SET_ERR_MSG_MOD(extack, "Match on enc_tos ecn = ECT(1) isn't supported");
2492 		netdev_warn(priv->netdev, "Match on enc_tos ecn = ECT(1) isn't supported");
2493 		return -EOPNOTSUPP;
2494 	}
2495 
2496 	if (outer_ecn_key != INET_ECN_CE)
2497 		return 0;
2498 
2499 	if (inner_ecn_key != INET_ECN_CE) {
2500 		/* Can't happen in software, as packet ecn will be changed to CE after decap */
2501 		NL_SET_ERR_MSG_MOD(extack,
2502 				   "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2503 		netdev_warn(priv->netdev,
2504 			    "Match on tos enc_tos ecn = CE while match on tos ecn != CE isn't supported");
2505 		return -EOPNOTSUPP;
2506 	}
2507 
2508 	/* outer ecn = CE, inner ecn = CE, as decap will change inner ecn to CE in anycase,
2509 	 * drop match on inner ecn
2510 	 */
2511 	*match_inner_ecn = false;
2512 
2513 	return 0;
2514 }
2515 
parse_tunnel_attr(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev,u8 * match_level,bool * match_inner)2516 static int parse_tunnel_attr(struct mlx5e_priv *priv,
2517 			     struct mlx5e_tc_flow *flow,
2518 			     struct mlx5_flow_spec *spec,
2519 			     struct flow_cls_offload *f,
2520 			     struct net_device *filter_dev,
2521 			     u8 *match_level,
2522 			     bool *match_inner)
2523 {
2524 	struct mlx5e_tc_tunnel *tunnel = mlx5e_get_tc_tun(filter_dev);
2525 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
2526 	struct netlink_ext_ack *extack = f->common.extack;
2527 	bool needs_mapping, sets_mapping;
2528 	int err;
2529 
2530 	if (!mlx5e_is_eswitch_flow(flow)) {
2531 		NL_SET_ERR_MSG_MOD(extack, "Match on tunnel is not supported");
2532 		return -EOPNOTSUPP;
2533 	}
2534 
2535 	needs_mapping = !!flow->attr->chain;
2536 	sets_mapping = flow_requires_tunnel_mapping(flow->attr->chain, f);
2537 	*match_inner = !needs_mapping;
2538 
2539 	if ((needs_mapping || sets_mapping) &&
2540 	    !mlx5_eswitch_reg_c1_loopback_enabled(esw)) {
2541 		NL_SET_ERR_MSG_MOD(extack,
2542 				   "Chains on tunnel devices isn't supported without register loopback support");
2543 		netdev_warn(priv->netdev,
2544 			    "Chains on tunnel devices isn't supported without register loopback support");
2545 		return -EOPNOTSUPP;
2546 	}
2547 
2548 	if (!flow->attr->chain) {
2549 		err = mlx5e_tc_tun_parse(filter_dev, priv, spec, f,
2550 					 match_level);
2551 		if (err) {
2552 			NL_SET_ERR_MSG_MOD(extack,
2553 					   "Failed to parse tunnel attributes");
2554 			netdev_warn(priv->netdev,
2555 				    "Failed to parse tunnel attributes");
2556 			return err;
2557 		}
2558 
2559 		/* With mpls over udp we decapsulate using packet reformat
2560 		 * object
2561 		 */
2562 		if (!netif_is_bareudp(filter_dev))
2563 			flow->attr->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2564 		err = mlx5e_tc_set_attr_rx_tun(flow, spec);
2565 		if (err)
2566 			return err;
2567 	} else if (tunnel) {
2568 		struct mlx5_flow_spec *tmp_spec;
2569 
2570 		tmp_spec = kvzalloc(sizeof(*tmp_spec), GFP_KERNEL);
2571 		if (!tmp_spec) {
2572 			NL_SET_ERR_MSG_MOD(extack, "Failed to allocate memory for tunnel tmp spec");
2573 			netdev_warn(priv->netdev, "Failed to allocate memory for tunnel tmp spec");
2574 			return -ENOMEM;
2575 		}
2576 		memcpy(tmp_spec, spec, sizeof(*tmp_spec));
2577 
2578 		err = mlx5e_tc_tun_parse(filter_dev, priv, tmp_spec, f, match_level);
2579 		if (err) {
2580 			kvfree(tmp_spec);
2581 			NL_SET_ERR_MSG_MOD(extack, "Failed to parse tunnel attributes");
2582 			netdev_warn(priv->netdev, "Failed to parse tunnel attributes");
2583 			return err;
2584 		}
2585 		err = mlx5e_tc_set_attr_rx_tun(flow, tmp_spec);
2586 		kvfree(tmp_spec);
2587 		if (err)
2588 			return err;
2589 	}
2590 
2591 	if (!needs_mapping && !sets_mapping)
2592 		return 0;
2593 
2594 	return mlx5e_get_flow_tunnel_id(priv, flow, f, filter_dev);
2595 }
2596 
get_match_inner_headers_criteria(struct mlx5_flow_spec * spec)2597 static void *get_match_inner_headers_criteria(struct mlx5_flow_spec *spec)
2598 {
2599 	return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2600 			    inner_headers);
2601 }
2602 
get_match_inner_headers_value(struct mlx5_flow_spec * spec)2603 static void *get_match_inner_headers_value(struct mlx5_flow_spec *spec)
2604 {
2605 	return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2606 			    inner_headers);
2607 }
2608 
get_match_outer_headers_criteria(struct mlx5_flow_spec * spec)2609 static void *get_match_outer_headers_criteria(struct mlx5_flow_spec *spec)
2610 {
2611 	return MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2612 			    outer_headers);
2613 }
2614 
get_match_outer_headers_value(struct mlx5_flow_spec * spec)2615 static void *get_match_outer_headers_value(struct mlx5_flow_spec *spec)
2616 {
2617 	return MLX5_ADDR_OF(fte_match_param, spec->match_value,
2618 			    outer_headers);
2619 }
2620 
mlx5e_get_match_headers_value(u32 flags,struct mlx5_flow_spec * spec)2621 void *mlx5e_get_match_headers_value(u32 flags, struct mlx5_flow_spec *spec)
2622 {
2623 	return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2624 		get_match_inner_headers_value(spec) :
2625 		get_match_outer_headers_value(spec);
2626 }
2627 
mlx5e_get_match_headers_criteria(u32 flags,struct mlx5_flow_spec * spec)2628 void *mlx5e_get_match_headers_criteria(u32 flags, struct mlx5_flow_spec *spec)
2629 {
2630 	return (flags & MLX5_FLOW_CONTEXT_ACTION_DECAP) ?
2631 		get_match_inner_headers_criteria(spec) :
2632 		get_match_outer_headers_criteria(spec);
2633 }
2634 
mlx5e_flower_parse_meta(struct net_device * filter_dev,struct flow_cls_offload * f)2635 static int mlx5e_flower_parse_meta(struct net_device *filter_dev,
2636 				   struct flow_cls_offload *f)
2637 {
2638 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2639 	struct netlink_ext_ack *extack = f->common.extack;
2640 	struct net_device *ingress_dev;
2641 	struct flow_match_meta match;
2642 
2643 	if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_META))
2644 		return 0;
2645 
2646 	flow_rule_match_meta(rule, &match);
2647 
2648 	if (match.mask->l2_miss) {
2649 		NL_SET_ERR_MSG_MOD(f->common.extack, "Can't match on \"l2_miss\"");
2650 		return -EOPNOTSUPP;
2651 	}
2652 
2653 	if (!match.mask->ingress_ifindex)
2654 		return 0;
2655 
2656 	if (match.mask->ingress_ifindex != 0xFFFFFFFF) {
2657 		NL_SET_ERR_MSG_MOD(extack, "Unsupported ingress ifindex mask");
2658 		return -EOPNOTSUPP;
2659 	}
2660 
2661 	ingress_dev = __dev_get_by_index(dev_net(filter_dev),
2662 					 match.key->ingress_ifindex);
2663 	if (!ingress_dev) {
2664 		NL_SET_ERR_MSG_MOD(extack,
2665 				   "Can't find the ingress port to match on");
2666 		return -ENOENT;
2667 	}
2668 
2669 	if (ingress_dev != filter_dev) {
2670 		NL_SET_ERR_MSG_MOD(extack,
2671 				   "Can't match on the ingress filter port");
2672 		return -EOPNOTSUPP;
2673 	}
2674 
2675 	return 0;
2676 }
2677 
skip_key_basic(struct net_device * filter_dev,struct flow_cls_offload * f)2678 static bool skip_key_basic(struct net_device *filter_dev,
2679 			   struct flow_cls_offload *f)
2680 {
2681 	/* When doing mpls over udp decap, the user needs to provide
2682 	 * MPLS_UC as the protocol in order to be able to match on mpls
2683 	 * label fields.  However, the actual ethertype is IP so we want to
2684 	 * avoid matching on this, otherwise we'll fail the match.
2685 	 */
2686 	if (netif_is_bareudp(filter_dev) && f->common.chain_index == 0)
2687 		return true;
2688 
2689 	return false;
2690 }
2691 
__parse_cls_flower(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev,u8 * inner_match_level,u8 * outer_match_level)2692 static int __parse_cls_flower(struct mlx5e_priv *priv,
2693 			      struct mlx5e_tc_flow *flow,
2694 			      struct mlx5_flow_spec *spec,
2695 			      struct flow_cls_offload *f,
2696 			      struct net_device *filter_dev,
2697 			      u8 *inner_match_level, u8 *outer_match_level)
2698 {
2699 	struct netlink_ext_ack *extack = f->common.extack;
2700 	void *headers_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2701 				       outer_headers);
2702 	void *headers_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2703 				       outer_headers);
2704 	void *misc_c = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2705 				    misc_parameters);
2706 	void *misc_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2707 				    misc_parameters);
2708 	void *misc_c_3 = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
2709 				    misc_parameters_3);
2710 	void *misc_v_3 = MLX5_ADDR_OF(fte_match_param, spec->match_value,
2711 				    misc_parameters_3);
2712 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
2713 	struct flow_dissector *dissector = rule->match.dissector;
2714 	enum fs_flow_table_type fs_type;
2715 	bool match_inner_ecn = true;
2716 	u16 addr_type = 0;
2717 	u8 ip_proto = 0;
2718 	u8 *match_level;
2719 	int err;
2720 
2721 	fs_type = mlx5e_is_eswitch_flow(flow) ? FS_FT_FDB : FS_FT_NIC_RX;
2722 	match_level = outer_match_level;
2723 
2724 	if (dissector->used_keys &
2725 	    ~(BIT_ULL(FLOW_DISSECTOR_KEY_META) |
2726 	      BIT_ULL(FLOW_DISSECTOR_KEY_CONTROL) |
2727 	      BIT_ULL(FLOW_DISSECTOR_KEY_BASIC) |
2728 	      BIT_ULL(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
2729 	      BIT_ULL(FLOW_DISSECTOR_KEY_VLAN) |
2730 	      BIT_ULL(FLOW_DISSECTOR_KEY_CVLAN) |
2731 	      BIT_ULL(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
2732 	      BIT_ULL(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
2733 	      BIT_ULL(FLOW_DISSECTOR_KEY_PORTS) |
2734 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_KEYID) |
2735 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV4_ADDRS) |
2736 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IPV6_ADDRS) |
2737 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_PORTS)	|
2738 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_CONTROL) |
2739 	      BIT_ULL(FLOW_DISSECTOR_KEY_TCP) |
2740 	      BIT_ULL(FLOW_DISSECTOR_KEY_IP)  |
2741 	      BIT_ULL(FLOW_DISSECTOR_KEY_CT) |
2742 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_IP) |
2743 	      BIT_ULL(FLOW_DISSECTOR_KEY_ENC_OPTS) |
2744 	      BIT_ULL(FLOW_DISSECTOR_KEY_ICMP) |
2745 	      BIT_ULL(FLOW_DISSECTOR_KEY_MPLS))) {
2746 		NL_SET_ERR_MSG_MOD(extack, "Unsupported key");
2747 		netdev_dbg(priv->netdev, "Unsupported key used: 0x%llx\n",
2748 			   dissector->used_keys);
2749 		return -EOPNOTSUPP;
2750 	}
2751 
2752 	if (mlx5e_get_tc_tun(filter_dev)) {
2753 		bool match_inner = false;
2754 
2755 		err = parse_tunnel_attr(priv, flow, spec, f, filter_dev,
2756 					outer_match_level, &match_inner);
2757 		if (err)
2758 			return err;
2759 
2760 		if (match_inner) {
2761 			/* header pointers should point to the inner headers
2762 			 * if the packet was decapsulated already.
2763 			 * outer headers are set by parse_tunnel_attr.
2764 			 */
2765 			match_level = inner_match_level;
2766 			headers_c = get_match_inner_headers_criteria(spec);
2767 			headers_v = get_match_inner_headers_value(spec);
2768 		}
2769 
2770 		err = mlx5e_tc_verify_tunnel_ecn(priv, f, &match_inner_ecn);
2771 		if (err)
2772 			return err;
2773 	}
2774 
2775 	err = mlx5e_flower_parse_meta(filter_dev, f);
2776 	if (err)
2777 		return err;
2778 
2779 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC) &&
2780 	    !skip_key_basic(filter_dev, f)) {
2781 		struct flow_match_basic match;
2782 
2783 		flow_rule_match_basic(rule, &match);
2784 		mlx5e_tc_set_ethertype(priv->mdev, &match,
2785 				       match_level == outer_match_level,
2786 				       headers_c, headers_v);
2787 
2788 		if (match.mask->n_proto)
2789 			*match_level = MLX5_MATCH_L2;
2790 	}
2791 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_VLAN) ||
2792 	    is_vlan_dev(filter_dev)) {
2793 		struct flow_dissector_key_vlan filter_dev_mask;
2794 		struct flow_dissector_key_vlan filter_dev_key;
2795 		struct flow_match_vlan match;
2796 
2797 		if (is_vlan_dev(filter_dev)) {
2798 			match.key = &filter_dev_key;
2799 			match.key->vlan_id = vlan_dev_vlan_id(filter_dev);
2800 			match.key->vlan_tpid = vlan_dev_vlan_proto(filter_dev);
2801 			match.key->vlan_priority = 0;
2802 			match.mask = &filter_dev_mask;
2803 			memset(match.mask, 0xff, sizeof(*match.mask));
2804 			match.mask->vlan_priority = 0;
2805 		} else {
2806 			flow_rule_match_vlan(rule, &match);
2807 		}
2808 		if (match.mask->vlan_id ||
2809 		    match.mask->vlan_priority ||
2810 		    match.mask->vlan_tpid) {
2811 			if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2812 				MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2813 					 svlan_tag, 1);
2814 				MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2815 					 svlan_tag, 1);
2816 			} else {
2817 				MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2818 					 cvlan_tag, 1);
2819 				MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2820 					 cvlan_tag, 1);
2821 			}
2822 
2823 			MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_vid,
2824 				 match.mask->vlan_id);
2825 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_vid,
2826 				 match.key->vlan_id);
2827 
2828 			MLX5_SET(fte_match_set_lyr_2_4, headers_c, first_prio,
2829 				 match.mask->vlan_priority);
2830 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, first_prio,
2831 				 match.key->vlan_priority);
2832 
2833 			*match_level = MLX5_MATCH_L2;
2834 
2835 			if (!flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN) &&
2836 			    match.mask->vlan_eth_type &&
2837 			    MLX5_CAP_FLOWTABLE_TYPE(priv->mdev,
2838 						    ft_field_support.outer_second_vid,
2839 						    fs_type)) {
2840 				MLX5_SET(fte_match_set_misc, misc_c,
2841 					 outer_second_cvlan_tag, 1);
2842 				spec->match_criteria_enable |=
2843 					MLX5_MATCH_MISC_PARAMETERS;
2844 			}
2845 		}
2846 	} else if (*match_level != MLX5_MATCH_NONE) {
2847 		/* cvlan_tag enabled in match criteria and
2848 		 * disabled in match value means both S & C tags
2849 		 * don't exist (untagged of both)
2850 		 */
2851 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, cvlan_tag, 1);
2852 		*match_level = MLX5_MATCH_L2;
2853 	}
2854 
2855 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CVLAN)) {
2856 		struct flow_match_vlan match;
2857 
2858 		flow_rule_match_cvlan(rule, &match);
2859 		if (match.mask->vlan_id ||
2860 		    match.mask->vlan_priority ||
2861 		    match.mask->vlan_tpid) {
2862 			if (!MLX5_CAP_FLOWTABLE_TYPE(priv->mdev, ft_field_support.outer_second_vid,
2863 						     fs_type)) {
2864 				NL_SET_ERR_MSG_MOD(extack,
2865 						   "Matching on CVLAN is not supported");
2866 				return -EOPNOTSUPP;
2867 			}
2868 
2869 			if (match.key->vlan_tpid == htons(ETH_P_8021AD)) {
2870 				MLX5_SET(fte_match_set_misc, misc_c,
2871 					 outer_second_svlan_tag, 1);
2872 				MLX5_SET(fte_match_set_misc, misc_v,
2873 					 outer_second_svlan_tag, 1);
2874 			} else {
2875 				MLX5_SET(fte_match_set_misc, misc_c,
2876 					 outer_second_cvlan_tag, 1);
2877 				MLX5_SET(fte_match_set_misc, misc_v,
2878 					 outer_second_cvlan_tag, 1);
2879 			}
2880 
2881 			MLX5_SET(fte_match_set_misc, misc_c, outer_second_vid,
2882 				 match.mask->vlan_id);
2883 			MLX5_SET(fte_match_set_misc, misc_v, outer_second_vid,
2884 				 match.key->vlan_id);
2885 			MLX5_SET(fte_match_set_misc, misc_c, outer_second_prio,
2886 				 match.mask->vlan_priority);
2887 			MLX5_SET(fte_match_set_misc, misc_v, outer_second_prio,
2888 				 match.key->vlan_priority);
2889 
2890 			*match_level = MLX5_MATCH_L2;
2891 			spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS;
2892 		}
2893 	}
2894 
2895 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
2896 		struct flow_match_eth_addrs match;
2897 
2898 		flow_rule_match_eth_addrs(rule, &match);
2899 		ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2900 					     dmac_47_16),
2901 				match.mask->dst);
2902 		ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2903 					     dmac_47_16),
2904 				match.key->dst);
2905 
2906 		ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2907 					     smac_47_16),
2908 				match.mask->src);
2909 		ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2910 					     smac_47_16),
2911 				match.key->src);
2912 
2913 		if (!is_zero_ether_addr(match.mask->src) ||
2914 		    !is_zero_ether_addr(match.mask->dst))
2915 			*match_level = MLX5_MATCH_L2;
2916 	}
2917 
2918 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_CONTROL)) {
2919 		struct flow_match_control match;
2920 
2921 		flow_rule_match_control(rule, &match);
2922 		addr_type = match.key->addr_type;
2923 
2924 		if (match.mask->flags & FLOW_DIS_IS_FRAGMENT) {
2925 			MLX5_SET(fte_match_set_lyr_2_4, headers_c, frag, 1);
2926 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, frag,
2927 				 match.key->flags & FLOW_DIS_IS_FRAGMENT);
2928 
2929 			/* the HW doesn't need L3 inline to match on frag=no */
2930 			if (!(match.key->flags & FLOW_DIS_IS_FRAGMENT))
2931 				*match_level = MLX5_MATCH_L2;
2932 	/* ***  L2 attributes parsing up to here *** */
2933 			else
2934 				*match_level = MLX5_MATCH_L3;
2935 		}
2936 
2937 		if (!flow_rule_is_supp_control_flags(FLOW_DIS_IS_FRAGMENT,
2938 						     match.mask->flags, extack))
2939 			return -EOPNOTSUPP;
2940 	}
2941 
2942 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_BASIC)) {
2943 		struct flow_match_basic match;
2944 
2945 		flow_rule_match_basic(rule, &match);
2946 		ip_proto = match.key->ip_proto;
2947 
2948 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2949 			 match.mask->ip_proto);
2950 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2951 			 match.key->ip_proto);
2952 
2953 		if (match.mask->ip_proto)
2954 			*match_level = MLX5_MATCH_L3;
2955 	}
2956 
2957 	if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
2958 		struct flow_match_ipv4_addrs match;
2959 
2960 		flow_rule_match_ipv4_addrs(rule, &match);
2961 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2962 				    src_ipv4_src_ipv6.ipv4_layout.ipv4),
2963 		       &match.mask->src, sizeof(match.mask->src));
2964 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2965 				    src_ipv4_src_ipv6.ipv4_layout.ipv4),
2966 		       &match.key->src, sizeof(match.key->src));
2967 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2968 				    dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2969 		       &match.mask->dst, sizeof(match.mask->dst));
2970 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2971 				    dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2972 		       &match.key->dst, sizeof(match.key->dst));
2973 
2974 		if (match.mask->src || match.mask->dst)
2975 			*match_level = MLX5_MATCH_L3;
2976 	}
2977 
2978 	if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
2979 		struct flow_match_ipv6_addrs match;
2980 
2981 		flow_rule_match_ipv6_addrs(rule, &match);
2982 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2983 				    src_ipv4_src_ipv6.ipv6_layout.ipv6),
2984 		       &match.mask->src, sizeof(match.mask->src));
2985 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2986 				    src_ipv4_src_ipv6.ipv6_layout.ipv6),
2987 		       &match.key->src, sizeof(match.key->src));
2988 
2989 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2990 				    dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2991 		       &match.mask->dst, sizeof(match.mask->dst));
2992 		memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2993 				    dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2994 		       &match.key->dst, sizeof(match.key->dst));
2995 
2996 		if (ipv6_addr_type(&match.mask->src) != IPV6_ADDR_ANY ||
2997 		    ipv6_addr_type(&match.mask->dst) != IPV6_ADDR_ANY)
2998 			*match_level = MLX5_MATCH_L3;
2999 	}
3000 
3001 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_IP)) {
3002 		struct flow_match_ip match;
3003 
3004 		flow_rule_match_ip(rule, &match);
3005 		if (match_inner_ecn) {
3006 			MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_ecn,
3007 				 match.mask->tos & 0x3);
3008 			MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_ecn,
3009 				 match.key->tos & 0x3);
3010 		}
3011 
3012 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_dscp,
3013 			 match.mask->tos >> 2);
3014 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_dscp,
3015 			 match.key->tos  >> 2);
3016 
3017 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, ttl_hoplimit,
3018 			 match.mask->ttl);
3019 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, ttl_hoplimit,
3020 			 match.key->ttl);
3021 
3022 		if (match.mask->ttl &&
3023 		    !MLX5_CAP_ESW_FLOWTABLE_FDB(priv->mdev,
3024 						ft_field_support.outer_ipv4_ttl)) {
3025 			NL_SET_ERR_MSG_MOD(extack,
3026 					   "Matching on TTL is not supported");
3027 			return -EOPNOTSUPP;
3028 		}
3029 
3030 		if (match.mask->tos || match.mask->ttl)
3031 			*match_level = MLX5_MATCH_L3;
3032 	}
3033 
3034 	/* ***  L3 attributes parsing up to here *** */
3035 
3036 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_PORTS)) {
3037 		struct flow_match_ports match;
3038 
3039 		flow_rule_match_ports(rule, &match);
3040 		switch (ip_proto) {
3041 		case IPPROTO_TCP:
3042 			MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3043 				 tcp_sport, ntohs(match.mask->src));
3044 			MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3045 				 tcp_sport, ntohs(match.key->src));
3046 
3047 			MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3048 				 tcp_dport, ntohs(match.mask->dst));
3049 			MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3050 				 tcp_dport, ntohs(match.key->dst));
3051 			break;
3052 
3053 		case IPPROTO_UDP:
3054 			MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3055 				 udp_sport, ntohs(match.mask->src));
3056 			MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3057 				 udp_sport, ntohs(match.key->src));
3058 
3059 			MLX5_SET(fte_match_set_lyr_2_4, headers_c,
3060 				 udp_dport, ntohs(match.mask->dst));
3061 			MLX5_SET(fte_match_set_lyr_2_4, headers_v,
3062 				 udp_dport, ntohs(match.key->dst));
3063 			break;
3064 		default:
3065 			NL_SET_ERR_MSG_MOD(extack,
3066 					   "Only UDP and TCP transports are supported for L4 matching");
3067 			netdev_err(priv->netdev,
3068 				   "Only UDP and TCP transport are supported\n");
3069 			return -EINVAL;
3070 		}
3071 
3072 		if (match.mask->src || match.mask->dst)
3073 			*match_level = MLX5_MATCH_L4;
3074 	}
3075 
3076 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_TCP)) {
3077 		struct flow_match_tcp match;
3078 
3079 		flow_rule_match_tcp(rule, &match);
3080 		MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_flags,
3081 			 ntohs(match.mask->flags));
3082 		MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_flags,
3083 			 ntohs(match.key->flags));
3084 
3085 		if (match.mask->flags)
3086 			*match_level = MLX5_MATCH_L4;
3087 	}
3088 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_ICMP)) {
3089 		struct flow_match_icmp match;
3090 
3091 		flow_rule_match_icmp(rule, &match);
3092 		switch (ip_proto) {
3093 		case IPPROTO_ICMP:
3094 			if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3095 			      MLX5_FLEX_PROTO_ICMP)) {
3096 				NL_SET_ERR_MSG_MOD(extack,
3097 						   "Match on Flex protocols for ICMP is not supported");
3098 				return -EOPNOTSUPP;
3099 			}
3100 			MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_type,
3101 				 match.mask->type);
3102 			MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_type,
3103 				 match.key->type);
3104 			MLX5_SET(fte_match_set_misc3, misc_c_3, icmp_code,
3105 				 match.mask->code);
3106 			MLX5_SET(fte_match_set_misc3, misc_v_3, icmp_code,
3107 				 match.key->code);
3108 			break;
3109 		case IPPROTO_ICMPV6:
3110 			if (!(MLX5_CAP_GEN(priv->mdev, flex_parser_protocols) &
3111 			      MLX5_FLEX_PROTO_ICMPV6)) {
3112 				NL_SET_ERR_MSG_MOD(extack,
3113 						   "Match on Flex protocols for ICMPV6 is not supported");
3114 				return -EOPNOTSUPP;
3115 			}
3116 			MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_type,
3117 				 match.mask->type);
3118 			MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_type,
3119 				 match.key->type);
3120 			MLX5_SET(fte_match_set_misc3, misc_c_3, icmpv6_code,
3121 				 match.mask->code);
3122 			MLX5_SET(fte_match_set_misc3, misc_v_3, icmpv6_code,
3123 				 match.key->code);
3124 			break;
3125 		default:
3126 			NL_SET_ERR_MSG_MOD(extack,
3127 					   "Code and type matching only with ICMP and ICMPv6");
3128 			netdev_err(priv->netdev,
3129 				   "Code and type matching only with ICMP and ICMPv6\n");
3130 			return -EINVAL;
3131 		}
3132 		if (match.mask->code || match.mask->type) {
3133 			*match_level = MLX5_MATCH_L4;
3134 			spec->match_criteria_enable |= MLX5_MATCH_MISC_PARAMETERS_3;
3135 		}
3136 	}
3137 	/* Currently supported only for MPLS over UDP */
3138 	if (flow_rule_match_key(rule, FLOW_DISSECTOR_KEY_MPLS) &&
3139 	    !netif_is_bareudp(filter_dev)) {
3140 		NL_SET_ERR_MSG_MOD(extack,
3141 				   "Matching on MPLS is supported only for MPLS over UDP");
3142 		netdev_err(priv->netdev,
3143 			   "Matching on MPLS is supported only for MPLS over UDP\n");
3144 		return -EOPNOTSUPP;
3145 	}
3146 
3147 	return 0;
3148 }
3149 
parse_cls_flower(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_spec * spec,struct flow_cls_offload * f,struct net_device * filter_dev)3150 static int parse_cls_flower(struct mlx5e_priv *priv,
3151 			    struct mlx5e_tc_flow *flow,
3152 			    struct mlx5_flow_spec *spec,
3153 			    struct flow_cls_offload *f,
3154 			    struct net_device *filter_dev)
3155 {
3156 	u8 inner_match_level, outer_match_level, non_tunnel_match_level;
3157 	struct netlink_ext_ack *extack = f->common.extack;
3158 	struct mlx5_core_dev *dev = priv->mdev;
3159 	struct mlx5_eswitch *esw = dev->priv.eswitch;
3160 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
3161 	struct mlx5_eswitch_rep *rep;
3162 	bool is_eswitch_flow;
3163 	int err;
3164 
3165 	inner_match_level = MLX5_MATCH_NONE;
3166 	outer_match_level = MLX5_MATCH_NONE;
3167 
3168 	err = __parse_cls_flower(priv, flow, spec, f, filter_dev,
3169 				 &inner_match_level, &outer_match_level);
3170 	non_tunnel_match_level = (inner_match_level == MLX5_MATCH_NONE) ?
3171 				 outer_match_level : inner_match_level;
3172 
3173 	is_eswitch_flow = mlx5e_is_eswitch_flow(flow);
3174 	if (!err && is_eswitch_flow) {
3175 		rep = rpriv->rep;
3176 		if (rep->vport != MLX5_VPORT_UPLINK &&
3177 		    (esw->offloads.inline_mode != MLX5_INLINE_MODE_NONE &&
3178 		    esw->offloads.inline_mode < non_tunnel_match_level)) {
3179 			NL_SET_ERR_MSG_MOD(extack,
3180 					   "Flow is not offloaded due to min inline setting");
3181 			netdev_warn(priv->netdev,
3182 				    "Flow is not offloaded due to min inline setting, required %d actual %d\n",
3183 				    non_tunnel_match_level, esw->offloads.inline_mode);
3184 			return -EOPNOTSUPP;
3185 		}
3186 	}
3187 
3188 	flow->attr->inner_match_level = inner_match_level;
3189 	flow->attr->outer_match_level = outer_match_level;
3190 
3191 
3192 	return err;
3193 }
3194 
3195 struct mlx5_fields {
3196 	u8  field;
3197 	u8  field_bsize;
3198 	u32 field_mask;
3199 	u32 offset;
3200 	u32 match_offset;
3201 };
3202 
3203 #define OFFLOAD(fw_field, field_bsize, field_mask, field, off, match_field) \
3204 		{MLX5_ACTION_IN_FIELD_OUT_ ## fw_field, field_bsize, field_mask, \
3205 		 offsetof(struct pedit_headers, field) + (off), \
3206 		 MLX5_BYTE_OFF(fte_match_set_lyr_2_4, match_field)}
3207 
3208 /* masked values are the same and there are no rewrites that do not have a
3209  * match.
3210  */
3211 #define SAME_VAL_MASK(type, valp, maskp, matchvalp, matchmaskp) ({ \
3212 	type matchmaskx = *(type *)(matchmaskp); \
3213 	type matchvalx = *(type *)(matchvalp); \
3214 	type maskx = *(type *)(maskp); \
3215 	type valx = *(type *)(valp); \
3216 	\
3217 	(valx & maskx) == (matchvalx & matchmaskx) && !(maskx & (maskx ^ \
3218 								 matchmaskx)); \
3219 })
3220 
cmp_val_mask(void * valp,void * maskp,void * matchvalp,void * matchmaskp,u8 bsize)3221 static bool cmp_val_mask(void *valp, void *maskp, void *matchvalp,
3222 			 void *matchmaskp, u8 bsize)
3223 {
3224 	bool same = false;
3225 
3226 	switch (bsize) {
3227 	case 8:
3228 		same = SAME_VAL_MASK(u8, valp, maskp, matchvalp, matchmaskp);
3229 		break;
3230 	case 16:
3231 		same = SAME_VAL_MASK(u16, valp, maskp, matchvalp, matchmaskp);
3232 		break;
3233 	case 32:
3234 		same = SAME_VAL_MASK(u32, valp, maskp, matchvalp, matchmaskp);
3235 		break;
3236 	}
3237 
3238 	return same;
3239 }
3240 
3241 static struct mlx5_fields fields[] = {
3242 	OFFLOAD(DMAC_47_16, 32, U32_MAX, eth.h_dest[0], 0, dmac_47_16),
3243 	OFFLOAD(DMAC_15_0,  16, U16_MAX, eth.h_dest[4], 0, dmac_15_0),
3244 	OFFLOAD(SMAC_47_16, 32, U32_MAX, eth.h_source[0], 0, smac_47_16),
3245 	OFFLOAD(SMAC_15_0,  16, U16_MAX, eth.h_source[4], 0, smac_15_0),
3246 	OFFLOAD(ETHERTYPE,  16, U16_MAX, eth.h_proto, 0, ethertype),
3247 	OFFLOAD(FIRST_VID,  16, U16_MAX, vlan.h_vlan_TCI, 0, first_vid),
3248 
3249 	OFFLOAD(IP_DSCP, 8,    0xfc, ip4.tos,   0, ip_dscp),
3250 	OFFLOAD(IP_TTL,  8,  U8_MAX, ip4.ttl,   0, ttl_hoplimit),
3251 	OFFLOAD(SIPV4,  32, U32_MAX, ip4.saddr, 0, src_ipv4_src_ipv6.ipv4_layout.ipv4),
3252 	OFFLOAD(DIPV4,  32, U32_MAX, ip4.daddr, 0, dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
3253 
3254 	OFFLOAD(SIPV6_127_96, 32, U32_MAX, ip6.saddr.s6_addr32[0], 0,
3255 		src_ipv4_src_ipv6.ipv6_layout.ipv6[0]),
3256 	OFFLOAD(SIPV6_95_64,  32, U32_MAX, ip6.saddr.s6_addr32[1], 0,
3257 		src_ipv4_src_ipv6.ipv6_layout.ipv6[4]),
3258 	OFFLOAD(SIPV6_63_32,  32, U32_MAX, ip6.saddr.s6_addr32[2], 0,
3259 		src_ipv4_src_ipv6.ipv6_layout.ipv6[8]),
3260 	OFFLOAD(SIPV6_31_0,   32, U32_MAX, ip6.saddr.s6_addr32[3], 0,
3261 		src_ipv4_src_ipv6.ipv6_layout.ipv6[12]),
3262 	OFFLOAD(DIPV6_127_96, 32, U32_MAX, ip6.daddr.s6_addr32[0], 0,
3263 		dst_ipv4_dst_ipv6.ipv6_layout.ipv6[0]),
3264 	OFFLOAD(DIPV6_95_64,  32, U32_MAX, ip6.daddr.s6_addr32[1], 0,
3265 		dst_ipv4_dst_ipv6.ipv6_layout.ipv6[4]),
3266 	OFFLOAD(DIPV6_63_32,  32, U32_MAX, ip6.daddr.s6_addr32[2], 0,
3267 		dst_ipv4_dst_ipv6.ipv6_layout.ipv6[8]),
3268 	OFFLOAD(DIPV6_31_0,   32, U32_MAX, ip6.daddr.s6_addr32[3], 0,
3269 		dst_ipv4_dst_ipv6.ipv6_layout.ipv6[12]),
3270 	OFFLOAD(IPV6_HOPLIMIT, 8,  U8_MAX, ip6.hop_limit, 0, ttl_hoplimit),
3271 	OFFLOAD(IP_DSCP, 16,  0x0fc0, ip6, 0, ip_dscp),
3272 
3273 	OFFLOAD(TCP_SPORT, 16, U16_MAX, tcp.source,  0, tcp_sport),
3274 	OFFLOAD(TCP_DPORT, 16, U16_MAX, tcp.dest,    0, tcp_dport),
3275 	/* in linux iphdr tcp_flags is 8 bits long */
3276 	OFFLOAD(TCP_FLAGS,  8,  U8_MAX, tcp.ack_seq, 5, tcp_flags),
3277 
3278 	OFFLOAD(UDP_SPORT, 16, U16_MAX, udp.source, 0, udp_sport),
3279 	OFFLOAD(UDP_DPORT, 16, U16_MAX, udp.dest,   0, udp_dport),
3280 };
3281 
mask_field_get(void * mask,struct mlx5_fields * f)3282 static u32 mask_field_get(void *mask, struct mlx5_fields *f)
3283 {
3284 	switch (f->field_bsize) {
3285 	case 32:
3286 		return be32_to_cpu(*(__be32 *)mask) & f->field_mask;
3287 	case 16:
3288 		return be16_to_cpu(*(__be16 *)mask) & (u16)f->field_mask;
3289 	default:
3290 		return *(u8 *)mask & (u8)f->field_mask;
3291 	}
3292 }
3293 
mask_field_clear(void * mask,struct mlx5_fields * f)3294 static void mask_field_clear(void *mask, struct mlx5_fields *f)
3295 {
3296 	switch (f->field_bsize) {
3297 	case 32:
3298 		*(__be32 *)mask &= ~cpu_to_be32(f->field_mask);
3299 		break;
3300 	case 16:
3301 		*(__be16 *)mask &= ~cpu_to_be16((u16)f->field_mask);
3302 		break;
3303 	default:
3304 		*(u8 *)mask &= ~(u8)f->field_mask;
3305 		break;
3306 	}
3307 }
3308 
offload_pedit_fields(struct mlx5e_priv * priv,int namespace,struct mlx5e_tc_flow_parse_attr * parse_attr,u32 * action_flags,struct netlink_ext_ack * extack)3309 static int offload_pedit_fields(struct mlx5e_priv *priv,
3310 				int namespace,
3311 				struct mlx5e_tc_flow_parse_attr *parse_attr,
3312 				u32 *action_flags,
3313 				struct netlink_ext_ack *extack)
3314 {
3315 	struct pedit_headers *set_masks, *add_masks, *set_vals, *add_vals;
3316 	struct pedit_headers_action *hdrs = parse_attr->hdrs;
3317 	void *headers_c, *headers_v, *action, *vals_p;
3318 	struct mlx5e_tc_mod_hdr_acts *mod_acts;
3319 	void *s_masks_p, *a_masks_p;
3320 	int i, first, last, next_z;
3321 	struct mlx5_fields *f;
3322 	unsigned long mask;
3323 	u32 s_mask, a_mask;
3324 	u8 cmd;
3325 
3326 	mod_acts = &parse_attr->mod_hdr_acts;
3327 	headers_c = mlx5e_get_match_headers_criteria(*action_flags, &parse_attr->spec);
3328 	headers_v = mlx5e_get_match_headers_value(*action_flags, &parse_attr->spec);
3329 
3330 	set_masks = &hdrs[TCA_PEDIT_KEY_EX_CMD_SET].masks;
3331 	add_masks = &hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].masks;
3332 	set_vals = &hdrs[TCA_PEDIT_KEY_EX_CMD_SET].vals;
3333 	add_vals = &hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].vals;
3334 
3335 	for (i = 0; i < ARRAY_SIZE(fields); i++) {
3336 		bool skip;
3337 
3338 		f = &fields[i];
3339 		s_masks_p = (void *)set_masks + f->offset;
3340 		a_masks_p = (void *)add_masks + f->offset;
3341 
3342 		s_mask = mask_field_get(s_masks_p, f);
3343 		a_mask = mask_field_get(a_masks_p, f);
3344 
3345 		if (!s_mask && !a_mask) /* nothing to offload here */
3346 			continue;
3347 
3348 		if (s_mask && a_mask) {
3349 			NL_SET_ERR_MSG_MOD(extack,
3350 					   "can't set and add to the same HW field");
3351 			netdev_warn(priv->netdev,
3352 				    "mlx5: can't set and add to the same HW field (%x)\n",
3353 				    f->field);
3354 			return -EOPNOTSUPP;
3355 		}
3356 
3357 		skip = false;
3358 		if (s_mask) {
3359 			void *match_mask = headers_c + f->match_offset;
3360 			void *match_val = headers_v + f->match_offset;
3361 
3362 			cmd  = MLX5_ACTION_TYPE_SET;
3363 			mask = s_mask;
3364 			vals_p = (void *)set_vals + f->offset;
3365 			/* don't rewrite if we have a match on the same value */
3366 			if (cmp_val_mask(vals_p, s_masks_p, match_val,
3367 					 match_mask, f->field_bsize))
3368 				skip = true;
3369 			/* clear to denote we consumed this field */
3370 			mask_field_clear(s_masks_p, f);
3371 		} else {
3372 			cmd  = MLX5_ACTION_TYPE_ADD;
3373 			mask = a_mask;
3374 			vals_p = (void *)add_vals + f->offset;
3375 			/* add 0 is no change */
3376 			if (!mask_field_get(vals_p, f))
3377 				skip = true;
3378 			/* clear to denote we consumed this field */
3379 			mask_field_clear(a_masks_p, f);
3380 		}
3381 		if (skip)
3382 			continue;
3383 
3384 		first = find_first_bit(&mask, f->field_bsize);
3385 		next_z = find_next_zero_bit(&mask, f->field_bsize, first);
3386 		last  = find_last_bit(&mask, f->field_bsize);
3387 		if (first < next_z && next_z < last) {
3388 			NL_SET_ERR_MSG_MOD(extack,
3389 					   "rewrite of few sub-fields isn't supported");
3390 			netdev_warn(priv->netdev,
3391 				    "mlx5: rewrite of few sub-fields (mask %lx) isn't offloaded\n",
3392 				    mask);
3393 			return -EOPNOTSUPP;
3394 		}
3395 
3396 		action = mlx5e_mod_hdr_alloc(priv->mdev, namespace, mod_acts);
3397 		if (IS_ERR(action)) {
3398 			NL_SET_ERR_MSG_MOD(extack,
3399 					   "too many pedit actions, can't offload");
3400 			mlx5_core_warn(priv->mdev,
3401 				       "mlx5: parsed %d pedit actions, can't do more\n",
3402 				       mod_acts->num_actions);
3403 			return PTR_ERR(action);
3404 		}
3405 
3406 		MLX5_SET(set_action_in, action, action_type, cmd);
3407 		MLX5_SET(set_action_in, action, field, f->field);
3408 
3409 		if (cmd == MLX5_ACTION_TYPE_SET) {
3410 			unsigned long field_mask = f->field_mask;
3411 			int start;
3412 
3413 			/* if field is bit sized it can start not from first bit */
3414 			start = find_first_bit(&field_mask, f->field_bsize);
3415 
3416 			MLX5_SET(set_action_in, action, offset, first - start);
3417 			/* length is num of bits to be written, zero means length of 32 */
3418 			MLX5_SET(set_action_in, action, length, (last - first + 1));
3419 		}
3420 
3421 		if (f->field_bsize == 32)
3422 			MLX5_SET(set_action_in, action, data, ntohl(*(__be32 *)vals_p) >> first);
3423 		else if (f->field_bsize == 16)
3424 			MLX5_SET(set_action_in, action, data, ntohs(*(__be16 *)vals_p) >> first);
3425 		else if (f->field_bsize == 8)
3426 			MLX5_SET(set_action_in, action, data, *(u8 *)vals_p >> first);
3427 
3428 		++mod_acts->num_actions;
3429 	}
3430 
3431 	return 0;
3432 }
3433 
3434 static const struct pedit_headers zero_masks = {};
3435 
verify_offload_pedit_fields(struct mlx5e_priv * priv,struct mlx5e_tc_flow_parse_attr * parse_attr,struct netlink_ext_ack * extack)3436 static int verify_offload_pedit_fields(struct mlx5e_priv *priv,
3437 				       struct mlx5e_tc_flow_parse_attr *parse_attr,
3438 				       struct netlink_ext_ack *extack)
3439 {
3440 	struct pedit_headers *cmd_masks;
3441 	u8 cmd;
3442 
3443 	for (cmd = 0; cmd < __PEDIT_CMD_MAX; cmd++) {
3444 		cmd_masks = &parse_attr->hdrs[cmd].masks;
3445 		if (memcmp(cmd_masks, &zero_masks, sizeof(zero_masks))) {
3446 			NL_SET_ERR_MSG_MOD(extack, "attempt to offload an unsupported field");
3447 			netdev_warn(priv->netdev, "attempt to offload an unsupported field (cmd %d)\n", cmd);
3448 			print_hex_dump(KERN_WARNING, "mask: ", DUMP_PREFIX_ADDRESS,
3449 				       16, 1, cmd_masks, sizeof(zero_masks), true);
3450 			return -EOPNOTSUPP;
3451 		}
3452 	}
3453 
3454 	return 0;
3455 }
3456 
alloc_tc_pedit_action(struct mlx5e_priv * priv,int namespace,struct mlx5e_tc_flow_parse_attr * parse_attr,u32 * action_flags,struct netlink_ext_ack * extack)3457 static int alloc_tc_pedit_action(struct mlx5e_priv *priv, int namespace,
3458 				 struct mlx5e_tc_flow_parse_attr *parse_attr,
3459 				 u32 *action_flags,
3460 				 struct netlink_ext_ack *extack)
3461 {
3462 	int err;
3463 
3464 	err = offload_pedit_fields(priv, namespace, parse_attr, action_flags, extack);
3465 	if (err)
3466 		goto out_dealloc_parsed_actions;
3467 
3468 	err = verify_offload_pedit_fields(priv, parse_attr, extack);
3469 	if (err)
3470 		goto out_dealloc_parsed_actions;
3471 
3472 	return 0;
3473 
3474 out_dealloc_parsed_actions:
3475 	mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3476 	return err;
3477 }
3478 
3479 struct ip_ttl_word {
3480 	__u8	ttl;
3481 	__u8	protocol;
3482 	__sum16	check;
3483 };
3484 
3485 struct ipv6_hoplimit_word {
3486 	__be16	payload_len;
3487 	__u8	nexthdr;
3488 	__u8	hop_limit;
3489 };
3490 
3491 static bool
is_flow_action_modify_ip_header(struct flow_action * flow_action)3492 is_flow_action_modify_ip_header(struct flow_action *flow_action)
3493 {
3494 	const struct flow_action_entry *act;
3495 	u32 mask, offset;
3496 	u8 htype;
3497 	int i;
3498 
3499 	/* For IPv4 & IPv6 header check 4 byte word,
3500 	 * to determine that modified fields
3501 	 * are NOT ttl & hop_limit only.
3502 	 */
3503 	flow_action_for_each(i, act, flow_action) {
3504 		if (act->id != FLOW_ACTION_MANGLE &&
3505 		    act->id != FLOW_ACTION_ADD)
3506 			continue;
3507 
3508 		htype = act->mangle.htype;
3509 		offset = act->mangle.offset;
3510 		mask = ~act->mangle.mask;
3511 
3512 		if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP4) {
3513 			struct ip_ttl_word *ttl_word =
3514 				(struct ip_ttl_word *)&mask;
3515 
3516 			if (offset != offsetof(struct iphdr, ttl) ||
3517 			    ttl_word->protocol ||
3518 			    ttl_word->check)
3519 				return true;
3520 		} else if (htype == FLOW_ACT_MANGLE_HDR_TYPE_IP6) {
3521 			struct ipv6_hoplimit_word *hoplimit_word =
3522 				(struct ipv6_hoplimit_word *)&mask;
3523 
3524 			if (offset != offsetof(struct ipv6hdr, payload_len) ||
3525 			    hoplimit_word->payload_len ||
3526 			    hoplimit_word->nexthdr)
3527 				return true;
3528 		}
3529 	}
3530 
3531 	return false;
3532 }
3533 
modify_header_match_supported(struct mlx5e_priv * priv,struct mlx5_flow_spec * spec,struct flow_action * flow_action,u32 actions,struct netlink_ext_ack * extack)3534 static bool modify_header_match_supported(struct mlx5e_priv *priv,
3535 					  struct mlx5_flow_spec *spec,
3536 					  struct flow_action *flow_action,
3537 					  u32 actions,
3538 					  struct netlink_ext_ack *extack)
3539 {
3540 	bool modify_ip_header;
3541 	void *headers_c;
3542 	void *headers_v;
3543 	u16 ethertype;
3544 	u8 ip_proto;
3545 
3546 	headers_c = mlx5e_get_match_headers_criteria(actions, spec);
3547 	headers_v = mlx5e_get_match_headers_value(actions, spec);
3548 	ethertype = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ethertype);
3549 
3550 	/* for non-IP we only re-write MACs, so we're okay */
3551 	if (MLX5_GET(fte_match_set_lyr_2_4, headers_c, ip_version) == 0 &&
3552 	    ethertype != ETH_P_IP && ethertype != ETH_P_IPV6)
3553 		goto out_ok;
3554 
3555 	modify_ip_header = is_flow_action_modify_ip_header(flow_action);
3556 	ip_proto = MLX5_GET(fte_match_set_lyr_2_4, headers_v, ip_protocol);
3557 	if (modify_ip_header && ip_proto != IPPROTO_TCP &&
3558 	    ip_proto != IPPROTO_UDP && ip_proto != IPPROTO_ICMP) {
3559 		NL_SET_ERR_MSG_MOD(extack,
3560 				   "can't offload re-write of non TCP/UDP");
3561 		netdev_info(priv->netdev, "can't offload re-write of ip proto %d\n",
3562 			    ip_proto);
3563 		return false;
3564 	}
3565 
3566 out_ok:
3567 	return true;
3568 }
3569 
3570 static bool
actions_match_supported_fdb(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3571 actions_match_supported_fdb(struct mlx5e_priv *priv,
3572 			    struct mlx5e_tc_flow *flow,
3573 			    struct netlink_ext_ack *extack)
3574 {
3575 	struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
3576 
3577 	if (esw_attr->split_count > 0 && !mlx5_esw_has_fwd_fdb(priv->mdev)) {
3578 		NL_SET_ERR_MSG_MOD(extack,
3579 				   "current firmware doesn't support split rule for port mirroring");
3580 		netdev_warn_once(priv->netdev,
3581 				 "current firmware doesn't support split rule for port mirroring\n");
3582 		return false;
3583 	}
3584 
3585 	return true;
3586 }
3587 
3588 static bool
actions_match_supported(struct mlx5e_priv * priv,struct flow_action * flow_action,u32 actions,struct mlx5e_tc_flow_parse_attr * parse_attr,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3589 actions_match_supported(struct mlx5e_priv *priv,
3590 			struct flow_action *flow_action,
3591 			u32 actions,
3592 			struct mlx5e_tc_flow_parse_attr *parse_attr,
3593 			struct mlx5e_tc_flow *flow,
3594 			struct netlink_ext_ack *extack)
3595 {
3596 	if (actions & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR &&
3597 	    !modify_header_match_supported(priv, &parse_attr->spec, flow_action, actions,
3598 					   extack))
3599 		return false;
3600 
3601 	if (mlx5e_is_eswitch_flow(flow) &&
3602 	    !actions_match_supported_fdb(priv, flow, extack))
3603 		return false;
3604 
3605 	return true;
3606 }
3607 
same_port_devs(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)3608 static bool same_port_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3609 {
3610 	return priv->mdev == peer_priv->mdev;
3611 }
3612 
mlx5e_same_hw_devs(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)3613 bool mlx5e_same_hw_devs(struct mlx5e_priv *priv, struct mlx5e_priv *peer_priv)
3614 {
3615 	struct mlx5_core_dev *fmdev, *pmdev;
3616 	u64 fsystem_guid, psystem_guid;
3617 
3618 	fmdev = priv->mdev;
3619 	pmdev = peer_priv->mdev;
3620 
3621 	fsystem_guid = mlx5_query_nic_system_image_guid(fmdev);
3622 	psystem_guid = mlx5_query_nic_system_image_guid(pmdev);
3623 
3624 	return (fsystem_guid == psystem_guid);
3625 }
3626 
3627 static int
actions_prepare_mod_hdr_actions(struct mlx5e_priv * priv,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct netlink_ext_ack * extack)3628 actions_prepare_mod_hdr_actions(struct mlx5e_priv *priv,
3629 				struct mlx5e_tc_flow *flow,
3630 				struct mlx5_flow_attr *attr,
3631 				struct netlink_ext_ack *extack)
3632 {
3633 	struct mlx5e_tc_flow_parse_attr *parse_attr = attr->parse_attr;
3634 	struct pedit_headers_action *hdrs = parse_attr->hdrs;
3635 	enum mlx5_flow_namespace_type ns_type;
3636 	int err;
3637 
3638 	if (!hdrs[TCA_PEDIT_KEY_EX_CMD_SET].pedits &&
3639 	    !hdrs[TCA_PEDIT_KEY_EX_CMD_ADD].pedits)
3640 		return 0;
3641 
3642 	ns_type = mlx5e_get_flow_namespace(flow);
3643 
3644 	err = alloc_tc_pedit_action(priv, ns_type, parse_attr, &attr->action, extack);
3645 	if (err)
3646 		return err;
3647 
3648 	if (parse_attr->mod_hdr_acts.num_actions > 0)
3649 		return 0;
3650 
3651 	/* In case all pedit actions are skipped, remove the MOD_HDR flag. */
3652 	attr->action &= ~MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
3653 	mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
3654 
3655 	if (ns_type != MLX5_FLOW_NAMESPACE_FDB)
3656 		return 0;
3657 
3658 	if (!((attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_POP) ||
3659 	      (attr->action & MLX5_FLOW_CONTEXT_ACTION_VLAN_PUSH)))
3660 		attr->esw_attr->split_count = 0;
3661 
3662 	return 0;
3663 }
3664 
3665 static struct mlx5_flow_attr*
mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr * attr,enum mlx5_flow_namespace_type ns_type)3666 mlx5e_clone_flow_attr_for_post_act(struct mlx5_flow_attr *attr,
3667 				   enum mlx5_flow_namespace_type ns_type)
3668 {
3669 	struct mlx5e_tc_flow_parse_attr *parse_attr;
3670 	u32 attr_sz = ns_to_attr_sz(ns_type);
3671 	struct mlx5_flow_attr *attr2;
3672 
3673 	attr2 = mlx5_alloc_flow_attr(ns_type);
3674 	parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
3675 	if (!attr2 || !parse_attr) {
3676 		kvfree(parse_attr);
3677 		kfree(attr2);
3678 		return NULL;
3679 	}
3680 
3681 	memcpy(attr2, attr, attr_sz);
3682 	INIT_LIST_HEAD(&attr2->list);
3683 	parse_attr->filter_dev = attr->parse_attr->filter_dev;
3684 	attr2->action = 0;
3685 	attr2->counter = NULL;
3686 	attr2->tc_act_cookies_count = 0;
3687 	attr2->flags = 0;
3688 	attr2->parse_attr = parse_attr;
3689 	attr2->dest_chain = 0;
3690 	attr2->dest_ft = NULL;
3691 	attr2->act_id_restore_rule = NULL;
3692 	memset(&attr2->ct_attr, 0, sizeof(attr2->ct_attr));
3693 
3694 	if (ns_type == MLX5_FLOW_NAMESPACE_FDB) {
3695 		attr2->esw_attr->out_count = 0;
3696 		attr2->esw_attr->split_count = 0;
3697 	}
3698 
3699 	attr2->branch_true = NULL;
3700 	attr2->branch_false = NULL;
3701 	attr2->jumping_attr = NULL;
3702 	return attr2;
3703 }
3704 
3705 struct mlx5_flow_attr *
mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow * flow)3706 mlx5e_tc_get_encap_attr(struct mlx5e_tc_flow *flow)
3707 {
3708 	struct mlx5_esw_flow_attr *esw_attr;
3709 	struct mlx5_flow_attr *attr;
3710 	int i;
3711 
3712 	list_for_each_entry(attr, &flow->attrs, list) {
3713 		esw_attr = attr->esw_attr;
3714 		for (i = 0; i < MLX5_MAX_FLOW_FWD_VPORTS; i++) {
3715 			if (esw_attr->dests[i].flags & MLX5_ESW_DEST_ENCAP)
3716 				return attr;
3717 		}
3718 	}
3719 
3720 	return NULL;
3721 }
3722 
3723 void
mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow * flow)3724 mlx5e_tc_unoffload_flow_post_acts(struct mlx5e_tc_flow *flow)
3725 {
3726 	struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3727 	struct mlx5_flow_attr *attr;
3728 
3729 	list_for_each_entry(attr, &flow->attrs, list) {
3730 		if (list_is_last(&attr->list, &flow->attrs))
3731 			break;
3732 
3733 		mlx5e_tc_post_act_unoffload(post_act, attr->post_act_handle);
3734 	}
3735 }
3736 
3737 static void
free_flow_post_acts(struct mlx5e_tc_flow * flow)3738 free_flow_post_acts(struct mlx5e_tc_flow *flow)
3739 {
3740 	struct mlx5_flow_attr *attr, *tmp;
3741 
3742 	list_for_each_entry_safe(attr, tmp, &flow->attrs, list) {
3743 		if (list_is_last(&attr->list, &flow->attrs))
3744 			break;
3745 
3746 		mlx5_free_flow_attr_actions(flow, attr);
3747 
3748 		list_del(&attr->list);
3749 		kvfree(attr->parse_attr);
3750 		kfree(attr);
3751 	}
3752 }
3753 
3754 int
mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow * flow)3755 mlx5e_tc_offload_flow_post_acts(struct mlx5e_tc_flow *flow)
3756 {
3757 	struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3758 	struct mlx5_flow_attr *attr;
3759 	int err = 0;
3760 
3761 	list_for_each_entry(attr, &flow->attrs, list) {
3762 		if (list_is_last(&attr->list, &flow->attrs))
3763 			break;
3764 
3765 		err = mlx5e_tc_post_act_offload(post_act, attr->post_act_handle);
3766 		if (err)
3767 			break;
3768 	}
3769 
3770 	return err;
3771 }
3772 
3773 /* TC filter rule HW translation:
3774  *
3775  * +---------------------+
3776  * + ft prio (tc chain)  +
3777  * + original match      +
3778  * +---------------------+
3779  *           |
3780  *           | if multi table action
3781  *           |
3782  *           v
3783  * +---------------------+
3784  * + post act ft         |<----.
3785  * + match fte id        |     | split on multi table action
3786  * + do actions          |-----'
3787  * +---------------------+
3788  *           |
3789  *           |
3790  *           v
3791  * Do rest of the actions after last multi table action.
3792  */
3793 static int
alloc_flow_post_acts(struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)3794 alloc_flow_post_acts(struct mlx5e_tc_flow *flow, struct netlink_ext_ack *extack)
3795 {
3796 	struct mlx5e_post_act *post_act = get_post_action(flow->priv);
3797 	struct mlx5_flow_attr *attr, *next_attr = NULL;
3798 	struct mlx5e_post_act_handle *handle;
3799 	int err;
3800 
3801 	/* This is going in reverse order as needed.
3802 	 * The first entry is the last attribute.
3803 	 */
3804 	list_for_each_entry(attr, &flow->attrs, list) {
3805 		if (!next_attr) {
3806 			/* Set counter action on last post act rule. */
3807 			attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3808 		}
3809 
3810 		if (next_attr && !(attr->flags & MLX5_ATTR_FLAG_TERMINATING)) {
3811 			err = mlx5e_tc_act_set_next_post_act(flow, attr, next_attr);
3812 			if (err)
3813 				goto out_free;
3814 		}
3815 
3816 		/* Don't add post_act rule for first attr (last in the list).
3817 		 * It's being handled by the caller.
3818 		 */
3819 		if (list_is_last(&attr->list, &flow->attrs))
3820 			break;
3821 
3822 		err = actions_prepare_mod_hdr_actions(flow->priv, flow, attr, extack);
3823 		if (err)
3824 			goto out_free;
3825 
3826 		err = post_process_attr(flow, attr, extack);
3827 		if (err)
3828 			goto out_free;
3829 
3830 		handle = mlx5e_tc_post_act_add(post_act, attr);
3831 		if (IS_ERR(handle)) {
3832 			err = PTR_ERR(handle);
3833 			goto out_free;
3834 		}
3835 
3836 		attr->post_act_handle = handle;
3837 
3838 		if (attr->jumping_attr) {
3839 			err = mlx5e_tc_act_set_next_post_act(flow, attr->jumping_attr, attr);
3840 			if (err)
3841 				goto out_free;
3842 		}
3843 
3844 		next_attr = attr;
3845 	}
3846 
3847 	if (flow_flag_test(flow, SLOW))
3848 		goto out;
3849 
3850 	err = mlx5e_tc_offload_flow_post_acts(flow);
3851 	if (err)
3852 		goto out_free;
3853 
3854 out:
3855 	return 0;
3856 
3857 out_free:
3858 	free_flow_post_acts(flow);
3859 	return err;
3860 }
3861 
3862 static int
set_branch_dest_ft(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr)3863 set_branch_dest_ft(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr)
3864 {
3865 	struct mlx5e_post_act *post_act = get_post_action(priv);
3866 
3867 	if (IS_ERR(post_act))
3868 		return PTR_ERR(post_act);
3869 
3870 	attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3871 	attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3872 
3873 	return 0;
3874 }
3875 
3876 static int
alloc_branch_attr(struct mlx5e_tc_flow * flow,struct mlx5e_tc_act_branch_ctrl * cond,struct mlx5_flow_attr ** cond_attr,u32 * jump_count,struct netlink_ext_ack * extack)3877 alloc_branch_attr(struct mlx5e_tc_flow *flow,
3878 		  struct mlx5e_tc_act_branch_ctrl *cond,
3879 		  struct mlx5_flow_attr **cond_attr,
3880 		  u32 *jump_count,
3881 		  struct netlink_ext_ack *extack)
3882 {
3883 	struct mlx5_flow_attr *attr;
3884 	int err = 0;
3885 
3886 	*cond_attr = mlx5e_clone_flow_attr_for_post_act(flow->attr,
3887 							mlx5e_get_flow_namespace(flow));
3888 	if (!(*cond_attr))
3889 		return -ENOMEM;
3890 
3891 	attr = *cond_attr;
3892 
3893 	switch (cond->act_id) {
3894 	case FLOW_ACTION_DROP:
3895 		attr->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
3896 		break;
3897 	case FLOW_ACTION_ACCEPT:
3898 	case FLOW_ACTION_PIPE:
3899 		err = set_branch_dest_ft(flow->priv, attr);
3900 		if (err)
3901 			goto out_err;
3902 		break;
3903 	case FLOW_ACTION_JUMP:
3904 		if (*jump_count) {
3905 			NL_SET_ERR_MSG_MOD(extack, "Cannot offload flows with nested jumps");
3906 			err = -EOPNOTSUPP;
3907 			goto out_err;
3908 		}
3909 		*jump_count = cond->extval;
3910 		err = set_branch_dest_ft(flow->priv, attr);
3911 		if (err)
3912 			goto out_err;
3913 		break;
3914 	default:
3915 		err = -EOPNOTSUPP;
3916 		goto out_err;
3917 	}
3918 
3919 	return err;
3920 out_err:
3921 	kfree(*cond_attr);
3922 	*cond_attr = NULL;
3923 	return err;
3924 }
3925 
3926 static void
dec_jump_count(struct flow_action_entry * act,struct mlx5e_tc_act * tc_act,struct mlx5_flow_attr * attr,struct mlx5e_priv * priv,struct mlx5e_tc_jump_state * jump_state)3927 dec_jump_count(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3928 	       struct mlx5_flow_attr *attr, struct mlx5e_priv *priv,
3929 	       struct mlx5e_tc_jump_state *jump_state)
3930 {
3931 	if (!jump_state->jump_count)
3932 		return;
3933 
3934 	/* Single tc action can instantiate multiple offload actions (e.g. pedit)
3935 	 * Jump only over a tc action
3936 	 */
3937 	if (act->id == jump_state->last_id && act->hw_index == jump_state->last_index)
3938 		return;
3939 
3940 	jump_state->last_id = act->id;
3941 	jump_state->last_index = act->hw_index;
3942 
3943 	/* nothing to do for intermediate actions */
3944 	if (--jump_state->jump_count > 1)
3945 		return;
3946 
3947 	if (jump_state->jump_count == 1) { /* last action in the jump action list */
3948 
3949 		/* create a new attribute after this action */
3950 		jump_state->jump_target = true;
3951 
3952 		if (tc_act->is_terminating_action) { /* the branch ends here */
3953 			attr->flags |= MLX5_ATTR_FLAG_TERMINATING;
3954 			attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
3955 		} else { /* the branch continues executing the rest of the actions */
3956 			struct mlx5e_post_act *post_act;
3957 
3958 			attr->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3959 			post_act = get_post_action(priv);
3960 			attr->dest_ft = mlx5e_tc_post_act_get_ft(post_act);
3961 		}
3962 	} else if (jump_state->jump_count == 0) { /* first attr after the jump action list */
3963 		/* This is the post action for the jumping attribute (either red or green)
3964 		 * Use the stored jumping_attr to set the post act id on the jumping attribute
3965 		 */
3966 		attr->jumping_attr = jump_state->jumping_attr;
3967 	}
3968 }
3969 
3970 static int
parse_branch_ctrl(struct flow_action_entry * act,struct mlx5e_tc_act * tc_act,struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr,struct mlx5e_tc_jump_state * jump_state,struct netlink_ext_ack * extack)3971 parse_branch_ctrl(struct flow_action_entry *act, struct mlx5e_tc_act *tc_act,
3972 		  struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr,
3973 		  struct mlx5e_tc_jump_state *jump_state,
3974 		  struct netlink_ext_ack *extack)
3975 {
3976 	struct mlx5e_tc_act_branch_ctrl cond_true, cond_false;
3977 	u32 jump_count = jump_state->jump_count;
3978 	int err;
3979 
3980 	if (!tc_act->get_branch_ctrl)
3981 		return 0;
3982 
3983 	tc_act->get_branch_ctrl(act, &cond_true, &cond_false);
3984 
3985 	err = alloc_branch_attr(flow, &cond_true,
3986 				&attr->branch_true, &jump_count, extack);
3987 	if (err)
3988 		goto out_err;
3989 
3990 	if (jump_count)
3991 		jump_state->jumping_attr = attr->branch_true;
3992 
3993 	err = alloc_branch_attr(flow, &cond_false,
3994 				&attr->branch_false, &jump_count, extack);
3995 	if (err)
3996 		goto err_branch_false;
3997 
3998 	if (jump_count && !jump_state->jumping_attr)
3999 		jump_state->jumping_attr = attr->branch_false;
4000 
4001 	jump_state->jump_count = jump_count;
4002 
4003 	/* branching action requires its own counter */
4004 	attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
4005 	flow_flag_set(flow, USE_ACT_STATS);
4006 
4007 	return 0;
4008 
4009 err_branch_false:
4010 	free_branch_attr(flow, attr->branch_true);
4011 out_err:
4012 	return err;
4013 }
4014 
4015 static int
parse_tc_actions(struct mlx5e_tc_act_parse_state * parse_state,struct flow_action * flow_action)4016 parse_tc_actions(struct mlx5e_tc_act_parse_state *parse_state,
4017 		 struct flow_action *flow_action)
4018 {
4019 	struct netlink_ext_ack *extack = parse_state->extack;
4020 	struct mlx5e_tc_flow *flow = parse_state->flow;
4021 	struct mlx5e_tc_jump_state jump_state = {};
4022 	struct mlx5_flow_attr *attr = flow->attr;
4023 	enum mlx5_flow_namespace_type ns_type;
4024 	struct mlx5e_priv *priv = flow->priv;
4025 	struct mlx5_flow_attr *prev_attr;
4026 	struct flow_action_entry *act;
4027 	struct mlx5e_tc_act *tc_act;
4028 	int err, i, i_split = 0;
4029 	bool is_missable;
4030 
4031 	ns_type = mlx5e_get_flow_namespace(flow);
4032 	list_add(&attr->list, &flow->attrs);
4033 
4034 	flow_action_for_each(i, act, flow_action) {
4035 		jump_state.jump_target = false;
4036 		is_missable = false;
4037 		prev_attr = attr;
4038 
4039 		tc_act = mlx5e_tc_act_get(act->id, ns_type);
4040 		if (!tc_act) {
4041 			NL_SET_ERR_MSG_MOD(extack, "Not implemented offload action");
4042 			err = -EOPNOTSUPP;
4043 			goto out_free_post_acts;
4044 		}
4045 
4046 		if (tc_act->can_offload && !tc_act->can_offload(parse_state, act, i, attr)) {
4047 			err = -EOPNOTSUPP;
4048 			goto out_free_post_acts;
4049 		}
4050 
4051 		err = tc_act->parse_action(parse_state, act, priv, attr);
4052 		if (err)
4053 			goto out_free_post_acts;
4054 
4055 		dec_jump_count(act, tc_act, attr, priv, &jump_state);
4056 
4057 		err = parse_branch_ctrl(act, tc_act, flow, attr, &jump_state, extack);
4058 		if (err)
4059 			goto out_free_post_acts;
4060 
4061 		parse_state->actions |= attr->action;
4062 
4063 		/* Split attr for multi table act if not the last act. */
4064 		if (jump_state.jump_target ||
4065 		    (tc_act->is_multi_table_act &&
4066 		    tc_act->is_multi_table_act(priv, act, attr) &&
4067 		    i < flow_action->num_entries - 1)) {
4068 			is_missable = tc_act->is_missable ? tc_act->is_missable(act) : false;
4069 
4070 			err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr,
4071 						      ns_type);
4072 			if (err)
4073 				goto out_free_post_acts;
4074 
4075 			attr = mlx5e_clone_flow_attr_for_post_act(flow->attr, ns_type);
4076 			if (!attr) {
4077 				err = -ENOMEM;
4078 				goto out_free_post_acts;
4079 			}
4080 
4081 			i_split = i + 1;
4082 			parse_state->if_count = 0;
4083 			list_add(&attr->list, &flow->attrs);
4084 		}
4085 
4086 		if (is_missable) {
4087 			/* Add counter to prev, and assign act to new (next) attr */
4088 			prev_attr->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
4089 			flow_flag_set(flow, USE_ACT_STATS);
4090 
4091 			attr->tc_act_cookies[attr->tc_act_cookies_count++] = act->cookie;
4092 		} else if (!tc_act->stats_action) {
4093 			prev_attr->tc_act_cookies[prev_attr->tc_act_cookies_count++] = act->cookie;
4094 		}
4095 	}
4096 
4097 	err = mlx5e_tc_act_post_parse(parse_state, flow_action, i_split, i, attr, ns_type);
4098 	if (err)
4099 		goto out_free_post_acts;
4100 
4101 	err = alloc_flow_post_acts(flow, extack);
4102 	if (err)
4103 		goto out_free_post_acts;
4104 
4105 	return 0;
4106 
4107 out_free_post_acts:
4108 	free_flow_post_acts(flow);
4109 
4110 	return err;
4111 }
4112 
4113 static int
flow_action_supported(struct flow_action * flow_action,struct netlink_ext_ack * extack)4114 flow_action_supported(struct flow_action *flow_action,
4115 		      struct netlink_ext_ack *extack)
4116 {
4117 	if (!flow_action_has_entries(flow_action)) {
4118 		NL_SET_ERR_MSG_MOD(extack, "Flow action doesn't have any entries");
4119 		return -EINVAL;
4120 	}
4121 
4122 	if (!flow_action_hw_stats_check(flow_action, extack,
4123 					FLOW_ACTION_HW_STATS_DELAYED_BIT)) {
4124 		NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
4125 		return -EOPNOTSUPP;
4126 	}
4127 
4128 	return 0;
4129 }
4130 
4131 static int
parse_tc_nic_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)4132 parse_tc_nic_actions(struct mlx5e_priv *priv,
4133 		     struct flow_action *flow_action,
4134 		     struct mlx5e_tc_flow *flow,
4135 		     struct netlink_ext_ack *extack)
4136 {
4137 	struct mlx5e_tc_act_parse_state *parse_state;
4138 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4139 	struct mlx5_flow_attr *attr = flow->attr;
4140 	int err;
4141 
4142 	err = flow_action_supported(flow_action, extack);
4143 	if (err)
4144 		return err;
4145 
4146 	attr->nic_attr->flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
4147 	parse_attr = attr->parse_attr;
4148 	parse_state = &parse_attr->parse_state;
4149 	mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4150 	parse_state->ct_priv = get_ct_priv(priv);
4151 
4152 	err = parse_tc_actions(parse_state, flow_action);
4153 	if (err)
4154 		return err;
4155 
4156 	err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4157 	if (err)
4158 		return err;
4159 
4160 	err = verify_attr_actions(attr->action, extack);
4161 	if (err)
4162 		return err;
4163 
4164 	if (!actions_match_supported(priv, flow_action, parse_state->actions,
4165 				     parse_attr, flow, extack))
4166 		return -EOPNOTSUPP;
4167 
4168 	return 0;
4169 }
4170 
is_merged_eswitch_vfs(struct mlx5e_priv * priv,struct net_device * peer_netdev)4171 static bool is_merged_eswitch_vfs(struct mlx5e_priv *priv,
4172 				  struct net_device *peer_netdev)
4173 {
4174 	struct mlx5e_priv *peer_priv;
4175 
4176 	peer_priv = netdev_priv(peer_netdev);
4177 
4178 	return (MLX5_CAP_ESW(priv->mdev, merged_eswitch) &&
4179 		mlx5e_eswitch_vf_rep(priv->netdev) &&
4180 		mlx5e_eswitch_vf_rep(peer_netdev) &&
4181 		mlx5e_same_hw_devs(priv, peer_priv));
4182 }
4183 
same_hw_reps(struct mlx5e_priv * priv,struct net_device * peer_netdev)4184 static bool same_hw_reps(struct mlx5e_priv *priv,
4185 			 struct net_device *peer_netdev)
4186 {
4187 	struct mlx5e_priv *peer_priv;
4188 
4189 	peer_priv = netdev_priv(peer_netdev);
4190 
4191 	return mlx5e_eswitch_rep(priv->netdev) &&
4192 	       mlx5e_eswitch_rep(peer_netdev) &&
4193 	       mlx5e_same_hw_devs(priv, peer_priv);
4194 }
4195 
is_lag_dev(struct mlx5e_priv * priv,struct net_device * peer_netdev)4196 static bool is_lag_dev(struct mlx5e_priv *priv,
4197 		       struct net_device *peer_netdev)
4198 {
4199 	return ((mlx5_lag_is_sriov(priv->mdev) ||
4200 		 mlx5_lag_is_multipath(priv->mdev)) &&
4201 		 same_hw_reps(priv, peer_netdev));
4202 }
4203 
is_multiport_eligible(struct mlx5e_priv * priv,struct net_device * out_dev)4204 static bool is_multiport_eligible(struct mlx5e_priv *priv, struct net_device *out_dev)
4205 {
4206 	return same_hw_reps(priv, out_dev) && mlx5_lag_is_mpesw(priv->mdev);
4207 }
4208 
mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv * priv,struct net_device * out_dev)4209 bool mlx5e_is_valid_eswitch_fwd_dev(struct mlx5e_priv *priv,
4210 				    struct net_device *out_dev)
4211 {
4212 	if (is_merged_eswitch_vfs(priv, out_dev))
4213 		return true;
4214 
4215 	if (is_multiport_eligible(priv, out_dev))
4216 		return true;
4217 
4218 	if (is_lag_dev(priv, out_dev))
4219 		return true;
4220 
4221 	return mlx5e_eswitch_rep(out_dev) &&
4222 	       same_port_devs(priv, netdev_priv(out_dev));
4223 }
4224 
mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,int ifindex,enum mlx5e_tc_int_port_type type,u32 * action,int out_index)4225 int mlx5e_set_fwd_to_int_port_actions(struct mlx5e_priv *priv,
4226 				      struct mlx5_flow_attr *attr,
4227 				      int ifindex,
4228 				      enum mlx5e_tc_int_port_type type,
4229 				      u32 *action,
4230 				      int out_index)
4231 {
4232 	struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4233 	struct mlx5e_tc_int_port_priv *int_port_priv;
4234 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4235 	struct mlx5e_tc_int_port *dest_int_port;
4236 	int err;
4237 
4238 	parse_attr = attr->parse_attr;
4239 	int_port_priv = mlx5e_get_int_port_priv(priv);
4240 
4241 	dest_int_port = mlx5e_tc_int_port_get(int_port_priv, ifindex, type);
4242 	if (IS_ERR(dest_int_port))
4243 		return PTR_ERR(dest_int_port);
4244 
4245 	err = mlx5e_tc_match_to_reg_set(priv->mdev, &parse_attr->mod_hdr_acts,
4246 					MLX5_FLOW_NAMESPACE_FDB, VPORT_TO_REG,
4247 					mlx5e_tc_int_port_get_metadata(dest_int_port));
4248 	if (err) {
4249 		mlx5e_tc_int_port_put(int_port_priv, dest_int_port);
4250 		return err;
4251 	}
4252 
4253 	*action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
4254 
4255 	esw_attr->dest_int_port = dest_int_port;
4256 	esw_attr->dests[out_index].flags |= MLX5_ESW_DEST_CHAIN_WITH_SRC_PORT_CHANGE;
4257 	esw_attr->split_count = out_index;
4258 
4259 	/* Forward to root fdb for matching against the new source vport */
4260 	attr->dest_chain = 0;
4261 
4262 	return 0;
4263 }
4264 
4265 static int
parse_tc_fdb_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct mlx5e_tc_flow * flow,struct netlink_ext_ack * extack)4266 parse_tc_fdb_actions(struct mlx5e_priv *priv,
4267 		     struct flow_action *flow_action,
4268 		     struct mlx5e_tc_flow *flow,
4269 		     struct netlink_ext_ack *extack)
4270 {
4271 	struct mlx5e_tc_act_parse_state *parse_state;
4272 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4273 	struct mlx5_flow_attr *attr = flow->attr;
4274 	struct mlx5_esw_flow_attr *esw_attr;
4275 	struct net_device *filter_dev;
4276 	int err;
4277 
4278 	err = flow_action_supported(flow_action, extack);
4279 	if (err)
4280 		return err;
4281 
4282 	esw_attr = attr->esw_attr;
4283 	parse_attr = attr->parse_attr;
4284 	filter_dev = parse_attr->filter_dev;
4285 	parse_state = &parse_attr->parse_state;
4286 	mlx5e_tc_act_init_parse_state(parse_state, flow, flow_action, extack);
4287 	parse_state->ct_priv = get_ct_priv(priv);
4288 
4289 	err = parse_tc_actions(parse_state, flow_action);
4290 	if (err)
4291 		return err;
4292 
4293 	/* Forward to/from internal port can only have 1 dest */
4294 	if ((netif_is_ovs_master(filter_dev) || esw_attr->dest_int_port) &&
4295 	    esw_attr->out_count > 1) {
4296 		NL_SET_ERR_MSG_MOD(extack,
4297 				   "Rules with internal port can have only one destination");
4298 		return -EOPNOTSUPP;
4299 	}
4300 
4301 	/* Forward from tunnel/internal port to internal port is not supported */
4302 	if ((mlx5e_get_tc_tun(filter_dev) || netif_is_ovs_master(filter_dev)) &&
4303 	    esw_attr->dest_int_port) {
4304 		NL_SET_ERR_MSG_MOD(extack,
4305 				   "Forwarding from tunnel/internal port to internal port is not supported");
4306 		return -EOPNOTSUPP;
4307 	}
4308 
4309 	err = actions_prepare_mod_hdr_actions(priv, flow, attr, extack);
4310 	if (err)
4311 		return err;
4312 
4313 	if (!actions_match_supported(priv, flow_action, parse_state->actions,
4314 				     parse_attr, flow, extack))
4315 		return -EOPNOTSUPP;
4316 
4317 	return 0;
4318 }
4319 
get_flags(int flags,unsigned long * flow_flags)4320 static void get_flags(int flags, unsigned long *flow_flags)
4321 {
4322 	unsigned long __flow_flags = 0;
4323 
4324 	if (flags & MLX5_TC_FLAG(INGRESS))
4325 		__flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_INGRESS);
4326 	if (flags & MLX5_TC_FLAG(EGRESS))
4327 		__flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_EGRESS);
4328 
4329 	if (flags & MLX5_TC_FLAG(ESW_OFFLOAD))
4330 		__flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4331 	if (flags & MLX5_TC_FLAG(NIC_OFFLOAD))
4332 		__flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4333 	if (flags & MLX5_TC_FLAG(FT_OFFLOAD))
4334 		__flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_FT);
4335 
4336 	*flow_flags = __flow_flags;
4337 }
4338 
4339 static const struct rhashtable_params tc_ht_params = {
4340 	.head_offset = offsetof(struct mlx5e_tc_flow, node),
4341 	.key_offset = offsetof(struct mlx5e_tc_flow, cookie),
4342 	.key_len = sizeof(((struct mlx5e_tc_flow *)0)->cookie),
4343 	.automatic_shrinking = true,
4344 };
4345 
get_tc_ht(struct mlx5e_priv * priv,unsigned long flags)4346 static struct rhashtable *get_tc_ht(struct mlx5e_priv *priv,
4347 				    unsigned long flags)
4348 {
4349 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
4350 	struct mlx5e_rep_priv *rpriv;
4351 
4352 	if (flags & MLX5_TC_FLAG(ESW_OFFLOAD)) {
4353 		rpriv = priv->ppriv;
4354 		return &rpriv->tc_ht;
4355 	} else /* NIC offload */
4356 		return &tc->ht;
4357 }
4358 
is_peer_flow_needed(struct mlx5e_tc_flow * flow)4359 static bool is_peer_flow_needed(struct mlx5e_tc_flow *flow)
4360 {
4361 	struct mlx5_esw_flow_attr *esw_attr = flow->attr->esw_attr;
4362 	struct mlx5_flow_attr *attr = flow->attr;
4363 	bool is_rep_ingress = esw_attr->in_rep->vport != MLX5_VPORT_UPLINK &&
4364 		flow_flag_test(flow, INGRESS);
4365 	bool act_is_encap = !!(attr->action &
4366 			       MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT);
4367 	bool esw_paired = mlx5_devcom_comp_is_ready(esw_attr->in_mdev->priv.eswitch->devcom);
4368 
4369 	if (!esw_paired)
4370 		return false;
4371 
4372 	if ((mlx5_lag_is_sriov(esw_attr->in_mdev) ||
4373 	     mlx5_lag_is_multipath(esw_attr->in_mdev)) &&
4374 	    (is_rep_ingress || act_is_encap))
4375 		return true;
4376 
4377 	if (mlx5_lag_is_mpesw(esw_attr->in_mdev))
4378 		return true;
4379 
4380 	return false;
4381 }
4382 
4383 struct mlx5_flow_attr *
mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)4384 mlx5_alloc_flow_attr(enum mlx5_flow_namespace_type type)
4385 {
4386 	u32 ex_attr_size = (type == MLX5_FLOW_NAMESPACE_FDB)  ?
4387 				sizeof(struct mlx5_esw_flow_attr) :
4388 				sizeof(struct mlx5_nic_flow_attr);
4389 	struct mlx5_flow_attr *attr;
4390 
4391 	attr = kzalloc(sizeof(*attr) + ex_attr_size, GFP_KERNEL);
4392 	if (!attr)
4393 		return attr;
4394 
4395 	INIT_LIST_HEAD(&attr->list);
4396 	return attr;
4397 }
4398 
4399 static void
mlx5_free_flow_attr_actions(struct mlx5e_tc_flow * flow,struct mlx5_flow_attr * attr)4400 mlx5_free_flow_attr_actions(struct mlx5e_tc_flow *flow, struct mlx5_flow_attr *attr)
4401 {
4402 	struct mlx5_core_dev *counter_dev = get_flow_counter_dev(flow);
4403 	struct mlx5_esw_flow_attr *esw_attr;
4404 
4405 	if (!attr)
4406 		return;
4407 
4408 	if (attr->post_act_handle)
4409 		mlx5e_tc_post_act_del(get_post_action(flow->priv), attr->post_act_handle);
4410 
4411 	mlx5e_tc_tun_encap_dests_unset(flow->priv, flow, attr);
4412 
4413 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
4414 		mlx5_fc_destroy(counter_dev, attr->counter);
4415 
4416 	if (attr->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR) {
4417 		mlx5e_mod_hdr_dealloc(&attr->parse_attr->mod_hdr_acts);
4418 		mlx5e_tc_detach_mod_hdr(flow->priv, flow, attr);
4419 	}
4420 
4421 	if (mlx5e_is_eswitch_flow(flow)) {
4422 		esw_attr = attr->esw_attr;
4423 
4424 		if (esw_attr->int_port)
4425 			mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4426 					      esw_attr->int_port);
4427 
4428 		if (esw_attr->dest_int_port)
4429 			mlx5e_tc_int_port_put(mlx5e_get_int_port_priv(flow->priv),
4430 					      esw_attr->dest_int_port);
4431 	}
4432 
4433 	mlx5_tc_ct_delete_flow(get_ct_priv(flow->priv), attr);
4434 
4435 	free_branch_attr(flow, attr->branch_true);
4436 	free_branch_attr(flow, attr->branch_false);
4437 }
4438 
4439 static int
mlx5e_alloc_flow(struct mlx5e_priv * priv,int attr_size,struct flow_cls_offload * f,unsigned long flow_flags,struct mlx5e_tc_flow_parse_attr ** __parse_attr,struct mlx5e_tc_flow ** __flow)4440 mlx5e_alloc_flow(struct mlx5e_priv *priv, int attr_size,
4441 		 struct flow_cls_offload *f, unsigned long flow_flags,
4442 		 struct mlx5e_tc_flow_parse_attr **__parse_attr,
4443 		 struct mlx5e_tc_flow **__flow)
4444 {
4445 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4446 	struct mlx5_flow_attr *attr;
4447 	struct mlx5e_tc_flow *flow;
4448 	int err = -ENOMEM;
4449 	int out_index;
4450 
4451 	flow = kzalloc(sizeof(*flow), GFP_KERNEL);
4452 	parse_attr = kvzalloc(sizeof(*parse_attr), GFP_KERNEL);
4453 	if (!parse_attr || !flow)
4454 		goto err_free;
4455 
4456 	flow->flags = flow_flags;
4457 	flow->cookie = f->cookie;
4458 	flow->priv = priv;
4459 
4460 	attr = mlx5_alloc_flow_attr(mlx5e_get_flow_namespace(flow));
4461 	if (!attr)
4462 		goto err_free;
4463 
4464 	flow->attr = attr;
4465 
4466 	for (out_index = 0; out_index < MLX5_MAX_FLOW_FWD_VPORTS; out_index++)
4467 		INIT_LIST_HEAD(&flow->encaps[out_index].list);
4468 	INIT_LIST_HEAD(&flow->hairpin);
4469 	INIT_LIST_HEAD(&flow->l3_to_l2_reformat);
4470 	INIT_LIST_HEAD(&flow->attrs);
4471 	INIT_LIST_HEAD(&flow->peer_flows);
4472 	refcount_set(&flow->refcnt, 1);
4473 	init_completion(&flow->init_done);
4474 	init_completion(&flow->del_hw_done);
4475 
4476 	*__flow = flow;
4477 	*__parse_attr = parse_attr;
4478 
4479 	return 0;
4480 
4481 err_free:
4482 	kfree(flow);
4483 	kvfree(parse_attr);
4484 	return err;
4485 }
4486 
4487 static void
mlx5e_flow_attr_init(struct mlx5_flow_attr * attr,struct mlx5e_tc_flow_parse_attr * parse_attr,struct flow_cls_offload * f)4488 mlx5e_flow_attr_init(struct mlx5_flow_attr *attr,
4489 		     struct mlx5e_tc_flow_parse_attr *parse_attr,
4490 		     struct flow_cls_offload *f)
4491 {
4492 	attr->parse_attr = parse_attr;
4493 	attr->chain = f->common.chain_index;
4494 	attr->prio = f->common.prio;
4495 }
4496 
4497 static void
mlx5e_flow_esw_attr_init(struct mlx5_flow_attr * attr,struct mlx5e_priv * priv,struct mlx5e_tc_flow_parse_attr * parse_attr,struct flow_cls_offload * f,struct mlx5_eswitch_rep * in_rep,struct mlx5_core_dev * in_mdev)4498 mlx5e_flow_esw_attr_init(struct mlx5_flow_attr *attr,
4499 			 struct mlx5e_priv *priv,
4500 			 struct mlx5e_tc_flow_parse_attr *parse_attr,
4501 			 struct flow_cls_offload *f,
4502 			 struct mlx5_eswitch_rep *in_rep,
4503 			 struct mlx5_core_dev *in_mdev)
4504 {
4505 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4506 	struct mlx5_esw_flow_attr *esw_attr = attr->esw_attr;
4507 
4508 	mlx5e_flow_attr_init(attr, parse_attr, f);
4509 
4510 	esw_attr->in_rep = in_rep;
4511 	esw_attr->in_mdev = in_mdev;
4512 
4513 	if (MLX5_CAP_ESW(esw->dev, counter_eswitch_affinity) ==
4514 	    MLX5_COUNTER_SOURCE_ESWITCH)
4515 		esw_attr->counter_dev = in_mdev;
4516 	else
4517 		esw_attr->counter_dev = priv->mdev;
4518 }
4519 
4520 static struct mlx5e_tc_flow *
__mlx5e_add_fdb_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5_eswitch_rep * in_rep,struct mlx5_core_dev * in_mdev)4521 __mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4522 		     struct flow_cls_offload *f,
4523 		     unsigned long flow_flags,
4524 		     struct net_device *filter_dev,
4525 		     struct mlx5_eswitch_rep *in_rep,
4526 		     struct mlx5_core_dev *in_mdev)
4527 {
4528 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4529 	struct netlink_ext_ack *extack = f->common.extack;
4530 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4531 	struct mlx5e_tc_flow *flow;
4532 	int attr_size, err;
4533 
4534 	flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_ESWITCH);
4535 	attr_size  = sizeof(struct mlx5_esw_flow_attr);
4536 	err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4537 			       &parse_attr, &flow);
4538 	if (err)
4539 		goto out;
4540 
4541 	parse_attr->filter_dev = filter_dev;
4542 	mlx5e_flow_esw_attr_init(flow->attr,
4543 				 priv, parse_attr,
4544 				 f, in_rep, in_mdev);
4545 
4546 	err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4547 			       f, filter_dev);
4548 	if (err)
4549 		goto err_free;
4550 
4551 	/* actions validation depends on parsing the ct matches first */
4552 	err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4553 				   &flow->attr->ct_attr, extack);
4554 	if (err)
4555 		goto err_free;
4556 
4557 	err = parse_tc_fdb_actions(priv, &rule->action, flow, extack);
4558 	if (err)
4559 		goto err_free;
4560 
4561 	err = mlx5e_tc_add_fdb_flow(priv, flow, extack);
4562 	complete_all(&flow->init_done);
4563 	if (err) {
4564 		if (!(err == -ENETUNREACH && mlx5_lag_is_multipath(in_mdev)))
4565 			goto err_free;
4566 
4567 		add_unready_flow(flow);
4568 	}
4569 
4570 	return flow;
4571 
4572 err_free:
4573 	mlx5e_flow_put(priv, flow);
4574 out:
4575 	return ERR_PTR(err);
4576 }
4577 
mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload * f,struct mlx5e_tc_flow * flow,unsigned long flow_flags,struct mlx5_eswitch * peer_esw)4578 static int mlx5e_tc_add_fdb_peer_flow(struct flow_cls_offload *f,
4579 				      struct mlx5e_tc_flow *flow,
4580 				      unsigned long flow_flags,
4581 				      struct mlx5_eswitch *peer_esw)
4582 {
4583 	struct mlx5e_priv *priv = flow->priv, *peer_priv;
4584 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4585 	struct mlx5_esw_flow_attr *attr = flow->attr->esw_attr;
4586 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4587 	int i = mlx5_get_dev_index(peer_esw->dev);
4588 	struct mlx5e_rep_priv *peer_urpriv;
4589 	struct mlx5e_tc_flow *peer_flow;
4590 	struct mlx5_core_dev *in_mdev;
4591 	int err = 0;
4592 
4593 	peer_urpriv = mlx5_eswitch_get_uplink_priv(peer_esw, REP_ETH);
4594 	peer_priv = netdev_priv(peer_urpriv->netdev);
4595 
4596 	/* in_mdev is assigned of which the packet originated from.
4597 	 * So packets redirected to uplink use the same mdev of the
4598 	 * original flow and packets redirected from uplink use the
4599 	 * peer mdev.
4600 	 * In multiport eswitch it's a special case that we need to
4601 	 * keep the original mdev.
4602 	 */
4603 	if (attr->in_rep->vport == MLX5_VPORT_UPLINK && !mlx5_lag_is_mpesw(priv->mdev))
4604 		in_mdev = peer_priv->mdev;
4605 	else
4606 		in_mdev = priv->mdev;
4607 
4608 	parse_attr = flow->attr->parse_attr;
4609 	peer_flow = __mlx5e_add_fdb_flow(peer_priv, f, flow_flags,
4610 					 parse_attr->filter_dev,
4611 					 attr->in_rep, in_mdev);
4612 	if (IS_ERR(peer_flow)) {
4613 		err = PTR_ERR(peer_flow);
4614 		goto out;
4615 	}
4616 
4617 	list_add_tail(&peer_flow->peer_flows, &flow->peer_flows);
4618 	flow_flag_set(flow, DUP);
4619 	mutex_lock(&esw->offloads.peer_mutex);
4620 	list_add_tail(&flow->peer[i], &esw->offloads.peer_flows[i]);
4621 	mutex_unlock(&esw->offloads.peer_mutex);
4622 
4623 out:
4624 	return err;
4625 }
4626 
4627 static int
mlx5e_add_fdb_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** __flow)4628 mlx5e_add_fdb_flow(struct mlx5e_priv *priv,
4629 		   struct flow_cls_offload *f,
4630 		   unsigned long flow_flags,
4631 		   struct net_device *filter_dev,
4632 		   struct mlx5e_tc_flow **__flow)
4633 {
4634 	struct mlx5_devcom_comp_dev *devcom = priv->mdev->priv.eswitch->devcom, *pos;
4635 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
4636 	struct mlx5_eswitch_rep *in_rep = rpriv->rep;
4637 	struct mlx5_core_dev *in_mdev = priv->mdev;
4638 	struct mlx5_eswitch *peer_esw;
4639 	struct mlx5e_tc_flow *flow;
4640 	int err;
4641 
4642 	flow = __mlx5e_add_fdb_flow(priv, f, flow_flags, filter_dev, in_rep,
4643 				    in_mdev);
4644 	if (IS_ERR(flow))
4645 		return PTR_ERR(flow);
4646 
4647 	if (!is_peer_flow_needed(flow)) {
4648 		*__flow = flow;
4649 		return 0;
4650 	}
4651 
4652 	if (!mlx5_devcom_for_each_peer_begin(devcom)) {
4653 		err = -ENODEV;
4654 		goto clean_flow;
4655 	}
4656 
4657 	mlx5_devcom_for_each_peer_entry(devcom, peer_esw, pos) {
4658 		err = mlx5e_tc_add_fdb_peer_flow(f, flow, flow_flags, peer_esw);
4659 		if (err)
4660 			goto peer_clean;
4661 	}
4662 
4663 	mlx5_devcom_for_each_peer_end(devcom);
4664 
4665 	*__flow = flow;
4666 	return 0;
4667 
4668 peer_clean:
4669 	mlx5e_tc_del_fdb_peers_flow(flow);
4670 	mlx5_devcom_for_each_peer_end(devcom);
4671 clean_flow:
4672 	mlx5e_tc_del_fdb_flow(priv, flow);
4673 	return err;
4674 }
4675 
4676 static int
mlx5e_add_nic_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flow_flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** __flow)4677 mlx5e_add_nic_flow(struct mlx5e_priv *priv,
4678 		   struct flow_cls_offload *f,
4679 		   unsigned long flow_flags,
4680 		   struct net_device *filter_dev,
4681 		   struct mlx5e_tc_flow **__flow)
4682 {
4683 	struct flow_rule *rule = flow_cls_offload_flow_rule(f);
4684 	struct netlink_ext_ack *extack = f->common.extack;
4685 	struct mlx5e_tc_flow_parse_attr *parse_attr;
4686 	struct mlx5e_tc_flow *flow;
4687 	int attr_size, err;
4688 
4689 	if (!MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level)) {
4690 		if (!tc_cls_can_offload_and_chain0(priv->netdev, &f->common))
4691 			return -EOPNOTSUPP;
4692 	} else if (!tc_can_offload_extack(priv->netdev, f->common.extack)) {
4693 		return -EOPNOTSUPP;
4694 	}
4695 
4696 	flow_flags |= BIT(MLX5E_TC_FLOW_FLAG_NIC);
4697 	attr_size  = sizeof(struct mlx5_nic_flow_attr);
4698 	err = mlx5e_alloc_flow(priv, attr_size, f, flow_flags,
4699 			       &parse_attr, &flow);
4700 	if (err)
4701 		goto out;
4702 
4703 	parse_attr->filter_dev = filter_dev;
4704 	mlx5e_flow_attr_init(flow->attr, parse_attr, f);
4705 
4706 	err = parse_cls_flower(flow->priv, flow, &parse_attr->spec,
4707 			       f, filter_dev);
4708 	if (err)
4709 		goto err_free;
4710 
4711 	err = mlx5_tc_ct_match_add(get_ct_priv(priv), &parse_attr->spec, f,
4712 				   &flow->attr->ct_attr, extack);
4713 	if (err)
4714 		goto err_free;
4715 
4716 	err = parse_tc_nic_actions(priv, &rule->action, flow, extack);
4717 	if (err)
4718 		goto err_free;
4719 
4720 	err = mlx5e_tc_add_nic_flow(priv, flow, extack);
4721 	if (err)
4722 		goto err_free;
4723 
4724 	flow_flag_set(flow, OFFLOADED);
4725 	*__flow = flow;
4726 
4727 	return 0;
4728 
4729 err_free:
4730 	flow_flag_set(flow, FAILED);
4731 	mlx5e_mod_hdr_dealloc(&parse_attr->mod_hdr_acts);
4732 	mlx5e_flow_put(priv, flow);
4733 out:
4734 	return err;
4735 }
4736 
4737 static int
mlx5e_tc_add_flow(struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags,struct net_device * filter_dev,struct mlx5e_tc_flow ** flow)4738 mlx5e_tc_add_flow(struct mlx5e_priv *priv,
4739 		  struct flow_cls_offload *f,
4740 		  unsigned long flags,
4741 		  struct net_device *filter_dev,
4742 		  struct mlx5e_tc_flow **flow)
4743 {
4744 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4745 	unsigned long flow_flags;
4746 	int err;
4747 
4748 	get_flags(flags, &flow_flags);
4749 
4750 	if (!tc_can_offload_extack(priv->netdev, f->common.extack))
4751 		return -EOPNOTSUPP;
4752 
4753 	if (esw && esw->mode == MLX5_ESWITCH_OFFLOADS)
4754 		err = mlx5e_add_fdb_flow(priv, f, flow_flags,
4755 					 filter_dev, flow);
4756 	else
4757 		err = mlx5e_add_nic_flow(priv, f, flow_flags,
4758 					 filter_dev, flow);
4759 
4760 	return err;
4761 }
4762 
is_flow_rule_duplicate_allowed(struct net_device * dev,struct mlx5e_rep_priv * rpriv)4763 static bool is_flow_rule_duplicate_allowed(struct net_device *dev,
4764 					   struct mlx5e_rep_priv *rpriv)
4765 {
4766 	/* Offloaded flow rule is allowed to duplicate on non-uplink representor
4767 	 * sharing tc block with other slaves of a lag device. Rpriv can be NULL if this
4768 	 * function is called from NIC mode.
4769 	 */
4770 	return netif_is_lag_port(dev) && rpriv && rpriv->rep->vport != MLX5_VPORT_UPLINK;
4771 }
4772 
4773 /* As IPsec and TC order is not aligned between software and hardware-offload,
4774  * either IPsec offload or TC offload, not both, is allowed for a specific interface.
4775  */
is_tc_ipsec_order_check_needed(struct net_device * filter,struct mlx5e_priv * priv)4776 static bool is_tc_ipsec_order_check_needed(struct net_device *filter, struct mlx5e_priv *priv)
4777 {
4778 	if (!IS_ENABLED(CONFIG_MLX5_EN_IPSEC))
4779 		return false;
4780 
4781 	if (filter != priv->netdev)
4782 		return false;
4783 
4784 	if (mlx5e_eswitch_vf_rep(priv->netdev))
4785 		return false;
4786 
4787 	return true;
4788 }
4789 
mlx5e_tc_block_ipsec_offload(struct net_device * filter,struct mlx5e_priv * priv)4790 static int mlx5e_tc_block_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4791 {
4792 	struct mlx5_core_dev *mdev = priv->mdev;
4793 
4794 	if (!is_tc_ipsec_order_check_needed(filter, priv))
4795 		return 0;
4796 
4797 	if (mdev->num_block_tc)
4798 		return -EBUSY;
4799 
4800 	mdev->num_block_ipsec++;
4801 
4802 	return 0;
4803 }
4804 
mlx5e_tc_unblock_ipsec_offload(struct net_device * filter,struct mlx5e_priv * priv)4805 static void mlx5e_tc_unblock_ipsec_offload(struct net_device *filter, struct mlx5e_priv *priv)
4806 {
4807 	if (!is_tc_ipsec_order_check_needed(filter, priv))
4808 		return;
4809 
4810 	priv->mdev->num_block_ipsec--;
4811 }
4812 
mlx5e_configure_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4813 int mlx5e_configure_flower(struct net_device *dev, struct mlx5e_priv *priv,
4814 			   struct flow_cls_offload *f, unsigned long flags)
4815 {
4816 	struct netlink_ext_ack *extack = f->common.extack;
4817 	struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4818 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
4819 	struct mlx5e_tc_flow *flow;
4820 	int err = 0;
4821 
4822 	if (!mlx5_esw_hold(priv->mdev))
4823 		return -EBUSY;
4824 
4825 	err = mlx5e_tc_block_ipsec_offload(dev, priv);
4826 	if (err)
4827 		goto esw_release;
4828 
4829 	mlx5_esw_get(priv->mdev);
4830 
4831 	rcu_read_lock();
4832 	flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4833 	if (flow) {
4834 		/* Same flow rule offloaded to non-uplink representor sharing tc block,
4835 		 * just return 0.
4836 		 */
4837 		if (is_flow_rule_duplicate_allowed(dev, rpriv) && flow->orig_dev != dev)
4838 			goto rcu_unlock;
4839 
4840 		NL_SET_ERR_MSG_MOD(extack,
4841 				   "flow cookie already exists, ignoring");
4842 		netdev_warn_once(priv->netdev,
4843 				 "flow cookie %lx already exists, ignoring\n",
4844 				 f->cookie);
4845 		err = -EEXIST;
4846 		goto rcu_unlock;
4847 	}
4848 rcu_unlock:
4849 	rcu_read_unlock();
4850 	if (flow)
4851 		goto out;
4852 
4853 	trace_mlx5e_configure_flower(f);
4854 	err = mlx5e_tc_add_flow(priv, f, flags, dev, &flow);
4855 	if (err)
4856 		goto out;
4857 
4858 	/* Flow rule offloaded to non-uplink representor sharing tc block,
4859 	 * set the flow's owner dev.
4860 	 */
4861 	if (is_flow_rule_duplicate_allowed(dev, rpriv))
4862 		flow->orig_dev = dev;
4863 
4864 	err = rhashtable_lookup_insert_fast(tc_ht, &flow->node, tc_ht_params);
4865 	if (err)
4866 		goto err_free;
4867 
4868 	mlx5_esw_release(priv->mdev);
4869 	return 0;
4870 
4871 err_free:
4872 	mlx5e_flow_put(priv, flow);
4873 out:
4874 	mlx5e_tc_unblock_ipsec_offload(dev, priv);
4875 	mlx5_esw_put(priv->mdev);
4876 esw_release:
4877 	mlx5_esw_release(priv->mdev);
4878 	return err;
4879 }
4880 
same_flow_direction(struct mlx5e_tc_flow * flow,int flags)4881 static bool same_flow_direction(struct mlx5e_tc_flow *flow, int flags)
4882 {
4883 	bool dir_ingress = !!(flags & MLX5_TC_FLAG(INGRESS));
4884 	bool dir_egress = !!(flags & MLX5_TC_FLAG(EGRESS));
4885 
4886 	return flow_flag_test(flow, INGRESS) == dir_ingress &&
4887 		flow_flag_test(flow, EGRESS) == dir_egress;
4888 }
4889 
mlx5e_delete_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4890 int mlx5e_delete_flower(struct net_device *dev, struct mlx5e_priv *priv,
4891 			struct flow_cls_offload *f, unsigned long flags)
4892 {
4893 	struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4894 	struct mlx5e_tc_flow *flow;
4895 	int err;
4896 
4897 	rcu_read_lock();
4898 	flow = rhashtable_lookup(tc_ht, &f->cookie, tc_ht_params);
4899 	if (!flow || !same_flow_direction(flow, flags)) {
4900 		err = -EINVAL;
4901 		goto errout;
4902 	}
4903 
4904 	/* Only delete the flow if it doesn't have MLX5E_TC_FLOW_DELETED flag
4905 	 * set.
4906 	 */
4907 	if (flow_flag_test_and_set(flow, DELETED)) {
4908 		err = -EINVAL;
4909 		goto errout;
4910 	}
4911 	rhashtable_remove_fast(tc_ht, &flow->node, tc_ht_params);
4912 	rcu_read_unlock();
4913 
4914 	trace_mlx5e_delete_flower(f);
4915 	mlx5e_flow_put(priv, flow);
4916 
4917 	mlx5e_tc_unblock_ipsec_offload(dev, priv);
4918 	mlx5_esw_put(priv->mdev);
4919 	return 0;
4920 
4921 errout:
4922 	rcu_read_unlock();
4923 	return err;
4924 }
4925 
mlx5e_tc_fill_action_stats(struct mlx5e_priv * priv,struct flow_offload_action * fl_act)4926 int mlx5e_tc_fill_action_stats(struct mlx5e_priv *priv,
4927 			       struct flow_offload_action *fl_act)
4928 {
4929 	return mlx5e_tc_act_stats_fill_stats(get_act_stats_handle(priv), fl_act);
4930 }
4931 
mlx5e_stats_flower(struct net_device * dev,struct mlx5e_priv * priv,struct flow_cls_offload * f,unsigned long flags)4932 int mlx5e_stats_flower(struct net_device *dev, struct mlx5e_priv *priv,
4933 		       struct flow_cls_offload *f, unsigned long flags)
4934 {
4935 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
4936 	struct rhashtable *tc_ht = get_tc_ht(priv, flags);
4937 	struct mlx5e_tc_flow *flow;
4938 	struct mlx5_fc *counter;
4939 	u64 lastuse = 0;
4940 	u64 packets = 0;
4941 	u64 bytes = 0;
4942 	int err = 0;
4943 
4944 	rcu_read_lock();
4945 	flow = mlx5e_flow_get(rhashtable_lookup(tc_ht, &f->cookie,
4946 						tc_ht_params));
4947 	rcu_read_unlock();
4948 	if (IS_ERR(flow))
4949 		return PTR_ERR(flow);
4950 
4951 	if (!same_flow_direction(flow, flags)) {
4952 		err = -EINVAL;
4953 		goto errout;
4954 	}
4955 
4956 	if (mlx5e_is_offloaded_flow(flow)) {
4957 		if (flow_flag_test(flow, USE_ACT_STATS)) {
4958 			f->use_act_stats = true;
4959 		} else {
4960 			counter = mlx5e_tc_get_counter(flow);
4961 			if (!counter)
4962 				goto errout;
4963 
4964 			mlx5_fc_query_cached(counter, &bytes, &packets, &lastuse);
4965 		}
4966 	}
4967 
4968 	/* Under multipath it's possible for one rule to be currently
4969 	 * un-offloaded while the other rule is offloaded.
4970 	 */
4971 	if (esw && !mlx5_devcom_for_each_peer_begin(esw->devcom))
4972 		goto out;
4973 
4974 	if (flow_flag_test(flow, DUP)) {
4975 		struct mlx5e_tc_flow *peer_flow;
4976 
4977 		list_for_each_entry(peer_flow, &flow->peer_flows, peer_flows) {
4978 			u64 packets2;
4979 			u64 lastuse2;
4980 			u64 bytes2;
4981 
4982 			if (!flow_flag_test(peer_flow, OFFLOADED))
4983 				continue;
4984 			if (flow_flag_test(flow, USE_ACT_STATS)) {
4985 				f->use_act_stats = true;
4986 				break;
4987 			}
4988 
4989 			counter = mlx5e_tc_get_counter(peer_flow);
4990 			if (!counter)
4991 				goto no_peer_counter;
4992 			mlx5_fc_query_cached(counter, &bytes2, &packets2,
4993 					     &lastuse2);
4994 
4995 			bytes += bytes2;
4996 			packets += packets2;
4997 			lastuse = max_t(u64, lastuse, lastuse2);
4998 		}
4999 	}
5000 
5001 no_peer_counter:
5002 	if (esw)
5003 		mlx5_devcom_for_each_peer_end(esw->devcom);
5004 out:
5005 	flow_stats_update(&f->stats, bytes, packets, 0, lastuse,
5006 			  FLOW_ACTION_HW_STATS_DELAYED);
5007 	trace_mlx5e_stats_flower(f);
5008 errout:
5009 	mlx5e_flow_put(priv, flow);
5010 	return err;
5011 }
5012 
apply_police_params(struct mlx5e_priv * priv,u64 rate,struct netlink_ext_ack * extack)5013 static int apply_police_params(struct mlx5e_priv *priv, u64 rate,
5014 			       struct netlink_ext_ack *extack)
5015 {
5016 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
5017 	struct mlx5_eswitch *esw;
5018 	u32 rate_mbps = 0;
5019 	u16 vport_num;
5020 	int err;
5021 
5022 	vport_num = rpriv->rep->vport;
5023 	if (vport_num >= MLX5_VPORT_ECPF) {
5024 		NL_SET_ERR_MSG_MOD(extack,
5025 				   "Ingress rate limit is supported only for Eswitch ports connected to VFs");
5026 		return -EOPNOTSUPP;
5027 	}
5028 
5029 	esw = priv->mdev->priv.eswitch;
5030 	/* rate is given in bytes/sec.
5031 	 * First convert to bits/sec and then round to the nearest mbit/secs.
5032 	 * mbit means million bits.
5033 	 * Moreover, if rate is non zero we choose to configure to a minimum of
5034 	 * 1 mbit/sec.
5035 	 */
5036 	if (rate) {
5037 		rate = (rate * BITS_PER_BYTE) + 500000;
5038 		do_div(rate, 1000000);
5039 		rate_mbps = max_t(u32, rate, 1);
5040 	}
5041 
5042 	err = mlx5_esw_qos_modify_vport_rate(esw, vport_num, rate_mbps);
5043 	if (err)
5044 		NL_SET_ERR_MSG_MOD(extack, "failed applying action to hardware");
5045 
5046 	return err;
5047 }
5048 
5049 static int
tc_matchall_police_validate(const struct flow_action * action,const struct flow_action_entry * act,struct netlink_ext_ack * extack)5050 tc_matchall_police_validate(const struct flow_action *action,
5051 			    const struct flow_action_entry *act,
5052 			    struct netlink_ext_ack *extack)
5053 {
5054 	if (act->police.notexceed.act_id != FLOW_ACTION_CONTINUE) {
5055 		NL_SET_ERR_MSG_MOD(extack,
5056 				   "Offload not supported when conform action is not continue");
5057 		return -EOPNOTSUPP;
5058 	}
5059 
5060 	if (act->police.exceed.act_id != FLOW_ACTION_DROP) {
5061 		NL_SET_ERR_MSG_MOD(extack,
5062 				   "Offload not supported when exceed action is not drop");
5063 		return -EOPNOTSUPP;
5064 	}
5065 
5066 	if (act->police.notexceed.act_id == FLOW_ACTION_ACCEPT &&
5067 	    !flow_action_is_last_entry(action, act)) {
5068 		NL_SET_ERR_MSG_MOD(extack,
5069 				   "Offload not supported when conform action is ok, but action is not last");
5070 		return -EOPNOTSUPP;
5071 	}
5072 
5073 	if (act->police.peakrate_bytes_ps ||
5074 	    act->police.avrate || act->police.overhead) {
5075 		NL_SET_ERR_MSG_MOD(extack,
5076 				   "Offload not supported when peakrate/avrate/overhead is configured");
5077 		return -EOPNOTSUPP;
5078 	}
5079 
5080 	return 0;
5081 }
5082 
scan_tc_matchall_fdb_actions(struct mlx5e_priv * priv,struct flow_action * flow_action,struct netlink_ext_ack * extack)5083 static int scan_tc_matchall_fdb_actions(struct mlx5e_priv *priv,
5084 					struct flow_action *flow_action,
5085 					struct netlink_ext_ack *extack)
5086 {
5087 	struct mlx5e_rep_priv *rpriv = priv->ppriv;
5088 	const struct flow_action_entry *act;
5089 	int err;
5090 	int i;
5091 
5092 	if (!flow_action_has_entries(flow_action)) {
5093 		NL_SET_ERR_MSG_MOD(extack, "matchall called with no action");
5094 		return -EINVAL;
5095 	}
5096 
5097 	if (!flow_offload_has_one_action(flow_action)) {
5098 		NL_SET_ERR_MSG_MOD(extack, "matchall policing support only a single action");
5099 		return -EOPNOTSUPP;
5100 	}
5101 
5102 	if (!flow_action_basic_hw_stats_check(flow_action, extack)) {
5103 		NL_SET_ERR_MSG_MOD(extack, "Flow action HW stats type is not supported");
5104 		return -EOPNOTSUPP;
5105 	}
5106 
5107 	flow_action_for_each(i, act, flow_action) {
5108 		switch (act->id) {
5109 		case FLOW_ACTION_POLICE:
5110 			err = tc_matchall_police_validate(flow_action, act, extack);
5111 			if (err)
5112 				return err;
5113 
5114 			err = apply_police_params(priv, act->police.rate_bytes_ps, extack);
5115 			if (err)
5116 				return err;
5117 
5118 			mlx5e_stats_copy_rep_stats(&rpriv->prev_vf_vport_stats,
5119 						   &priv->stats.rep_stats);
5120 			break;
5121 		default:
5122 			NL_SET_ERR_MSG_MOD(extack, "mlx5 supports only police action for matchall");
5123 			return -EOPNOTSUPP;
5124 		}
5125 	}
5126 
5127 	return 0;
5128 }
5129 
mlx5e_tc_configure_matchall(struct mlx5e_priv * priv,struct tc_cls_matchall_offload * ma)5130 int mlx5e_tc_configure_matchall(struct mlx5e_priv *priv,
5131 				struct tc_cls_matchall_offload *ma)
5132 {
5133 	struct netlink_ext_ack *extack = ma->common.extack;
5134 
5135 	if (ma->common.prio != 1) {
5136 		NL_SET_ERR_MSG_MOD(extack, "only priority 1 is supported");
5137 		return -EINVAL;
5138 	}
5139 
5140 	return scan_tc_matchall_fdb_actions(priv, &ma->rule->action, extack);
5141 }
5142 
mlx5e_tc_delete_matchall(struct mlx5e_priv * priv,struct tc_cls_matchall_offload * ma)5143 int mlx5e_tc_delete_matchall(struct mlx5e_priv *priv,
5144 			     struct tc_cls_matchall_offload *ma)
5145 {
5146 	struct netlink_ext_ack *extack = ma->common.extack;
5147 
5148 	return apply_police_params(priv, 0, extack);
5149 }
5150 
mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv * priv,struct mlx5e_priv * peer_priv)5151 static void mlx5e_tc_hairpin_update_dead_peer(struct mlx5e_priv *priv,
5152 					      struct mlx5e_priv *peer_priv)
5153 {
5154 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5155 	struct mlx5_core_dev *peer_mdev = peer_priv->mdev;
5156 	struct mlx5e_hairpin_entry *hpe, *tmp;
5157 	LIST_HEAD(init_wait_list);
5158 	u16 peer_vhca_id;
5159 	int bkt;
5160 
5161 	if (!mlx5e_same_hw_devs(priv, peer_priv))
5162 		return;
5163 
5164 	peer_vhca_id = MLX5_CAP_GEN(peer_mdev, vhca_id);
5165 
5166 	mutex_lock(&tc->hairpin_tbl_lock);
5167 	hash_for_each(tc->hairpin_tbl, bkt, hpe, hairpin_hlist)
5168 		if (refcount_inc_not_zero(&hpe->refcnt))
5169 			list_add(&hpe->dead_peer_wait_list, &init_wait_list);
5170 	mutex_unlock(&tc->hairpin_tbl_lock);
5171 
5172 	list_for_each_entry_safe(hpe, tmp, &init_wait_list, dead_peer_wait_list) {
5173 		wait_for_completion(&hpe->res_ready);
5174 		if (!IS_ERR_OR_NULL(hpe->hp) && hpe->peer_vhca_id == peer_vhca_id)
5175 			mlx5_core_hairpin_clear_dead_peer(hpe->hp->pair);
5176 
5177 		mlx5e_hairpin_put(priv, hpe);
5178 	}
5179 }
5180 
mlx5e_tc_netdev_event(struct notifier_block * this,unsigned long event,void * ptr)5181 static int mlx5e_tc_netdev_event(struct notifier_block *this,
5182 				 unsigned long event, void *ptr)
5183 {
5184 	struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
5185 	struct mlx5e_priv *peer_priv;
5186 	struct mlx5e_tc_table *tc;
5187 	struct mlx5e_priv *priv;
5188 
5189 	if (ndev->netdev_ops != &mlx5e_netdev_ops ||
5190 	    event != NETDEV_UNREGISTER ||
5191 	    ndev->reg_state == NETREG_REGISTERED)
5192 		return NOTIFY_DONE;
5193 
5194 	tc = container_of(this, struct mlx5e_tc_table, netdevice_nb);
5195 	priv = tc->priv;
5196 	peer_priv = netdev_priv(ndev);
5197 	if (priv == peer_priv ||
5198 	    !(priv->netdev->features & NETIF_F_HW_TC))
5199 		return NOTIFY_DONE;
5200 
5201 	mlx5e_tc_hairpin_update_dead_peer(priv, peer_priv);
5202 
5203 	return NOTIFY_DONE;
5204 }
5205 
mlx5e_tc_nic_create_miss_table(struct mlx5e_priv * priv)5206 static int mlx5e_tc_nic_create_miss_table(struct mlx5e_priv *priv)
5207 {
5208 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5209 	struct mlx5_flow_table **ft = &tc->miss_t;
5210 	struct mlx5_flow_table_attr ft_attr = {};
5211 	struct mlx5_flow_namespace *ns;
5212 	int err = 0;
5213 
5214 	ft_attr.max_fte = 1;
5215 	ft_attr.autogroup.max_num_groups = 1;
5216 	ft_attr.level = MLX5E_TC_MISS_LEVEL;
5217 	ft_attr.prio = 0;
5218 	ns = mlx5_get_flow_namespace(priv->mdev, MLX5_FLOW_NAMESPACE_KERNEL);
5219 
5220 	*ft = mlx5_create_auto_grouped_flow_table(ns, &ft_attr);
5221 	if (IS_ERR(*ft)) {
5222 		err = PTR_ERR(*ft);
5223 		netdev_err(priv->netdev, "failed to create tc nic miss table err=%d\n", err);
5224 	}
5225 
5226 	return err;
5227 }
5228 
mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv * priv)5229 static void mlx5e_tc_nic_destroy_miss_table(struct mlx5e_priv *priv)
5230 {
5231 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5232 
5233 	mlx5_destroy_flow_table(tc->miss_t);
5234 }
5235 
mlx5e_tc_nic_init(struct mlx5e_priv * priv)5236 int mlx5e_tc_nic_init(struct mlx5e_priv *priv)
5237 {
5238 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5239 	struct mlx5_core_dev *dev = priv->mdev;
5240 	struct mapping_ctx *chains_mapping;
5241 	struct mlx5_chains_attr attr = {};
5242 	u64 mapping_id;
5243 	int err;
5244 
5245 	mlx5e_mod_hdr_tbl_init(&tc->mod_hdr);
5246 	mutex_init(&tc->t_lock);
5247 	mutex_init(&tc->hairpin_tbl_lock);
5248 	hash_init(tc->hairpin_tbl);
5249 	tc->priv = priv;
5250 
5251 	err = rhashtable_init(&tc->ht, &tc_ht_params);
5252 	if (err)
5253 		return err;
5254 
5255 	lockdep_set_class(&tc->ht.mutex, &tc_ht_lock_key);
5256 	lockdep_init_map(&tc->ht.run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5257 
5258 	mapping_id = mlx5_query_nic_system_image_guid(dev);
5259 
5260 	chains_mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_CHAIN,
5261 					       sizeof(struct mlx5_mapped_obj),
5262 					       MLX5E_TC_TABLE_CHAIN_TAG_MASK, true);
5263 
5264 	if (IS_ERR(chains_mapping)) {
5265 		err = PTR_ERR(chains_mapping);
5266 		goto err_mapping;
5267 	}
5268 	tc->mapping = chains_mapping;
5269 
5270 	err = mlx5e_tc_nic_create_miss_table(priv);
5271 	if (err)
5272 		goto err_chains;
5273 
5274 	if (MLX5_CAP_FLOWTABLE_NIC_RX(priv->mdev, ignore_flow_level))
5275 		attr.flags = MLX5_CHAINS_AND_PRIOS_SUPPORTED |
5276 			MLX5_CHAINS_IGNORE_FLOW_LEVEL_SUPPORTED;
5277 	attr.ns = MLX5_FLOW_NAMESPACE_KERNEL;
5278 	attr.max_grp_num = MLX5E_TC_TABLE_NUM_GROUPS;
5279 	attr.default_ft = tc->miss_t;
5280 	attr.mapping = chains_mapping;
5281 	attr.fs_base_prio = MLX5E_TC_PRIO;
5282 
5283 	tc->chains = mlx5_chains_create(dev, &attr);
5284 	if (IS_ERR(tc->chains)) {
5285 		err = PTR_ERR(tc->chains);
5286 		goto err_miss;
5287 	}
5288 
5289 	mlx5_chains_print_info(tc->chains);
5290 
5291 	tc->post_act = mlx5e_tc_post_act_init(priv, tc->chains, MLX5_FLOW_NAMESPACE_KERNEL);
5292 	tc->ct = mlx5_tc_ct_init(priv, tc->chains, &tc->mod_hdr,
5293 				 MLX5_FLOW_NAMESPACE_KERNEL, tc->post_act);
5294 
5295 	tc->netdevice_nb.notifier_call = mlx5e_tc_netdev_event;
5296 	err = register_netdevice_notifier_dev_net(priv->netdev,
5297 						  &tc->netdevice_nb,
5298 						  &tc->netdevice_nn);
5299 	if (err) {
5300 		tc->netdevice_nb.notifier_call = NULL;
5301 		mlx5_core_warn(priv->mdev, "Failed to register netdev notifier\n");
5302 		goto err_reg;
5303 	}
5304 
5305 	mlx5e_tc_debugfs_init(tc, mlx5e_fs_get_debugfs_root(priv->fs));
5306 
5307 	tc->action_stats_handle = mlx5e_tc_act_stats_create();
5308 	if (IS_ERR(tc->action_stats_handle)) {
5309 		err = PTR_ERR(tc->action_stats_handle);
5310 		goto err_act_stats;
5311 	}
5312 
5313 	return 0;
5314 
5315 err_act_stats:
5316 	unregister_netdevice_notifier_dev_net(priv->netdev,
5317 					      &tc->netdevice_nb,
5318 					      &tc->netdevice_nn);
5319 err_reg:
5320 	mlx5_tc_ct_clean(tc->ct);
5321 	mlx5e_tc_post_act_destroy(tc->post_act);
5322 	mlx5_chains_destroy(tc->chains);
5323 err_miss:
5324 	mlx5e_tc_nic_destroy_miss_table(priv);
5325 err_chains:
5326 	mapping_destroy(chains_mapping);
5327 err_mapping:
5328 	rhashtable_destroy(&tc->ht);
5329 	return err;
5330 }
5331 
_mlx5e_tc_del_flow(void * ptr,void * arg)5332 static void _mlx5e_tc_del_flow(void *ptr, void *arg)
5333 {
5334 	struct mlx5e_tc_flow *flow = ptr;
5335 	struct mlx5e_priv *priv = flow->priv;
5336 
5337 	mlx5e_tc_del_flow(priv, flow);
5338 	kfree(flow);
5339 }
5340 
mlx5e_tc_nic_cleanup(struct mlx5e_priv * priv)5341 void mlx5e_tc_nic_cleanup(struct mlx5e_priv *priv)
5342 {
5343 	struct mlx5e_tc_table *tc = mlx5e_fs_get_tc(priv->fs);
5344 
5345 	debugfs_remove_recursive(tc->dfs_root);
5346 
5347 	if (tc->netdevice_nb.notifier_call)
5348 		unregister_netdevice_notifier_dev_net(priv->netdev,
5349 						      &tc->netdevice_nb,
5350 						      &tc->netdevice_nn);
5351 
5352 	mlx5e_mod_hdr_tbl_destroy(&tc->mod_hdr);
5353 	mutex_destroy(&tc->hairpin_tbl_lock);
5354 
5355 	rhashtable_free_and_destroy(&tc->ht, _mlx5e_tc_del_flow, NULL);
5356 
5357 	if (!IS_ERR_OR_NULL(tc->t)) {
5358 		mlx5_chains_put_table(tc->chains, 0, 1, MLX5E_TC_FT_LEVEL);
5359 		tc->t = NULL;
5360 	}
5361 	mutex_destroy(&tc->t_lock);
5362 
5363 	mlx5_tc_ct_clean(tc->ct);
5364 	mlx5e_tc_post_act_destroy(tc->post_act);
5365 	mapping_destroy(tc->mapping);
5366 	mlx5_chains_destroy(tc->chains);
5367 	mlx5e_tc_nic_destroy_miss_table(priv);
5368 	mlx5e_tc_act_stats_free(tc->action_stats_handle);
5369 }
5370 
mlx5e_tc_ht_init(struct rhashtable * tc_ht)5371 int mlx5e_tc_ht_init(struct rhashtable *tc_ht)
5372 {
5373 	int err;
5374 
5375 	err = rhashtable_init(tc_ht, &tc_ht_params);
5376 	if (err)
5377 		return err;
5378 
5379 	lockdep_set_class(&tc_ht->mutex, &tc_ht_lock_key);
5380 	lockdep_init_map(&tc_ht->run_work.lockdep_map, "tc_ht_wq_key", &tc_ht_wq_key, 0);
5381 
5382 	return 0;
5383 }
5384 
mlx5e_tc_ht_cleanup(struct rhashtable * tc_ht)5385 void mlx5e_tc_ht_cleanup(struct rhashtable *tc_ht)
5386 {
5387 	rhashtable_free_and_destroy(tc_ht, _mlx5e_tc_del_flow, NULL);
5388 }
5389 
mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv * uplink_priv)5390 int mlx5e_tc_esw_init(struct mlx5_rep_uplink_priv *uplink_priv)
5391 {
5392 	const size_t sz_enc_opts = sizeof(struct tunnel_match_enc_opts);
5393 	struct netdev_phys_item_id ppid;
5394 	struct mlx5e_rep_priv *rpriv;
5395 	struct mapping_ctx *mapping;
5396 	struct mlx5_eswitch *esw;
5397 	struct mlx5e_priv *priv;
5398 	u64 mapping_id, key;
5399 	int err = 0;
5400 
5401 	rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5402 	priv = netdev_priv(rpriv->netdev);
5403 	esw = priv->mdev->priv.eswitch;
5404 
5405 	uplink_priv->post_act = mlx5e_tc_post_act_init(priv, esw_chains(esw),
5406 						       MLX5_FLOW_NAMESPACE_FDB);
5407 	uplink_priv->ct_priv = mlx5_tc_ct_init(netdev_priv(priv->netdev),
5408 					       esw_chains(esw),
5409 					       &esw->offloads.mod_hdr,
5410 					       MLX5_FLOW_NAMESPACE_FDB,
5411 					       uplink_priv->post_act);
5412 
5413 	uplink_priv->int_port_priv = mlx5e_tc_int_port_init(netdev_priv(priv->netdev));
5414 
5415 	uplink_priv->tc_psample = mlx5e_tc_sample_init(esw, uplink_priv->post_act);
5416 
5417 	mapping_id = mlx5_query_nic_system_image_guid(esw->dev);
5418 
5419 	mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL,
5420 					sizeof(struct tunnel_match_key),
5421 					TUNNEL_INFO_BITS_MASK, true);
5422 
5423 	if (IS_ERR(mapping)) {
5424 		err = PTR_ERR(mapping);
5425 		goto err_tun_mapping;
5426 	}
5427 	uplink_priv->tunnel_mapping = mapping;
5428 
5429 	/* Two last values are reserved for stack devices slow path table mark
5430 	 * and bridge ingress push mark.
5431 	 */
5432 	mapping = mapping_create_for_id(mapping_id, MAPPING_TYPE_TUNNEL_ENC_OPTS,
5433 					sz_enc_opts, ENC_OPTS_BITS_MASK - 2, true);
5434 	if (IS_ERR(mapping)) {
5435 		err = PTR_ERR(mapping);
5436 		goto err_enc_opts_mapping;
5437 	}
5438 	uplink_priv->tunnel_enc_opts_mapping = mapping;
5439 
5440 	uplink_priv->encap = mlx5e_tc_tun_init(priv);
5441 	if (IS_ERR(uplink_priv->encap)) {
5442 		err = PTR_ERR(uplink_priv->encap);
5443 		goto err_register_fib_notifier;
5444 	}
5445 
5446 	uplink_priv->action_stats_handle = mlx5e_tc_act_stats_create();
5447 	if (IS_ERR(uplink_priv->action_stats_handle)) {
5448 		err = PTR_ERR(uplink_priv->action_stats_handle);
5449 		goto err_action_counter;
5450 	}
5451 
5452 	err = dev_get_port_parent_id(priv->netdev, &ppid, false);
5453 	if (!err) {
5454 		memcpy(&key, &ppid.id, sizeof(key));
5455 		mlx5_esw_offloads_devcom_init(esw, key);
5456 	}
5457 
5458 	return 0;
5459 
5460 err_action_counter:
5461 	mlx5e_tc_tun_cleanup(uplink_priv->encap);
5462 err_register_fib_notifier:
5463 	mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5464 err_enc_opts_mapping:
5465 	mapping_destroy(uplink_priv->tunnel_mapping);
5466 err_tun_mapping:
5467 	mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5468 	mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5469 	mlx5_tc_ct_clean(uplink_priv->ct_priv);
5470 	netdev_warn(priv->netdev,
5471 		    "Failed to initialize tc (eswitch), err: %d", err);
5472 	mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5473 	return err;
5474 }
5475 
mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv * uplink_priv)5476 void mlx5e_tc_esw_cleanup(struct mlx5_rep_uplink_priv *uplink_priv)
5477 {
5478 	struct mlx5e_rep_priv *rpriv;
5479 	struct mlx5_eswitch *esw;
5480 	struct mlx5e_priv *priv;
5481 
5482 	rpriv = container_of(uplink_priv, struct mlx5e_rep_priv, uplink_priv);
5483 	priv = netdev_priv(rpriv->netdev);
5484 	esw = priv->mdev->priv.eswitch;
5485 
5486 	mlx5_esw_offloads_devcom_cleanup(esw);
5487 
5488 	mlx5e_tc_tun_cleanup(uplink_priv->encap);
5489 
5490 	mapping_destroy(uplink_priv->tunnel_enc_opts_mapping);
5491 	mapping_destroy(uplink_priv->tunnel_mapping);
5492 
5493 	mlx5e_tc_sample_cleanup(uplink_priv->tc_psample);
5494 	mlx5e_tc_int_port_cleanup(uplink_priv->int_port_priv);
5495 	mlx5_tc_ct_clean(uplink_priv->ct_priv);
5496 	mlx5e_flow_meters_cleanup(uplink_priv->flow_meters);
5497 	mlx5e_tc_post_act_destroy(uplink_priv->post_act);
5498 	mlx5e_tc_act_stats_free(uplink_priv->action_stats_handle);
5499 }
5500 
mlx5e_tc_num_filters(struct mlx5e_priv * priv,unsigned long flags)5501 int mlx5e_tc_num_filters(struct mlx5e_priv *priv, unsigned long flags)
5502 {
5503 	struct rhashtable *tc_ht = get_tc_ht(priv, flags);
5504 
5505 	return atomic_read(&tc_ht->nelems);
5506 }
5507 
mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch * esw)5508 void mlx5e_tc_clean_fdb_peer_flows(struct mlx5_eswitch *esw)
5509 {
5510 	struct mlx5e_tc_flow *flow, *tmp;
5511 	int i;
5512 
5513 	for (i = 0; i < MLX5_MAX_PORTS; i++) {
5514 		if (i == mlx5_get_dev_index(esw->dev))
5515 			continue;
5516 		list_for_each_entry_safe(flow, tmp, &esw->offloads.peer_flows[i], peer[i])
5517 			mlx5e_tc_del_fdb_peers_flow(flow);
5518 	}
5519 }
5520 
mlx5e_tc_reoffload_flows_work(struct work_struct * work)5521 void mlx5e_tc_reoffload_flows_work(struct work_struct *work)
5522 {
5523 	struct mlx5_rep_uplink_priv *rpriv =
5524 		container_of(work, struct mlx5_rep_uplink_priv,
5525 			     reoffload_flows_work);
5526 	struct mlx5e_tc_flow *flow, *tmp;
5527 
5528 	mutex_lock(&rpriv->unready_flows_lock);
5529 	list_for_each_entry_safe(flow, tmp, &rpriv->unready_flows, unready) {
5530 		if (!mlx5e_tc_add_fdb_flow(flow->priv, flow, NULL))
5531 			unready_flow_del(flow);
5532 	}
5533 	mutex_unlock(&rpriv->unready_flows_lock);
5534 }
5535 
mlx5e_setup_tc_cls_flower(struct mlx5e_priv * priv,struct flow_cls_offload * cls_flower,unsigned long flags)5536 static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
5537 				     struct flow_cls_offload *cls_flower,
5538 				     unsigned long flags)
5539 {
5540 	switch (cls_flower->command) {
5541 	case FLOW_CLS_REPLACE:
5542 		return mlx5e_configure_flower(priv->netdev, priv, cls_flower,
5543 					      flags);
5544 	case FLOW_CLS_DESTROY:
5545 		return mlx5e_delete_flower(priv->netdev, priv, cls_flower,
5546 					   flags);
5547 	case FLOW_CLS_STATS:
5548 		return mlx5e_stats_flower(priv->netdev, priv, cls_flower,
5549 					  flags);
5550 	default:
5551 		return -EOPNOTSUPP;
5552 	}
5553 }
5554 
mlx5e_setup_tc_block_cb(enum tc_setup_type type,void * type_data,void * cb_priv)5555 int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
5556 			    void *cb_priv)
5557 {
5558 	unsigned long flags = MLX5_TC_FLAG(INGRESS);
5559 	struct mlx5e_priv *priv = cb_priv;
5560 
5561 	if (!priv->netdev || !netif_device_present(priv->netdev))
5562 		return -EOPNOTSUPP;
5563 
5564 	if (mlx5e_is_uplink_rep(priv))
5565 		flags |= MLX5_TC_FLAG(ESW_OFFLOAD);
5566 	else
5567 		flags |= MLX5_TC_FLAG(NIC_OFFLOAD);
5568 
5569 	switch (type) {
5570 	case TC_SETUP_CLSFLOWER:
5571 		return mlx5e_setup_tc_cls_flower(priv, type_data, flags);
5572 	default:
5573 		return -EOPNOTSUPP;
5574 	}
5575 }
5576 
mlx5e_tc_restore_tunnel(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5e_tc_update_priv * tc_priv,u32 tunnel_id)5577 static bool mlx5e_tc_restore_tunnel(struct mlx5e_priv *priv, struct sk_buff *skb,
5578 				    struct mlx5e_tc_update_priv *tc_priv,
5579 				    u32 tunnel_id)
5580 {
5581 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5582 	struct tunnel_match_enc_opts enc_opts = {};
5583 	struct mlx5_rep_uplink_priv *uplink_priv;
5584 	IP_TUNNEL_DECLARE_FLAGS(flags) = { };
5585 	struct mlx5e_rep_priv *uplink_rpriv;
5586 	struct metadata_dst *tun_dst;
5587 	struct tunnel_match_key key;
5588 	u32 tun_id, enc_opts_id;
5589 	struct net_device *dev;
5590 	int err;
5591 
5592 	__set_bit(IP_TUNNEL_KEY_BIT, flags);
5593 
5594 	enc_opts_id = tunnel_id & ENC_OPTS_BITS_MASK;
5595 	tun_id = tunnel_id >> ENC_OPTS_BITS;
5596 
5597 	if (!tun_id)
5598 		return true;
5599 
5600 	uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5601 	uplink_priv = &uplink_rpriv->uplink_priv;
5602 
5603 	err = mapping_find(uplink_priv->tunnel_mapping, tun_id, &key);
5604 	if (err) {
5605 		netdev_dbg(priv->netdev,
5606 			   "Couldn't find tunnel for tun_id: %d, err: %d\n",
5607 			   tun_id, err);
5608 		return false;
5609 	}
5610 
5611 	if (enc_opts_id) {
5612 		err = mapping_find(uplink_priv->tunnel_enc_opts_mapping,
5613 				   enc_opts_id, &enc_opts);
5614 		if (err) {
5615 			netdev_dbg(priv->netdev,
5616 				   "Couldn't find tunnel (opts) for tun_id: %d, err: %d\n",
5617 				   enc_opts_id, err);
5618 			return false;
5619 		}
5620 	}
5621 
5622 	switch (key.enc_control.addr_type) {
5623 	case FLOW_DISSECTOR_KEY_IPV4_ADDRS:
5624 		tun_dst = __ip_tun_set_dst(key.enc_ipv4.src, key.enc_ipv4.dst,
5625 					   key.enc_ip.tos, key.enc_ip.ttl,
5626 					   key.enc_tp.dst, flags,
5627 					   key32_to_tunnel_id(key.enc_key_id.keyid),
5628 					   enc_opts.key.len);
5629 		break;
5630 	case FLOW_DISSECTOR_KEY_IPV6_ADDRS:
5631 		tun_dst = __ipv6_tun_set_dst(&key.enc_ipv6.src, &key.enc_ipv6.dst,
5632 					     key.enc_ip.tos, key.enc_ip.ttl,
5633 					     key.enc_tp.dst, 0, flags,
5634 					     key32_to_tunnel_id(key.enc_key_id.keyid),
5635 					     enc_opts.key.len);
5636 		break;
5637 	default:
5638 		netdev_dbg(priv->netdev,
5639 			   "Couldn't restore tunnel, unsupported addr_type: %d\n",
5640 			   key.enc_control.addr_type);
5641 		return false;
5642 	}
5643 
5644 	if (!tun_dst) {
5645 		netdev_dbg(priv->netdev, "Couldn't restore tunnel, no tun_dst\n");
5646 		return false;
5647 	}
5648 
5649 	tun_dst->u.tun_info.key.tp_src = key.enc_tp.src;
5650 
5651 	if (enc_opts.key.len) {
5652 		ip_tunnel_flags_zero(flags);
5653 		if (enc_opts.key.dst_opt_type)
5654 			__set_bit(enc_opts.key.dst_opt_type, flags);
5655 
5656 		ip_tunnel_info_opts_set(&tun_dst->u.tun_info,
5657 					enc_opts.key.data,
5658 					enc_opts.key.len,
5659 					flags);
5660 	}
5661 
5662 	skb_dst_set(skb, (struct dst_entry *)tun_dst);
5663 	dev = dev_get_by_index(&init_net, key.filter_ifindex);
5664 	if (!dev) {
5665 		netdev_dbg(priv->netdev,
5666 			   "Couldn't find tunnel device with ifindex: %d\n",
5667 			   key.filter_ifindex);
5668 		return false;
5669 	}
5670 
5671 	/* Set fwd_dev so we do dev_put() after datapath */
5672 	tc_priv->fwd_dev = dev;
5673 
5674 	skb->dev = dev;
5675 
5676 	return true;
5677 }
5678 
mlx5e_tc_restore_skb_tc_meta(struct sk_buff * skb,struct mlx5_tc_ct_priv * ct_priv,struct mlx5_mapped_obj * mapped_obj,u32 zone_restore_id,u32 tunnel_id,struct mlx5e_tc_update_priv * tc_priv)5679 static bool mlx5e_tc_restore_skb_tc_meta(struct sk_buff *skb, struct mlx5_tc_ct_priv *ct_priv,
5680 					 struct mlx5_mapped_obj *mapped_obj, u32 zone_restore_id,
5681 					 u32 tunnel_id,  struct mlx5e_tc_update_priv *tc_priv)
5682 {
5683 	struct mlx5e_priv *priv = netdev_priv(skb->dev);
5684 	struct tc_skb_ext *tc_skb_ext;
5685 	u64 act_miss_cookie;
5686 	u32 chain;
5687 
5688 	chain = mapped_obj->type == MLX5_MAPPED_OBJ_CHAIN ? mapped_obj->chain : 0;
5689 	act_miss_cookie = mapped_obj->type == MLX5_MAPPED_OBJ_ACT_MISS ?
5690 			  mapped_obj->act_miss_cookie : 0;
5691 	if (chain || act_miss_cookie) {
5692 		if (!mlx5e_tc_ct_restore_flow(ct_priv, skb, zone_restore_id))
5693 			return false;
5694 
5695 		tc_skb_ext = tc_skb_ext_alloc(skb);
5696 		if (!tc_skb_ext) {
5697 			WARN_ON(1);
5698 			return false;
5699 		}
5700 
5701 		if (act_miss_cookie) {
5702 			tc_skb_ext->act_miss_cookie = act_miss_cookie;
5703 			tc_skb_ext->act_miss = 1;
5704 		} else {
5705 			tc_skb_ext->chain = chain;
5706 		}
5707 	}
5708 
5709 	if (tc_priv)
5710 		return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5711 
5712 	return true;
5713 }
5714 
mlx5e_tc_restore_skb_sample(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5_mapped_obj * mapped_obj,struct mlx5e_tc_update_priv * tc_priv)5715 static void mlx5e_tc_restore_skb_sample(struct mlx5e_priv *priv, struct sk_buff *skb,
5716 					struct mlx5_mapped_obj *mapped_obj,
5717 					struct mlx5e_tc_update_priv *tc_priv)
5718 {
5719 	if (!mlx5e_tc_restore_tunnel(priv, skb, tc_priv, mapped_obj->sample.tunnel_id)) {
5720 		netdev_dbg(priv->netdev,
5721 			   "Failed to restore tunnel info for sampled packet\n");
5722 		return;
5723 	}
5724 	mlx5e_tc_sample_skb(skb, mapped_obj);
5725 }
5726 
mlx5e_tc_restore_skb_int_port(struct mlx5e_priv * priv,struct sk_buff * skb,struct mlx5_mapped_obj * mapped_obj,struct mlx5e_tc_update_priv * tc_priv,u32 tunnel_id)5727 static bool mlx5e_tc_restore_skb_int_port(struct mlx5e_priv *priv, struct sk_buff *skb,
5728 					  struct mlx5_mapped_obj *mapped_obj,
5729 					  struct mlx5e_tc_update_priv *tc_priv,
5730 					  u32 tunnel_id)
5731 {
5732 	struct mlx5_eswitch *esw = priv->mdev->priv.eswitch;
5733 	struct mlx5_rep_uplink_priv *uplink_priv;
5734 	struct mlx5e_rep_priv *uplink_rpriv;
5735 	bool forward_tx = false;
5736 
5737 	/* Tunnel restore takes precedence over int port restore */
5738 	if (tunnel_id)
5739 		return mlx5e_tc_restore_tunnel(priv, skb, tc_priv, tunnel_id);
5740 
5741 	uplink_rpriv = mlx5_eswitch_get_uplink_priv(esw, REP_ETH);
5742 	uplink_priv = &uplink_rpriv->uplink_priv;
5743 
5744 	if (mlx5e_tc_int_port_dev_fwd(uplink_priv->int_port_priv, skb,
5745 				      mapped_obj->int_port_metadata, &forward_tx)) {
5746 		/* Set fwd_dev for future dev_put */
5747 		tc_priv->fwd_dev = skb->dev;
5748 		tc_priv->forward_tx = forward_tx;
5749 
5750 		return true;
5751 	}
5752 
5753 	return false;
5754 }
5755 
mlx5e_tc_update_skb(struct mlx5_cqe64 * cqe,struct sk_buff * skb,struct mapping_ctx * mapping_ctx,u32 mapped_obj_id,struct mlx5_tc_ct_priv * ct_priv,u32 zone_restore_id,u32 tunnel_id,struct mlx5e_tc_update_priv * tc_priv)5756 bool mlx5e_tc_update_skb(struct mlx5_cqe64 *cqe, struct sk_buff *skb,
5757 			 struct mapping_ctx *mapping_ctx, u32 mapped_obj_id,
5758 			 struct mlx5_tc_ct_priv *ct_priv,
5759 			 u32 zone_restore_id, u32 tunnel_id,
5760 			 struct mlx5e_tc_update_priv *tc_priv)
5761 {
5762 	struct mlx5e_priv *priv = netdev_priv(skb->dev);
5763 	struct mlx5_mapped_obj mapped_obj;
5764 	int err;
5765 
5766 	err = mapping_find(mapping_ctx, mapped_obj_id, &mapped_obj);
5767 	if (err) {
5768 		netdev_dbg(skb->dev,
5769 			   "Couldn't find mapped object for mapped_obj_id: %d, err: %d\n",
5770 			   mapped_obj_id, err);
5771 		return false;
5772 	}
5773 
5774 	switch (mapped_obj.type) {
5775 	case MLX5_MAPPED_OBJ_CHAIN:
5776 	case MLX5_MAPPED_OBJ_ACT_MISS:
5777 		return mlx5e_tc_restore_skb_tc_meta(skb, ct_priv, &mapped_obj, zone_restore_id,
5778 						    tunnel_id, tc_priv);
5779 	case MLX5_MAPPED_OBJ_SAMPLE:
5780 		mlx5e_tc_restore_skb_sample(priv, skb, &mapped_obj, tc_priv);
5781 		tc_priv->skb_done = true;
5782 		return true;
5783 	case MLX5_MAPPED_OBJ_INT_PORT_METADATA:
5784 		return mlx5e_tc_restore_skb_int_port(priv, skb, &mapped_obj, tc_priv, tunnel_id);
5785 	default:
5786 		netdev_dbg(priv->netdev, "Invalid mapped object type: %d\n", mapped_obj.type);
5787 		return false;
5788 	}
5789 
5790 	return false;
5791 }
5792 
mlx5e_tc_update_skb_nic(struct mlx5_cqe64 * cqe,struct sk_buff * skb)5793 bool mlx5e_tc_update_skb_nic(struct mlx5_cqe64 *cqe, struct sk_buff *skb)
5794 {
5795 	struct mlx5e_priv *priv = netdev_priv(skb->dev);
5796 	u32 mapped_obj_id, reg_b, zone_restore_id;
5797 	struct mlx5_tc_ct_priv *ct_priv;
5798 	struct mapping_ctx *mapping_ctx;
5799 	struct mlx5e_tc_table *tc;
5800 
5801 	reg_b = be32_to_cpu(cqe->ft_metadata);
5802 	tc = mlx5e_fs_get_tc(priv->fs);
5803 	mapped_obj_id = reg_b & MLX5E_TC_TABLE_CHAIN_TAG_MASK;
5804 	zone_restore_id = (reg_b >> MLX5_REG_MAPPING_MOFFSET(NIC_ZONE_RESTORE_TO_REG)) &
5805 			  ESW_ZONE_ID_MASK;
5806 	ct_priv = tc->ct;
5807 	mapping_ctx = tc->mapping;
5808 
5809 	return mlx5e_tc_update_skb(cqe, skb, mapping_ctx, mapped_obj_id, ct_priv, zone_restore_id,
5810 				   0, NULL);
5811 }
5812 
5813 static struct mapping_ctx *
mlx5e_get_priv_obj_mapping(struct mlx5e_priv * priv)5814 mlx5e_get_priv_obj_mapping(struct mlx5e_priv *priv)
5815 {
5816 	struct mlx5e_tc_table *tc;
5817 	struct mlx5_eswitch *esw;
5818 	struct mapping_ctx *ctx;
5819 
5820 	if (is_mdev_switchdev_mode(priv->mdev)) {
5821 		esw = priv->mdev->priv.eswitch;
5822 		ctx = esw->offloads.reg_c0_obj_pool;
5823 	} else {
5824 		tc = mlx5e_fs_get_tc(priv->fs);
5825 		ctx = tc->mapping;
5826 	}
5827 
5828 	return ctx;
5829 }
5830 
mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,u64 act_miss_cookie,u32 * act_miss_mapping)5831 int mlx5e_tc_action_miss_mapping_get(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5832 				     u64 act_miss_cookie, u32 *act_miss_mapping)
5833 {
5834 	struct mlx5_mapped_obj mapped_obj = {};
5835 	struct mlx5_eswitch *esw;
5836 	struct mapping_ctx *ctx;
5837 	int err;
5838 
5839 	ctx = mlx5e_get_priv_obj_mapping(priv);
5840 	mapped_obj.type = MLX5_MAPPED_OBJ_ACT_MISS;
5841 	mapped_obj.act_miss_cookie = act_miss_cookie;
5842 	err = mapping_add(ctx, &mapped_obj, act_miss_mapping);
5843 	if (err)
5844 		return err;
5845 
5846 	if (!is_mdev_switchdev_mode(priv->mdev))
5847 		return 0;
5848 
5849 	esw = priv->mdev->priv.eswitch;
5850 	attr->act_id_restore_rule = esw_add_restore_rule(esw, *act_miss_mapping);
5851 	if (IS_ERR(attr->act_id_restore_rule)) {
5852 		err = PTR_ERR(attr->act_id_restore_rule);
5853 		goto err_rule;
5854 	}
5855 
5856 	return 0;
5857 
5858 err_rule:
5859 	mapping_remove(ctx, *act_miss_mapping);
5860 	return err;
5861 }
5862 
mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv * priv,struct mlx5_flow_attr * attr,u32 act_miss_mapping)5863 void mlx5e_tc_action_miss_mapping_put(struct mlx5e_priv *priv, struct mlx5_flow_attr *attr,
5864 				      u32 act_miss_mapping)
5865 {
5866 	struct mapping_ctx *ctx = mlx5e_get_priv_obj_mapping(priv);
5867 
5868 	if (is_mdev_switchdev_mode(priv->mdev))
5869 		mlx5_del_flow_rules(attr->act_id_restore_rule);
5870 	mapping_remove(ctx, act_miss_mapping);
5871 }
5872