1 // SPDX-License-Identifier: MIT 2 // 3 // Copyright 2024 Advanced Micro Devices, Inc. 4 5 #ifndef __DML2_CORE_SHARED_TYPES_H__ 6 #define __DML2_CORE_SHARED_TYPES_H__ 7 8 #include "dml2_external_lib_deps.h" 9 #include "dml_top_display_cfg_types.h" 10 #include "dml_top_types.h" 11 12 #define __DML_VBA_DEBUG__ 13 #define __DML2_CALCS_MAX_VRATIO_PRE_OTO__ 4.0 //<brief max vratio for one-to-one prefetch bw scheduling 14 #define __DML2_CALCS_MAX_VRATIO_PRE_EQU__ 6.0 //<brief max vratio for equalized prefetch bw scheduling 15 #define __DML2_CALCS_MAX_VRATIO_PRE__ 8.0 //<brief max prefetch vratio register limit 16 17 #define __DML2_CALCS_DPP_INVALID__ 0 18 #define __DML2_CALCS_DCFCLK_FACTOR__ 1.15 //<brief fudge factor for min dcfclk calclation 19 #define __DML2_CALCS_PIPE_NO_PLANE__ 99 20 21 struct dml2_core_ip_params { 22 unsigned int vblank_nom_default_us; 23 unsigned int remote_iommu_outstanding_translations; 24 unsigned int rob_buffer_size_kbytes; 25 unsigned int config_return_buffer_size_in_kbytes; 26 unsigned int config_return_buffer_segment_size_in_kbytes; 27 unsigned int compressed_buffer_segment_size_in_kbytes; 28 unsigned int meta_fifo_size_in_kentries; 29 unsigned int dpte_buffer_size_in_pte_reqs_luma; 30 unsigned int dpte_buffer_size_in_pte_reqs_chroma; 31 unsigned int pixel_chunk_size_kbytes; 32 unsigned int alpha_pixel_chunk_size_kbytes; 33 unsigned int min_pixel_chunk_size_bytes; 34 unsigned int writeback_chunk_size_kbytes; 35 unsigned int line_buffer_size_bits; 36 unsigned int max_line_buffer_lines; 37 unsigned int writeback_interface_buffer_size_kbytes; 38 unsigned int max_num_dpp; 39 unsigned int max_num_otg; 40 unsigned int max_num_wb; 41 unsigned int max_dchub_pscl_bw_pix_per_clk; 42 unsigned int max_pscl_lb_bw_pix_per_clk; 43 unsigned int max_lb_vscl_bw_pix_per_clk; 44 unsigned int max_vscl_hscl_bw_pix_per_clk; 45 double max_hscl_ratio; 46 double max_vscl_ratio; 47 unsigned int max_hscl_taps; 48 unsigned int max_vscl_taps; 49 unsigned int num_dsc; 50 unsigned int maximum_dsc_bits_per_component; 51 unsigned int maximum_pixels_per_line_per_dsc_unit; 52 bool dsc422_native_support; 53 bool cursor_64bpp_support; 54 double dispclk_ramp_margin_percent; 55 unsigned int dppclk_delay_subtotal; 56 unsigned int dppclk_delay_scl; 57 unsigned int dppclk_delay_scl_lb_only; 58 unsigned int dppclk_delay_cnvc_formatter; 59 unsigned int dppclk_delay_cnvc_cursor; 60 unsigned int cursor_buffer_size; 61 unsigned int cursor_chunk_size; 62 unsigned int dispclk_delay_subtotal; 63 bool dynamic_metadata_vm_enabled; 64 unsigned int max_inter_dcn_tile_repeaters; 65 unsigned int max_num_hdmi_frl_outputs; 66 unsigned int max_num_dp2p0_outputs; 67 unsigned int max_num_dp2p0_streams; 68 bool dcc_supported; 69 bool ptoi_supported; 70 double writeback_max_hscl_ratio; 71 double writeback_max_vscl_ratio; 72 double writeback_min_hscl_ratio; 73 double writeback_min_vscl_ratio; 74 unsigned int writeback_max_hscl_taps; 75 unsigned int writeback_max_vscl_taps; 76 unsigned int writeback_line_buffer_buffer_size; 77 78 unsigned int words_per_channel; 79 bool imall_supported; 80 unsigned int max_flip_time_us; 81 unsigned int max_flip_time_lines; 82 unsigned int subvp_swath_height_margin_lines; 83 unsigned int subvp_fw_processing_delay_us; 84 unsigned int subvp_pstate_allow_width_us; 85 86 // MRQ 87 bool dcn_mrq_present; 88 unsigned int zero_size_buffer_entries; 89 unsigned int compbuf_reserved_space_zs; 90 unsigned int dcc_meta_buffer_size_bytes; 91 unsigned int meta_chunk_size_kbytes; 92 unsigned int min_meta_chunk_size_bytes; 93 94 unsigned int dchub_arb_to_ret_delay; // num of dcfclk 95 unsigned int hostvm_mode; 96 }; 97 98 struct dml2_core_internal_DmlPipe { 99 double Dppclk; 100 double Dispclk; 101 double PixelClock; 102 double DCFClkDeepSleep; 103 unsigned int DPPPerSurface; 104 bool ScalerEnabled; 105 enum dml2_rotation_angle RotationAngle; 106 bool mirrored; 107 unsigned int ViewportHeight; 108 unsigned int ViewportHeightC; 109 unsigned int BlockWidth256BytesY; 110 unsigned int BlockHeight256BytesY; 111 unsigned int BlockWidth256BytesC; 112 unsigned int BlockHeight256BytesC; 113 unsigned int BlockWidthY; 114 unsigned int BlockHeightY; 115 unsigned int BlockWidthC; 116 unsigned int BlockHeightC; 117 unsigned int InterlaceEnable; 118 unsigned int NumberOfCursors; 119 unsigned int VBlank; 120 unsigned int HTotal; 121 unsigned int HActive; 122 bool DCCEnable; 123 enum dml2_odm_mode ODMMode; 124 enum dml2_source_format_class SourcePixelFormat; 125 enum dml2_swizzle_mode SurfaceTiling; 126 unsigned int BytePerPixelY; 127 unsigned int BytePerPixelC; 128 bool ProgressiveToInterlaceUnitInOPP; 129 double VRatio; 130 double VRatioChroma; 131 unsigned int VTaps; 132 unsigned int VTapsChroma; 133 unsigned int PitchY; 134 unsigned int PitchC; 135 bool ViewportStationary; 136 unsigned int ViewportXStart; 137 unsigned int ViewportYStart; 138 unsigned int ViewportXStartC; 139 unsigned int ViewportYStartC; 140 bool FORCE_ONE_ROW_FOR_FRAME; 141 unsigned int SwathHeightY; 142 unsigned int SwathHeightC; 143 144 unsigned int DCCMetaPitchY; 145 unsigned int DCCMetaPitchC; 146 }; 147 148 enum dml2_core_internal_request_type { 149 dml2_core_internal_request_type_256_bytes = 0, 150 dml2_core_internal_request_type_128_bytes_non_contiguous = 1, 151 dml2_core_internal_request_type_128_bytes_contiguous = 2, 152 dml2_core_internal_request_type_na = 3 153 }; 154 enum dml2_core_internal_bw_type { 155 dml2_core_internal_bw_sdp = 0, 156 dml2_core_internal_bw_dram = 1, 157 dml2_core_internal_bw_max 158 }; 159 160 enum dml2_core_internal_soc_state_type { 161 dml2_core_internal_soc_state_sys_active = 0, 162 dml2_core_internal_soc_state_svp_prefetch = 1, 163 dml2_core_internal_soc_state_sys_idle = 2, 164 dml2_core_internal_soc_state_max 165 }; 166 167 enum dml2_core_internal_output_type { 168 dml2_core_internal_output_type_unknown = 0, 169 dml2_core_internal_output_type_dp = 1, 170 dml2_core_internal_output_type_edp = 2, 171 dml2_core_internal_output_type_dp2p0 = 3, 172 dml2_core_internal_output_type_hdmi = 4, 173 dml2_core_internal_output_type_hdmifrl = 5 174 }; 175 176 enum dml2_core_internal_output_type_rate { 177 dml2_core_internal_output_rate_unknown = 0, 178 dml2_core_internal_output_rate_dp_rate_hbr = 1, 179 dml2_core_internal_output_rate_dp_rate_hbr2 = 2, 180 dml2_core_internal_output_rate_dp_rate_hbr3 = 3, 181 dml2_core_internal_output_rate_dp_rate_uhbr10 = 4, 182 dml2_core_internal_output_rate_dp_rate_uhbr13p5 = 5, 183 dml2_core_internal_output_rate_dp_rate_uhbr20 = 6, 184 dml2_core_internal_output_rate_hdmi_rate_3x3 = 7, 185 dml2_core_internal_output_rate_hdmi_rate_6x3 = 8, 186 dml2_core_internal_output_rate_hdmi_rate_6x4 = 9, 187 dml2_core_internal_output_rate_hdmi_rate_8x4 = 10, 188 dml2_core_internal_output_rate_hdmi_rate_10x4 = 11, 189 dml2_core_internal_output_rate_hdmi_rate_12x4 = 12 190 }; 191 192 struct dml2_core_internal_watermarks { 193 double UrgentWatermark; 194 double WritebackUrgentWatermark; 195 double DRAMClockChangeWatermark; 196 double FCLKChangeWatermark; 197 double WritebackDRAMClockChangeWatermark; 198 double WritebackFCLKChangeWatermark; 199 double StutterExitWatermark; 200 double StutterEnterPlusExitWatermark; 201 double Z8StutterExitWatermark; 202 double Z8StutterEnterPlusExitWatermark; 203 double USRRetrainingWatermark; 204 double g6_temp_read_watermark_us; 205 }; 206 207 struct dml2_core_internal_mode_support_info { 208 //----------------- 209 // Mode Support Information 210 //----------------- 211 bool ImmediateFlipSupport; //<brief Means mode support immediate flip at the max combine setting; determine in mode support and used in mode programming 212 213 // Mode Support Reason/ 214 bool WritebackLatencySupport; 215 bool ScaleRatioAndTapsSupport; 216 bool SourceFormatPixelAndScanSupport; 217 bool P2IWith420; 218 bool DSCSlicesODMModeSupported; 219 bool DSCOnlyIfNecessaryWithBPP; 220 bool DSC422NativeNotSupported; 221 bool LinkRateDoesNotMatchDPVersion; 222 bool LinkRateForMultistreamNotIndicated; 223 bool BPPForMultistreamNotIndicated; 224 bool MultistreamWithHDMIOreDP; 225 bool MSOOrODMSplitWithNonDPLink; 226 bool NotEnoughLanesForMSO; 227 bool NumberOfOTGSupport; 228 bool NumberOfHDMIFRLSupport; 229 bool NumberOfDP2p0Support; 230 bool WritebackScaleRatioAndTapsSupport; 231 bool CursorSupport; 232 bool PitchSupport; 233 bool ViewportExceedsSurface; 234 //bool ImmediateFlipRequiredButTheRequirementForEachSurfaceIsNotSpecified; 235 bool ImmediateFlipOrHostVMAndPStateWithMALLFullFrameOrPhantomPipe; 236 bool InvalidCombinationOfMALLUseForPStateAndStaticScreen; 237 bool InvalidCombinationOfMALLUseForPState; 238 bool ExceededMALLSize; 239 bool EnoughWritebackUnits; 240 241 bool ExceededMultistreamSlots; 242 bool NotEnoughDSCUnits; 243 bool NotEnoughDSCSlices; 244 bool PixelsPerLinePerDSCUnitSupport; 245 bool DSCCLKRequiredMoreThanSupported; 246 bool DTBCLKRequiredMoreThanSupported; 247 bool LinkCapacitySupport; 248 249 bool ROBSupport; 250 bool OutstandingRequestsSupport; 251 bool OutstandingRequestsUrgencyAvoidance; 252 253 bool PTEBufferSizeNotExceeded; 254 bool DCCMetaBufferSizeNotExceeded; 255 enum dml2_dram_clock_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 256 enum dml2_fclock_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 257 bool global_dram_clock_change_supported; 258 bool global_fclk_change_supported; 259 bool USRRetrainingSupport; 260 bool AvgBandwidthSupport; 261 bool UrgVactiveBandwidthSupport; 262 bool EnoughUrgentLatencyHidingSupport; 263 bool PrefetchSupported; 264 bool PrefetchBandwidthSupported; 265 bool DynamicMetadataSupported; 266 bool VRatioInPrefetchSupported; 267 bool DISPCLK_DPPCLK_Support; 268 bool TotalAvailablePipesSupport; 269 bool ModeSupport; 270 bool ViewportSizeSupport; 271 272 bool MPCCombineEnable[DML2_MAX_PLANES]; /// <brief Indicate if the MPC Combine enable in the given state and optimize mpc combine setting 273 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; /// <brief ODM mode that is chosen in the mode check stage and will be used in mode programming stage 274 unsigned int DPPPerSurface[DML2_MAX_PLANES]; /// <brief How many DPPs are needed drive the surface to output. If MPCC or ODMC could be 2 or 4. 275 bool DSCEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the DSC is actually required; used in mode_programming 276 bool FECEnabled[DML2_MAX_PLANES]; /// <brief Indicate if the FEC is actually required 277 unsigned int NumberOfDSCSlices[DML2_MAX_PLANES]; /// <brief Indicate how many slices needed to support the given mode 278 279 double OutputBpp[DML2_MAX_PLANES]; 280 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 281 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 282 283 unsigned int AlignedYPitch[DML2_MAX_PLANES]; 284 unsigned int AlignedCPitch[DML2_MAX_PLANES]; 285 286 unsigned int AlignedDCCMetaPitchY[DML2_MAX_PLANES]; 287 unsigned int AlignedDCCMetaPitchC[DML2_MAX_PLANES]; 288 289 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 290 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 291 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 292 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 293 294 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 295 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 296 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 297 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 298 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 299 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 300 301 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 302 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 303 double urg_bandwidth_available_min_latency[dml2_core_internal_soc_state_max]; // min between SDP and DRAM, for latency evaluation 304 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 305 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 306 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm etc. 307 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 308 309 double avg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 310 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 311 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 312 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 313 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 314 315 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 316 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 317 318 bool avg_bandwidth_support_ok[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 319 320 double max_urgent_latency_us; 321 double avg_non_urgent_latency_us; 322 double avg_urgent_latency_us; 323 324 bool incorrect_imall_usage; 325 326 bool g6_temp_read_support; 327 328 struct dml2_core_internal_watermarks watermarks; 329 }; 330 331 struct dml2_core_internal_mode_support { 332 // Physical info; only using for programming 333 unsigned int state_idx; // <brief min clk state table index for mode support call 334 unsigned int qos_param_index; // to access the uclk dependent qos_parameters table 335 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 336 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 337 338 // Calculated Clocks 339 double RequiredDISPCLK; /// <brief Required DISPCLK; depends on pixel rate; odm mode etc. 340 double RequiredDPPCLK[DML2_MAX_PLANES]; 341 double RequiredDISPCLKPerSurface[DML2_MAX_PLANES]; 342 double RequiredDTBCLK[DML2_MAX_PLANES]; 343 344 double required_dscclk_freq_mhz[DML2_MAX_PLANES]; 345 346 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 347 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 348 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 349 double GlobalDPPCLK; /// <brief the Max DPPCLK freq out of all pipes 350 double uclk_freq_mhz; 351 double dram_bw_mbps; 352 double max_dram_bw_mbps; 353 354 double MaxFabricClock; /// <brief Basically just the clock freq at the min (or given) state 355 double MaxDCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 356 double max_dispclk_freq_mhz; 357 double max_dppclk_freq_mhz; 358 double max_dscclk_freq_mhz; 359 360 bool NoTimeForPrefetch[DML2_MAX_PLANES]; 361 bool NoTimeForDynamicMetadata[DML2_MAX_PLANES]; 362 363 // ---------------------------------- 364 // Mode Support Info and fail reason 365 // ---------------------------------- 366 struct dml2_core_internal_mode_support_info support; 367 368 // These are calculated before the ModeSupport and ModeProgram step 369 // They represent the bound for the return buffer sizing 370 unsigned int MaxTotalDETInKByte; 371 unsigned int NomDETInKByte; 372 unsigned int MinCompressedBufferSizeInKByte; 373 374 // Info obtained at the end of mode support calculations 375 // The reported info is at the "optimal" state and combine setting 376 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 377 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 378 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 379 unsigned int SwathHeightY[DML2_MAX_PLANES]; 380 unsigned int SwathHeightC[DML2_MAX_PLANES]; 381 unsigned int SwathWidthY[DML2_MAX_PLANES]; 382 unsigned int SwathWidthC[DML2_MAX_PLANES]; 383 384 // ---------------------------------- 385 // Intermediates/Informational 386 // ---------------------------------- 387 unsigned int TotImmediateFlipBytes; 388 bool DCCEnabledInAnySurface; 389 double WritebackRequiredDISPCLK; 390 double TimeCalc; 391 double TWait[DML2_MAX_PLANES]; 392 393 bool UnboundedRequestEnabled; 394 unsigned int CompressedBufferSizeInkByte; 395 double VRatioPreY[DML2_MAX_PLANES]; 396 double VRatioPreC[DML2_MAX_PLANES]; 397 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 398 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 399 unsigned int RequiredSlots[DML2_MAX_PLANES]; 400 unsigned int vm_bytes[DML2_MAX_PLANES]; 401 unsigned int DPTEBytesPerRow[DML2_MAX_PLANES]; 402 unsigned int PrefetchLinesY[DML2_MAX_PLANES]; 403 unsigned int PrefetchLinesC[DML2_MAX_PLANES]; 404 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 405 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; /// <brief Max number of swath for prefetch 406 unsigned int PrefillY[DML2_MAX_PLANES]; 407 unsigned int PrefillC[DML2_MAX_PLANES]; 408 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 409 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 410 411 bool use_one_row_for_frame[DML2_MAX_PLANES]; 412 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 413 414 double dst_y_prefetch[DML2_MAX_PLANES]; 415 double LinesForVM[DML2_MAX_PLANES]; 416 double LinesForDPTERow[DML2_MAX_PLANES]; 417 double SwathWidthYSingleDPP[DML2_MAX_PLANES]; 418 double SwathWidthCSingleDPP[DML2_MAX_PLANES]; 419 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 420 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 421 double BytePerPixelInDETY[DML2_MAX_PLANES]; 422 double BytePerPixelInDETC[DML2_MAX_PLANES]; 423 424 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 425 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 426 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 427 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 428 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 429 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 430 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 431 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 432 433 bool surf_linear128_l[DML2_MAX_PLANES]; 434 bool surf_linear128_c[DML2_MAX_PLANES]; 435 436 double PSCL_FACTOR[DML2_MAX_PLANES]; 437 double PSCL_FACTOR_CHROMA[DML2_MAX_PLANES]; 438 double MaximumSwathWidthLuma[DML2_MAX_PLANES]; 439 double MaximumSwathWidthChroma[DML2_MAX_PLANES]; 440 double Tno_bw[DML2_MAX_PLANES]; 441 double Tno_bw_flip[DML2_MAX_PLANES]; 442 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 443 double dst_y_per_row_flip[DML2_MAX_PLANES]; 444 double WritebackDelayTime[DML2_MAX_PLANES]; 445 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 446 unsigned int dpte_row_height[DML2_MAX_PLANES]; 447 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 448 double UrgLatency; 449 double TripToMemory; 450 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 451 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 452 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 453 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 454 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 455 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 456 double MaximumSwathWidthInLineBufferLuma; 457 double MaximumSwathWidthInLineBufferChroma; 458 double ExtraLatency; 459 double ExtraLatency_sr; 460 double ExtraLatencyPrefetch; 461 462 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 463 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 464 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; // overhead to request meta 465 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 466 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; // overhead to the imall or phantom pipe 467 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 468 469 // Backend 470 bool RequiresDSC[DML2_MAX_PLANES]; 471 bool RequiresFEC[DML2_MAX_PLANES]; 472 double OutputBpp[DML2_MAX_PLANES]; 473 unsigned int DSCDelay[DML2_MAX_PLANES]; 474 enum dml2_core_internal_output_type OutputType[DML2_MAX_PLANES]; 475 enum dml2_core_internal_output_type_rate OutputRate[DML2_MAX_PLANES]; 476 477 // Bandwidth Related Info 478 double BandwidthAvailableForImmediateFlip; 479 double SurfaceReadBandwidthLuma[DML2_MAX_PLANES]; // no dcc overhead, for the plane 480 double SurfaceReadBandwidthChroma[DML2_MAX_PLANES]; 481 double WriteBandwidth[DML2_MAX_PLANES]; 482 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 483 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 484 double cursor_bw[DML2_MAX_PLANES]; 485 double prefetch_cursor_bw[DML2_MAX_PLANES]; 486 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 487 double final_flip_bw[DML2_MAX_PLANES]; 488 double meta_row_bw[DML2_MAX_PLANES]; 489 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 490 double dpte_row_bw[DML2_MAX_PLANES]; 491 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 492 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 493 double surface_avg_vactive_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 494 double surface_peak_required_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 495 496 // Something that should be feedback to caller 497 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 498 unsigned int SurfaceSizeInMALL[DML2_MAX_PLANES]; 499 unsigned int NoOfDPP[DML2_MAX_PLANES]; 500 bool MPCCombine[DML2_MAX_PLANES]; 501 double dcfclk_deepsleep; 502 double MinDPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 503 bool SingleDPPViewportSizeSupportPerSurface[DML2_MAX_PLANES]; 504 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 505 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 506 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 507 bool PTEBufferSizeNotExceeded[DML2_MAX_PLANES]; 508 bool DCCMetaBufferSizeNotExceeded[DML2_MAX_PLANES]; 509 unsigned int TotalNumberOfActiveDPP; 510 unsigned int TotalNumberOfSingleDPPSurfaces; 511 unsigned int TotalNumberOfDCCActiveDPP; 512 unsigned int Total3dlutActive; 513 514 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 515 double VActiveLatencyHidingMargin[DML2_MAX_PLANES]; 516 double VActiveLatencyHidingUs[DML2_MAX_PLANES]; 517 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; 518 double dram_change_vactive_det_fill_delay_us[DML2_MAX_PLANES]; 519 520 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 521 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 522 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 523 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 524 525 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 526 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 527 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 528 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 529 530 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 531 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 532 bool lc_comb_mcache[DML2_MAX_PLANES]; 533 534 535 }; 536 537 /// @brief A mega structure that houses various info for model programming step. 538 struct dml2_core_internal_mode_program { 539 unsigned int qos_param_index; // to access the uclk dependent dpm table 540 unsigned int active_min_uclk_dpm_index; // to access the min_clk table 541 double FabricClock; /// <brief Basically just the clock freq at the min (or given) state 542 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting 543 double dram_bw_mbps; 544 double uclk_freq_mhz; 545 unsigned int NoOfDPP[DML2_MAX_PLANES]; 546 enum dml2_odm_mode ODMMode[DML2_MAX_PLANES]; 547 548 //------------- 549 // Intermediate/Informational 550 //------------- 551 double UrgentLatency; 552 double TripToMemory; 553 double MetaTripToMemory; 554 unsigned int VInitPreFillY[DML2_MAX_PLANES]; 555 unsigned int VInitPreFillC[DML2_MAX_PLANES]; 556 unsigned int MaxNumSwathY[DML2_MAX_PLANES]; 557 unsigned int MaxNumSwathC[DML2_MAX_PLANES]; 558 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 559 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 560 561 double BytePerPixelInDETY[DML2_MAX_PLANES]; 562 double BytePerPixelInDETC[DML2_MAX_PLANES]; 563 unsigned int BytePerPixelY[DML2_MAX_PLANES]; 564 unsigned int BytePerPixelC[DML2_MAX_PLANES]; 565 unsigned int SwathWidthY[DML2_MAX_PLANES]; 566 unsigned int SwathWidthC[DML2_MAX_PLANES]; 567 unsigned int req_per_swath_ub_l[DML2_MAX_PLANES]; 568 unsigned int req_per_swath_ub_c[DML2_MAX_PLANES]; 569 unsigned int SwathWidthSingleDPPY[DML2_MAX_PLANES]; 570 unsigned int SwathWidthSingleDPPC[DML2_MAX_PLANES]; 571 double SurfaceReadBandwidthLuma[DML2_MAX_PLANES]; 572 double SurfaceReadBandwidthChroma[DML2_MAX_PLANES]; 573 double excess_vactive_fill_bw_l[DML2_MAX_PLANES]; 574 double excess_vactive_fill_bw_c[DML2_MAX_PLANES]; 575 576 unsigned int PixelPTEBytesPerRow[DML2_MAX_PLANES]; 577 unsigned int vm_bytes[DML2_MAX_PLANES]; 578 unsigned int PrefetchSourceLinesY[DML2_MAX_PLANES]; 579 double RequiredPrefetchPixelDataBWLuma[DML2_MAX_PLANES]; 580 double RequiredPrefetchPixelDataBWChroma[DML2_MAX_PLANES]; 581 unsigned int PrefetchSourceLinesC[DML2_MAX_PLANES]; 582 double PSCL_THROUGHPUT[DML2_MAX_PLANES]; 583 double PSCL_THROUGHPUT_CHROMA[DML2_MAX_PLANES]; 584 unsigned int DSCDelay[DML2_MAX_PLANES]; 585 double DPPCLKUsingSingleDPP[DML2_MAX_PLANES]; 586 587 unsigned int Read256BlockHeightY[DML2_MAX_PLANES]; 588 unsigned int Read256BlockWidthY[DML2_MAX_PLANES]; 589 unsigned int Read256BlockHeightC[DML2_MAX_PLANES]; 590 unsigned int Read256BlockWidthC[DML2_MAX_PLANES]; 591 unsigned int MacroTileHeightY[DML2_MAX_PLANES]; 592 unsigned int MacroTileHeightC[DML2_MAX_PLANES]; 593 unsigned int MacroTileWidthY[DML2_MAX_PLANES]; 594 unsigned int MacroTileWidthC[DML2_MAX_PLANES]; 595 596 bool surf_linear128_l[DML2_MAX_PLANES]; 597 bool surf_linear128_c[DML2_MAX_PLANES]; 598 599 unsigned int SurfaceSizeInTheMALL[DML2_MAX_PLANES]; 600 double VRatioPrefetchY[DML2_MAX_PLANES]; 601 double VRatioPrefetchC[DML2_MAX_PLANES]; 602 double Tno_bw[DML2_MAX_PLANES]; 603 double Tno_bw_flip[DML2_MAX_PLANES]; 604 double final_flip_bw[DML2_MAX_PLANES]; 605 double prefetch_vmrow_bw[DML2_MAX_PLANES]; 606 double cursor_bw[DML2_MAX_PLANES]; 607 double prefetch_cursor_bw[DML2_MAX_PLANES]; 608 double WritebackDelay[DML2_MAX_PLANES]; 609 unsigned int dpte_row_height[DML2_MAX_PLANES]; 610 unsigned int dpte_row_height_linear[DML2_MAX_PLANES]; 611 unsigned int dpte_row_width_luma_ub[DML2_MAX_PLANES]; 612 unsigned int dpte_row_width_chroma_ub[DML2_MAX_PLANES]; 613 unsigned int dpte_row_height_chroma[DML2_MAX_PLANES]; 614 unsigned int dpte_row_height_linear_chroma[DML2_MAX_PLANES]; 615 unsigned int vm_group_bytes[DML2_MAX_PLANES]; 616 unsigned int dpte_group_bytes[DML2_MAX_PLANES]; 617 618 double dpte_row_bw[DML2_MAX_PLANES]; 619 double time_per_tdlut_group[DML2_MAX_PLANES]; 620 double UrgentBurstFactorCursor[DML2_MAX_PLANES]; 621 double UrgentBurstFactorCursorPre[DML2_MAX_PLANES]; 622 double UrgentBurstFactorLuma[DML2_MAX_PLANES]; 623 double UrgentBurstFactorLumaPre[DML2_MAX_PLANES]; 624 double UrgentBurstFactorChroma[DML2_MAX_PLANES]; 625 double UrgentBurstFactorChromaPre[DML2_MAX_PLANES]; 626 627 double meta_row_bw[DML2_MAX_PLANES]; 628 unsigned int meta_row_bytes[DML2_MAX_PLANES]; 629 unsigned int meta_req_width[DML2_MAX_PLANES]; 630 unsigned int meta_req_height[DML2_MAX_PLANES]; 631 unsigned int meta_row_width[DML2_MAX_PLANES]; 632 unsigned int meta_row_height[DML2_MAX_PLANES]; 633 unsigned int meta_req_width_chroma[DML2_MAX_PLANES]; 634 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 635 unsigned int meta_row_width_chroma[DML2_MAX_PLANES]; 636 unsigned int meta_req_height_chroma[DML2_MAX_PLANES]; 637 638 unsigned int swath_width_luma_ub[DML2_MAX_PLANES]; 639 unsigned int swath_width_chroma_ub[DML2_MAX_PLANES]; 640 unsigned int PixelPTEReqWidthY[DML2_MAX_PLANES]; 641 unsigned int PixelPTEReqHeightY[DML2_MAX_PLANES]; 642 unsigned int PTERequestSizeY[DML2_MAX_PLANES]; 643 unsigned int PixelPTEReqWidthC[DML2_MAX_PLANES]; 644 unsigned int PixelPTEReqHeightC[DML2_MAX_PLANES]; 645 unsigned int PTERequestSizeC[DML2_MAX_PLANES]; 646 647 double TWait[DML2_MAX_PLANES]; 648 double Tdmdl_vm[DML2_MAX_PLANES]; 649 double Tdmdl[DML2_MAX_PLANES]; 650 double TSetup[DML2_MAX_PLANES]; 651 unsigned int dpde0_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 652 unsigned int dpde0_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 653 654 unsigned int meta_pte_bytes_per_frame_ub_l[DML2_MAX_PLANES]; 655 unsigned int meta_pte_bytes_per_frame_ub_c[DML2_MAX_PLANES]; 656 657 bool UnboundedRequestEnabled; 658 unsigned int CompressedBufferSizeInkByte; 659 unsigned int compbuf_reserved_space_64b; 660 bool hw_debug5; 661 unsigned int dcfclk_deep_sleep_hysteresis; 662 unsigned int min_return_latency_in_dcfclk; 663 664 bool NotEnoughUrgentLatencyHiding[DML2_MAX_PLANES]; 665 bool NotEnoughUrgentLatencyHidingPre[DML2_MAX_PLANES]; 666 double ExtraLatency; 667 double ExtraLatency_sr; 668 double ExtraLatencyPrefetch; 669 bool PrefetchAndImmediateFlipSupported; 670 double TotalDataReadBandwidth; 671 double BandwidthAvailableForImmediateFlip; 672 bool NotEnoughTimeForDynamicMetadata[DML2_MAX_PLANES]; 673 674 bool use_one_row_for_frame[DML2_MAX_PLANES]; 675 bool use_one_row_for_frame_flip[DML2_MAX_PLANES]; 676 677 double TCalc; 678 unsigned int TotImmediateFlipBytes; 679 680 // ------------------- 681 // Output 682 // ------------------- 683 unsigned int pipe_plane[DML2_MAX_PLANES]; // <brief used mainly by dv to map the pipe inst to plane index within DML core; the plane idx of a pipe 684 unsigned int num_active_pipes; 685 686 bool NoTimeToPrefetch[DML2_MAX_PLANES]; // <brief Prefetch schedule calculation result 687 688 // Support 689 bool UrgVactiveBandwidthSupport; 690 bool PrefetchModeSupported; // <brief Is the prefetch mode (bandwidth and latency) supported 691 bool ImmediateFlipSupported; 692 bool ImmediateFlipSupportedForPipe[DML2_MAX_PLANES]; 693 694 // Clock 695 double Dcfclk; 696 double Dispclk; // <brief dispclk being used in mode programming 697 double Dppclk[DML2_MAX_PLANES]; // <brief dppclk being used in mode programming 698 double GlobalDPPCLK; 699 700 double DSCCLK[DML2_MAX_PLANES]; //< brief Required DSCCLK freq. Backend; not used in any subsequent calculations for now 701 double DCFCLKDeepSleep; 702 703 // ARB reg 704 bool DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 705 struct dml2_core_internal_watermarks Watermark; 706 707 // DCC compression control 708 unsigned int request_size_bytes_luma[DML2_MAX_PLANES]; 709 unsigned int request_size_bytes_chroma[DML2_MAX_PLANES]; 710 enum dml2_core_internal_request_type RequestLuma[DML2_MAX_PLANES]; 711 enum dml2_core_internal_request_type RequestChroma[DML2_MAX_PLANES]; 712 unsigned int DCCYMaxUncompressedBlock[DML2_MAX_PLANES]; 713 unsigned int DCCYMaxCompressedBlock[DML2_MAX_PLANES]; 714 unsigned int DCCYIndependentBlock[DML2_MAX_PLANES]; 715 unsigned int DCCCMaxUncompressedBlock[DML2_MAX_PLANES]; 716 unsigned int DCCCMaxCompressedBlock[DML2_MAX_PLANES]; 717 unsigned int DCCCIndependentBlock[DML2_MAX_PLANES]; 718 719 // Stutter Efficiency 720 double StutterEfficiency; 721 double StutterEfficiencyNotIncludingVBlank; 722 unsigned int NumberOfStutterBurstsPerFrame; 723 double Z8StutterEfficiency; 724 unsigned int Z8NumberOfStutterBurstsPerFrame; 725 double Z8StutterEfficiencyNotIncludingVBlank; 726 double StutterPeriod; 727 double Z8StutterEfficiencyBestCase; 728 unsigned int Z8NumberOfStutterBurstsPerFrameBestCase; 729 double Z8StutterEfficiencyNotIncludingVBlankBestCase; 730 double StutterPeriodBestCase; 731 732 // DLG TTU reg 733 double MIN_DST_Y_NEXT_START[DML2_MAX_PLANES]; 734 bool VREADY_AT_OR_AFTER_VSYNC[DML2_MAX_PLANES]; 735 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 736 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 737 double dst_y_prefetch[DML2_MAX_PLANES]; 738 double dst_y_per_vm_vblank[DML2_MAX_PLANES]; 739 double dst_y_per_row_vblank[DML2_MAX_PLANES]; 740 double dst_y_per_vm_flip[DML2_MAX_PLANES]; 741 double dst_y_per_row_flip[DML2_MAX_PLANES]; 742 double MinTTUVBlank[DML2_MAX_PLANES]; 743 double DisplayPipeLineDeliveryTimeLuma[DML2_MAX_PLANES]; 744 double DisplayPipeLineDeliveryTimeChroma[DML2_MAX_PLANES]; 745 double DisplayPipeLineDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 746 double DisplayPipeLineDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 747 double DisplayPipeRequestDeliveryTimeLuma[DML2_MAX_PLANES]; 748 double DisplayPipeRequestDeliveryTimeChroma[DML2_MAX_PLANES]; 749 double DisplayPipeRequestDeliveryTimeLumaPrefetch[DML2_MAX_PLANES]; 750 double DisplayPipeRequestDeliveryTimeChromaPrefetch[DML2_MAX_PLANES]; 751 unsigned int CursorDstXOffset[DML2_MAX_PLANES]; 752 unsigned int CursorDstYOffset[DML2_MAX_PLANES]; 753 unsigned int CursorChunkHDLAdjust[DML2_MAX_PLANES]; 754 755 double DST_Y_PER_PTE_ROW_NOM_L[DML2_MAX_PLANES]; 756 double DST_Y_PER_PTE_ROW_NOM_C[DML2_MAX_PLANES]; 757 double time_per_pte_group_nom_luma[DML2_MAX_PLANES]; 758 double time_per_pte_group_nom_chroma[DML2_MAX_PLANES]; 759 double time_per_pte_group_vblank_luma[DML2_MAX_PLANES]; 760 double time_per_pte_group_vblank_chroma[DML2_MAX_PLANES]; 761 double time_per_pte_group_flip_luma[DML2_MAX_PLANES]; 762 double time_per_pte_group_flip_chroma[DML2_MAX_PLANES]; 763 double TimePerVMGroupVBlank[DML2_MAX_PLANES]; 764 double TimePerVMGroupFlip[DML2_MAX_PLANES]; 765 double TimePerVMRequestVBlank[DML2_MAX_PLANES]; 766 double TimePerVMRequestFlip[DML2_MAX_PLANES]; 767 768 double DST_Y_PER_META_ROW_NOM_L[DML2_MAX_PLANES]; 769 double DST_Y_PER_META_ROW_NOM_C[DML2_MAX_PLANES]; 770 double TimePerMetaChunkNominal[DML2_MAX_PLANES]; 771 double TimePerChromaMetaChunkNominal[DML2_MAX_PLANES]; 772 double TimePerMetaChunkVBlank[DML2_MAX_PLANES]; 773 double TimePerChromaMetaChunkVBlank[DML2_MAX_PLANES]; 774 double TimePerMetaChunkFlip[DML2_MAX_PLANES]; 775 double TimePerChromaMetaChunkFlip[DML2_MAX_PLANES]; 776 777 double FractionOfUrgentBandwidth; 778 double FractionOfUrgentBandwidthImmediateFlip; 779 double FractionOfUrgentBandwidthMALL; 780 781 // RQ registers 782 bool PTE_BUFFER_MODE[DML2_MAX_PLANES]; 783 unsigned int BIGK_FRAGMENT_SIZE[DML2_MAX_PLANES]; 784 785 unsigned int SubViewportLinesNeededInMALL[DML2_MAX_PLANES]; 786 bool is_using_mall_for_ss[DML2_MAX_PLANES]; 787 788 // OTG 789 unsigned int VStartupMin[DML2_MAX_PLANES]; /// <brief Minimum vstartup to meet the prefetch schedule (i.e. the prefetch solution can be found at this vstartup time); not the actual global sync vstartup pos. 790 unsigned int VStartup[DML2_MAX_PLANES]; /// <brief The vstartup value for OTG programming (will set to max vstartup; but now bounded by min(vblank_nom. actual vblank)) 791 unsigned int VUpdateOffsetPix[DML2_MAX_PLANES]; 792 unsigned int VUpdateWidthPix[DML2_MAX_PLANES]; 793 unsigned int VReadyOffsetPix[DML2_MAX_PLANES]; 794 unsigned int pstate_keepout_dst_lines[DML2_MAX_PLANES]; 795 796 // Latency and Support 797 double MaxActiveFCLKChangeLatencySupported; 798 bool USRRetrainingSupport; 799 bool g6_temp_read_support; 800 enum dml2_fclock_change_support FCLKChangeSupport[DML2_MAX_PLANES]; 801 enum dml2_dram_clock_change_support DRAMClockChangeSupport[DML2_MAX_PLANES]; 802 bool global_dram_clock_change_supported; 803 bool global_fclk_change_supported; 804 double MaxActiveDRAMClockChangeLatencySupported[DML2_MAX_PLANES]; 805 double WritebackAllowFCLKChangeEndPosition[DML2_MAX_PLANES]; 806 double WritebackAllowDRAMClockChangeEndPosition[DML2_MAX_PLANES]; 807 808 // buffer sizing 809 unsigned int DETBufferSizeInKByte[DML2_MAX_PLANES]; // <brief Recommended DET size configuration for this plane. All pipes under this plane should program the DET buffer size to the calculated value. 810 unsigned int DETBufferSizeY[DML2_MAX_PLANES]; 811 unsigned int DETBufferSizeC[DML2_MAX_PLANES]; 812 unsigned int SwathHeightY[DML2_MAX_PLANES]; 813 unsigned int SwathHeightC[DML2_MAX_PLANES]; 814 815 double urg_vactive_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // active bandwidth, scaled by urg burst factor 816 double urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor 817 double urg_bandwidth_required_qual[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth, scaled by urg burst factor, use qual_row_bw 818 double urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // include vm, prefetch, active bandwidth + flip 819 double non_urg_bandwidth_required[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; // same as urg_bandwidth, except not scaled by urg burst factor 820 double non_urg_bandwidth_required_flip[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 821 822 double avg_bandwidth_available_min[dml2_core_internal_soc_state_max]; 823 double avg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 824 double urg_bandwidth_available_min[dml2_core_internal_soc_state_max]; // min between SDP and DRAM 825 double urg_bandwidth_available[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 826 double urg_bandwidth_available_vm_only[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_vm_only bw, sdp has no different derate for vm/non-vm traffic etc. 827 double urg_bandwidth_available_pixel_and_vm[dml2_core_internal_soc_state_max]; // the min of sdp bw and dram_pixel_and_vm bw, sdp has no different derate for vm/non-vm etc. 828 829 double dcc_dram_bw_nom_overhead_factor_p0[DML2_MAX_PLANES]; 830 double dcc_dram_bw_nom_overhead_factor_p1[DML2_MAX_PLANES]; 831 double dcc_dram_bw_pref_overhead_factor_p0[DML2_MAX_PLANES]; 832 double dcc_dram_bw_pref_overhead_factor_p1[DML2_MAX_PLANES]; 833 double mall_prefetch_sdp_overhead_factor[DML2_MAX_PLANES]; 834 double mall_prefetch_dram_overhead_factor[DML2_MAX_PLANES]; 835 836 unsigned int num_mcaches_l[DML2_MAX_PLANES]; 837 unsigned int mcache_row_bytes_l[DML2_MAX_PLANES]; 838 unsigned int mcache_offsets_l[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 839 unsigned int mcache_shift_granularity_l[DML2_MAX_PLANES]; 840 841 unsigned int num_mcaches_c[DML2_MAX_PLANES]; 842 unsigned int mcache_row_bytes_c[DML2_MAX_PLANES]; 843 unsigned int mcache_offsets_c[DML2_MAX_PLANES][DML2_MAX_MCACHES + 1]; 844 unsigned int mcache_shift_granularity_c[DML2_MAX_PLANES]; 845 846 bool mall_comb_mcache_l[DML2_MAX_PLANES]; 847 bool mall_comb_mcache_c[DML2_MAX_PLANES]; 848 bool lc_comb_mcache[DML2_MAX_PLANES]; 849 }; 850 851 struct dml2_core_internal_SOCParametersList { 852 double UrgentLatency; 853 double ExtraLatency_sr; 854 double ExtraLatency; 855 double WritebackLatency; 856 double DRAMClockChangeLatency; 857 double FCLKChangeLatency; 858 double SRExitTime; 859 double SREnterPlusExitTime; 860 double SRExitZ8Time; 861 double SREnterPlusExitZ8Time; 862 double USRRetrainingLatency; 863 double SMNLatency; 864 double g6_temp_read_blackout_us; 865 double max_urgent_latency_us; 866 double df_response_time_us; 867 enum dml2_qos_param_type qos_type; 868 }; 869 870 struct dml2_core_calcs_mode_support_locals { 871 double PixelClockBackEnd[DML2_MAX_PLANES]; 872 double OutputBpp[DML2_MAX_PLANES]; 873 874 unsigned int meta_row_height_luma[DML2_MAX_PLANES]; 875 unsigned int meta_row_height_chroma[DML2_MAX_PLANES]; 876 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 877 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 878 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 879 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 880 881 bool dummy_boolean[3]; 882 unsigned int dummy_integer[3]; 883 unsigned int dummy_integer_array[36][DML2_MAX_PLANES]; 884 enum dml2_odm_mode dummy_odm_mode[DML2_MAX_PLANES]; 885 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 886 double dummy_single[3]; 887 double dummy_single_array[DML2_MAX_PLANES]; 888 struct dml2_core_internal_watermarks dummy_watermark; 889 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 890 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 891 892 unsigned int MaximumVStartup[DML2_MAX_PLANES]; 893 unsigned int DSTYAfterScaler[DML2_MAX_PLANES]; 894 unsigned int DSTXAfterScaler[DML2_MAX_PLANES]; 895 struct dml2_core_internal_SOCParametersList mSOCParameters; 896 struct dml2_core_internal_DmlPipe myPipe; 897 struct dml2_core_internal_DmlPipe SurfParameters[DML2_MAX_PLANES]; 898 unsigned int TotalNumberOfActiveWriteback; 899 unsigned int MaximumSwathWidthSupportLuma; 900 unsigned int MaximumSwathWidthSupportChroma; 901 bool MPCCombineMethodAsNeededForPStateChangeAndVoltage; 902 bool MPCCombineMethodAsPossible; 903 bool TotalAvailablePipesSupportNoDSC; 904 unsigned int NumberOfDPPNoDSC; 905 enum dml2_odm_mode ODMModeNoDSC; 906 double RequiredDISPCLKPerSurfaceNoDSC; 907 bool TotalAvailablePipesSupportDSC; 908 unsigned int NumberOfDPPDSC; 909 enum dml2_odm_mode ODMModeDSC; 910 double RequiredDISPCLKPerSurfaceDSC; 911 double BWOfNonCombinedSurfaceOfMaximumBandwidth; 912 unsigned int NumberOfNonCombinedSurfaceOfMaximumBandwidth; 913 unsigned int TotalNumberOfActiveOTG; 914 unsigned int TotalNumberOfActiveHDMIFRL; 915 unsigned int TotalNumberOfActiveDP2p0; 916 unsigned int TotalNumberOfActiveDP2p0Outputs; 917 unsigned int TotalSlots; 918 unsigned int DSCFormatFactor; 919 unsigned int TotalDSCUnitsRequired; 920 unsigned int ReorderingBytes; 921 bool ImmediateFlipRequired; 922 bool FullFrameMALLPStateMethod; 923 bool SubViewportMALLPStateMethod; 924 bool PhantomPipeMALLPStateMethod; 925 bool SubViewportMALLRefreshGreaterThan120Hz; 926 927 double HostVMInefficiencyFactor; 928 double HostVMInefficiencyFactorPrefetch; 929 unsigned int MaxVStartup; 930 double PixelClockBackEndFactor; 931 unsigned int NumDSCUnitRequired; 932 933 double Tvm_trips[DML2_MAX_PLANES]; 934 double Tr0_trips[DML2_MAX_PLANES]; 935 double Tvm_trips_flip[DML2_MAX_PLANES]; 936 double Tr0_trips_flip[DML2_MAX_PLANES]; 937 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 938 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 939 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 940 941 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 942 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 943 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 944 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 945 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 946 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 947 948 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 949 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 950 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 951 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 952 double tdlut_opt_time[DML2_MAX_PLANES]; 953 double tdlut_drain_time[DML2_MAX_PLANES]; 954 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 955 956 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 957 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 958 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 959 unsigned int cursor_bytes[DML2_MAX_PLANES]; 960 bool stream_visited[DML2_MAX_PLANES]; 961 962 unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 963 unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 964 }; 965 966 struct dml2_core_calcs_mode_programming_locals { 967 double PixelClockBackEnd[DML2_MAX_PLANES]; 968 double OutputBpp[DML2_MAX_PLANES]; 969 unsigned int num_active_planes; // <brief As determined by either e2e_pipe_param or display_cfg 970 unsigned int MaxTotalDETInKByte; 971 unsigned int NomDETInKByte; 972 unsigned int MinCompressedBufferSizeInKByte; 973 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state 974 975 double dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max]; 976 double surface_dummy_bw[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 977 double surface_dummy_bw0[dml2_core_internal_soc_state_max][dml2_core_internal_bw_max][DML2_MAX_PLANES]; 978 unsigned int dummy_integer_array[2][DML2_MAX_PLANES]; 979 enum dml2_output_encoder_class dummy_output_encoder_array[DML2_MAX_PLANES]; 980 double dummy_single_array[2][DML2_MAX_PLANES]; 981 unsigned int dummy_long_array[4][DML2_MAX_PLANES]; 982 bool dummy_boolean_array[2][DML2_MAX_PLANES]; 983 bool dummy_boolean[2]; 984 double dummy_single[2]; 985 struct dml2_core_internal_watermarks dummy_watermark; 986 987 unsigned int DSCFormatFactor; 988 struct dml2_core_internal_DmlPipe SurfaceParameters[DML2_MAX_PLANES]; 989 unsigned int ReorderingBytes; 990 double HostVMInefficiencyFactor; 991 double HostVMInefficiencyFactorPrefetch; 992 unsigned int TotalDCCActiveDPP; 993 unsigned int TotalActiveDPP; 994 unsigned int Total3dlutActive; 995 unsigned int MaxVStartupLines[DML2_MAX_PLANES]; /// <brief more like vblank for the plane's OTG 996 bool immediate_flip_required; // any pipes need immediate flip 997 bool DestinationLineTimesForPrefetchLessThan2; 998 bool VRatioPrefetchMoreThanMax; 999 double MaxTotalRDBandwidthNotIncludingMALLPrefetch; 1000 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1001 double Tvstartup_margin; 1002 double dlg_vblank_start; 1003 double LSetup; 1004 double blank_lines_remaining; 1005 double TotalWRBandwidth; 1006 double WRBandwidth; 1007 struct dml2_core_internal_DmlPipe myPipe; 1008 double PixelClockBackEndFactor; 1009 unsigned int vmpg_width_y[DML2_MAX_PLANES]; 1010 unsigned int vmpg_height_y[DML2_MAX_PLANES]; 1011 unsigned int vmpg_width_c[DML2_MAX_PLANES]; 1012 unsigned int vmpg_height_c[DML2_MAX_PLANES]; 1013 unsigned int full_swath_bytes_l[DML2_MAX_PLANES]; 1014 unsigned int full_swath_bytes_c[DML2_MAX_PLANES]; 1015 1016 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1017 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1018 unsigned int dpte_row_bytes_per_row_l[DML2_MAX_PLANES]; 1019 unsigned int dpte_row_bytes_per_row_c[DML2_MAX_PLANES]; 1020 1021 unsigned int tdlut_pte_bytes_per_frame[DML2_MAX_PLANES]; 1022 unsigned int tdlut_bytes_per_frame[DML2_MAX_PLANES]; 1023 unsigned int tdlut_row_bytes[DML2_MAX_PLANES]; 1024 unsigned int tdlut_groups_per_2row_ub[DML2_MAX_PLANES]; 1025 double tdlut_opt_time[DML2_MAX_PLANES]; 1026 double tdlut_drain_time[DML2_MAX_PLANES]; 1027 unsigned int tdlut_bytes_per_group[DML2_MAX_PLANES]; 1028 1029 unsigned int cursor_bytes_per_chunk[DML2_MAX_PLANES]; 1030 unsigned int cursor_bytes_per_line[DML2_MAX_PLANES]; 1031 unsigned int cursor_lines_per_chunk[DML2_MAX_PLANES]; 1032 unsigned int cursor_bytes[DML2_MAX_PLANES]; 1033 1034 double Tvm_trips[DML2_MAX_PLANES]; 1035 double Tr0_trips[DML2_MAX_PLANES]; 1036 double Tvm_trips_flip[DML2_MAX_PLANES]; 1037 double Tr0_trips_flip[DML2_MAX_PLANES]; 1038 double Tvm_trips_flip_rounded[DML2_MAX_PLANES]; 1039 double Tr0_trips_flip_rounded[DML2_MAX_PLANES]; 1040 unsigned int per_pipe_flip_bytes[DML2_MAX_PLANES]; 1041 1042 unsigned int pstate_bytes_required_l[DML2_MAX_PLANES]; 1043 unsigned int pstate_bytes_required_c[DML2_MAX_PLANES]; 1044 }; 1045 1046 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals { 1047 double ActiveDRAMClockChangeLatencyMargin[DML2_MAX_PLANES]; 1048 double ActiveFCLKChangeLatencyMargin[DML2_MAX_PLANES]; 1049 double USRRetrainingLatencyMargin[DML2_MAX_PLANES]; 1050 double g6_temp_read_latency_margin[DML2_MAX_PLANES]; 1051 1052 double EffectiveLBLatencyHidingY; 1053 double EffectiveLBLatencyHidingC; 1054 double LinesInDETY[DML2_MAX_PLANES]; 1055 double LinesInDETC[DML2_MAX_PLANES]; 1056 unsigned int LinesInDETYRoundedDownToSwath[DML2_MAX_PLANES]; 1057 unsigned int LinesInDETCRoundedDownToSwath[DML2_MAX_PLANES]; 1058 double FullDETBufferingTimeY; 1059 double FullDETBufferingTimeC; 1060 double WritebackDRAMClockChangeLatencyMargin; 1061 double WritebackFCLKChangeLatencyMargin; 1062 double WritebackLatencyHiding; 1063 1064 unsigned int TotalActiveWriteback; 1065 unsigned int LBLatencyHidingSourceLinesY[DML2_MAX_PLANES]; 1066 unsigned int LBLatencyHidingSourceLinesC[DML2_MAX_PLANES]; 1067 double TotalPixelBW; 1068 double EffectiveDETBufferSizeY; 1069 double ActiveClockChangeLatencyHidingY; 1070 double ActiveClockChangeLatencyHidingC; 1071 double ActiveClockChangeLatencyHiding; 1072 unsigned int dst_y_pstate; 1073 unsigned int src_y_pstate_l; 1074 unsigned int src_y_pstate_c; 1075 unsigned int src_y_ahead_l; 1076 unsigned int src_y_ahead_c; 1077 unsigned int sub_vp_lines_l; 1078 unsigned int sub_vp_lines_c; 1079 1080 }; 1081 1082 struct dml2_core_calcs_CalculateVMRowAndSwath_locals { 1083 unsigned int PTEBufferSizeInRequestsForLuma[DML2_MAX_PLANES]; 1084 unsigned int PTEBufferSizeInRequestsForChroma[DML2_MAX_PLANES]; 1085 unsigned int vm_bytes_l; 1086 unsigned int vm_bytes_c; 1087 unsigned int PixelPTEBytesPerRowY[DML2_MAX_PLANES]; 1088 unsigned int PixelPTEBytesPerRowC[DML2_MAX_PLANES]; 1089 unsigned int PixelPTEBytesPerRowStorageY[DML2_MAX_PLANES]; 1090 unsigned int PixelPTEBytesPerRowStorageC[DML2_MAX_PLANES]; 1091 unsigned int PixelPTEBytesPerRowY_one_row_per_frame[DML2_MAX_PLANES]; 1092 unsigned int PixelPTEBytesPerRowC_one_row_per_frame[DML2_MAX_PLANES]; 1093 unsigned int dpte_row_width_luma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1094 unsigned int dpte_row_height_luma_one_row_per_frame[DML2_MAX_PLANES]; 1095 unsigned int dpte_row_width_chroma_ub_one_row_per_frame[DML2_MAX_PLANES]; 1096 unsigned int dpte_row_height_chroma_one_row_per_frame[DML2_MAX_PLANES]; 1097 bool one_row_per_frame_fits_in_buffer[DML2_MAX_PLANES]; 1098 unsigned int HostVMDynamicLevels; 1099 unsigned int meta_row_bytes_per_row_ub_l[DML2_MAX_PLANES]; 1100 unsigned int meta_row_bytes_per_row_ub_c[DML2_MAX_PLANES]; 1101 }; 1102 1103 struct dml2_core_calcs_CalculateVMRowAndSwath_params { 1104 const struct dml2_display_cfg *display_cfg; 1105 unsigned int NumberOfActiveSurfaces; 1106 struct dml2_core_internal_DmlPipe *myPipe; 1107 unsigned int *SurfaceSizeInMALL; 1108 unsigned int PTEBufferSizeInRequestsLuma; 1109 unsigned int PTEBufferSizeInRequestsChroma; 1110 unsigned int MALLAllocatedForDCN; 1111 unsigned int *SwathWidthY; 1112 unsigned int *SwathWidthC; 1113 unsigned int HostVMMinPageSize; 1114 unsigned int DCCMetaBufferSizeBytes; 1115 bool mrq_present; 1116 1117 // Output 1118 bool *PTEBufferSizeNotExceeded; 1119 bool *DCCMetaBufferSizeNotExceeded; 1120 1121 unsigned int *dpte_row_width_luma_ub; 1122 unsigned int *dpte_row_width_chroma_ub; 1123 unsigned int *dpte_row_height_luma; 1124 unsigned int *dpte_row_height_chroma; 1125 unsigned int *dpte_row_height_linear_luma; // VBA_DELTA 1126 unsigned int *dpte_row_height_linear_chroma; // VBA_DELTA 1127 1128 unsigned int *vm_group_bytes; 1129 unsigned int *dpte_group_bytes; 1130 unsigned int *PixelPTEReqWidthY; 1131 unsigned int *PixelPTEReqHeightY; 1132 unsigned int *PTERequestSizeY; 1133 unsigned int *vmpg_width_y; 1134 unsigned int *vmpg_height_y; 1135 1136 unsigned int *PixelPTEReqWidthC; 1137 unsigned int *PixelPTEReqHeightC; 1138 unsigned int *PTERequestSizeC; 1139 unsigned int *vmpg_width_c; 1140 unsigned int *vmpg_height_c; 1141 1142 unsigned int *dpde0_bytes_per_frame_ub_l; 1143 unsigned int *dpde0_bytes_per_frame_ub_c; 1144 1145 unsigned int *PrefetchSourceLinesY; 1146 unsigned int *PrefetchSourceLinesC; 1147 unsigned int *VInitPreFillY; 1148 unsigned int *VInitPreFillC; 1149 unsigned int *MaxNumSwathY; 1150 unsigned int *MaxNumSwathC; 1151 double *dpte_row_bw; 1152 unsigned int *PixelPTEBytesPerRow; 1153 unsigned int *dpte_row_bytes_per_row_l; 1154 unsigned int *dpte_row_bytes_per_row_c; 1155 unsigned int *vm_bytes; 1156 bool *use_one_row_for_frame; 1157 bool *use_one_row_for_frame_flip; 1158 bool *is_using_mall_for_ss; 1159 bool *PTE_BUFFER_MODE; 1160 unsigned int *BIGK_FRAGMENT_SIZE; 1161 1162 // MRQ 1163 unsigned int *meta_req_width_luma; 1164 unsigned int *meta_req_height_luma; 1165 unsigned int *meta_row_width_luma; 1166 unsigned int *meta_row_height_luma; 1167 unsigned int *meta_pte_bytes_per_frame_ub_l; 1168 1169 unsigned int *meta_req_width_chroma; 1170 unsigned int *meta_req_height_chroma; 1171 unsigned int *meta_row_width_chroma; 1172 unsigned int *meta_row_height_chroma; 1173 unsigned int *meta_pte_bytes_per_frame_ub_c; 1174 double *meta_row_bw; 1175 unsigned int *meta_row_bytes; 1176 unsigned int *meta_row_bytes_per_row_ub_l; 1177 unsigned int *meta_row_bytes_per_row_ub_c; 1178 }; 1179 1180 struct dml2_core_calcs_CalculatePrefetchSchedule_locals { 1181 bool NoTimeToPrefetch; 1182 unsigned int DPPCycles; 1183 unsigned int DISPCLKCycles; 1184 double DSTTotalPixelsAfterScaler; 1185 double LineTime; 1186 double dst_y_prefetch_equ; 1187 double prefetch_bw_oto; 1188 double Tvm_oto; 1189 double Tr0_oto; 1190 double Tvm_no_trip_oto; 1191 double Tr0_no_trip_oto; 1192 double Tvm_oto_lines; 1193 double Tr0_oto_lines; 1194 double dst_y_prefetch_oto; 1195 double TimeForFetchingVM; 1196 double TimeForFetchingRowInVBlank; 1197 double dst_y_per_vm_no_trip_vblank; 1198 double dst_y_per_row_no_trip_vblank; 1199 double LinesToRequestPrefetchPixelData; 1200 unsigned int HostVMDynamicLevelsTrips; 1201 double trip_to_mem; 1202 double Tvm_trips_rounded; 1203 double Tr0_trips_rounded; 1204 double max_Tsw; 1205 double Lsw_oto; 1206 double Lsw_equ; 1207 double Tpre_rounded; 1208 double prefetch_bw_equ; 1209 double Tvm_equ; 1210 double Tr0_equ; 1211 double Tdmbf; 1212 double Tdmec; 1213 double Tdmsks; 1214 double prefetch_sw_bytes; 1215 double total_row_bytes; 1216 double prefetch_bw_pr; 1217 double bytes_pp; 1218 double dep_bytes; 1219 double min_Lsw_oto; 1220 double min_Lsw_equ; 1221 double Tsw_est1; 1222 double Tsw_est2; 1223 double Tsw_est3; 1224 double prefetch_bw1; 1225 double prefetch_bw2; 1226 double prefetch_bw3; 1227 double prefetch_bw4; 1228 1229 double TWait_p; 1230 unsigned int cursor_prefetch_bytes; 1231 }; 1232 1233 struct dml2_core_shared_calculate_det_buffer_size_params { 1234 const struct dml2_display_cfg *display_cfg; 1235 bool ForceSingleDPP; 1236 unsigned int NumberOfActiveSurfaces; 1237 bool UnboundedRequestEnabled; 1238 unsigned int nomDETInKByte; 1239 unsigned int MaxTotalDETInKByte; 1240 unsigned int ConfigReturnBufferSizeInKByte; 1241 unsigned int MinCompressedBufferSizeInKByte; 1242 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1243 unsigned int CompressedBufferSegmentSizeInkByte; 1244 double *ReadBandwidthLuma; 1245 double *ReadBandwidthChroma; 1246 unsigned int *full_swath_bytes_l; 1247 unsigned int *full_swath_bytes_c; 1248 unsigned int *swath_time_value_us; 1249 unsigned int *DPPPerSurface; 1250 bool TryToAllocateForWriteLatency; 1251 unsigned int bestEffortMinActiveLatencyHidingUs; 1252 1253 // Output 1254 unsigned int *DETBufferSizeInKByte; 1255 unsigned int *CompressedBufferSizeInkByte; 1256 }; 1257 1258 struct dml2_core_shared_calculate_vm_and_row_bytes_params { 1259 bool ViewportStationary; 1260 bool DCCEnable; 1261 unsigned int NumberOfDPPs; 1262 unsigned int BlockHeight256Bytes; 1263 unsigned int BlockWidth256Bytes; 1264 enum dml2_source_format_class SourcePixelFormat; 1265 unsigned int SurfaceTiling; 1266 unsigned int BytePerPixel; 1267 enum dml2_rotation_angle RotationAngle; 1268 unsigned int SwathWidth; // per pipe 1269 unsigned int ViewportHeight; 1270 unsigned int ViewportXStart; 1271 unsigned int ViewportYStart; 1272 bool GPUVMEnable; 1273 unsigned int GPUVMMaxPageTableLevels; 1274 unsigned int GPUVMMinPageSizeKBytes; 1275 unsigned int PTEBufferSizeInRequests; 1276 unsigned int Pitch; 1277 unsigned int MacroTileWidth; 1278 unsigned int MacroTileHeight; 1279 bool is_phantom; 1280 unsigned int DCCMetaPitch; 1281 bool mrq_present; 1282 1283 // Output 1284 unsigned int *PixelPTEBytesPerRow; // for bandwidth calculation 1285 unsigned int *PixelPTEBytesPerRowStorage; // for PTE buffer size check 1286 unsigned int *dpte_row_width_ub; 1287 unsigned int *dpte_row_height; 1288 unsigned int *dpte_row_height_linear; 1289 unsigned int *PixelPTEBytesPerRow_one_row_per_frame; 1290 unsigned int *dpte_row_width_ub_one_row_per_frame; 1291 unsigned int *dpte_row_height_one_row_per_frame; 1292 unsigned int *vmpg_width; 1293 unsigned int *vmpg_height; 1294 unsigned int *PixelPTEReqWidth; 1295 unsigned int *PixelPTEReqHeight; 1296 unsigned int *PTERequestSize; 1297 unsigned int *dpde0_bytes_per_frame_ub; 1298 1299 unsigned int *meta_row_bytes; 1300 unsigned int *MetaRequestWidth; 1301 unsigned int *MetaRequestHeight; 1302 unsigned int *meta_row_width; 1303 unsigned int *meta_row_height; 1304 unsigned int *meta_pte_bytes_per_frame_ub; 1305 }; 1306 1307 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals { 1308 unsigned int MaximumSwathHeightY[DML2_MAX_PLANES]; 1309 unsigned int MaximumSwathHeightC[DML2_MAX_PLANES]; 1310 unsigned int RoundedUpSwathSizeBytesY[DML2_MAX_PLANES]; 1311 unsigned int RoundedUpSwathSizeBytesC[DML2_MAX_PLANES]; 1312 unsigned int SwathWidthSingleDPP[DML2_MAX_PLANES]; 1313 unsigned int SwathWidthSingleDPPChroma[DML2_MAX_PLANES]; 1314 unsigned int SwathTimeValueUs[DML2_MAX_PLANES]; 1315 1316 struct dml2_core_shared_calculate_det_buffer_size_params calculate_det_buffer_size_params; 1317 }; 1318 1319 struct dml2_core_shared_TruncToValidBPP_locals { 1320 }; 1321 1322 struct dml2_core_shared_CalculateDETBufferSize_locals { 1323 unsigned int DETBufferSizePoolInKByte; 1324 unsigned int NextDETBufferPieceInKByte; 1325 unsigned int NextSurfaceToAssignDETPiece; 1326 double TotalBandwidth; 1327 double BandwidthOfSurfacesNotAssignedDETPiece; 1328 unsigned int max_minDET; 1329 unsigned int minDET; 1330 unsigned int minDET_pipe; 1331 unsigned int TotalBandwidthPerStream[DML2_MAX_PLANES]; 1332 unsigned int TotalPixelRate; 1333 unsigned int DETBudgetPerStream[DML2_MAX_PLANES]; 1334 unsigned int RemainingDETBudgetPerStream[DML2_MAX_PLANES]; 1335 unsigned int IdealDETBudget, DeltaDETBudget; 1336 unsigned int ResidualDETAfterRounding; 1337 }; 1338 1339 struct dml2_core_shared_get_urgent_bandwidth_required_locals { 1340 double required_bandwidth_mbps; 1341 double required_bandwidth_mbps_this_surface; 1342 double adj_factor_p0; 1343 double adj_factor_p1; 1344 double adj_factor_cur; 1345 double adj_factor_p0_pre; 1346 double adj_factor_p1_pre; 1347 double adj_factor_cur_pre; 1348 double per_plane_flip_bw[DML2_MAX_PLANES]; 1349 double mall_svp_prefetch_factor; 1350 double tmp_nom_adj_factor_p0; 1351 double tmp_nom_adj_factor_p1; 1352 double tmp_pref_adj_factor_p0; 1353 double tmp_pref_adj_factor_p1; 1354 double vm_row_bw; 1355 double flip_and_active_bw; 1356 double flip_and_prefetch_bw; 1357 double active_and_excess_bw; 1358 }; 1359 1360 struct dml2_core_shared_calculate_peak_bandwidth_required_locals { 1361 double unity_array[DML2_MAX_PLANES]; 1362 double zero_array[DML2_MAX_PLANES]; 1363 double surface_dummy_bw[DML2_MAX_PLANES]; 1364 }; 1365 1366 struct dml2_core_shared_CalculateFlipSchedule_locals { 1367 double min_row_time; 1368 double Tvm_flip; 1369 double Tr0_flip; 1370 double ImmediateFlipBW; 1371 double dpte_row_bytes; 1372 double min_row_height; 1373 double min_row_height_chroma; 1374 double max_flip_time; 1375 double lb_flip_bw; 1376 double hvm_scaled_vm_bytes; 1377 double num_rows; 1378 double hvm_scaled_row_bytes; 1379 double hvm_scaled_vm_row_bytes; 1380 bool dual_plane; 1381 }; 1382 1383 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals { 1384 unsigned int plane_idx; 1385 enum dml2_source_format_class source_format; 1386 const struct dml2_timing_cfg *timing; 1387 bool dual_plane; 1388 enum dml2_odm_mode odm_mode; 1389 1390 unsigned int htotal; 1391 unsigned int hactive; 1392 unsigned int hblank_end; 1393 unsigned int vblank_end; 1394 bool interlaced; 1395 double pclk_freq_in_mhz; 1396 double refclk_freq_in_mhz; 1397 double ref_freq_to_pix_freq; 1398 1399 unsigned int num_active_pipes; 1400 unsigned int first_pipe_idx_in_plane; 1401 unsigned int pipe_idx_in_combine; 1402 unsigned int odm_combine_factor; 1403 1404 double min_ttu_vblank; 1405 unsigned int min_dst_y_next_start; 1406 1407 unsigned int vready_after_vcount0; 1408 1409 unsigned int dst_x_after_scaler; 1410 unsigned int dst_y_after_scaler; 1411 1412 double dst_y_prefetch; 1413 double dst_y_per_vm_vblank; 1414 double dst_y_per_row_vblank; 1415 double dst_y_per_vm_flip; 1416 double dst_y_per_row_flip; 1417 1418 double max_dst_y_per_vm_vblank; 1419 double max_dst_y_per_row_vblank; 1420 1421 double vratio_pre_l; 1422 double vratio_pre_c; 1423 1424 double refcyc_per_line_delivery_pre_l; 1425 double refcyc_per_line_delivery_l; 1426 1427 double refcyc_per_line_delivery_pre_c; 1428 double refcyc_per_line_delivery_c; 1429 1430 double refcyc_per_req_delivery_pre_l; 1431 double refcyc_per_req_delivery_l; 1432 1433 double refcyc_per_req_delivery_pre_c; 1434 double refcyc_per_req_delivery_c; 1435 1436 double dst_y_per_pte_row_nom_l; 1437 double dst_y_per_pte_row_nom_c; 1438 double refcyc_per_pte_group_nom_l; 1439 double refcyc_per_pte_group_nom_c; 1440 double refcyc_per_pte_group_vblank_l; 1441 double refcyc_per_pte_group_vblank_c; 1442 double refcyc_per_pte_group_flip_l; 1443 double refcyc_per_pte_group_flip_c; 1444 double refcyc_per_tdlut_group; 1445 1446 double dst_y_per_meta_row_nom_l; 1447 double dst_y_per_meta_row_nom_c; 1448 double refcyc_per_meta_chunk_nom_l; 1449 double refcyc_per_meta_chunk_nom_c; 1450 double refcyc_per_meta_chunk_vblank_l; 1451 double refcyc_per_meta_chunk_vblank_c; 1452 double refcyc_per_meta_chunk_flip_l; 1453 double refcyc_per_meta_chunk_flip_c; 1454 }; 1455 1456 struct dml2_core_shared_CalculateMetaAndPTETimes_params { 1457 struct dml2_core_internal_scratch *scratch; 1458 const struct dml2_display_cfg *display_cfg; 1459 unsigned int NumberOfActiveSurfaces; 1460 bool *use_one_row_for_frame; 1461 double *dst_y_per_row_vblank; 1462 double *dst_y_per_row_flip; 1463 unsigned int *BytePerPixelY; 1464 unsigned int *BytePerPixelC; 1465 unsigned int *dpte_row_height; 1466 unsigned int *dpte_row_height_chroma; 1467 unsigned int *dpte_group_bytes; 1468 unsigned int *PTERequestSizeY; 1469 unsigned int *PTERequestSizeC; 1470 unsigned int *PixelPTEReqWidthY; 1471 unsigned int *PixelPTEReqHeightY; 1472 unsigned int *PixelPTEReqWidthC; 1473 unsigned int *PixelPTEReqHeightC; 1474 unsigned int *dpte_row_width_luma_ub; 1475 unsigned int *dpte_row_width_chroma_ub; 1476 unsigned int *tdlut_groups_per_2row_ub; 1477 bool mrq_present; 1478 unsigned int MetaChunkSize; 1479 unsigned int MinMetaChunkSizeBytes; 1480 unsigned int *meta_row_width; 1481 unsigned int *meta_row_width_chroma; 1482 unsigned int *meta_row_height; 1483 unsigned int *meta_row_height_chroma; 1484 unsigned int *meta_req_width; 1485 unsigned int *meta_req_width_chroma; 1486 unsigned int *meta_req_height; 1487 unsigned int *meta_req_height_chroma; 1488 1489 // Output 1490 double *time_per_tdlut_group; 1491 double *DST_Y_PER_PTE_ROW_NOM_L; 1492 double *DST_Y_PER_PTE_ROW_NOM_C; 1493 double *time_per_pte_group_nom_luma; 1494 double *time_per_pte_group_vblank_luma; 1495 double *time_per_pte_group_flip_luma; 1496 double *time_per_pte_group_nom_chroma; 1497 double *time_per_pte_group_vblank_chroma; 1498 double *time_per_pte_group_flip_chroma; 1499 1500 double *DST_Y_PER_META_ROW_NOM_L; 1501 double *DST_Y_PER_META_ROW_NOM_C; 1502 1503 double *TimePerMetaChunkNominal; 1504 double *TimePerChromaMetaChunkNominal; 1505 double *TimePerMetaChunkVBlank; 1506 double *TimePerChromaMetaChunkVBlank; 1507 double *TimePerMetaChunkFlip; 1508 double *TimePerChromaMetaChunkFlip; 1509 }; 1510 1511 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params { 1512 const struct dml2_display_cfg *display_cfg; 1513 bool USRRetrainingRequired; 1514 unsigned int NumberOfActiveSurfaces; 1515 unsigned int MaxLineBufferLines; 1516 unsigned int LineBufferSize; 1517 unsigned int WritebackInterfaceBufferSize; 1518 double DCFCLK; 1519 double ReturnBW; 1520 bool SynchronizeTimings; 1521 bool SynchronizeDRRDisplaysForUCLKPStateChange; 1522 unsigned int *dpte_group_bytes; 1523 struct dml2_core_internal_SOCParametersList mmSOCParameters; 1524 unsigned int WritebackChunkSize; 1525 double SOCCLK; 1526 double DCFClkDeepSleep; 1527 unsigned int *DETBufferSizeY; 1528 unsigned int *DETBufferSizeC; 1529 unsigned int *SwathHeightY; 1530 unsigned int *SwathHeightC; 1531 unsigned int *SwathWidthY; 1532 unsigned int *SwathWidthC; 1533 unsigned int *DPPPerSurface; 1534 double *BytePerPixelDETY; 1535 double *BytePerPixelDETC; 1536 unsigned int *DSTXAfterScaler; 1537 unsigned int *DSTYAfterScaler; 1538 bool UnboundedRequestEnabled; 1539 unsigned int CompressedBufferSizeInkByte; 1540 bool max_oustanding_when_urgent_expected; 1541 unsigned int max_outstanding_requests; 1542 unsigned int max_request_size_bytes; 1543 unsigned int *meta_row_height_l; 1544 unsigned int *meta_row_height_c; 1545 1546 // Output 1547 struct dml2_core_internal_watermarks *Watermark; 1548 enum dml2_dram_clock_change_support *DRAMClockChangeSupport; 1549 bool *global_dram_clock_change_supported; 1550 double *MaxActiveDRAMClockChangeLatencySupported; 1551 unsigned int *SubViewportLinesNeededInMALL; 1552 enum dml2_fclock_change_support *FCLKChangeSupport; 1553 bool *global_fclk_change_supported; 1554 double *MaxActiveFCLKChangeLatencySupported; 1555 bool *USRRetrainingSupport; 1556 double *VActiveLatencyHidingMargin; 1557 double *VActiveLatencyHidingUs; 1558 bool *g6_temp_read_support; 1559 }; 1560 1561 1562 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params { 1563 const struct dml2_display_cfg *display_cfg; 1564 unsigned int ConfigReturnBufferSizeInKByte; 1565 unsigned int MaxTotalDETInKByte; 1566 unsigned int MinCompressedBufferSizeInKByte; 1567 unsigned int rob_buffer_size_kbytes; 1568 unsigned int pixel_chunk_size_kbytes; 1569 bool ForceSingleDPP; 1570 unsigned int NumberOfActiveSurfaces; 1571 unsigned int nomDETInKByte; 1572 unsigned int ConfigReturnBufferSegmentSizeInkByte; 1573 unsigned int CompressedBufferSegmentSizeInkByte; 1574 double *ReadBandwidthLuma; 1575 double *ReadBandwidthChroma; 1576 double *MaximumSwathWidthLuma; 1577 double *MaximumSwathWidthChroma; 1578 unsigned int *Read256BytesBlockHeightY; 1579 unsigned int *Read256BytesBlockHeightC; 1580 unsigned int *Read256BytesBlockWidthY; 1581 unsigned int *Read256BytesBlockWidthC; 1582 bool *surf_linear128_l; 1583 bool *surf_linear128_c; 1584 enum dml2_odm_mode *ODMMode; 1585 unsigned int *BytePerPixY; 1586 unsigned int *BytePerPixC; 1587 double *BytePerPixDETY; 1588 double *BytePerPixDETC; 1589 unsigned int *DPPPerSurface; 1590 bool mrq_present; 1591 1592 // output 1593 unsigned int *req_per_swath_ub_l; 1594 unsigned int *req_per_swath_ub_c; 1595 unsigned int *swath_width_luma_ub; 1596 unsigned int *swath_width_chroma_ub; 1597 unsigned int *SwathWidth; 1598 unsigned int *SwathWidthChroma; 1599 unsigned int *SwathHeightY; 1600 unsigned int *SwathHeightC; 1601 unsigned int *request_size_bytes_luma; 1602 unsigned int *request_size_bytes_chroma; 1603 unsigned int *DETBufferSizeInKByte; 1604 unsigned int *DETBufferSizeY; 1605 unsigned int *DETBufferSizeC; 1606 unsigned int *full_swath_bytes_l; 1607 unsigned int *full_swath_bytes_c; 1608 bool *UnboundedRequestEnabled; 1609 unsigned int *compbuf_reserved_space_64b; 1610 unsigned int *CompressedBufferSizeInkByte; 1611 bool *ViewportSizeSupportPerSurface; 1612 bool *ViewportSizeSupport; 1613 bool *hw_debug5; 1614 1615 struct dml2_core_shared_calculation_funcs *funcs; 1616 }; 1617 1618 struct dml2_core_calcs_CalculateStutterEfficiency_locals { 1619 double DETBufferingTimeY; 1620 double SwathWidthYCriticalSurface; 1621 double SwathHeightYCriticalSurface; 1622 double VActiveTimeCriticalSurface; 1623 double FrameTimeCriticalSurface; 1624 unsigned int BytePerPixelYCriticalSurface; 1625 unsigned int DETBufferSizeYCriticalSurface; 1626 double MinTTUVBlankCriticalSurface; 1627 unsigned int BlockWidth256BytesYCriticalSurface; 1628 bool SinglePlaneCriticalSurface; 1629 bool SinglePipeCriticalSurface; 1630 double TotalCompressedReadBandwidth; 1631 double TotalRowReadBandwidth; 1632 double AverageDCCCompressionRate; 1633 double EffectiveCompressedBufferSize; 1634 double PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer; 1635 double StutterBurstTime; 1636 unsigned int TotalActiveWriteback; 1637 double LinesInDETY; 1638 double LinesInDETYRoundedDownToSwath; 1639 double MaximumEffectiveCompressionLuma; 1640 double MaximumEffectiveCompressionChroma; 1641 double TotalZeroSizeRequestReadBandwidth; 1642 double TotalZeroSizeCompressedReadBandwidth; 1643 double AverageDCCZeroSizeFraction; 1644 double AverageZeroSizeCompressionRate; 1645 bool stream_visited[DML2_MAX_PLANES]; 1646 }; 1647 1648 struct dml2_core_calcs_CalculateStutterEfficiency_params { 1649 const struct dml2_display_cfg *display_cfg; 1650 unsigned int CompressedBufferSizeInkByte; 1651 bool UnboundedRequestEnabled; 1652 unsigned int MetaFIFOSizeInKEntries; 1653 unsigned int ZeroSizeBufferEntries; 1654 unsigned int PixelChunkSizeInKByte; 1655 unsigned int NumberOfActiveSurfaces; 1656 unsigned int ROBBufferSizeInKByte; 1657 double TotalDataReadBandwidth; 1658 double DCFCLK; 1659 double ReturnBW; 1660 unsigned int CompbufReservedSpace64B; 1661 unsigned int CompbufReservedSpaceZs; 1662 bool hw_debug5; 1663 double SRExitTime; 1664 double SRExitZ8Time; 1665 bool SynchronizeTimings; 1666 double StutterEnterPlusExitWatermark; 1667 double Z8StutterEnterPlusExitWatermark; 1668 bool ProgressiveToInterlaceUnitInOPP; 1669 double *MinTTUVBlank; 1670 unsigned int *DPPPerSurface; 1671 unsigned int *DETBufferSizeY; 1672 unsigned int *BytePerPixelY; 1673 double *BytePerPixelDETY; 1674 unsigned int *SwathWidthY; 1675 unsigned int *SwathHeightY; 1676 unsigned int *SwathHeightC; 1677 unsigned int *BlockHeight256BytesY; 1678 unsigned int *BlockWidth256BytesY; 1679 unsigned int *BlockHeight256BytesC; 1680 unsigned int *BlockWidth256BytesC; 1681 unsigned int *DCCYMaxUncompressedBlock; 1682 unsigned int *DCCCMaxUncompressedBlock; 1683 double *ReadBandwidthSurfaceLuma; 1684 double *ReadBandwidthSurfaceChroma; 1685 double *meta_row_bw; 1686 double *dpte_row_bw; 1687 bool rob_alloc_compressed; 1688 1689 // output 1690 double *StutterEfficiencyNotIncludingVBlank; 1691 double *StutterEfficiency; 1692 unsigned int *NumberOfStutterBurstsPerFrame; 1693 double *Z8StutterEfficiencyNotIncludingVBlank; 1694 double *Z8StutterEfficiency; 1695 unsigned int *Z8NumberOfStutterBurstsPerFrame; 1696 double *StutterPeriod; 1697 bool *DCHUBBUB_ARB_CSTATE_MAX_CAP_MODE; 1698 }; 1699 1700 struct dml2_core_calcs_CalculatePrefetchSchedule_params { 1701 const struct dml2_display_cfg *display_cfg; 1702 double HostVMInefficiencyFactor; 1703 struct dml2_core_internal_DmlPipe *myPipe; 1704 unsigned int DSCDelay; 1705 double DPPCLKDelaySubtotalPlusCNVCFormater; 1706 double DPPCLKDelaySCL; 1707 double DPPCLKDelaySCLLBOnly; 1708 double DPPCLKDelayCNVCCursor; 1709 double DISPCLKDelaySubtotal; 1710 unsigned int DPP_RECOUT_WIDTH; 1711 enum dml2_output_format_class OutputFormat; 1712 unsigned int MaxInterDCNTileRepeaters; 1713 unsigned int VStartup; 1714 unsigned int HostVMMinPageSize; 1715 bool DynamicMetadataEnable; 1716 bool DynamicMetadataVMEnabled; 1717 unsigned int DynamicMetadataLinesBeforeActiveRequired; 1718 unsigned int DynamicMetadataTransmittedBytes; 1719 double UrgentLatency; 1720 double ExtraLatencyPrefetch; 1721 double TCalc; 1722 unsigned int vm_bytes; 1723 unsigned int PixelPTEBytesPerRow; 1724 double PrefetchSourceLinesY; 1725 unsigned int VInitPreFillY; 1726 unsigned int MaxNumSwathY; 1727 double PrefetchSourceLinesC; 1728 unsigned int VInitPreFillC; 1729 unsigned int MaxNumSwathC; 1730 unsigned int swath_width_luma_ub; 1731 unsigned int swath_width_chroma_ub; 1732 unsigned int SwathHeightY; 1733 unsigned int SwathHeightC; 1734 double TWait; 1735 double Ttrip; 1736 double Turg; 1737 bool setup_for_tdlut; 1738 unsigned int tdlut_pte_bytes_per_frame; 1739 unsigned int tdlut_bytes_per_frame; 1740 double tdlut_opt_time; 1741 double tdlut_drain_time; 1742 1743 unsigned int num_cursors; 1744 unsigned int cursor_bytes_per_chunk; 1745 unsigned int cursor_bytes_per_line; 1746 1747 // MRQ 1748 bool dcc_enable; 1749 bool mrq_present; 1750 unsigned int meta_row_bytes; 1751 double mall_prefetch_sdp_overhead_factor; 1752 1753 // output 1754 unsigned int *DSTXAfterScaler; 1755 unsigned int *DSTYAfterScaler; 1756 double *dst_y_prefetch; 1757 double *dst_y_per_vm_vblank; 1758 double *dst_y_per_row_vblank; 1759 double *VRatioPrefetchY; 1760 double *VRatioPrefetchC; 1761 double *RequiredPrefetchPixelDataBWLuma; 1762 double *RequiredPrefetchPixelDataBWChroma; 1763 bool *NotEnoughTimeForDynamicMetadata; 1764 double *Tno_bw; 1765 double *Tno_bw_flip; 1766 double *prefetch_vmrow_bw; 1767 double *Tdmdl_vm; 1768 double *Tdmdl; 1769 double *TSetup; 1770 double *Tvm_trips; 1771 double *Tr0_trips; 1772 double *Tvm_trips_flip; 1773 double *Tr0_trips_flip; 1774 double *Tvm_trips_flip_rounded; 1775 double *Tr0_trips_flip_rounded; 1776 unsigned int *VUpdateOffsetPix; 1777 unsigned int *VUpdateWidthPix; 1778 unsigned int *VReadyOffsetPix; 1779 double *prefetch_cursor_bw; 1780 }; 1781 1782 struct dml2_core_calcs_calculate_mcache_row_bytes_params { 1783 unsigned int num_chans; 1784 unsigned int mem_word_bytes; 1785 unsigned int mcache_size_bytes; 1786 unsigned int mcache_line_size_bytes; 1787 unsigned int gpuvm_enable; 1788 unsigned int gpuvm_page_size_kbytes; 1789 1790 //enum dml_rotation_angle rotation_angle; 1791 bool surf_vert; 1792 unsigned int vp_stationary; 1793 unsigned int tiling_mode; 1794 bool imall_enable; 1795 1796 unsigned int vp_start_x; 1797 unsigned int vp_start_y; 1798 unsigned int full_vp_width; 1799 unsigned int full_vp_height; 1800 unsigned int blk_width; 1801 unsigned int blk_height; 1802 unsigned int vmpg_width; 1803 unsigned int vmpg_height; 1804 unsigned int full_swath_bytes; 1805 unsigned int bytes_per_pixel; 1806 1807 // output 1808 unsigned int *num_mcaches; 1809 unsigned int *mcache_row_bytes; 1810 unsigned int *meta_row_width_ub; 1811 double *dcc_dram_bw_nom_overhead_factor; 1812 double *dcc_dram_bw_pref_overhead_factor; 1813 unsigned int *mvmpg_width; 1814 unsigned int *mvmpg_height; 1815 unsigned int *full_vp_access_width_mvmpg_aligned; 1816 unsigned int *mvmpg_per_mcache_lb; 1817 }; 1818 1819 struct dml2_core_shared_calculate_mcache_setting_locals { 1820 struct dml2_core_calcs_calculate_mcache_row_bytes_params l_p; 1821 struct dml2_core_calcs_calculate_mcache_row_bytes_params c_p; 1822 1823 bool is_dual_plane; 1824 unsigned int mvmpg_width_l; 1825 unsigned int mvmpg_height_l; 1826 unsigned int full_vp_access_width_mvmpg_aligned_l; 1827 unsigned int mvmpg_per_mcache_lb_l; 1828 unsigned int meta_row_width_l; 1829 1830 unsigned int mvmpg_width_c; 1831 unsigned int mvmpg_height_c; 1832 unsigned int full_vp_access_width_mvmpg_aligned_c; 1833 unsigned int mvmpg_per_mcache_lb_c; 1834 unsigned int meta_row_width_c; 1835 1836 unsigned int lc_comb_last_mcache_size; 1837 double luma_time_factor; 1838 double mcache_remainder_l; 1839 double mcache_remainder_c; 1840 unsigned int mvmpg_access_width_l; 1841 unsigned int mvmpg_access_width_c; 1842 unsigned int avg_mcache_element_size_l; 1843 unsigned int avg_mcache_element_size_c; 1844 1845 unsigned int full_vp_access_width_l; 1846 unsigned int full_vp_access_width_c; 1847 }; 1848 1849 struct dml2_core_calcs_calculate_mcache_setting_params { 1850 bool dcc_enable; 1851 unsigned int num_chans; 1852 unsigned int mem_word_bytes; 1853 unsigned int mcache_size_bytes; 1854 unsigned int mcache_line_size_bytes; 1855 unsigned int gpuvm_enable; 1856 unsigned int gpuvm_page_size_kbytes; 1857 1858 enum dml2_source_format_class source_format; 1859 bool surf_vert; 1860 unsigned int vp_stationary; 1861 unsigned int tiling_mode; 1862 bool imall_enable; 1863 1864 unsigned int vp_start_x_l; 1865 unsigned int vp_start_y_l; 1866 unsigned int full_vp_width_l; 1867 unsigned int full_vp_height_l; 1868 unsigned int blk_width_l; 1869 unsigned int blk_height_l; 1870 unsigned int vmpg_width_l; 1871 unsigned int vmpg_height_l; 1872 unsigned int full_swath_bytes_l; 1873 unsigned int bytes_per_pixel_l; 1874 1875 unsigned int vp_start_x_c; 1876 unsigned int vp_start_y_c; 1877 unsigned int full_vp_width_c; 1878 unsigned int full_vp_height_c; 1879 unsigned int blk_width_c; 1880 unsigned int blk_height_c; 1881 unsigned int vmpg_width_c; 1882 unsigned int vmpg_height_c; 1883 unsigned int full_swath_bytes_c; 1884 unsigned int bytes_per_pixel_c; 1885 1886 // output 1887 unsigned int *num_mcaches_l; 1888 unsigned int *mcache_row_bytes_l; 1889 unsigned int *mcache_offsets_l; 1890 unsigned int *mcache_shift_granularity_l; 1891 double *dcc_dram_bw_nom_overhead_factor_l; 1892 double *dcc_dram_bw_pref_overhead_factor_l; 1893 1894 unsigned int *num_mcaches_c; 1895 unsigned int *mcache_row_bytes_c; 1896 unsigned int *mcache_offsets_c; 1897 unsigned int *mcache_shift_granularity_c; 1898 double *dcc_dram_bw_nom_overhead_factor_c; 1899 double *dcc_dram_bw_pref_overhead_factor_c; 1900 1901 bool *mall_comb_mcache_l; 1902 bool *mall_comb_mcache_c; 1903 bool *lc_comb_mcache; 1904 }; 1905 1906 struct dml2_core_calcs_calculate_tdlut_setting_params { 1907 // input params 1908 double dispclk_mhz; 1909 bool setup_for_tdlut; 1910 enum dml2_tdlut_width_mode tdlut_width_mode; 1911 enum dml2_tdlut_addressing_mode tdlut_addressing_mode; 1912 unsigned int cursor_buffer_size; 1913 bool gpuvm_enable; 1914 unsigned int gpuvm_page_size_kbytes; 1915 bool is_gfx11; 1916 bool tdlut_mpc_width_flag; 1917 1918 // output param 1919 unsigned int *tdlut_pte_bytes_per_frame; 1920 unsigned int *tdlut_bytes_per_frame; 1921 unsigned int *tdlut_groups_per_2row_ub; 1922 double *tdlut_opt_time; 1923 double *tdlut_drain_time; 1924 unsigned int *tdlut_bytes_per_group; 1925 }; 1926 1927 struct dml2_core_calcs_calculate_peak_bandwidth_required_params { 1928 // output 1929 double (*urg_vactive_bandwidth_required)[dml2_core_internal_bw_max]; 1930 double (*urg_bandwidth_required)[dml2_core_internal_bw_max]; 1931 double (*urg_bandwidth_required_qual)[dml2_core_internal_bw_max]; 1932 double (*non_urg_bandwidth_required)[dml2_core_internal_bw_max]; 1933 double (*surface_avg_vactive_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1934 double (*surface_peak_required_bw)[dml2_core_internal_bw_max][DML2_MAX_PLANES]; 1935 1936 // input 1937 const struct dml2_display_cfg *display_cfg; 1938 bool inc_flip_bw; 1939 unsigned int num_active_planes; 1940 unsigned int *num_of_dpp; 1941 double *dcc_dram_bw_nom_overhead_factor_p0; 1942 double *dcc_dram_bw_nom_overhead_factor_p1; 1943 double *dcc_dram_bw_pref_overhead_factor_p0; 1944 double *dcc_dram_bw_pref_overhead_factor_p1; 1945 double *mall_prefetch_sdp_overhead_factor; 1946 double *mall_prefetch_dram_overhead_factor; 1947 double *surface_read_bandwidth_l; 1948 double *surface_read_bandwidth_c; 1949 double *prefetch_bandwidth_l; 1950 double *prefetch_bandwidth_c; 1951 double *excess_vactive_fill_bw_l; 1952 double *excess_vactive_fill_bw_c; 1953 double *cursor_bw; 1954 double *dpte_row_bw; 1955 double *meta_row_bw; 1956 double *prefetch_cursor_bw; 1957 double *prefetch_vmrow_bw; 1958 double *flip_bw; 1959 double *urgent_burst_factor_l; 1960 double *urgent_burst_factor_c; 1961 double *urgent_burst_factor_cursor; 1962 double *urgent_burst_factor_prefetch_l; 1963 double *urgent_burst_factor_prefetch_c; 1964 double *urgent_burst_factor_prefetch_cursor; 1965 }; 1966 1967 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params { 1968 /* inputs */ 1969 const struct dml2_display_cfg *display_cfg; 1970 bool mrq_present; 1971 unsigned int num_active_planes; 1972 unsigned int *num_of_dpp; 1973 unsigned int *meta_row_height_l; 1974 unsigned int *meta_row_height_c; 1975 unsigned int *meta_row_bytes_per_row_ub_l; 1976 unsigned int *meta_row_bytes_per_row_ub_c; 1977 unsigned int *dpte_row_height_l; 1978 unsigned int *dpte_row_height_c; 1979 unsigned int *dpte_bytes_per_row_l; 1980 unsigned int *dpte_bytes_per_row_c; 1981 unsigned int *byte_per_pix_l; 1982 unsigned int *byte_per_pix_c; 1983 unsigned int *swath_width_l; 1984 unsigned int *swath_width_c; 1985 unsigned int *swath_height_l; 1986 unsigned int *swath_height_c; 1987 double latency_to_hide_us; 1988 1989 /* outputs */ 1990 unsigned int *bytes_required_l; 1991 unsigned int *bytes_required_c; 1992 }; 1993 1994 // A list of overridable function pointers in the core 1995 // shared calculation library. 1996 struct dml2_core_shared_calculation_funcs { 1997 void (*calculate_det_buffer_size)(struct dml2_core_shared_calculate_det_buffer_size_params *p); 1998 }; 1999 2000 struct dml2_core_internal_scratch { 2001 // Scratch space for function locals 2002 struct dml2_core_calcs_mode_support_locals dml_core_mode_support_locals; 2003 struct dml2_core_calcs_mode_programming_locals dml_core_mode_programming_locals; 2004 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_locals; 2005 struct dml2_core_calcs_CalculateVMRowAndSwath_locals CalculateVMRowAndSwath_locals; 2006 struct dml2_core_calcs_CalculatePrefetchSchedule_locals CalculatePrefetchSchedule_locals; 2007 struct dml2_core_shared_CalculateSwathAndDETConfiguration_locals CalculateSwathAndDETConfiguration_locals; 2008 struct dml2_core_shared_TruncToValidBPP_locals TruncToValidBPP_locals; 2009 struct dml2_core_shared_CalculateDETBufferSize_locals CalculateDETBufferSize_locals; 2010 struct dml2_core_shared_get_urgent_bandwidth_required_locals get_urgent_bandwidth_required_locals; 2011 struct dml2_core_shared_calculate_peak_bandwidth_required_locals calculate_peak_bandwidth_required_locals; 2012 struct dml2_core_shared_CalculateFlipSchedule_locals CalculateFlipSchedule_locals; 2013 struct dml2_core_shared_rq_dlg_get_dlg_reg_locals rq_dlg_get_dlg_reg_locals; 2014 struct dml2_core_calcs_CalculateStutterEfficiency_locals CalculateStutterEfficiency_locals; 2015 2016 // Scratch space for function params 2017 struct dml2_core_calcs_CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport_params; 2018 struct dml2_core_calcs_CalculateVMRowAndSwath_params CalculateVMRowAndSwath_params; 2019 struct dml2_core_calcs_CalculateSwathAndDETConfiguration_params CalculateSwathAndDETConfiguration_params; 2020 struct dml2_core_calcs_CalculateStutterEfficiency_params CalculateStutterEfficiency_params; 2021 struct dml2_core_calcs_CalculatePrefetchSchedule_params CalculatePrefetchSchedule_params; 2022 struct dml2_core_calcs_calculate_mcache_setting_params calculate_mcache_setting_params; 2023 struct dml2_core_calcs_calculate_tdlut_setting_params calculate_tdlut_setting_params; 2024 struct dml2_core_shared_calculate_vm_and_row_bytes_params calculate_vm_and_row_bytes_params; 2025 struct dml2_core_shared_calculate_mcache_setting_locals calculate_mcache_setting_locals; 2026 struct dml2_core_shared_CalculateMetaAndPTETimes_params CalculateMetaAndPTETimes_params; 2027 struct dml2_core_calcs_calculate_peak_bandwidth_required_params calculate_peak_bandwidth_params; 2028 struct dml2_core_calcs_calculate_bytes_to_fetch_required_to_hide_latency_params calculate_bytes_to_fetch_required_to_hide_latency_params; 2029 }; 2030 2031 //struct dml2_svp_mode_override; 2032 struct dml2_core_internal_display_mode_lib { 2033 struct dml2_core_ip_params ip; 2034 struct dml2_soc_bb soc; 2035 struct dml2_ip_capabilities ip_caps; 2036 2037 //@brief Mode Support and Mode programming struct 2038 // Used to hold input; intermediate and output of the calculations 2039 struct dml2_core_internal_mode_support ms; // struct for mode support 2040 struct dml2_core_internal_mode_program mp; // struct for mode programming 2041 2042 // Available overridable calculators for core_shared. 2043 // if null, core_shared will use default calculators. 2044 struct dml2_core_shared_calculation_funcs funcs; 2045 2046 struct dml2_core_internal_scratch scratch; 2047 }; 2048 2049 struct dml2_core_calcs_mode_support_ex { 2050 struct dml2_core_internal_display_mode_lib *mode_lib; 2051 const struct dml2_display_cfg *in_display_cfg; 2052 const struct dml2_mcg_min_clock_table *min_clk_table; 2053 int min_clk_index; 2054 2055 //unsigned int in_state_index; 2056 struct dml2_core_internal_mode_support_info *out_evaluation_info; 2057 }; 2058 2059 struct core_display_cfg_support_info; 2060 2061 struct dml2_core_calcs_mode_programming_ex { 2062 struct dml2_core_internal_display_mode_lib *mode_lib; 2063 const struct dml2_display_cfg *in_display_cfg; 2064 const struct dml2_mcg_min_clock_table *min_clk_table; 2065 const struct core_display_cfg_support_info *cfg_support_info; 2066 int min_clk_index; 2067 2068 struct dml2_display_cfg_programming *programming; 2069 2070 }; 2071 2072 #endif 2073