1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/debugfs.h>
16 #include <linux/kvm_host.h>
17 #include <linux/mm.h>
18 #include <linux/printk.h>
19 #include <linux/uaccess.h>
20
21 #include <asm/arm_pmuv3.h>
22 #include <asm/cacheflush.h>
23 #include <asm/cputype.h>
24 #include <asm/debug-monitors.h>
25 #include <asm/esr.h>
26 #include <asm/kvm_arm.h>
27 #include <asm/kvm_emulate.h>
28 #include <asm/kvm_hyp.h>
29 #include <asm/kvm_mmu.h>
30 #include <asm/kvm_nested.h>
31 #include <asm/perf_event.h>
32 #include <asm/sysreg.h>
33
34 #include <trace/events/kvm.h>
35
36 #include "sys_regs.h"
37 #include "vgic/vgic.h"
38
39 #include "trace.h"
40
41 /*
42 * For AArch32, we only take care of what is being trapped. Anything
43 * that has to do with init and userspace access has to go via the
44 * 64bit interface.
45 */
46
47 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
48 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
49 u64 val);
50
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)51 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
52 const struct sys_reg_desc *r)
53 {
54 kvm_inject_undefined(vcpu);
55 return false;
56 }
57
bad_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r,const char * msg)58 static bool bad_trap(struct kvm_vcpu *vcpu,
59 struct sys_reg_params *params,
60 const struct sys_reg_desc *r,
61 const char *msg)
62 {
63 WARN_ONCE(1, "Unexpected %s\n", msg);
64 print_sys_reg_instr(params);
65 return undef_access(vcpu, params, r);
66 }
67
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)68 static bool read_from_write_only(struct kvm_vcpu *vcpu,
69 struct sys_reg_params *params,
70 const struct sys_reg_desc *r)
71 {
72 return bad_trap(vcpu, params, r,
73 "sys_reg read to write-only register");
74 }
75
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)76 static bool write_to_read_only(struct kvm_vcpu *vcpu,
77 struct sys_reg_params *params,
78 const struct sys_reg_desc *r)
79 {
80 return bad_trap(vcpu, params, r,
81 "sys_reg write to read-only register");
82 }
83
84 #define PURE_EL2_SYSREG(el2) \
85 case el2: { \
86 *el1r = el2; \
87 return true; \
88 }
89
90 #define MAPPED_EL2_SYSREG(el2, el1, fn) \
91 case el2: { \
92 *xlate = fn; \
93 *el1r = el1; \
94 return true; \
95 }
96
get_el2_to_el1_mapping(unsigned int reg,unsigned int * el1r,u64 (** xlate)(u64))97 static bool get_el2_to_el1_mapping(unsigned int reg,
98 unsigned int *el1r, u64 (**xlate)(u64))
99 {
100 switch (reg) {
101 PURE_EL2_SYSREG( VPIDR_EL2 );
102 PURE_EL2_SYSREG( VMPIDR_EL2 );
103 PURE_EL2_SYSREG( ACTLR_EL2 );
104 PURE_EL2_SYSREG( HCR_EL2 );
105 PURE_EL2_SYSREG( MDCR_EL2 );
106 PURE_EL2_SYSREG( HSTR_EL2 );
107 PURE_EL2_SYSREG( HACR_EL2 );
108 PURE_EL2_SYSREG( VTTBR_EL2 );
109 PURE_EL2_SYSREG( VTCR_EL2 );
110 PURE_EL2_SYSREG( RVBAR_EL2 );
111 PURE_EL2_SYSREG( TPIDR_EL2 );
112 PURE_EL2_SYSREG( HPFAR_EL2 );
113 PURE_EL2_SYSREG( CNTHCTL_EL2 );
114 MAPPED_EL2_SYSREG(SCTLR_EL2, SCTLR_EL1,
115 translate_sctlr_el2_to_sctlr_el1 );
116 MAPPED_EL2_SYSREG(CPTR_EL2, CPACR_EL1,
117 translate_cptr_el2_to_cpacr_el1 );
118 MAPPED_EL2_SYSREG(TTBR0_EL2, TTBR0_EL1,
119 translate_ttbr0_el2_to_ttbr0_el1 );
120 MAPPED_EL2_SYSREG(TTBR1_EL2, TTBR1_EL1, NULL );
121 MAPPED_EL2_SYSREG(TCR_EL2, TCR_EL1,
122 translate_tcr_el2_to_tcr_el1 );
123 MAPPED_EL2_SYSREG(VBAR_EL2, VBAR_EL1, NULL );
124 MAPPED_EL2_SYSREG(AFSR0_EL2, AFSR0_EL1, NULL );
125 MAPPED_EL2_SYSREG(AFSR1_EL2, AFSR1_EL1, NULL );
126 MAPPED_EL2_SYSREG(ESR_EL2, ESR_EL1, NULL );
127 MAPPED_EL2_SYSREG(FAR_EL2, FAR_EL1, NULL );
128 MAPPED_EL2_SYSREG(MAIR_EL2, MAIR_EL1, NULL );
129 MAPPED_EL2_SYSREG(AMAIR_EL2, AMAIR_EL1, NULL );
130 MAPPED_EL2_SYSREG(ELR_EL2, ELR_EL1, NULL );
131 MAPPED_EL2_SYSREG(SPSR_EL2, SPSR_EL1, NULL );
132 MAPPED_EL2_SYSREG(ZCR_EL2, ZCR_EL1, NULL );
133 default:
134 return false;
135 }
136 }
137
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)138 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
139 {
140 u64 val = 0x8badf00d8badf00d;
141 u64 (*xlate)(u64) = NULL;
142 unsigned int el1r;
143
144 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
145 goto memory_read;
146
147 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
148 if (!is_hyp_ctxt(vcpu))
149 goto memory_read;
150
151 /*
152 * If this register does not have an EL1 counterpart,
153 * then read the stored EL2 version.
154 */
155 if (reg == el1r)
156 goto memory_read;
157
158 /*
159 * If we have a non-VHE guest and that the sysreg
160 * requires translation to be used at EL1, use the
161 * in-memory copy instead.
162 */
163 if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
164 goto memory_read;
165
166 /* Get the current version of the EL1 counterpart. */
167 WARN_ON(!__vcpu_read_sys_reg_from_cpu(el1r, &val));
168 return val;
169 }
170
171 /* EL1 register can't be on the CPU if the guest is in vEL2. */
172 if (unlikely(is_hyp_ctxt(vcpu)))
173 goto memory_read;
174
175 if (__vcpu_read_sys_reg_from_cpu(reg, &val))
176 return val;
177
178 memory_read:
179 return __vcpu_sys_reg(vcpu, reg);
180 }
181
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)182 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
183 {
184 u64 (*xlate)(u64) = NULL;
185 unsigned int el1r;
186
187 if (!vcpu_get_flag(vcpu, SYSREGS_ON_CPU))
188 goto memory_write;
189
190 if (unlikely(get_el2_to_el1_mapping(reg, &el1r, &xlate))) {
191 if (!is_hyp_ctxt(vcpu))
192 goto memory_write;
193
194 /*
195 * Always store a copy of the write to memory to avoid having
196 * to reverse-translate virtual EL2 system registers for a
197 * non-VHE guest hypervisor.
198 */
199 __vcpu_sys_reg(vcpu, reg) = val;
200
201 /* No EL1 counterpart? We're done here.? */
202 if (reg == el1r)
203 return;
204
205 if (!vcpu_el2_e2h_is_set(vcpu) && xlate)
206 val = xlate(val);
207
208 /* Redirect this to the EL1 version of the register. */
209 WARN_ON(!__vcpu_write_sys_reg_to_cpu(val, el1r));
210 return;
211 }
212
213 /* EL1 register can't be on the CPU if the guest is in vEL2. */
214 if (unlikely(is_hyp_ctxt(vcpu)))
215 goto memory_write;
216
217 if (__vcpu_write_sys_reg_to_cpu(val, reg))
218 return;
219
220 memory_write:
221 __vcpu_sys_reg(vcpu, reg) = val;
222 }
223
224 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
225 #define CSSELR_MAX 14
226
227 /*
228 * Returns the minimum line size for the selected cache, expressed as
229 * Log2(bytes).
230 */
get_min_cache_line_size(bool icache)231 static u8 get_min_cache_line_size(bool icache)
232 {
233 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
234 u8 field;
235
236 if (icache)
237 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
238 else
239 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
240
241 /*
242 * Cache line size is represented as Log2(words) in CTR_EL0.
243 * Log2(bytes) can be derived with the following:
244 *
245 * Log2(words) + 2 = Log2(bytes / 4) + 2
246 * = Log2(bytes) - 2 + 2
247 * = Log2(bytes)
248 */
249 return field + 2;
250 }
251
252 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)253 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
254 {
255 u8 line_size;
256
257 if (vcpu->arch.ccsidr)
258 return vcpu->arch.ccsidr[csselr];
259
260 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
261
262 /*
263 * Fabricate a CCSIDR value as the overriding value does not exist.
264 * The real CCSIDR value will not be used as it can vary by the
265 * physical CPU which the vcpu currently resides in.
266 *
267 * The line size is determined with get_min_cache_line_size(), which
268 * should be valid for all CPUs even if they have different cache
269 * configuration.
270 *
271 * The associativity bits are cleared, meaning the geometry of all data
272 * and unified caches (which are guaranteed to be PIPT and thus
273 * non-aliasing) are 1 set and 1 way.
274 * Guests should not be doing cache operations by set/way at all, and
275 * for this reason, we trap them and attempt to infer the intent, so
276 * that we can flush the entire guest's address space at the appropriate
277 * time. The exposed geometry minimizes the number of the traps.
278 * [If guests should attempt to infer aliasing properties from the
279 * geometry (which is not permitted by the architecture), they would
280 * only do so for virtually indexed caches.]
281 *
282 * We don't check if the cache level exists as it is allowed to return
283 * an UNKNOWN value if not.
284 */
285 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
286 }
287
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)288 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
289 {
290 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
291 u32 *ccsidr = vcpu->arch.ccsidr;
292 u32 i;
293
294 if ((val & CCSIDR_EL1_RES0) ||
295 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
296 return -EINVAL;
297
298 if (!ccsidr) {
299 if (val == get_ccsidr(vcpu, csselr))
300 return 0;
301
302 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
303 if (!ccsidr)
304 return -ENOMEM;
305
306 for (i = 0; i < CSSELR_MAX; i++)
307 ccsidr[i] = get_ccsidr(vcpu, i);
308
309 vcpu->arch.ccsidr = ccsidr;
310 }
311
312 ccsidr[csselr] = val;
313
314 return 0;
315 }
316
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)317 static bool access_rw(struct kvm_vcpu *vcpu,
318 struct sys_reg_params *p,
319 const struct sys_reg_desc *r)
320 {
321 if (p->is_write)
322 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
323 else
324 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
325
326 return true;
327 }
328
329 /*
330 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
331 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)332 static bool access_dcsw(struct kvm_vcpu *vcpu,
333 struct sys_reg_params *p,
334 const struct sys_reg_desc *r)
335 {
336 if (!p->is_write)
337 return read_from_write_only(vcpu, p, r);
338
339 /*
340 * Only track S/W ops if we don't have FWB. It still indicates
341 * that the guest is a bit broken (S/W operations should only
342 * be done by firmware, knowing that there is only a single
343 * CPU left in the system, and certainly not from non-secure
344 * software).
345 */
346 if (!cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
347 kvm_set_way_flush(vcpu);
348
349 return true;
350 }
351
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)352 static bool access_dcgsw(struct kvm_vcpu *vcpu,
353 struct sys_reg_params *p,
354 const struct sys_reg_desc *r)
355 {
356 if (!kvm_has_mte(vcpu->kvm))
357 return undef_access(vcpu, p, r);
358
359 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
360 return access_dcsw(vcpu, p, r);
361 }
362
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)363 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
364 {
365 switch (r->aarch32_map) {
366 case AA32_LO:
367 *mask = GENMASK_ULL(31, 0);
368 *shift = 0;
369 break;
370 case AA32_HI:
371 *mask = GENMASK_ULL(63, 32);
372 *shift = 32;
373 break;
374 default:
375 *mask = GENMASK_ULL(63, 0);
376 *shift = 0;
377 break;
378 }
379 }
380
381 /*
382 * Generic accessor for VM registers. Only called as long as HCR_TVM
383 * is set. If the guest enables the MMU, we stop trapping the VM
384 * sys_regs and leave it in complete control of the caches.
385 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)386 static bool access_vm_reg(struct kvm_vcpu *vcpu,
387 struct sys_reg_params *p,
388 const struct sys_reg_desc *r)
389 {
390 bool was_enabled = vcpu_has_cache_enabled(vcpu);
391 u64 val, mask, shift;
392
393 if (reg_to_encoding(r) == SYS_TCR2_EL1 &&
394 !kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, TCRX, IMP))
395 return undef_access(vcpu, p, r);
396
397 BUG_ON(!p->is_write);
398
399 get_access_mask(r, &mask, &shift);
400
401 if (~mask) {
402 val = vcpu_read_sys_reg(vcpu, r->reg);
403 val &= ~mask;
404 } else {
405 val = 0;
406 }
407
408 val |= (p->regval & (mask >> shift)) << shift;
409 vcpu_write_sys_reg(vcpu, val, r->reg);
410
411 kvm_toggle_cache(vcpu, was_enabled);
412 return true;
413 }
414
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)415 static bool access_actlr(struct kvm_vcpu *vcpu,
416 struct sys_reg_params *p,
417 const struct sys_reg_desc *r)
418 {
419 u64 mask, shift;
420
421 if (p->is_write)
422 return ignore_write(vcpu, p);
423
424 get_access_mask(r, &mask, &shift);
425 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
426
427 return true;
428 }
429
430 /*
431 * Trap handler for the GICv3 SGI generation system register.
432 * Forward the request to the VGIC emulation.
433 * The cp15_64 code makes sure this automatically works
434 * for both AArch64 and AArch32 accesses.
435 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)436 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
437 struct sys_reg_params *p,
438 const struct sys_reg_desc *r)
439 {
440 bool g1;
441
442 if (!kvm_has_gicv3(vcpu->kvm))
443 return undef_access(vcpu, p, r);
444
445 if (!p->is_write)
446 return read_from_write_only(vcpu, p, r);
447
448 /*
449 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
450 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
451 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
452 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
453 * group.
454 */
455 if (p->Op0 == 0) { /* AArch32 */
456 switch (p->Op1) {
457 default: /* Keep GCC quiet */
458 case 0: /* ICC_SGI1R */
459 g1 = true;
460 break;
461 case 1: /* ICC_ASGI1R */
462 case 2: /* ICC_SGI0R */
463 g1 = false;
464 break;
465 }
466 } else { /* AArch64 */
467 switch (p->Op2) {
468 default: /* Keep GCC quiet */
469 case 5: /* ICC_SGI1R_EL1 */
470 g1 = true;
471 break;
472 case 6: /* ICC_ASGI1R_EL1 */
473 case 7: /* ICC_SGI0R_EL1 */
474 g1 = false;
475 break;
476 }
477 }
478
479 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
480
481 return true;
482 }
483
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)484 static bool access_gic_sre(struct kvm_vcpu *vcpu,
485 struct sys_reg_params *p,
486 const struct sys_reg_desc *r)
487 {
488 if (!kvm_has_gicv3(vcpu->kvm))
489 return undef_access(vcpu, p, r);
490
491 if (p->is_write)
492 return ignore_write(vcpu, p);
493
494 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
495 return true;
496 }
497
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)498 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
499 struct sys_reg_params *p,
500 const struct sys_reg_desc *r)
501 {
502 if (p->is_write)
503 return ignore_write(vcpu, p);
504 else
505 return read_zero(vcpu, p);
506 }
507
508 /*
509 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
510 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
511 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
512 * treat it separately.
513 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)514 static bool trap_loregion(struct kvm_vcpu *vcpu,
515 struct sys_reg_params *p,
516 const struct sys_reg_desc *r)
517 {
518 u32 sr = reg_to_encoding(r);
519
520 if (!kvm_has_feat(vcpu->kvm, ID_AA64MMFR1_EL1, LO, IMP))
521 return undef_access(vcpu, p, r);
522
523 if (p->is_write && sr == SYS_LORID_EL1)
524 return write_to_read_only(vcpu, p, r);
525
526 return trap_raz_wi(vcpu, p, r);
527 }
528
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)529 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
530 struct sys_reg_params *p,
531 const struct sys_reg_desc *r)
532 {
533 u64 oslsr;
534
535 if (!p->is_write)
536 return read_from_write_only(vcpu, p, r);
537
538 /* Forward the OSLK bit to OSLSR */
539 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK;
540 if (p->regval & OSLAR_EL1_OSLK)
541 oslsr |= OSLSR_EL1_OSLK;
542
543 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
544 return true;
545 }
546
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)547 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
548 struct sys_reg_params *p,
549 const struct sys_reg_desc *r)
550 {
551 if (p->is_write)
552 return write_to_read_only(vcpu, p, r);
553
554 p->regval = __vcpu_sys_reg(vcpu, r->reg);
555 return true;
556 }
557
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)558 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
559 u64 val)
560 {
561 /*
562 * The only modifiable bit is the OSLK bit. Refuse the write if
563 * userspace attempts to change any other bit in the register.
564 */
565 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
566 return -EINVAL;
567
568 __vcpu_sys_reg(vcpu, rd->reg) = val;
569 return 0;
570 }
571
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)572 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
573 struct sys_reg_params *p,
574 const struct sys_reg_desc *r)
575 {
576 if (p->is_write) {
577 return ignore_write(vcpu, p);
578 } else {
579 p->regval = read_sysreg(dbgauthstatus_el1);
580 return true;
581 }
582 }
583
584 /*
585 * We want to avoid world-switching all the DBG registers all the
586 * time:
587 *
588 * - If we've touched any debug register, it is likely that we're
589 * going to touch more of them. It then makes sense to disable the
590 * traps and start doing the save/restore dance
591 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
592 * then mandatory to save/restore the registers, as the guest
593 * depends on them.
594 *
595 * For this, we use a DIRTY bit, indicating the guest has modified the
596 * debug registers, used as follow:
597 *
598 * On guest entry:
599 * - If the dirty bit is set (because we're coming back from trapping),
600 * disable the traps, save host registers, restore guest registers.
601 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
602 * set the dirty bit, disable the traps, save host registers,
603 * restore guest registers.
604 * - Otherwise, enable the traps
605 *
606 * On guest exit:
607 * - If the dirty bit is set, save guest registers, restore host
608 * registers and clear the dirty bit. This ensure that the host can
609 * now use the debug registers.
610 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)611 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
612 struct sys_reg_params *p,
613 const struct sys_reg_desc *r)
614 {
615 access_rw(vcpu, p, r);
616 if (p->is_write)
617 vcpu_set_flag(vcpu, DEBUG_DIRTY);
618
619 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
620
621 return true;
622 }
623
624 /*
625 * reg_to_dbg/dbg_to_reg
626 *
627 * A 32 bit write to a debug register leave top bits alone
628 * A 32 bit read from a debug register only returns the bottom bits
629 *
630 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
631 * switches between host and guest values in future.
632 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)633 static void reg_to_dbg(struct kvm_vcpu *vcpu,
634 struct sys_reg_params *p,
635 const struct sys_reg_desc *rd,
636 u64 *dbg_reg)
637 {
638 u64 mask, shift, val;
639
640 get_access_mask(rd, &mask, &shift);
641
642 val = *dbg_reg;
643 val &= ~mask;
644 val |= (p->regval & (mask >> shift)) << shift;
645 *dbg_reg = val;
646
647 vcpu_set_flag(vcpu, DEBUG_DIRTY);
648 }
649
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)650 static void dbg_to_reg(struct kvm_vcpu *vcpu,
651 struct sys_reg_params *p,
652 const struct sys_reg_desc *rd,
653 u64 *dbg_reg)
654 {
655 u64 mask, shift;
656
657 get_access_mask(rd, &mask, &shift);
658 p->regval = (*dbg_reg & mask) >> shift;
659 }
660
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)661 static bool trap_bvr(struct kvm_vcpu *vcpu,
662 struct sys_reg_params *p,
663 const struct sys_reg_desc *rd)
664 {
665 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
666
667 if (p->is_write)
668 reg_to_dbg(vcpu, p, rd, dbg_reg);
669 else
670 dbg_to_reg(vcpu, p, rd, dbg_reg);
671
672 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
673
674 return true;
675 }
676
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)677 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
678 u64 val)
679 {
680 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
681 return 0;
682 }
683
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)684 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
685 u64 *val)
686 {
687 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
688 return 0;
689 }
690
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)691 static u64 reset_bvr(struct kvm_vcpu *vcpu,
692 const struct sys_reg_desc *rd)
693 {
694 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
695 return rd->val;
696 }
697
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)698 static bool trap_bcr(struct kvm_vcpu *vcpu,
699 struct sys_reg_params *p,
700 const struct sys_reg_desc *rd)
701 {
702 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
703
704 if (p->is_write)
705 reg_to_dbg(vcpu, p, rd, dbg_reg);
706 else
707 dbg_to_reg(vcpu, p, rd, dbg_reg);
708
709 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
710
711 return true;
712 }
713
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)714 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
715 u64 val)
716 {
717 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
718 return 0;
719 }
720
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)721 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
722 u64 *val)
723 {
724 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
725 return 0;
726 }
727
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)728 static u64 reset_bcr(struct kvm_vcpu *vcpu,
729 const struct sys_reg_desc *rd)
730 {
731 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
732 return rd->val;
733 }
734
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)735 static bool trap_wvr(struct kvm_vcpu *vcpu,
736 struct sys_reg_params *p,
737 const struct sys_reg_desc *rd)
738 {
739 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
740
741 if (p->is_write)
742 reg_to_dbg(vcpu, p, rd, dbg_reg);
743 else
744 dbg_to_reg(vcpu, p, rd, dbg_reg);
745
746 trace_trap_reg(__func__, rd->CRm, p->is_write,
747 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
748
749 return true;
750 }
751
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)752 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
753 u64 val)
754 {
755 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
756 return 0;
757 }
758
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)759 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
760 u64 *val)
761 {
762 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
763 return 0;
764 }
765
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)766 static u64 reset_wvr(struct kvm_vcpu *vcpu,
767 const struct sys_reg_desc *rd)
768 {
769 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
770 return rd->val;
771 }
772
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)773 static bool trap_wcr(struct kvm_vcpu *vcpu,
774 struct sys_reg_params *p,
775 const struct sys_reg_desc *rd)
776 {
777 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
778
779 if (p->is_write)
780 reg_to_dbg(vcpu, p, rd, dbg_reg);
781 else
782 dbg_to_reg(vcpu, p, rd, dbg_reg);
783
784 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
785
786 return true;
787 }
788
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)789 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
790 u64 val)
791 {
792 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
793 return 0;
794 }
795
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)796 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
797 u64 *val)
798 {
799 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
800 return 0;
801 }
802
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)803 static u64 reset_wcr(struct kvm_vcpu *vcpu,
804 const struct sys_reg_desc *rd)
805 {
806 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
807 return rd->val;
808 }
809
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)810 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
811 {
812 u64 amair = read_sysreg(amair_el1);
813 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
814 return amair;
815 }
816
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)817 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
818 {
819 u64 actlr = read_sysreg(actlr_el1);
820 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
821 return actlr;
822 }
823
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)824 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
825 {
826 u64 mpidr;
827
828 /*
829 * Map the vcpu_id into the first three affinity level fields of
830 * the MPIDR. We limit the number of VCPUs in level 0 due to a
831 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
832 * of the GICv3 to be able to address each CPU directly when
833 * sending IPIs.
834 */
835 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
836 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
837 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
838 mpidr |= (1ULL << 31);
839 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
840
841 return mpidr;
842 }
843
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)844 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
845 const struct sys_reg_desc *r)
846 {
847 if (kvm_vcpu_has_pmu(vcpu))
848 return 0;
849
850 return REG_HIDDEN;
851 }
852
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)853 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
854 {
855 u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
856 u8 n = vcpu->kvm->arch.pmcr_n;
857
858 if (n)
859 mask |= GENMASK(n - 1, 0);
860
861 reset_unknown(vcpu, r);
862 __vcpu_sys_reg(vcpu, r->reg) &= mask;
863
864 return __vcpu_sys_reg(vcpu, r->reg);
865 }
866
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)867 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
868 {
869 reset_unknown(vcpu, r);
870 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
871
872 return __vcpu_sys_reg(vcpu, r->reg);
873 }
874
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)875 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
876 {
877 /* This thing will UNDEF, who cares about the reset value? */
878 if (!kvm_vcpu_has_pmu(vcpu))
879 return 0;
880
881 reset_unknown(vcpu, r);
882 __vcpu_sys_reg(vcpu, r->reg) &= kvm_pmu_evtyper_mask(vcpu->kvm);
883
884 return __vcpu_sys_reg(vcpu, r->reg);
885 }
886
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)887 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
888 {
889 reset_unknown(vcpu, r);
890 __vcpu_sys_reg(vcpu, r->reg) &= PMSELR_EL0_SEL_MASK;
891
892 return __vcpu_sys_reg(vcpu, r->reg);
893 }
894
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)895 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
896 {
897 u64 pmcr = 0;
898
899 if (!kvm_supports_32bit_el0())
900 pmcr |= ARMV8_PMU_PMCR_LC;
901
902 /*
903 * The value of PMCR.N field is included when the
904 * vCPU register is read via kvm_vcpu_read_pmcr().
905 */
906 __vcpu_sys_reg(vcpu, r->reg) = pmcr;
907
908 return __vcpu_sys_reg(vcpu, r->reg);
909 }
910
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)911 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
912 {
913 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
914 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
915
916 if (!enabled)
917 kvm_inject_undefined(vcpu);
918
919 return !enabled;
920 }
921
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)922 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
923 {
924 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
925 }
926
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)927 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
928 {
929 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
930 }
931
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)932 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
933 {
934 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
935 }
936
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)937 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
938 {
939 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
940 }
941
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)942 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
943 const struct sys_reg_desc *r)
944 {
945 u64 val;
946
947 if (pmu_access_el0_disabled(vcpu))
948 return false;
949
950 if (p->is_write) {
951 /*
952 * Only update writeable bits of PMCR (continuing into
953 * kvm_pmu_handle_pmcr() as well)
954 */
955 val = kvm_vcpu_read_pmcr(vcpu);
956 val &= ~ARMV8_PMU_PMCR_MASK;
957 val |= p->regval & ARMV8_PMU_PMCR_MASK;
958 if (!kvm_supports_32bit_el0())
959 val |= ARMV8_PMU_PMCR_LC;
960 kvm_pmu_handle_pmcr(vcpu, val);
961 } else {
962 /* PMCR.P & PMCR.C are RAZ */
963 val = kvm_vcpu_read_pmcr(vcpu)
964 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
965 p->regval = val;
966 }
967
968 return true;
969 }
970
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)971 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
972 const struct sys_reg_desc *r)
973 {
974 if (pmu_access_event_counter_el0_disabled(vcpu))
975 return false;
976
977 if (p->is_write)
978 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
979 else
980 /* return PMSELR.SEL field */
981 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
982 & PMSELR_EL0_SEL_MASK;
983
984 return true;
985 }
986
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)987 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
988 const struct sys_reg_desc *r)
989 {
990 u64 pmceid, mask, shift;
991
992 BUG_ON(p->is_write);
993
994 if (pmu_access_el0_disabled(vcpu))
995 return false;
996
997 get_access_mask(r, &mask, &shift);
998
999 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
1000 pmceid &= mask;
1001 pmceid >>= shift;
1002
1003 p->regval = pmceid;
1004
1005 return true;
1006 }
1007
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)1008 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
1009 {
1010 u64 pmcr, val;
1011
1012 pmcr = kvm_vcpu_read_pmcr(vcpu);
1013 val = FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
1014 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
1015 kvm_inject_undefined(vcpu);
1016 return false;
1017 }
1018
1019 return true;
1020 }
1021
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1022 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1023 u64 *val)
1024 {
1025 u64 idx;
1026
1027 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
1028 /* PMCCNTR_EL0 */
1029 idx = ARMV8_PMU_CYCLE_IDX;
1030 else
1031 /* PMEVCNTRn_EL0 */
1032 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1033
1034 *val = kvm_pmu_get_counter_value(vcpu, idx);
1035 return 0;
1036 }
1037
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1038 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
1039 struct sys_reg_params *p,
1040 const struct sys_reg_desc *r)
1041 {
1042 u64 idx = ~0UL;
1043
1044 if (r->CRn == 9 && r->CRm == 13) {
1045 if (r->Op2 == 2) {
1046 /* PMXEVCNTR_EL0 */
1047 if (pmu_access_event_counter_el0_disabled(vcpu))
1048 return false;
1049
1050 idx = SYS_FIELD_GET(PMSELR_EL0, SEL,
1051 __vcpu_sys_reg(vcpu, PMSELR_EL0));
1052 } else if (r->Op2 == 0) {
1053 /* PMCCNTR_EL0 */
1054 if (pmu_access_cycle_counter_el0_disabled(vcpu))
1055 return false;
1056
1057 idx = ARMV8_PMU_CYCLE_IDX;
1058 }
1059 } else if (r->CRn == 0 && r->CRm == 9) {
1060 /* PMCCNTR */
1061 if (pmu_access_event_counter_el0_disabled(vcpu))
1062 return false;
1063
1064 idx = ARMV8_PMU_CYCLE_IDX;
1065 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
1066 /* PMEVCNTRn_EL0 */
1067 if (pmu_access_event_counter_el0_disabled(vcpu))
1068 return false;
1069
1070 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1071 }
1072
1073 /* Catch any decoding mistake */
1074 WARN_ON(idx == ~0UL);
1075
1076 if (!pmu_counter_idx_valid(vcpu, idx))
1077 return false;
1078
1079 if (p->is_write) {
1080 if (pmu_access_el0_disabled(vcpu))
1081 return false;
1082
1083 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
1084 } else {
1085 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
1086 }
1087
1088 return true;
1089 }
1090
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1091 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1092 const struct sys_reg_desc *r)
1093 {
1094 u64 idx, reg;
1095
1096 if (pmu_access_el0_disabled(vcpu))
1097 return false;
1098
1099 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
1100 /* PMXEVTYPER_EL0 */
1101 idx = SYS_FIELD_GET(PMSELR_EL0, SEL, __vcpu_sys_reg(vcpu, PMSELR_EL0));
1102 reg = PMEVTYPER0_EL0 + idx;
1103 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
1104 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
1105 if (idx == ARMV8_PMU_CYCLE_IDX)
1106 reg = PMCCFILTR_EL0;
1107 else
1108 /* PMEVTYPERn_EL0 */
1109 reg = PMEVTYPER0_EL0 + idx;
1110 } else {
1111 BUG();
1112 }
1113
1114 if (!pmu_counter_idx_valid(vcpu, idx))
1115 return false;
1116
1117 if (p->is_write) {
1118 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
1119 kvm_vcpu_pmu_restore_guest(vcpu);
1120 } else {
1121 p->regval = __vcpu_sys_reg(vcpu, reg);
1122 }
1123
1124 return true;
1125 }
1126
set_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1127 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 val)
1128 {
1129 bool set;
1130
1131 val &= kvm_pmu_valid_counter_mask(vcpu);
1132
1133 switch (r->reg) {
1134 case PMOVSSET_EL0:
1135 /* CRm[1] being set indicates a SET register, and CLR otherwise */
1136 set = r->CRm & 2;
1137 break;
1138 default:
1139 /* Op2[0] being set indicates a SET register, and CLR otherwise */
1140 set = r->Op2 & 1;
1141 break;
1142 }
1143
1144 if (set)
1145 __vcpu_sys_reg(vcpu, r->reg) |= val;
1146 else
1147 __vcpu_sys_reg(vcpu, r->reg) &= ~val;
1148
1149 return 0;
1150 }
1151
get_pmreg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1152 static int get_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, u64 *val)
1153 {
1154 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1155
1156 *val = __vcpu_sys_reg(vcpu, r->reg) & mask;
1157 return 0;
1158 }
1159
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1160 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1161 const struct sys_reg_desc *r)
1162 {
1163 u64 val, mask;
1164
1165 if (pmu_access_el0_disabled(vcpu))
1166 return false;
1167
1168 mask = kvm_pmu_valid_counter_mask(vcpu);
1169 if (p->is_write) {
1170 val = p->regval & mask;
1171 if (r->Op2 & 0x1) {
1172 /* accessing PMCNTENSET_EL0 */
1173 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
1174 kvm_pmu_enable_counter_mask(vcpu, val);
1175 kvm_vcpu_pmu_restore_guest(vcpu);
1176 } else {
1177 /* accessing PMCNTENCLR_EL0 */
1178 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
1179 kvm_pmu_disable_counter_mask(vcpu, val);
1180 }
1181 } else {
1182 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
1183 }
1184
1185 return true;
1186 }
1187
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1188 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1189 const struct sys_reg_desc *r)
1190 {
1191 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1192
1193 if (check_pmu_access_disabled(vcpu, 0))
1194 return false;
1195
1196 if (p->is_write) {
1197 u64 val = p->regval & mask;
1198
1199 if (r->Op2 & 0x1)
1200 /* accessing PMINTENSET_EL1 */
1201 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
1202 else
1203 /* accessing PMINTENCLR_EL1 */
1204 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1205 } else {
1206 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1207 }
1208
1209 return true;
1210 }
1211
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1212 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1213 const struct sys_reg_desc *r)
1214 {
1215 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1216
1217 if (pmu_access_el0_disabled(vcpu))
1218 return false;
1219
1220 if (p->is_write) {
1221 if (r->CRm & 0x2)
1222 /* accessing PMOVSSET_EL0 */
1223 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
1224 else
1225 /* accessing PMOVSCLR_EL0 */
1226 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
1227 } else {
1228 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1229 }
1230
1231 return true;
1232 }
1233
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1234 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1235 const struct sys_reg_desc *r)
1236 {
1237 u64 mask;
1238
1239 if (!p->is_write)
1240 return read_from_write_only(vcpu, p, r);
1241
1242 if (pmu_write_swinc_el0_disabled(vcpu))
1243 return false;
1244
1245 mask = kvm_pmu_valid_counter_mask(vcpu);
1246 kvm_pmu_software_increment(vcpu, p->regval & mask);
1247 return true;
1248 }
1249
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1250 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1251 const struct sys_reg_desc *r)
1252 {
1253 if (p->is_write) {
1254 if (!vcpu_mode_priv(vcpu))
1255 return undef_access(vcpu, p, r);
1256
1257 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1258 p->regval & ARMV8_PMU_USERENR_MASK;
1259 } else {
1260 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1261 & ARMV8_PMU_USERENR_MASK;
1262 }
1263
1264 return true;
1265 }
1266
get_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)1267 static int get_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1268 u64 *val)
1269 {
1270 *val = kvm_vcpu_read_pmcr(vcpu);
1271 return 0;
1272 }
1273
set_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 val)1274 static int set_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
1275 u64 val)
1276 {
1277 u8 new_n = FIELD_GET(ARMV8_PMU_PMCR_N, val);
1278 struct kvm *kvm = vcpu->kvm;
1279
1280 mutex_lock(&kvm->arch.config_lock);
1281
1282 /*
1283 * The vCPU can't have more counters than the PMU hardware
1284 * implements. Ignore this error to maintain compatibility
1285 * with the existing KVM behavior.
1286 */
1287 if (!kvm_vm_has_ran_once(kvm) &&
1288 new_n <= kvm_arm_pmu_get_max_counters(kvm))
1289 kvm->arch.pmcr_n = new_n;
1290
1291 mutex_unlock(&kvm->arch.config_lock);
1292
1293 /*
1294 * Ignore writes to RES0 bits, read only bits that are cleared on
1295 * vCPU reset, and writable bits that KVM doesn't support yet.
1296 * (i.e. only PMCR.N and bits [7:0] are mutable from userspace)
1297 * The LP bit is RES0 when FEAT_PMUv3p5 is not supported on the vCPU.
1298 * But, we leave the bit as it is here, as the vCPU's PMUver might
1299 * be changed later (NOTE: the bit will be cleared on first vCPU run
1300 * if necessary).
1301 */
1302 val &= ARMV8_PMU_PMCR_MASK;
1303
1304 /* The LC bit is RES1 when AArch32 is not supported */
1305 if (!kvm_supports_32bit_el0())
1306 val |= ARMV8_PMU_PMCR_LC;
1307
1308 __vcpu_sys_reg(vcpu, r->reg) = val;
1309 return 0;
1310 }
1311
1312 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1313 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1314 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1315 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1316 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1317 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1318 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1319 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1320 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1321 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1322
1323 #define PMU_SYS_REG(name) \
1324 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1325 .visibility = pmu_visibility
1326
1327 /* Macro to expand the PMEVCNTRn_EL0 register */
1328 #define PMU_PMEVCNTR_EL0(n) \
1329 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
1330 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
1331 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1332
1333 /* Macro to expand the PMEVTYPERn_EL0 register */
1334 #define PMU_PMEVTYPER_EL0(n) \
1335 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
1336 .reset = reset_pmevtyper, \
1337 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1338
1339 /* Macro to expand the AMU counter and type registers*/
1340 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1341 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1342 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1343 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1344
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1345 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1346 const struct sys_reg_desc *rd)
1347 {
1348 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1349 }
1350
1351 /*
1352 * If we land here on a PtrAuth access, that is because we didn't
1353 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1354 * way this happens is when the guest does not have PtrAuth support
1355 * enabled.
1356 */
1357 #define __PTRAUTH_KEY(k) \
1358 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1359 .visibility = ptrauth_visibility}
1360
1361 #define PTRAUTH_KEY(k) \
1362 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1363 __PTRAUTH_KEY(k ## KEYHI_EL1)
1364
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1365 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1366 struct sys_reg_params *p,
1367 const struct sys_reg_desc *r)
1368 {
1369 enum kvm_arch_timers tmr;
1370 enum kvm_arch_timer_regs treg;
1371 u64 reg = reg_to_encoding(r);
1372
1373 switch (reg) {
1374 case SYS_CNTP_TVAL_EL0:
1375 case SYS_AARCH32_CNTP_TVAL:
1376 tmr = TIMER_PTIMER;
1377 treg = TIMER_REG_TVAL;
1378 break;
1379 case SYS_CNTP_CTL_EL0:
1380 case SYS_AARCH32_CNTP_CTL:
1381 tmr = TIMER_PTIMER;
1382 treg = TIMER_REG_CTL;
1383 break;
1384 case SYS_CNTP_CVAL_EL0:
1385 case SYS_AARCH32_CNTP_CVAL:
1386 tmr = TIMER_PTIMER;
1387 treg = TIMER_REG_CVAL;
1388 break;
1389 case SYS_CNTPCT_EL0:
1390 case SYS_CNTPCTSS_EL0:
1391 case SYS_AARCH32_CNTPCT:
1392 tmr = TIMER_PTIMER;
1393 treg = TIMER_REG_CNT;
1394 break;
1395 default:
1396 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1397 return undef_access(vcpu, p, r);
1398 }
1399
1400 if (p->is_write)
1401 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1402 else
1403 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1404
1405 return true;
1406 }
1407
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1408 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1409 s64 new, s64 cur)
1410 {
1411 struct arm64_ftr_bits kvm_ftr = *ftrp;
1412
1413 /* Some features have different safe value type in KVM than host features */
1414 switch (id) {
1415 case SYS_ID_AA64DFR0_EL1:
1416 switch (kvm_ftr.shift) {
1417 case ID_AA64DFR0_EL1_PMUVer_SHIFT:
1418 kvm_ftr.type = FTR_LOWER_SAFE;
1419 break;
1420 case ID_AA64DFR0_EL1_DebugVer_SHIFT:
1421 kvm_ftr.type = FTR_LOWER_SAFE;
1422 break;
1423 }
1424 break;
1425 case SYS_ID_DFR0_EL1:
1426 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1427 kvm_ftr.type = FTR_LOWER_SAFE;
1428 break;
1429 }
1430
1431 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1432 }
1433
1434 /*
1435 * arm64_check_features() - Check if a feature register value constitutes
1436 * a subset of features indicated by the idreg's KVM sanitised limit.
1437 *
1438 * This function will check if each feature field of @val is the "safe" value
1439 * against idreg's KVM sanitised limit return from reset() callback.
1440 * If a field value in @val is the same as the one in limit, it is always
1441 * considered the safe value regardless For register fields that are not in
1442 * writable, only the value in limit is considered the safe value.
1443 *
1444 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1445 */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1446 static int arm64_check_features(struct kvm_vcpu *vcpu,
1447 const struct sys_reg_desc *rd,
1448 u64 val)
1449 {
1450 const struct arm64_ftr_reg *ftr_reg;
1451 const struct arm64_ftr_bits *ftrp = NULL;
1452 u32 id = reg_to_encoding(rd);
1453 u64 writable_mask = rd->val;
1454 u64 limit = rd->reset(vcpu, rd);
1455 u64 mask = 0;
1456
1457 /*
1458 * Hidden and unallocated ID registers may not have a corresponding
1459 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1460 * only safe value is 0.
1461 */
1462 if (sysreg_visible_as_raz(vcpu, rd))
1463 return val ? -E2BIG : 0;
1464
1465 ftr_reg = get_arm64_ftr_reg(id);
1466 if (!ftr_reg)
1467 return -EINVAL;
1468
1469 ftrp = ftr_reg->ftr_bits;
1470
1471 for (; ftrp && ftrp->width; ftrp++) {
1472 s64 f_val, f_lim, safe_val;
1473 u64 ftr_mask;
1474
1475 ftr_mask = arm64_ftr_mask(ftrp);
1476 if ((ftr_mask & writable_mask) != ftr_mask)
1477 continue;
1478
1479 f_val = arm64_ftr_value(ftrp, val);
1480 f_lim = arm64_ftr_value(ftrp, limit);
1481 mask |= ftr_mask;
1482
1483 if (f_val == f_lim)
1484 safe_val = f_val;
1485 else
1486 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1487
1488 if (safe_val != f_val)
1489 return -E2BIG;
1490 }
1491
1492 /* For fields that are not writable, values in limit are the safe values. */
1493 if ((val & ~mask) != (limit & ~mask))
1494 return -E2BIG;
1495
1496 return 0;
1497 }
1498
pmuver_to_perfmon(u8 pmuver)1499 static u8 pmuver_to_perfmon(u8 pmuver)
1500 {
1501 switch (pmuver) {
1502 case ID_AA64DFR0_EL1_PMUVer_IMP:
1503 return ID_DFR0_EL1_PerfMon_PMUv3;
1504 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1505 return ID_DFR0_EL1_PerfMon_IMPDEF;
1506 default:
1507 /* Anything ARMv8.1+ and NI have the same value. For now. */
1508 return pmuver;
1509 }
1510 }
1511
1512 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1513 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1514 const struct sys_reg_desc *r)
1515 {
1516 u32 id = reg_to_encoding(r);
1517 u64 val;
1518
1519 if (sysreg_visible_as_raz(vcpu, r))
1520 return 0;
1521
1522 val = read_sanitised_ftr_reg(id);
1523
1524 switch (id) {
1525 case SYS_ID_AA64PFR1_EL1:
1526 if (!kvm_has_mte(vcpu->kvm))
1527 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1528
1529 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1530 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_RNDR_trap);
1531 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_NMI);
1532 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE_frac);
1533 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_GCS);
1534 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_THE);
1535 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTEX);
1536 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_DF2);
1537 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_PFAR);
1538 break;
1539 case SYS_ID_AA64PFR2_EL1:
1540 /* We only expose FPMR */
1541 val &= ID_AA64PFR2_EL1_FPMR;
1542 break;
1543 case SYS_ID_AA64ISAR1_EL1:
1544 if (!vcpu_has_ptrauth(vcpu))
1545 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1546 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1547 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1548 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1549 break;
1550 case SYS_ID_AA64ISAR2_EL1:
1551 if (!vcpu_has_ptrauth(vcpu))
1552 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1553 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1554 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1555 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1556 break;
1557 case SYS_ID_AA64MMFR2_EL1:
1558 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1559 break;
1560 case SYS_ID_AA64MMFR3_EL1:
1561 val &= ID_AA64MMFR3_EL1_TCRX | ID_AA64MMFR3_EL1_S1POE |
1562 ID_AA64MMFR3_EL1_S1PIE;
1563 break;
1564 case SYS_ID_MMFR4_EL1:
1565 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1566 break;
1567 }
1568
1569 return val;
1570 }
1571
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1572 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1573 const struct sys_reg_desc *r)
1574 {
1575 return __kvm_read_sanitised_id_reg(vcpu, r);
1576 }
1577
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1578 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1579 {
1580 return kvm_read_vm_id_reg(vcpu->kvm, reg_to_encoding(r));
1581 }
1582
is_feature_id_reg(u32 encoding)1583 static bool is_feature_id_reg(u32 encoding)
1584 {
1585 return (sys_reg_Op0(encoding) == 3 &&
1586 (sys_reg_Op1(encoding) < 2 || sys_reg_Op1(encoding) == 3) &&
1587 sys_reg_CRn(encoding) == 0 &&
1588 sys_reg_CRm(encoding) <= 7);
1589 }
1590
1591 /*
1592 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1593 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8, which is the range of ID
1594 * registers KVM maintains on a per-VM basis.
1595 */
is_vm_ftr_id_reg(u32 id)1596 static inline bool is_vm_ftr_id_reg(u32 id)
1597 {
1598 if (id == SYS_CTR_EL0)
1599 return true;
1600
1601 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1602 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1603 sys_reg_CRm(id) < 8);
1604 }
1605
is_vcpu_ftr_id_reg(u32 id)1606 static inline bool is_vcpu_ftr_id_reg(u32 id)
1607 {
1608 return is_feature_id_reg(id) && !is_vm_ftr_id_reg(id);
1609 }
1610
is_aa32_id_reg(u32 id)1611 static inline bool is_aa32_id_reg(u32 id)
1612 {
1613 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1614 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1615 sys_reg_CRm(id) <= 3);
1616 }
1617
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1618 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1619 const struct sys_reg_desc *r)
1620 {
1621 u32 id = reg_to_encoding(r);
1622
1623 switch (id) {
1624 case SYS_ID_AA64ZFR0_EL1:
1625 if (!vcpu_has_sve(vcpu))
1626 return REG_RAZ;
1627 break;
1628 }
1629
1630 return 0;
1631 }
1632
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1633 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1634 const struct sys_reg_desc *r)
1635 {
1636 /*
1637 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1638 * EL. Promote to RAZ/WI in order to guarantee consistency between
1639 * systems.
1640 */
1641 if (!kvm_supports_32bit_el0())
1642 return REG_RAZ | REG_USER_WI;
1643
1644 return id_visibility(vcpu, r);
1645 }
1646
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1647 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1648 const struct sys_reg_desc *r)
1649 {
1650 return REG_RAZ;
1651 }
1652
1653 /* cpufeature ID register access trap handlers */
1654
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1655 static bool access_id_reg(struct kvm_vcpu *vcpu,
1656 struct sys_reg_params *p,
1657 const struct sys_reg_desc *r)
1658 {
1659 if (p->is_write)
1660 return write_to_read_only(vcpu, p, r);
1661
1662 p->regval = read_id_reg(vcpu, r);
1663
1664 return true;
1665 }
1666
1667 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1668 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1669 const struct sys_reg_desc *rd)
1670 {
1671 if (vcpu_has_sve(vcpu))
1672 return 0;
1673
1674 return REG_HIDDEN;
1675 }
1676
sme_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1677 static unsigned int sme_visibility(const struct kvm_vcpu *vcpu,
1678 const struct sys_reg_desc *rd)
1679 {
1680 if (kvm_has_feat(vcpu->kvm, ID_AA64PFR1_EL1, SME, IMP))
1681 return 0;
1682
1683 return REG_HIDDEN;
1684 }
1685
fp8_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1686 static unsigned int fp8_visibility(const struct kvm_vcpu *vcpu,
1687 const struct sys_reg_desc *rd)
1688 {
1689 if (kvm_has_fpmr(vcpu->kvm))
1690 return 0;
1691
1692 return REG_HIDDEN;
1693 }
1694
read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1695 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1696 const struct sys_reg_desc *rd)
1697 {
1698 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1699
1700 if (!vcpu_has_sve(vcpu))
1701 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
1702
1703 /*
1704 * The default is to expose CSV2 == 1 if the HW isn't affected.
1705 * Although this is a per-CPU feature, we make it global because
1706 * asymmetric systems are just a nuisance.
1707 *
1708 * Userspace can override this as long as it doesn't promise
1709 * the impossible.
1710 */
1711 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1712 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1713 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1714 }
1715 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1716 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1717 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1718 }
1719
1720 if (kvm_vgic_global_state.type == VGIC_V3) {
1721 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1722 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1723 }
1724
1725 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
1726
1727 return val;
1728 }
1729
1730 #define ID_REG_LIMIT_FIELD_ENUM(val, reg, field, limit) \
1731 ({ \
1732 u64 __f_val = FIELD_GET(reg##_##field##_MASK, val); \
1733 (val) &= ~reg##_##field##_MASK; \
1734 (val) |= FIELD_PREP(reg##_##field##_MASK, \
1735 min(__f_val, \
1736 (u64)SYS_FIELD_VALUE(reg, field, limit))); \
1737 (val); \
1738 })
1739
read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1740 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1741 const struct sys_reg_desc *rd)
1742 {
1743 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1744
1745 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_AA64DFR0_EL1, DebugVer, V8P8);
1746
1747 /*
1748 * Only initialize the PMU version if the vCPU was configured with one.
1749 */
1750 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1751 if (kvm_vcpu_has_pmu(vcpu))
1752 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1753 kvm_arm_pmu_get_pmuver_limit());
1754
1755 /* Hide SPE from guests */
1756 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1757
1758 return val;
1759 }
1760
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1761 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1762 const struct sys_reg_desc *rd,
1763 u64 val)
1764 {
1765 u8 debugver = SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, val);
1766 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
1767
1768 /*
1769 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1770 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1771 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1772 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1773 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1774 *
1775 * At minimum, we're on the hook to allow values that were given to
1776 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1777 * with a more sensible NI. The value of an ID register changing under
1778 * the nose of the guest is unfortunate, but is certainly no more
1779 * surprising than an ill-guided PMU driver poking at impdef system
1780 * registers that end in an UNDEF...
1781 */
1782 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1783 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1784
1785 /*
1786 * ID_AA64DFR0_EL1.DebugVer is one of those awkward fields with a
1787 * nonzero minimum safe value.
1788 */
1789 if (debugver < ID_AA64DFR0_EL1_DebugVer_IMP)
1790 return -EINVAL;
1791
1792 return set_id_reg(vcpu, rd, val);
1793 }
1794
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1795 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1796 const struct sys_reg_desc *rd)
1797 {
1798 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1799 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
1800
1801 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1802 if (kvm_vcpu_has_pmu(vcpu))
1803 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
1804
1805 val = ID_REG_LIMIT_FIELD_ENUM(val, ID_DFR0_EL1, CopDbg, Debugv8p8);
1806
1807 return val;
1808 }
1809
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1810 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1811 const struct sys_reg_desc *rd,
1812 u64 val)
1813 {
1814 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
1815 u8 copdbg = SYS_FIELD_GET(ID_DFR0_EL1, CopDbg, val);
1816
1817 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1818 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1819 perfmon = 0;
1820 }
1821
1822 /*
1823 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1824 * it doesn't promise more than what the HW gives us on the
1825 * AArch64 side (as everything is emulated with that), and
1826 * that this is a PMUv3.
1827 */
1828 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
1829 return -EINVAL;
1830
1831 if (copdbg < ID_DFR0_EL1_CopDbg_Armv8)
1832 return -EINVAL;
1833
1834 return set_id_reg(vcpu, rd, val);
1835 }
1836
1837 /*
1838 * cpufeature ID register user accessors
1839 *
1840 * For now, these registers are immutable for userspace, so no values
1841 * are stored, and for set_id_reg() we don't allow the effective value
1842 * to be changed.
1843 */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1844 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1845 u64 *val)
1846 {
1847 /*
1848 * Avoid locking if the VM has already started, as the ID registers are
1849 * guaranteed to be invariant at that point.
1850 */
1851 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1852 *val = read_id_reg(vcpu, rd);
1853 return 0;
1854 }
1855
1856 mutex_lock(&vcpu->kvm->arch.config_lock);
1857 *val = read_id_reg(vcpu, rd);
1858 mutex_unlock(&vcpu->kvm->arch.config_lock);
1859
1860 return 0;
1861 }
1862
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1863 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1864 u64 val)
1865 {
1866 u32 id = reg_to_encoding(rd);
1867 int ret;
1868
1869 mutex_lock(&vcpu->kvm->arch.config_lock);
1870
1871 /*
1872 * Once the VM has started the ID registers are immutable. Reject any
1873 * write that does not match the final register value.
1874 */
1875 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1876 if (val != read_id_reg(vcpu, rd))
1877 ret = -EBUSY;
1878 else
1879 ret = 0;
1880
1881 mutex_unlock(&vcpu->kvm->arch.config_lock);
1882 return ret;
1883 }
1884
1885 ret = arm64_check_features(vcpu, rd, val);
1886 if (!ret)
1887 kvm_set_vm_id_reg(vcpu->kvm, id, val);
1888
1889 mutex_unlock(&vcpu->kvm->arch.config_lock);
1890
1891 /*
1892 * arm64_check_features() returns -E2BIG to indicate the register's
1893 * feature set is a superset of the maximally-allowed register value.
1894 * While it would be nice to precisely describe this to userspace, the
1895 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
1896 * writes return -EINVAL.
1897 */
1898 if (ret == -E2BIG)
1899 ret = -EINVAL;
1900 return ret;
1901 }
1902
kvm_set_vm_id_reg(struct kvm * kvm,u32 reg,u64 val)1903 void kvm_set_vm_id_reg(struct kvm *kvm, u32 reg, u64 val)
1904 {
1905 u64 *p = __vm_id_reg(&kvm->arch, reg);
1906
1907 lockdep_assert_held(&kvm->arch.config_lock);
1908
1909 if (KVM_BUG_ON(kvm_vm_has_ran_once(kvm) || !p, kvm))
1910 return;
1911
1912 *p = val;
1913 }
1914
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1915 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1916 u64 *val)
1917 {
1918 *val = 0;
1919 return 0;
1920 }
1921
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1922 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1923 u64 val)
1924 {
1925 return 0;
1926 }
1927
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1928 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1929 const struct sys_reg_desc *r)
1930 {
1931 if (p->is_write)
1932 return write_to_read_only(vcpu, p, r);
1933
1934 p->regval = kvm_read_vm_id_reg(vcpu->kvm, SYS_CTR_EL0);
1935 return true;
1936 }
1937
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1938 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1939 const struct sys_reg_desc *r)
1940 {
1941 if (p->is_write)
1942 return write_to_read_only(vcpu, p, r);
1943
1944 p->regval = __vcpu_sys_reg(vcpu, r->reg);
1945 return true;
1946 }
1947
1948 /*
1949 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
1950 * by the physical CPU which the vcpu currently resides in.
1951 */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1952 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1953 {
1954 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1955 u64 clidr;
1956 u8 loc;
1957
1958 if ((ctr_el0 & CTR_EL0_IDC)) {
1959 /*
1960 * Data cache clean to the PoU is not required so LoUU and LoUIS
1961 * will not be set and a unified cache, which will be marked as
1962 * LoC, will be added.
1963 *
1964 * If not DIC, let the unified cache L2 so that an instruction
1965 * cache can be added as L1 later.
1966 */
1967 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
1968 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
1969 } else {
1970 /*
1971 * Data cache clean to the PoU is required so let L1 have a data
1972 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
1973 * it can be marked as LoC too.
1974 */
1975 loc = 1;
1976 clidr = 1 << CLIDR_LOUU_SHIFT;
1977 clidr |= 1 << CLIDR_LOUIS_SHIFT;
1978 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
1979 }
1980
1981 /*
1982 * Instruction cache invalidation to the PoU is required so let L1 have
1983 * an instruction cache. If L1 already has a data cache, it will be
1984 * CACHE_TYPE_SEPARATE.
1985 */
1986 if (!(ctr_el0 & CTR_EL0_DIC))
1987 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
1988
1989 clidr |= loc << CLIDR_LOC_SHIFT;
1990
1991 /*
1992 * Add tag cache unified to data cache. Allocation tags and data are
1993 * unified in a cache line so that it looks valid even if there is only
1994 * one cache line.
1995 */
1996 if (kvm_has_mte(vcpu->kvm))
1997 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
1998
1999 __vcpu_sys_reg(vcpu, r->reg) = clidr;
2000
2001 return __vcpu_sys_reg(vcpu, r->reg);
2002 }
2003
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)2004 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
2005 u64 val)
2006 {
2007 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
2008 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
2009
2010 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
2011 return -EINVAL;
2012
2013 __vcpu_sys_reg(vcpu, rd->reg) = val;
2014
2015 return 0;
2016 }
2017
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2018 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2019 const struct sys_reg_desc *r)
2020 {
2021 int reg = r->reg;
2022
2023 if (p->is_write)
2024 vcpu_write_sys_reg(vcpu, p->regval, reg);
2025 else
2026 p->regval = vcpu_read_sys_reg(vcpu, reg);
2027 return true;
2028 }
2029
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2030 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2031 const struct sys_reg_desc *r)
2032 {
2033 u32 csselr;
2034
2035 if (p->is_write)
2036 return write_to_read_only(vcpu, p, r);
2037
2038 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
2039 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
2040 if (csselr < CSSELR_MAX)
2041 p->regval = get_ccsidr(vcpu, csselr);
2042
2043 return true;
2044 }
2045
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2046 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
2047 const struct sys_reg_desc *rd)
2048 {
2049 if (kvm_has_mte(vcpu->kvm))
2050 return 0;
2051
2052 return REG_HIDDEN;
2053 }
2054
2055 #define MTE_REG(name) { \
2056 SYS_DESC(SYS_##name), \
2057 .access = undef_access, \
2058 .reset = reset_unknown, \
2059 .reg = name, \
2060 .visibility = mte_visibility, \
2061 }
2062
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2063 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
2064 const struct sys_reg_desc *rd)
2065 {
2066 if (vcpu_has_nv(vcpu))
2067 return 0;
2068
2069 return REG_HIDDEN;
2070 }
2071
bad_vncr_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2072 static bool bad_vncr_trap(struct kvm_vcpu *vcpu,
2073 struct sys_reg_params *p,
2074 const struct sys_reg_desc *r)
2075 {
2076 /*
2077 * We really shouldn't be here, and this is likely the result
2078 * of a misconfigured trap, as this register should target the
2079 * VNCR page, and nothing else.
2080 */
2081 return bad_trap(vcpu, p, r,
2082 "trap of VNCR-backed register");
2083 }
2084
bad_redir_trap(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2085 static bool bad_redir_trap(struct kvm_vcpu *vcpu,
2086 struct sys_reg_params *p,
2087 const struct sys_reg_desc *r)
2088 {
2089 /*
2090 * We really shouldn't be here, and this is likely the result
2091 * of a misconfigured trap, as this register should target the
2092 * corresponding EL1, and nothing else.
2093 */
2094 return bad_trap(vcpu, p, r,
2095 "trap of EL2 register redirected to EL1");
2096 }
2097
2098 #define EL2_REG(name, acc, rst, v) { \
2099 SYS_DESC(SYS_##name), \
2100 .access = acc, \
2101 .reset = rst, \
2102 .reg = name, \
2103 .visibility = el2_visibility, \
2104 .val = v, \
2105 }
2106
2107 #define EL2_REG_VNCR(name, rst, v) EL2_REG(name, bad_vncr_trap, rst, v)
2108 #define EL2_REG_REDIR(name, rst, v) EL2_REG(name, bad_redir_trap, rst, v)
2109
2110 /*
2111 * Since reset() callback and field val are not used for idregs, they will be
2112 * used for specific purposes for idregs.
2113 * The reset() would return KVM sanitised register value. The value would be the
2114 * same as the host kernel sanitised value if there is no KVM sanitisation.
2115 * The val would be used as a mask indicating writable fields for the idreg.
2116 * Only bits with 1 are writable from userspace. This mask might not be
2117 * necessary in the future whenever all ID registers are enabled as writable
2118 * from userspace.
2119 */
2120
2121 #define ID_DESC(name) \
2122 SYS_DESC(SYS_##name), \
2123 .access = access_id_reg, \
2124 .get_user = get_id_reg \
2125
2126 /* sys_reg_desc initialiser for known cpufeature ID registers */
2127 #define ID_SANITISED(name) { \
2128 ID_DESC(name), \
2129 .set_user = set_id_reg, \
2130 .visibility = id_visibility, \
2131 .reset = kvm_read_sanitised_id_reg, \
2132 .val = 0, \
2133 }
2134
2135 /* sys_reg_desc initialiser for known cpufeature ID registers */
2136 #define AA32_ID_SANITISED(name) { \
2137 ID_DESC(name), \
2138 .set_user = set_id_reg, \
2139 .visibility = aa32_id_visibility, \
2140 .reset = kvm_read_sanitised_id_reg, \
2141 .val = 0, \
2142 }
2143
2144 /* sys_reg_desc initialiser for writable ID registers */
2145 #define ID_WRITABLE(name, mask) { \
2146 ID_DESC(name), \
2147 .set_user = set_id_reg, \
2148 .visibility = id_visibility, \
2149 .reset = kvm_read_sanitised_id_reg, \
2150 .val = mask, \
2151 }
2152
2153 /*
2154 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
2155 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
2156 * (1 <= crm < 8, 0 <= Op2 < 8).
2157 */
2158 #define ID_UNALLOCATED(crm, op2) { \
2159 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
2160 .access = access_id_reg, \
2161 .get_user = get_id_reg, \
2162 .set_user = set_id_reg, \
2163 .visibility = raz_visibility, \
2164 .reset = kvm_read_sanitised_id_reg, \
2165 .val = 0, \
2166 }
2167
2168 /*
2169 * sys_reg_desc initialiser for known ID registers that we hide from guests.
2170 * For now, these are exposed just like unallocated ID regs: they appear
2171 * RAZ for the guest.
2172 */
2173 #define ID_HIDDEN(name) { \
2174 ID_DESC(name), \
2175 .set_user = set_id_reg, \
2176 .visibility = raz_visibility, \
2177 .reset = kvm_read_sanitised_id_reg, \
2178 .val = 0, \
2179 }
2180
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2181 static bool access_sp_el1(struct kvm_vcpu *vcpu,
2182 struct sys_reg_params *p,
2183 const struct sys_reg_desc *r)
2184 {
2185 if (p->is_write)
2186 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
2187 else
2188 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
2189
2190 return true;
2191 }
2192
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2193 static bool access_elr(struct kvm_vcpu *vcpu,
2194 struct sys_reg_params *p,
2195 const struct sys_reg_desc *r)
2196 {
2197 if (p->is_write)
2198 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
2199 else
2200 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
2201
2202 return true;
2203 }
2204
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2205 static bool access_spsr(struct kvm_vcpu *vcpu,
2206 struct sys_reg_params *p,
2207 const struct sys_reg_desc *r)
2208 {
2209 if (p->is_write)
2210 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
2211 else
2212 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
2213
2214 return true;
2215 }
2216
access_cntkctl_el12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2217 static bool access_cntkctl_el12(struct kvm_vcpu *vcpu,
2218 struct sys_reg_params *p,
2219 const struct sys_reg_desc *r)
2220 {
2221 if (p->is_write)
2222 __vcpu_sys_reg(vcpu, CNTKCTL_EL1) = p->regval;
2223 else
2224 p->regval = __vcpu_sys_reg(vcpu, CNTKCTL_EL1);
2225
2226 return true;
2227 }
2228
reset_hcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)2229 static u64 reset_hcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
2230 {
2231 u64 val = r->val;
2232
2233 if (!cpus_have_final_cap(ARM64_HAS_HCR_NV1))
2234 val |= HCR_E2H;
2235
2236 return __vcpu_sys_reg(vcpu, r->reg) = val;
2237 }
2238
sve_el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2239 static unsigned int sve_el2_visibility(const struct kvm_vcpu *vcpu,
2240 const struct sys_reg_desc *rd)
2241 {
2242 unsigned int r;
2243
2244 r = el2_visibility(vcpu, rd);
2245 if (r)
2246 return r;
2247
2248 return sve_visibility(vcpu, rd);
2249 }
2250
access_zcr_el2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2251 static bool access_zcr_el2(struct kvm_vcpu *vcpu,
2252 struct sys_reg_params *p,
2253 const struct sys_reg_desc *r)
2254 {
2255 unsigned int vq;
2256
2257 if (guest_hyp_sve_traps_enabled(vcpu)) {
2258 kvm_inject_nested_sve_trap(vcpu);
2259 return true;
2260 }
2261
2262 if (!p->is_write) {
2263 p->regval = vcpu_read_sys_reg(vcpu, ZCR_EL2);
2264 return true;
2265 }
2266
2267 vq = SYS_FIELD_GET(ZCR_ELx, LEN, p->regval) + 1;
2268 vq = min(vq, vcpu_sve_max_vq(vcpu));
2269 vcpu_write_sys_reg(vcpu, vq - 1, ZCR_EL2);
2270 return true;
2271 }
2272
s1poe_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)2273 static unsigned int s1poe_visibility(const struct kvm_vcpu *vcpu,
2274 const struct sys_reg_desc *rd)
2275 {
2276 if (kvm_has_feat(vcpu->kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
2277 return 0;
2278
2279 return REG_HIDDEN;
2280 }
2281
2282 /*
2283 * Architected system registers.
2284 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
2285 *
2286 * Debug handling: We do trap most, if not all debug related system
2287 * registers. The implementation is good enough to ensure that a guest
2288 * can use these with minimal performance degradation. The drawback is
2289 * that we don't implement any of the external debug architecture.
2290 * This should be revisited if we ever encounter a more demanding
2291 * guest...
2292 */
2293 static const struct sys_reg_desc sys_reg_descs[] = {
2294 DBG_BCR_BVR_WCR_WVR_EL1(0),
2295 DBG_BCR_BVR_WCR_WVR_EL1(1),
2296 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
2297 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
2298 DBG_BCR_BVR_WCR_WVR_EL1(2),
2299 DBG_BCR_BVR_WCR_WVR_EL1(3),
2300 DBG_BCR_BVR_WCR_WVR_EL1(4),
2301 DBG_BCR_BVR_WCR_WVR_EL1(5),
2302 DBG_BCR_BVR_WCR_WVR_EL1(6),
2303 DBG_BCR_BVR_WCR_WVR_EL1(7),
2304 DBG_BCR_BVR_WCR_WVR_EL1(8),
2305 DBG_BCR_BVR_WCR_WVR_EL1(9),
2306 DBG_BCR_BVR_WCR_WVR_EL1(10),
2307 DBG_BCR_BVR_WCR_WVR_EL1(11),
2308 DBG_BCR_BVR_WCR_WVR_EL1(12),
2309 DBG_BCR_BVR_WCR_WVR_EL1(13),
2310 DBG_BCR_BVR_WCR_WVR_EL1(14),
2311 DBG_BCR_BVR_WCR_WVR_EL1(15),
2312
2313 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
2314 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
2315 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
2316 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
2317 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
2318 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
2319 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
2320 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
2321 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
2322
2323 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
2324 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
2325 // DBGDTR[TR]X_EL0 share the same encoding
2326 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
2327
2328 { SYS_DESC(SYS_DBGVCR32_EL2), undef_access, reset_val, DBGVCR32_EL2, 0 },
2329
2330 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
2331
2332 /*
2333 * ID regs: all ID_SANITISED() entries here must have corresponding
2334 * entries in arm64_ftr_regs[].
2335 */
2336
2337 /* AArch64 mappings of the AArch32 ID registers */
2338 /* CRm=1 */
2339 AA32_ID_SANITISED(ID_PFR0_EL1),
2340 AA32_ID_SANITISED(ID_PFR1_EL1),
2341 { SYS_DESC(SYS_ID_DFR0_EL1),
2342 .access = access_id_reg,
2343 .get_user = get_id_reg,
2344 .set_user = set_id_dfr0_el1,
2345 .visibility = aa32_id_visibility,
2346 .reset = read_sanitised_id_dfr0_el1,
2347 .val = ID_DFR0_EL1_PerfMon_MASK |
2348 ID_DFR0_EL1_CopDbg_MASK, },
2349 ID_HIDDEN(ID_AFR0_EL1),
2350 AA32_ID_SANITISED(ID_MMFR0_EL1),
2351 AA32_ID_SANITISED(ID_MMFR1_EL1),
2352 AA32_ID_SANITISED(ID_MMFR2_EL1),
2353 AA32_ID_SANITISED(ID_MMFR3_EL1),
2354
2355 /* CRm=2 */
2356 AA32_ID_SANITISED(ID_ISAR0_EL1),
2357 AA32_ID_SANITISED(ID_ISAR1_EL1),
2358 AA32_ID_SANITISED(ID_ISAR2_EL1),
2359 AA32_ID_SANITISED(ID_ISAR3_EL1),
2360 AA32_ID_SANITISED(ID_ISAR4_EL1),
2361 AA32_ID_SANITISED(ID_ISAR5_EL1),
2362 AA32_ID_SANITISED(ID_MMFR4_EL1),
2363 AA32_ID_SANITISED(ID_ISAR6_EL1),
2364
2365 /* CRm=3 */
2366 AA32_ID_SANITISED(MVFR0_EL1),
2367 AA32_ID_SANITISED(MVFR1_EL1),
2368 AA32_ID_SANITISED(MVFR2_EL1),
2369 ID_UNALLOCATED(3,3),
2370 AA32_ID_SANITISED(ID_PFR2_EL1),
2371 ID_HIDDEN(ID_DFR1_EL1),
2372 AA32_ID_SANITISED(ID_MMFR5_EL1),
2373 ID_UNALLOCATED(3,7),
2374
2375 /* AArch64 ID registers */
2376 /* CRm=4 */
2377 { SYS_DESC(SYS_ID_AA64PFR0_EL1),
2378 .access = access_id_reg,
2379 .get_user = get_id_reg,
2380 .set_user = set_id_reg,
2381 .reset = read_sanitised_id_aa64pfr0_el1,
2382 .val = ~(ID_AA64PFR0_EL1_AMU |
2383 ID_AA64PFR0_EL1_MPAM |
2384 ID_AA64PFR0_EL1_SVE |
2385 ID_AA64PFR0_EL1_RAS |
2386 ID_AA64PFR0_EL1_AdvSIMD |
2387 ID_AA64PFR0_EL1_FP), },
2388 ID_WRITABLE(ID_AA64PFR1_EL1, ~(ID_AA64PFR1_EL1_PFAR |
2389 ID_AA64PFR1_EL1_DF2 |
2390 ID_AA64PFR1_EL1_MTEX |
2391 ID_AA64PFR1_EL1_THE |
2392 ID_AA64PFR1_EL1_GCS |
2393 ID_AA64PFR1_EL1_MTE_frac |
2394 ID_AA64PFR1_EL1_NMI |
2395 ID_AA64PFR1_EL1_RNDR_trap |
2396 ID_AA64PFR1_EL1_SME |
2397 ID_AA64PFR1_EL1_RES0 |
2398 ID_AA64PFR1_EL1_MPAM_frac |
2399 ID_AA64PFR1_EL1_RAS_frac |
2400 ID_AA64PFR1_EL1_MTE)),
2401 ID_WRITABLE(ID_AA64PFR2_EL1, ID_AA64PFR2_EL1_FPMR),
2402 ID_UNALLOCATED(4,3),
2403 ID_WRITABLE(ID_AA64ZFR0_EL1, ~ID_AA64ZFR0_EL1_RES0),
2404 ID_HIDDEN(ID_AA64SMFR0_EL1),
2405 ID_UNALLOCATED(4,6),
2406 ID_WRITABLE(ID_AA64FPFR0_EL1, ~ID_AA64FPFR0_EL1_RES0),
2407
2408 /* CRm=5 */
2409 { SYS_DESC(SYS_ID_AA64DFR0_EL1),
2410 .access = access_id_reg,
2411 .get_user = get_id_reg,
2412 .set_user = set_id_aa64dfr0_el1,
2413 .reset = read_sanitised_id_aa64dfr0_el1,
2414 /*
2415 * Prior to FEAT_Debugv8.9, the architecture defines context-aware
2416 * breakpoints (CTX_CMPs) as the highest numbered breakpoints (BRPs).
2417 * KVM does not trap + emulate the breakpoint registers, and as such
2418 * cannot support a layout that misaligns with the underlying hardware.
2419 * While it may be possible to describe a subset that aligns with
2420 * hardware, just prevent changes to BRPs and CTX_CMPs altogether for
2421 * simplicity.
2422 *
2423 * See DDI0487K.a, section D2.8.3 Breakpoint types and linking
2424 * of breakpoints for more details.
2425 */
2426 .val = ID_AA64DFR0_EL1_DoubleLock_MASK |
2427 ID_AA64DFR0_EL1_WRPs_MASK |
2428 ID_AA64DFR0_EL1_PMUVer_MASK |
2429 ID_AA64DFR0_EL1_DebugVer_MASK, },
2430 ID_SANITISED(ID_AA64DFR1_EL1),
2431 ID_UNALLOCATED(5,2),
2432 ID_UNALLOCATED(5,3),
2433 ID_HIDDEN(ID_AA64AFR0_EL1),
2434 ID_HIDDEN(ID_AA64AFR1_EL1),
2435 ID_UNALLOCATED(5,6),
2436 ID_UNALLOCATED(5,7),
2437
2438 /* CRm=6 */
2439 ID_WRITABLE(ID_AA64ISAR0_EL1, ~ID_AA64ISAR0_EL1_RES0),
2440 ID_WRITABLE(ID_AA64ISAR1_EL1, ~(ID_AA64ISAR1_EL1_GPI |
2441 ID_AA64ISAR1_EL1_GPA |
2442 ID_AA64ISAR1_EL1_API |
2443 ID_AA64ISAR1_EL1_APA)),
2444 ID_WRITABLE(ID_AA64ISAR2_EL1, ~(ID_AA64ISAR2_EL1_RES0 |
2445 ID_AA64ISAR2_EL1_APA3 |
2446 ID_AA64ISAR2_EL1_GPA3)),
2447 ID_UNALLOCATED(6,3),
2448 ID_UNALLOCATED(6,4),
2449 ID_UNALLOCATED(6,5),
2450 ID_UNALLOCATED(6,6),
2451 ID_UNALLOCATED(6,7),
2452
2453 /* CRm=7 */
2454 ID_WRITABLE(ID_AA64MMFR0_EL1, ~(ID_AA64MMFR0_EL1_RES0 |
2455 ID_AA64MMFR0_EL1_TGRAN4_2 |
2456 ID_AA64MMFR0_EL1_TGRAN64_2 |
2457 ID_AA64MMFR0_EL1_TGRAN16_2)),
2458 ID_WRITABLE(ID_AA64MMFR1_EL1, ~(ID_AA64MMFR1_EL1_RES0 |
2459 ID_AA64MMFR1_EL1_HCX |
2460 ID_AA64MMFR1_EL1_TWED |
2461 ID_AA64MMFR1_EL1_XNX |
2462 ID_AA64MMFR1_EL1_VH |
2463 ID_AA64MMFR1_EL1_VMIDBits)),
2464 ID_WRITABLE(ID_AA64MMFR2_EL1, ~(ID_AA64MMFR2_EL1_RES0 |
2465 ID_AA64MMFR2_EL1_EVT |
2466 ID_AA64MMFR2_EL1_FWB |
2467 ID_AA64MMFR2_EL1_IDS |
2468 ID_AA64MMFR2_EL1_NV |
2469 ID_AA64MMFR2_EL1_CCIDX)),
2470 ID_WRITABLE(ID_AA64MMFR3_EL1, (ID_AA64MMFR3_EL1_TCRX |
2471 ID_AA64MMFR3_EL1_S1PIE |
2472 ID_AA64MMFR3_EL1_S1POE)),
2473 ID_SANITISED(ID_AA64MMFR4_EL1),
2474 ID_UNALLOCATED(7,5),
2475 ID_UNALLOCATED(7,6),
2476 ID_UNALLOCATED(7,7),
2477
2478 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2479 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2480 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2481
2482 MTE_REG(RGSR_EL1),
2483 MTE_REG(GCR_EL1),
2484
2485 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2486 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2487 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2488 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2489 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2490 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2491 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2492 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2493
2494 PTRAUTH_KEY(APIA),
2495 PTRAUTH_KEY(APIB),
2496 PTRAUTH_KEY(APDA),
2497 PTRAUTH_KEY(APDB),
2498 PTRAUTH_KEY(APGA),
2499
2500 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2501 { SYS_DESC(SYS_ELR_EL1), access_elr},
2502
2503 { SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
2504
2505 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2506 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2507 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2508
2509 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2510 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2511 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2512 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2513 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2514 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2515 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2516 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2517
2518 MTE_REG(TFSR_EL1),
2519 MTE_REG(TFSRE0_EL1),
2520
2521 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2522 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2523
2524 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2525 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2526 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2527 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2528 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2529 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2530 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2531 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2532 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2533 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2534 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2535 /* PMBIDR_EL1 is not trapped */
2536
2537 { PMU_SYS_REG(PMINTENSET_EL1),
2538 .access = access_pminten, .reg = PMINTENSET_EL1,
2539 .get_user = get_pmreg, .set_user = set_pmreg },
2540 { PMU_SYS_REG(PMINTENCLR_EL1),
2541 .access = access_pminten, .reg = PMINTENSET_EL1,
2542 .get_user = get_pmreg, .set_user = set_pmreg },
2543 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2544
2545 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2546 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 },
2547 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 },
2548 { SYS_DESC(SYS_POR_EL1), NULL, reset_unknown, POR_EL1,
2549 .visibility = s1poe_visibility },
2550 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2551
2552 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2553 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2554 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2555 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2556 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
2557
2558 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2559 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2560
2561 { SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
2562 { SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
2563 { SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
2564 { SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
2565 { SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
2566 { SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
2567 { SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
2568 { SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
2569 { SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
2570 { SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
2571 { SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
2572 { SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
2573 { SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
2574 { SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
2575 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2576 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2577 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2578 { SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
2579 { SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
2580 { SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
2581 { SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
2582 { SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
2583 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2584 { SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
2585 { SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
2586
2587 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2588 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2589
2590 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2591
2592 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2593
2594 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2595
2596 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2597 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2598 .set_user = set_clidr, .val = ~CLIDR_EL1_RES0 },
2599 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2600 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2601 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2602 ID_WRITABLE(CTR_EL0, CTR_EL0_DIC_MASK |
2603 CTR_EL0_IDC_MASK |
2604 CTR_EL0_DminLine_MASK |
2605 CTR_EL0_IminLine_MASK),
2606 { SYS_DESC(SYS_SVCR), undef_access, reset_val, SVCR, 0, .visibility = sme_visibility },
2607 { SYS_DESC(SYS_FPMR), undef_access, reset_val, FPMR, 0, .visibility = fp8_visibility },
2608
2609 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr, .reset = reset_pmcr,
2610 .reg = PMCR_EL0, .get_user = get_pmcr, .set_user = set_pmcr },
2611 { PMU_SYS_REG(PMCNTENSET_EL0),
2612 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2613 .get_user = get_pmreg, .set_user = set_pmreg },
2614 { PMU_SYS_REG(PMCNTENCLR_EL0),
2615 .access = access_pmcnten, .reg = PMCNTENSET_EL0,
2616 .get_user = get_pmreg, .set_user = set_pmreg },
2617 { PMU_SYS_REG(PMOVSCLR_EL0),
2618 .access = access_pmovs, .reg = PMOVSSET_EL0,
2619 .get_user = get_pmreg, .set_user = set_pmreg },
2620 /*
2621 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2622 * previously (and pointlessly) advertised in the past...
2623 */
2624 { PMU_SYS_REG(PMSWINC_EL0),
2625 .get_user = get_raz_reg, .set_user = set_wi_reg,
2626 .access = access_pmswinc, .reset = NULL },
2627 { PMU_SYS_REG(PMSELR_EL0),
2628 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2629 { PMU_SYS_REG(PMCEID0_EL0),
2630 .access = access_pmceid, .reset = NULL },
2631 { PMU_SYS_REG(PMCEID1_EL0),
2632 .access = access_pmceid, .reset = NULL },
2633 { PMU_SYS_REG(PMCCNTR_EL0),
2634 .access = access_pmu_evcntr, .reset = reset_unknown,
2635 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2636 { PMU_SYS_REG(PMXEVTYPER_EL0),
2637 .access = access_pmu_evtyper, .reset = NULL },
2638 { PMU_SYS_REG(PMXEVCNTR_EL0),
2639 .access = access_pmu_evcntr, .reset = NULL },
2640 /*
2641 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2642 * in 32bit mode. Here we choose to reset it as zero for consistency.
2643 */
2644 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2645 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2646 { PMU_SYS_REG(PMOVSSET_EL0),
2647 .access = access_pmovs, .reg = PMOVSSET_EL0,
2648 .get_user = get_pmreg, .set_user = set_pmreg },
2649
2650 { SYS_DESC(SYS_POR_EL0), NULL, reset_unknown, POR_EL0,
2651 .visibility = s1poe_visibility },
2652 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2653 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2654 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2655
2656 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2657
2658 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2659 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2660 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2661 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2662 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2663 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2664 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2665 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2666 AMU_AMEVCNTR0_EL0(0),
2667 AMU_AMEVCNTR0_EL0(1),
2668 AMU_AMEVCNTR0_EL0(2),
2669 AMU_AMEVCNTR0_EL0(3),
2670 AMU_AMEVCNTR0_EL0(4),
2671 AMU_AMEVCNTR0_EL0(5),
2672 AMU_AMEVCNTR0_EL0(6),
2673 AMU_AMEVCNTR0_EL0(7),
2674 AMU_AMEVCNTR0_EL0(8),
2675 AMU_AMEVCNTR0_EL0(9),
2676 AMU_AMEVCNTR0_EL0(10),
2677 AMU_AMEVCNTR0_EL0(11),
2678 AMU_AMEVCNTR0_EL0(12),
2679 AMU_AMEVCNTR0_EL0(13),
2680 AMU_AMEVCNTR0_EL0(14),
2681 AMU_AMEVCNTR0_EL0(15),
2682 AMU_AMEVTYPER0_EL0(0),
2683 AMU_AMEVTYPER0_EL0(1),
2684 AMU_AMEVTYPER0_EL0(2),
2685 AMU_AMEVTYPER0_EL0(3),
2686 AMU_AMEVTYPER0_EL0(4),
2687 AMU_AMEVTYPER0_EL0(5),
2688 AMU_AMEVTYPER0_EL0(6),
2689 AMU_AMEVTYPER0_EL0(7),
2690 AMU_AMEVTYPER0_EL0(8),
2691 AMU_AMEVTYPER0_EL0(9),
2692 AMU_AMEVTYPER0_EL0(10),
2693 AMU_AMEVTYPER0_EL0(11),
2694 AMU_AMEVTYPER0_EL0(12),
2695 AMU_AMEVTYPER0_EL0(13),
2696 AMU_AMEVTYPER0_EL0(14),
2697 AMU_AMEVTYPER0_EL0(15),
2698 AMU_AMEVCNTR1_EL0(0),
2699 AMU_AMEVCNTR1_EL0(1),
2700 AMU_AMEVCNTR1_EL0(2),
2701 AMU_AMEVCNTR1_EL0(3),
2702 AMU_AMEVCNTR1_EL0(4),
2703 AMU_AMEVCNTR1_EL0(5),
2704 AMU_AMEVCNTR1_EL0(6),
2705 AMU_AMEVCNTR1_EL0(7),
2706 AMU_AMEVCNTR1_EL0(8),
2707 AMU_AMEVCNTR1_EL0(9),
2708 AMU_AMEVCNTR1_EL0(10),
2709 AMU_AMEVCNTR1_EL0(11),
2710 AMU_AMEVCNTR1_EL0(12),
2711 AMU_AMEVCNTR1_EL0(13),
2712 AMU_AMEVCNTR1_EL0(14),
2713 AMU_AMEVCNTR1_EL0(15),
2714 AMU_AMEVTYPER1_EL0(0),
2715 AMU_AMEVTYPER1_EL0(1),
2716 AMU_AMEVTYPER1_EL0(2),
2717 AMU_AMEVTYPER1_EL0(3),
2718 AMU_AMEVTYPER1_EL0(4),
2719 AMU_AMEVTYPER1_EL0(5),
2720 AMU_AMEVTYPER1_EL0(6),
2721 AMU_AMEVTYPER1_EL0(7),
2722 AMU_AMEVTYPER1_EL0(8),
2723 AMU_AMEVTYPER1_EL0(9),
2724 AMU_AMEVTYPER1_EL0(10),
2725 AMU_AMEVTYPER1_EL0(11),
2726 AMU_AMEVTYPER1_EL0(12),
2727 AMU_AMEVTYPER1_EL0(13),
2728 AMU_AMEVTYPER1_EL0(14),
2729 AMU_AMEVTYPER1_EL0(15),
2730
2731 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2732 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
2733 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2734 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2735 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
2736
2737 /* PMEVCNTRn_EL0 */
2738 PMU_PMEVCNTR_EL0(0),
2739 PMU_PMEVCNTR_EL0(1),
2740 PMU_PMEVCNTR_EL0(2),
2741 PMU_PMEVCNTR_EL0(3),
2742 PMU_PMEVCNTR_EL0(4),
2743 PMU_PMEVCNTR_EL0(5),
2744 PMU_PMEVCNTR_EL0(6),
2745 PMU_PMEVCNTR_EL0(7),
2746 PMU_PMEVCNTR_EL0(8),
2747 PMU_PMEVCNTR_EL0(9),
2748 PMU_PMEVCNTR_EL0(10),
2749 PMU_PMEVCNTR_EL0(11),
2750 PMU_PMEVCNTR_EL0(12),
2751 PMU_PMEVCNTR_EL0(13),
2752 PMU_PMEVCNTR_EL0(14),
2753 PMU_PMEVCNTR_EL0(15),
2754 PMU_PMEVCNTR_EL0(16),
2755 PMU_PMEVCNTR_EL0(17),
2756 PMU_PMEVCNTR_EL0(18),
2757 PMU_PMEVCNTR_EL0(19),
2758 PMU_PMEVCNTR_EL0(20),
2759 PMU_PMEVCNTR_EL0(21),
2760 PMU_PMEVCNTR_EL0(22),
2761 PMU_PMEVCNTR_EL0(23),
2762 PMU_PMEVCNTR_EL0(24),
2763 PMU_PMEVCNTR_EL0(25),
2764 PMU_PMEVCNTR_EL0(26),
2765 PMU_PMEVCNTR_EL0(27),
2766 PMU_PMEVCNTR_EL0(28),
2767 PMU_PMEVCNTR_EL0(29),
2768 PMU_PMEVCNTR_EL0(30),
2769 /* PMEVTYPERn_EL0 */
2770 PMU_PMEVTYPER_EL0(0),
2771 PMU_PMEVTYPER_EL0(1),
2772 PMU_PMEVTYPER_EL0(2),
2773 PMU_PMEVTYPER_EL0(3),
2774 PMU_PMEVTYPER_EL0(4),
2775 PMU_PMEVTYPER_EL0(5),
2776 PMU_PMEVTYPER_EL0(6),
2777 PMU_PMEVTYPER_EL0(7),
2778 PMU_PMEVTYPER_EL0(8),
2779 PMU_PMEVTYPER_EL0(9),
2780 PMU_PMEVTYPER_EL0(10),
2781 PMU_PMEVTYPER_EL0(11),
2782 PMU_PMEVTYPER_EL0(12),
2783 PMU_PMEVTYPER_EL0(13),
2784 PMU_PMEVTYPER_EL0(14),
2785 PMU_PMEVTYPER_EL0(15),
2786 PMU_PMEVTYPER_EL0(16),
2787 PMU_PMEVTYPER_EL0(17),
2788 PMU_PMEVTYPER_EL0(18),
2789 PMU_PMEVTYPER_EL0(19),
2790 PMU_PMEVTYPER_EL0(20),
2791 PMU_PMEVTYPER_EL0(21),
2792 PMU_PMEVTYPER_EL0(22),
2793 PMU_PMEVTYPER_EL0(23),
2794 PMU_PMEVTYPER_EL0(24),
2795 PMU_PMEVTYPER_EL0(25),
2796 PMU_PMEVTYPER_EL0(26),
2797 PMU_PMEVTYPER_EL0(27),
2798 PMU_PMEVTYPER_EL0(28),
2799 PMU_PMEVTYPER_EL0(29),
2800 PMU_PMEVTYPER_EL0(30),
2801 /*
2802 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
2803 * in 32bit mode. Here we choose to reset it as zero for consistency.
2804 */
2805 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
2806 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2807
2808 EL2_REG_VNCR(VPIDR_EL2, reset_unknown, 0),
2809 EL2_REG_VNCR(VMPIDR_EL2, reset_unknown, 0),
2810 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2811 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2812 EL2_REG_VNCR(HCR_EL2, reset_hcr, 0),
2813 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2814 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2815 EL2_REG_VNCR(HSTR_EL2, reset_val, 0),
2816 EL2_REG_VNCR(HFGRTR_EL2, reset_val, 0),
2817 EL2_REG_VNCR(HFGWTR_EL2, reset_val, 0),
2818 EL2_REG_VNCR(HFGITR_EL2, reset_val, 0),
2819 EL2_REG_VNCR(HACR_EL2, reset_val, 0),
2820
2821 { SYS_DESC(SYS_ZCR_EL2), .access = access_zcr_el2, .reset = reset_val,
2822 .visibility = sve_el2_visibility, .reg = ZCR_EL2 },
2823
2824 EL2_REG_VNCR(HCRX_EL2, reset_val, 0),
2825
2826 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2827 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2828 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2829 EL2_REG_VNCR(VTTBR_EL2, reset_val, 0),
2830 EL2_REG_VNCR(VTCR_EL2, reset_val, 0),
2831
2832 { SYS_DESC(SYS_DACR32_EL2), undef_access, reset_unknown, DACR32_EL2 },
2833 EL2_REG_VNCR(HDFGRTR_EL2, reset_val, 0),
2834 EL2_REG_VNCR(HDFGWTR_EL2, reset_val, 0),
2835 EL2_REG_VNCR(HAFGRTR_EL2, reset_val, 0),
2836 EL2_REG_REDIR(SPSR_EL2, reset_val, 0),
2837 EL2_REG_REDIR(ELR_EL2, reset_val, 0),
2838 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
2839
2840 /* AArch32 SPSR_* are RES0 if trapped from a NV guest */
2841 { SYS_DESC(SYS_SPSR_irq), .access = trap_raz_wi },
2842 { SYS_DESC(SYS_SPSR_abt), .access = trap_raz_wi },
2843 { SYS_DESC(SYS_SPSR_und), .access = trap_raz_wi },
2844 { SYS_DESC(SYS_SPSR_fiq), .access = trap_raz_wi },
2845
2846 { SYS_DESC(SYS_IFSR32_EL2), undef_access, reset_unknown, IFSR32_EL2 },
2847 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2848 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2849 EL2_REG_REDIR(ESR_EL2, reset_val, 0),
2850 { SYS_DESC(SYS_FPEXC32_EL2), undef_access, reset_val, FPEXC32_EL2, 0x700 },
2851
2852 EL2_REG_REDIR(FAR_EL2, reset_val, 0),
2853 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2854
2855 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2856 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2857
2858 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2859 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2860 { SYS_DESC(SYS_RMR_EL2), undef_access },
2861
2862 EL2_REG_VNCR(ICH_HCR_EL2, reset_val, 0),
2863
2864 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2865 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2866
2867 EL2_REG_VNCR(CNTVOFF_EL2, reset_val, 0),
2868 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2869
2870 { SYS_DESC(SYS_CNTKCTL_EL12), access_cntkctl_el12 },
2871
2872 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
2873 };
2874
handle_at_s1e01(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2875 static bool handle_at_s1e01(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2876 const struct sys_reg_desc *r)
2877 {
2878 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2879
2880 __kvm_at_s1e01(vcpu, op, p->regval);
2881
2882 return true;
2883 }
2884
handle_at_s1e2(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2885 static bool handle_at_s1e2(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2886 const struct sys_reg_desc *r)
2887 {
2888 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2889
2890 /* There is no FGT associated with AT S1E2A :-( */
2891 if (op == OP_AT_S1E2A &&
2892 !kvm_has_feat(vcpu->kvm, ID_AA64ISAR2_EL1, ATS1A, IMP)) {
2893 kvm_inject_undefined(vcpu);
2894 return false;
2895 }
2896
2897 __kvm_at_s1e2(vcpu, op, p->regval);
2898
2899 return true;
2900 }
2901
handle_at_s12(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2902 static bool handle_at_s12(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2903 const struct sys_reg_desc *r)
2904 {
2905 u32 op = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2906
2907 __kvm_at_s12(vcpu, op, p->regval);
2908
2909 return true;
2910 }
2911
kvm_supported_tlbi_s12_op(struct kvm_vcpu * vpcu,u32 instr)2912 static bool kvm_supported_tlbi_s12_op(struct kvm_vcpu *vpcu, u32 instr)
2913 {
2914 struct kvm *kvm = vpcu->kvm;
2915 u8 CRm = sys_reg_CRm(instr);
2916
2917 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
2918 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
2919 return false;
2920
2921 if (CRm == TLBI_CRm_nROS &&
2922 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
2923 return false;
2924
2925 return true;
2926 }
2927
handle_alle1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2928 static bool handle_alle1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
2929 const struct sys_reg_desc *r)
2930 {
2931 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
2932
2933 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
2934 return undef_access(vcpu, p, r);
2935
2936 write_lock(&vcpu->kvm->mmu_lock);
2937
2938 /*
2939 * Drop all shadow S2s, resulting in S1/S2 TLBIs for each of the
2940 * corresponding VMIDs.
2941 */
2942 kvm_nested_s2_unmap(vcpu->kvm, true);
2943
2944 write_unlock(&vcpu->kvm->mmu_lock);
2945
2946 return true;
2947 }
2948
kvm_supported_tlbi_ipas2_op(struct kvm_vcpu * vpcu,u32 instr)2949 static bool kvm_supported_tlbi_ipas2_op(struct kvm_vcpu *vpcu, u32 instr)
2950 {
2951 struct kvm *kvm = vpcu->kvm;
2952 u8 CRm = sys_reg_CRm(instr);
2953 u8 Op2 = sys_reg_Op2(instr);
2954
2955 if (sys_reg_CRn(instr) == TLBI_CRn_nXS &&
2956 !kvm_has_feat(kvm, ID_AA64ISAR1_EL1, XS, IMP))
2957 return false;
2958
2959 if (CRm == TLBI_CRm_IPAIS && (Op2 == 2 || Op2 == 6) &&
2960 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
2961 return false;
2962
2963 if (CRm == TLBI_CRm_IPAONS && (Op2 == 0 || Op2 == 4) &&
2964 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
2965 return false;
2966
2967 if (CRm == TLBI_CRm_IPAONS && (Op2 == 3 || Op2 == 7) &&
2968 !kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
2969 return false;
2970
2971 return true;
2972 }
2973
2974 /* Only defined here as this is an internal "abstraction" */
2975 union tlbi_info {
2976 struct {
2977 u64 start;
2978 u64 size;
2979 } range;
2980
2981 struct {
2982 u64 addr;
2983 } ipa;
2984
2985 struct {
2986 u64 addr;
2987 u32 encoding;
2988 } va;
2989 };
2990
s2_mmu_unmap_range(struct kvm_s2_mmu * mmu,const union tlbi_info * info)2991 static void s2_mmu_unmap_range(struct kvm_s2_mmu *mmu,
2992 const union tlbi_info *info)
2993 {
2994 /*
2995 * The unmap operation is allowed to drop the MMU lock and block, which
2996 * means that @mmu could be used for a different context than the one
2997 * currently being invalidated.
2998 *
2999 * This behavior is still safe, as:
3000 *
3001 * 1) The vCPU(s) that recycled the MMU are responsible for invalidating
3002 * the entire MMU before reusing it, which still honors the intent
3003 * of a TLBI.
3004 *
3005 * 2) Until the guest TLBI instruction is 'retired' (i.e. increment PC
3006 * and ERET to the guest), other vCPUs are allowed to use stale
3007 * translations.
3008 *
3009 * 3) Accidentally unmapping an unrelated MMU context is nonfatal, and
3010 * at worst may cause more aborts for shadow stage-2 fills.
3011 *
3012 * Dropping the MMU lock also implies that shadow stage-2 fills could
3013 * happen behind the back of the TLBI. This is still safe, though, as
3014 * the L1 needs to put its stage-2 in a consistent state before doing
3015 * the TLBI.
3016 */
3017 kvm_stage2_unmap_range(mmu, info->range.start, info->range.size, true);
3018 }
3019
handle_vmalls12e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3020 static bool handle_vmalls12e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3021 const struct sys_reg_desc *r)
3022 {
3023 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3024 u64 limit, vttbr;
3025
3026 if (!kvm_supported_tlbi_s12_op(vcpu, sys_encoding))
3027 return undef_access(vcpu, p, r);
3028
3029 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3030 limit = BIT_ULL(kvm_get_pa_bits(vcpu->kvm));
3031
3032 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3033 &(union tlbi_info) {
3034 .range = {
3035 .start = 0,
3036 .size = limit,
3037 },
3038 },
3039 s2_mmu_unmap_range);
3040
3041 return true;
3042 }
3043
handle_ripas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3044 static bool handle_ripas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3045 const struct sys_reg_desc *r)
3046 {
3047 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3048 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3049 u64 base, range, tg, num, scale;
3050 int shift;
3051
3052 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
3053 return undef_access(vcpu, p, r);
3054
3055 /*
3056 * Because the shadow S2 structure doesn't necessarily reflect that
3057 * of the guest's S2 (different base granule size, for example), we
3058 * decide to ignore TTL and only use the described range.
3059 */
3060 tg = FIELD_GET(GENMASK(47, 46), p->regval);
3061 scale = FIELD_GET(GENMASK(45, 44), p->regval);
3062 num = FIELD_GET(GENMASK(43, 39), p->regval);
3063 base = p->regval & GENMASK(36, 0);
3064
3065 switch(tg) {
3066 case 1:
3067 shift = 12;
3068 break;
3069 case 2:
3070 shift = 14;
3071 break;
3072 case 3:
3073 default: /* IMPDEF: handle tg==0 as 64k */
3074 shift = 16;
3075 break;
3076 }
3077
3078 base <<= shift;
3079 range = __TLBI_RANGE_PAGES(num, scale) << shift;
3080
3081 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3082 &(union tlbi_info) {
3083 .range = {
3084 .start = base,
3085 .size = range,
3086 },
3087 },
3088 s2_mmu_unmap_range);
3089
3090 return true;
3091 }
3092
s2_mmu_unmap_ipa(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3093 static void s2_mmu_unmap_ipa(struct kvm_s2_mmu *mmu,
3094 const union tlbi_info *info)
3095 {
3096 unsigned long max_size;
3097 u64 base_addr;
3098
3099 /*
3100 * We drop a number of things from the supplied value:
3101 *
3102 * - NS bit: we're non-secure only.
3103 *
3104 * - IPA[51:48]: We don't support 52bit IPA just yet...
3105 *
3106 * And of course, adjust the IPA to be on an actual address.
3107 */
3108 base_addr = (info->ipa.addr & GENMASK_ULL(35, 0)) << 12;
3109 max_size = compute_tlb_inval_range(mmu, info->ipa.addr);
3110 base_addr &= ~(max_size - 1);
3111
3112 /*
3113 * See comment in s2_mmu_unmap_range() for why this is allowed to
3114 * reschedule.
3115 */
3116 kvm_stage2_unmap_range(mmu, base_addr, max_size, true);
3117 }
3118
handle_ipas2e1is(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3119 static bool handle_ipas2e1is(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3120 const struct sys_reg_desc *r)
3121 {
3122 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3123 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3124
3125 if (!kvm_supported_tlbi_ipas2_op(vcpu, sys_encoding))
3126 return undef_access(vcpu, p, r);
3127
3128 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3129 &(union tlbi_info) {
3130 .ipa = {
3131 .addr = p->regval,
3132 },
3133 },
3134 s2_mmu_unmap_ipa);
3135
3136 return true;
3137 }
3138
s2_mmu_tlbi_s1e1(struct kvm_s2_mmu * mmu,const union tlbi_info * info)3139 static void s2_mmu_tlbi_s1e1(struct kvm_s2_mmu *mmu,
3140 const union tlbi_info *info)
3141 {
3142 WARN_ON(__kvm_tlbi_s1e2(mmu, info->va.addr, info->va.encoding));
3143 }
3144
handle_tlbi_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3145 static bool handle_tlbi_el1(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
3146 const struct sys_reg_desc *r)
3147 {
3148 u32 sys_encoding = sys_insn(p->Op0, p->Op1, p->CRn, p->CRm, p->Op2);
3149 u64 vttbr = vcpu_read_sys_reg(vcpu, VTTBR_EL2);
3150
3151 /*
3152 * If we're here, this is because we've trapped on a EL1 TLBI
3153 * instruction that affects the EL1 translation regime while
3154 * we're running in a context that doesn't allow us to let the
3155 * HW do its thing (aka vEL2):
3156 *
3157 * - HCR_EL2.E2H == 0 : a non-VHE guest
3158 * - HCR_EL2.{E2H,TGE} == { 1, 0 } : a VHE guest in guest mode
3159 *
3160 * We don't expect these helpers to ever be called when running
3161 * in a vEL1 context.
3162 */
3163
3164 WARN_ON(!vcpu_is_el2(vcpu));
3165
3166 if (!kvm_supported_tlbi_s1e1_op(vcpu, sys_encoding))
3167 return undef_access(vcpu, p, r);
3168
3169 kvm_s2_mmu_iterate_by_vmid(vcpu->kvm, get_vmid(vttbr),
3170 &(union tlbi_info) {
3171 .va = {
3172 .addr = p->regval,
3173 .encoding = sys_encoding,
3174 },
3175 },
3176 s2_mmu_tlbi_s1e1);
3177
3178 return true;
3179 }
3180
3181 #define SYS_INSN(insn, access_fn) \
3182 { \
3183 SYS_DESC(OP_##insn), \
3184 .access = (access_fn), \
3185 }
3186
3187 static struct sys_reg_desc sys_insn_descs[] = {
3188 { SYS_DESC(SYS_DC_ISW), access_dcsw },
3189 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
3190 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
3191
3192 SYS_INSN(AT_S1E1R, handle_at_s1e01),
3193 SYS_INSN(AT_S1E1W, handle_at_s1e01),
3194 SYS_INSN(AT_S1E0R, handle_at_s1e01),
3195 SYS_INSN(AT_S1E0W, handle_at_s1e01),
3196 SYS_INSN(AT_S1E1RP, handle_at_s1e01),
3197 SYS_INSN(AT_S1E1WP, handle_at_s1e01),
3198
3199 { SYS_DESC(SYS_DC_CSW), access_dcsw },
3200 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
3201 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
3202 { SYS_DESC(SYS_DC_CISW), access_dcsw },
3203 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
3204 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
3205
3206 SYS_INSN(TLBI_VMALLE1OS, handle_tlbi_el1),
3207 SYS_INSN(TLBI_VAE1OS, handle_tlbi_el1),
3208 SYS_INSN(TLBI_ASIDE1OS, handle_tlbi_el1),
3209 SYS_INSN(TLBI_VAAE1OS, handle_tlbi_el1),
3210 SYS_INSN(TLBI_VALE1OS, handle_tlbi_el1),
3211 SYS_INSN(TLBI_VAALE1OS, handle_tlbi_el1),
3212
3213 SYS_INSN(TLBI_RVAE1IS, handle_tlbi_el1),
3214 SYS_INSN(TLBI_RVAAE1IS, handle_tlbi_el1),
3215 SYS_INSN(TLBI_RVALE1IS, handle_tlbi_el1),
3216 SYS_INSN(TLBI_RVAALE1IS, handle_tlbi_el1),
3217
3218 SYS_INSN(TLBI_VMALLE1IS, handle_tlbi_el1),
3219 SYS_INSN(TLBI_VAE1IS, handle_tlbi_el1),
3220 SYS_INSN(TLBI_ASIDE1IS, handle_tlbi_el1),
3221 SYS_INSN(TLBI_VAAE1IS, handle_tlbi_el1),
3222 SYS_INSN(TLBI_VALE1IS, handle_tlbi_el1),
3223 SYS_INSN(TLBI_VAALE1IS, handle_tlbi_el1),
3224
3225 SYS_INSN(TLBI_RVAE1OS, handle_tlbi_el1),
3226 SYS_INSN(TLBI_RVAAE1OS, handle_tlbi_el1),
3227 SYS_INSN(TLBI_RVALE1OS, handle_tlbi_el1),
3228 SYS_INSN(TLBI_RVAALE1OS, handle_tlbi_el1),
3229
3230 SYS_INSN(TLBI_RVAE1, handle_tlbi_el1),
3231 SYS_INSN(TLBI_RVAAE1, handle_tlbi_el1),
3232 SYS_INSN(TLBI_RVALE1, handle_tlbi_el1),
3233 SYS_INSN(TLBI_RVAALE1, handle_tlbi_el1),
3234
3235 SYS_INSN(TLBI_VMALLE1, handle_tlbi_el1),
3236 SYS_INSN(TLBI_VAE1, handle_tlbi_el1),
3237 SYS_INSN(TLBI_ASIDE1, handle_tlbi_el1),
3238 SYS_INSN(TLBI_VAAE1, handle_tlbi_el1),
3239 SYS_INSN(TLBI_VALE1, handle_tlbi_el1),
3240 SYS_INSN(TLBI_VAALE1, handle_tlbi_el1),
3241
3242 SYS_INSN(TLBI_VMALLE1OSNXS, handle_tlbi_el1),
3243 SYS_INSN(TLBI_VAE1OSNXS, handle_tlbi_el1),
3244 SYS_INSN(TLBI_ASIDE1OSNXS, handle_tlbi_el1),
3245 SYS_INSN(TLBI_VAAE1OSNXS, handle_tlbi_el1),
3246 SYS_INSN(TLBI_VALE1OSNXS, handle_tlbi_el1),
3247 SYS_INSN(TLBI_VAALE1OSNXS, handle_tlbi_el1),
3248
3249 SYS_INSN(TLBI_RVAE1ISNXS, handle_tlbi_el1),
3250 SYS_INSN(TLBI_RVAAE1ISNXS, handle_tlbi_el1),
3251 SYS_INSN(TLBI_RVALE1ISNXS, handle_tlbi_el1),
3252 SYS_INSN(TLBI_RVAALE1ISNXS, handle_tlbi_el1),
3253
3254 SYS_INSN(TLBI_VMALLE1ISNXS, handle_tlbi_el1),
3255 SYS_INSN(TLBI_VAE1ISNXS, handle_tlbi_el1),
3256 SYS_INSN(TLBI_ASIDE1ISNXS, handle_tlbi_el1),
3257 SYS_INSN(TLBI_VAAE1ISNXS, handle_tlbi_el1),
3258 SYS_INSN(TLBI_VALE1ISNXS, handle_tlbi_el1),
3259 SYS_INSN(TLBI_VAALE1ISNXS, handle_tlbi_el1),
3260
3261 SYS_INSN(TLBI_RVAE1OSNXS, handle_tlbi_el1),
3262 SYS_INSN(TLBI_RVAAE1OSNXS, handle_tlbi_el1),
3263 SYS_INSN(TLBI_RVALE1OSNXS, handle_tlbi_el1),
3264 SYS_INSN(TLBI_RVAALE1OSNXS, handle_tlbi_el1),
3265
3266 SYS_INSN(TLBI_RVAE1NXS, handle_tlbi_el1),
3267 SYS_INSN(TLBI_RVAAE1NXS, handle_tlbi_el1),
3268 SYS_INSN(TLBI_RVALE1NXS, handle_tlbi_el1),
3269 SYS_INSN(TLBI_RVAALE1NXS, handle_tlbi_el1),
3270
3271 SYS_INSN(TLBI_VMALLE1NXS, handle_tlbi_el1),
3272 SYS_INSN(TLBI_VAE1NXS, handle_tlbi_el1),
3273 SYS_INSN(TLBI_ASIDE1NXS, handle_tlbi_el1),
3274 SYS_INSN(TLBI_VAAE1NXS, handle_tlbi_el1),
3275 SYS_INSN(TLBI_VALE1NXS, handle_tlbi_el1),
3276 SYS_INSN(TLBI_VAALE1NXS, handle_tlbi_el1),
3277
3278 SYS_INSN(AT_S1E2R, handle_at_s1e2),
3279 SYS_INSN(AT_S1E2W, handle_at_s1e2),
3280 SYS_INSN(AT_S12E1R, handle_at_s12),
3281 SYS_INSN(AT_S12E1W, handle_at_s12),
3282 SYS_INSN(AT_S12E0R, handle_at_s12),
3283 SYS_INSN(AT_S12E0W, handle_at_s12),
3284 SYS_INSN(AT_S1E2A, handle_at_s1e2),
3285
3286 SYS_INSN(TLBI_IPAS2E1IS, handle_ipas2e1is),
3287 SYS_INSN(TLBI_RIPAS2E1IS, handle_ripas2e1is),
3288 SYS_INSN(TLBI_IPAS2LE1IS, handle_ipas2e1is),
3289 SYS_INSN(TLBI_RIPAS2LE1IS, handle_ripas2e1is),
3290
3291 SYS_INSN(TLBI_ALLE2OS, undef_access),
3292 SYS_INSN(TLBI_VAE2OS, undef_access),
3293 SYS_INSN(TLBI_ALLE1OS, handle_alle1is),
3294 SYS_INSN(TLBI_VALE2OS, undef_access),
3295 SYS_INSN(TLBI_VMALLS12E1OS, handle_vmalls12e1is),
3296
3297 SYS_INSN(TLBI_RVAE2IS, undef_access),
3298 SYS_INSN(TLBI_RVALE2IS, undef_access),
3299
3300 SYS_INSN(TLBI_ALLE1IS, handle_alle1is),
3301 SYS_INSN(TLBI_VMALLS12E1IS, handle_vmalls12e1is),
3302 SYS_INSN(TLBI_IPAS2E1OS, handle_ipas2e1is),
3303 SYS_INSN(TLBI_IPAS2E1, handle_ipas2e1is),
3304 SYS_INSN(TLBI_RIPAS2E1, handle_ripas2e1is),
3305 SYS_INSN(TLBI_RIPAS2E1OS, handle_ripas2e1is),
3306 SYS_INSN(TLBI_IPAS2LE1OS, handle_ipas2e1is),
3307 SYS_INSN(TLBI_IPAS2LE1, handle_ipas2e1is),
3308 SYS_INSN(TLBI_RIPAS2LE1, handle_ripas2e1is),
3309 SYS_INSN(TLBI_RIPAS2LE1OS, handle_ripas2e1is),
3310 SYS_INSN(TLBI_RVAE2OS, undef_access),
3311 SYS_INSN(TLBI_RVALE2OS, undef_access),
3312 SYS_INSN(TLBI_RVAE2, undef_access),
3313 SYS_INSN(TLBI_RVALE2, undef_access),
3314 SYS_INSN(TLBI_ALLE1, handle_alle1is),
3315 SYS_INSN(TLBI_VMALLS12E1, handle_vmalls12e1is),
3316
3317 SYS_INSN(TLBI_IPAS2E1ISNXS, handle_ipas2e1is),
3318 SYS_INSN(TLBI_RIPAS2E1ISNXS, handle_ripas2e1is),
3319 SYS_INSN(TLBI_IPAS2LE1ISNXS, handle_ipas2e1is),
3320 SYS_INSN(TLBI_RIPAS2LE1ISNXS, handle_ripas2e1is),
3321
3322 SYS_INSN(TLBI_ALLE2OSNXS, undef_access),
3323 SYS_INSN(TLBI_VAE2OSNXS, undef_access),
3324 SYS_INSN(TLBI_ALLE1OSNXS, handle_alle1is),
3325 SYS_INSN(TLBI_VALE2OSNXS, undef_access),
3326 SYS_INSN(TLBI_VMALLS12E1OSNXS, handle_vmalls12e1is),
3327
3328 SYS_INSN(TLBI_RVAE2ISNXS, undef_access),
3329 SYS_INSN(TLBI_RVALE2ISNXS, undef_access),
3330 SYS_INSN(TLBI_ALLE2ISNXS, undef_access),
3331 SYS_INSN(TLBI_VAE2ISNXS, undef_access),
3332
3333 SYS_INSN(TLBI_ALLE1ISNXS, handle_alle1is),
3334 SYS_INSN(TLBI_VALE2ISNXS, undef_access),
3335 SYS_INSN(TLBI_VMALLS12E1ISNXS, handle_vmalls12e1is),
3336 SYS_INSN(TLBI_IPAS2E1OSNXS, handle_ipas2e1is),
3337 SYS_INSN(TLBI_IPAS2E1NXS, handle_ipas2e1is),
3338 SYS_INSN(TLBI_RIPAS2E1NXS, handle_ripas2e1is),
3339 SYS_INSN(TLBI_RIPAS2E1OSNXS, handle_ripas2e1is),
3340 SYS_INSN(TLBI_IPAS2LE1OSNXS, handle_ipas2e1is),
3341 SYS_INSN(TLBI_IPAS2LE1NXS, handle_ipas2e1is),
3342 SYS_INSN(TLBI_RIPAS2LE1NXS, handle_ripas2e1is),
3343 SYS_INSN(TLBI_RIPAS2LE1OSNXS, handle_ripas2e1is),
3344 SYS_INSN(TLBI_RVAE2OSNXS, undef_access),
3345 SYS_INSN(TLBI_RVALE2OSNXS, undef_access),
3346 SYS_INSN(TLBI_RVAE2NXS, undef_access),
3347 SYS_INSN(TLBI_RVALE2NXS, undef_access),
3348 SYS_INSN(TLBI_ALLE2NXS, undef_access),
3349 SYS_INSN(TLBI_VAE2NXS, undef_access),
3350 SYS_INSN(TLBI_ALLE1NXS, handle_alle1is),
3351 SYS_INSN(TLBI_VALE2NXS, undef_access),
3352 SYS_INSN(TLBI_VMALLS12E1NXS, handle_vmalls12e1is),
3353 };
3354
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)3355 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
3356 struct sys_reg_params *p,
3357 const struct sys_reg_desc *r)
3358 {
3359 if (p->is_write) {
3360 return ignore_write(vcpu, p);
3361 } else {
3362 u64 dfr = kvm_read_vm_id_reg(vcpu->kvm, SYS_ID_AA64DFR0_EL1);
3363 u32 el3 = kvm_has_feat(vcpu->kvm, ID_AA64PFR0_EL1, EL3, IMP);
3364
3365 p->regval = ((SYS_FIELD_GET(ID_AA64DFR0_EL1, WRPs, dfr) << 28) |
3366 (SYS_FIELD_GET(ID_AA64DFR0_EL1, BRPs, dfr) << 24) |
3367 (SYS_FIELD_GET(ID_AA64DFR0_EL1, CTX_CMPs, dfr) << 20) |
3368 (SYS_FIELD_GET(ID_AA64DFR0_EL1, DebugVer, dfr) << 16) |
3369 (1 << 15) | (el3 << 14) | (el3 << 12));
3370 return true;
3371 }
3372 }
3373
3374 /*
3375 * AArch32 debug register mappings
3376 *
3377 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
3378 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
3379 *
3380 * None of the other registers share their location, so treat them as
3381 * if they were 64bit.
3382 */
3383 #define DBG_BCR_BVR_WCR_WVR(n) \
3384 /* DBGBVRn */ \
3385 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
3386 /* DBGBCRn */ \
3387 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
3388 /* DBGWVRn */ \
3389 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
3390 /* DBGWCRn */ \
3391 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
3392
3393 #define DBGBXVR(n) \
3394 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
3395
3396 /*
3397 * Trapped cp14 registers. We generally ignore most of the external
3398 * debug, on the principle that they don't really make sense to a
3399 * guest. Revisit this one day, would this principle change.
3400 */
3401 static const struct sys_reg_desc cp14_regs[] = {
3402 /* DBGDIDR */
3403 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
3404 /* DBGDTRRXext */
3405 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
3406
3407 DBG_BCR_BVR_WCR_WVR(0),
3408 /* DBGDSCRint */
3409 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
3410 DBG_BCR_BVR_WCR_WVR(1),
3411 /* DBGDCCINT */
3412 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
3413 /* DBGDSCRext */
3414 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
3415 DBG_BCR_BVR_WCR_WVR(2),
3416 /* DBGDTR[RT]Xint */
3417 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
3418 /* DBGDTR[RT]Xext */
3419 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
3420 DBG_BCR_BVR_WCR_WVR(3),
3421 DBG_BCR_BVR_WCR_WVR(4),
3422 DBG_BCR_BVR_WCR_WVR(5),
3423 /* DBGWFAR */
3424 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
3425 /* DBGOSECCR */
3426 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
3427 DBG_BCR_BVR_WCR_WVR(6),
3428 /* DBGVCR */
3429 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
3430 DBG_BCR_BVR_WCR_WVR(7),
3431 DBG_BCR_BVR_WCR_WVR(8),
3432 DBG_BCR_BVR_WCR_WVR(9),
3433 DBG_BCR_BVR_WCR_WVR(10),
3434 DBG_BCR_BVR_WCR_WVR(11),
3435 DBG_BCR_BVR_WCR_WVR(12),
3436 DBG_BCR_BVR_WCR_WVR(13),
3437 DBG_BCR_BVR_WCR_WVR(14),
3438 DBG_BCR_BVR_WCR_WVR(15),
3439
3440 /* DBGDRAR (32bit) */
3441 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
3442
3443 DBGBXVR(0),
3444 /* DBGOSLAR */
3445 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
3446 DBGBXVR(1),
3447 /* DBGOSLSR */
3448 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
3449 DBGBXVR(2),
3450 DBGBXVR(3),
3451 /* DBGOSDLR */
3452 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
3453 DBGBXVR(4),
3454 /* DBGPRCR */
3455 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
3456 DBGBXVR(5),
3457 DBGBXVR(6),
3458 DBGBXVR(7),
3459 DBGBXVR(8),
3460 DBGBXVR(9),
3461 DBGBXVR(10),
3462 DBGBXVR(11),
3463 DBGBXVR(12),
3464 DBGBXVR(13),
3465 DBGBXVR(14),
3466 DBGBXVR(15),
3467
3468 /* DBGDSAR (32bit) */
3469 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
3470
3471 /* DBGDEVID2 */
3472 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
3473 /* DBGDEVID1 */
3474 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
3475 /* DBGDEVID */
3476 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
3477 /* DBGCLAIMSET */
3478 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
3479 /* DBGCLAIMCLR */
3480 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
3481 /* DBGAUTHSTATUS */
3482 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
3483 };
3484
3485 /* Trapped cp14 64bit registers */
3486 static const struct sys_reg_desc cp14_64_regs[] = {
3487 /* DBGDRAR (64bit) */
3488 { Op1( 0), CRm( 1), .access = trap_raz_wi },
3489
3490 /* DBGDSAR (64bit) */
3491 { Op1( 0), CRm( 2), .access = trap_raz_wi },
3492 };
3493
3494 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
3495 AA32(_map), \
3496 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
3497 .visibility = pmu_visibility
3498
3499 /* Macro to expand the PMEVCNTRn register */
3500 #define PMU_PMEVCNTR(n) \
3501 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3502 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3503 .access = access_pmu_evcntr }
3504
3505 /* Macro to expand the PMEVTYPERn register */
3506 #define PMU_PMEVTYPER(n) \
3507 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
3508 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
3509 .access = access_pmu_evtyper }
3510 /*
3511 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
3512 * depending on the way they are accessed (as a 32bit or a 64bit
3513 * register).
3514 */
3515 static const struct sys_reg_desc cp15_regs[] = {
3516 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
3517 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
3518 /* ACTLR */
3519 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
3520 /* ACTLR2 */
3521 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
3522 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
3523 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
3524 /* TTBCR */
3525 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
3526 /* TTBCR2 */
3527 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
3528 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
3529 { CP15_SYS_DESC(SYS_ICC_PMR_EL1), undef_access },
3530 /* DFSR */
3531 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
3532 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
3533 /* ADFSR */
3534 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
3535 /* AIFSR */
3536 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
3537 /* DFAR */
3538 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
3539 /* IFAR */
3540 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
3541
3542 /*
3543 * DC{C,I,CI}SW operations:
3544 */
3545 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
3546 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
3547 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
3548
3549 /* PMU */
3550 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
3551 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
3552 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
3553 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
3554 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
3555 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
3556 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
3557 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
3558 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
3559 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
3560 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
3561 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
3562 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
3563 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
3564 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
3565 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
3566 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
3567 /* PMMIR */
3568 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
3569
3570 /* PRRR/MAIR0 */
3571 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
3572 /* NMRR/MAIR1 */
3573 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
3574 /* AMAIR0 */
3575 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
3576 /* AMAIR1 */
3577 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
3578
3579 { CP15_SYS_DESC(SYS_ICC_IAR0_EL1), undef_access },
3580 { CP15_SYS_DESC(SYS_ICC_EOIR0_EL1), undef_access },
3581 { CP15_SYS_DESC(SYS_ICC_HPPIR0_EL1), undef_access },
3582 { CP15_SYS_DESC(SYS_ICC_BPR0_EL1), undef_access },
3583 { CP15_SYS_DESC(SYS_ICC_AP0R0_EL1), undef_access },
3584 { CP15_SYS_DESC(SYS_ICC_AP0R1_EL1), undef_access },
3585 { CP15_SYS_DESC(SYS_ICC_AP0R2_EL1), undef_access },
3586 { CP15_SYS_DESC(SYS_ICC_AP0R3_EL1), undef_access },
3587 { CP15_SYS_DESC(SYS_ICC_AP1R0_EL1), undef_access },
3588 { CP15_SYS_DESC(SYS_ICC_AP1R1_EL1), undef_access },
3589 { CP15_SYS_DESC(SYS_ICC_AP1R2_EL1), undef_access },
3590 { CP15_SYS_DESC(SYS_ICC_AP1R3_EL1), undef_access },
3591 { CP15_SYS_DESC(SYS_ICC_DIR_EL1), undef_access },
3592 { CP15_SYS_DESC(SYS_ICC_RPR_EL1), undef_access },
3593 { CP15_SYS_DESC(SYS_ICC_IAR1_EL1), undef_access },
3594 { CP15_SYS_DESC(SYS_ICC_EOIR1_EL1), undef_access },
3595 { CP15_SYS_DESC(SYS_ICC_HPPIR1_EL1), undef_access },
3596 { CP15_SYS_DESC(SYS_ICC_BPR1_EL1), undef_access },
3597 { CP15_SYS_DESC(SYS_ICC_CTLR_EL1), undef_access },
3598 { CP15_SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
3599 { CP15_SYS_DESC(SYS_ICC_IGRPEN0_EL1), undef_access },
3600 { CP15_SYS_DESC(SYS_ICC_IGRPEN1_EL1), undef_access },
3601
3602 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
3603
3604 /* Arch Tmers */
3605 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
3606 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
3607
3608 /* PMEVCNTRn */
3609 PMU_PMEVCNTR(0),
3610 PMU_PMEVCNTR(1),
3611 PMU_PMEVCNTR(2),
3612 PMU_PMEVCNTR(3),
3613 PMU_PMEVCNTR(4),
3614 PMU_PMEVCNTR(5),
3615 PMU_PMEVCNTR(6),
3616 PMU_PMEVCNTR(7),
3617 PMU_PMEVCNTR(8),
3618 PMU_PMEVCNTR(9),
3619 PMU_PMEVCNTR(10),
3620 PMU_PMEVCNTR(11),
3621 PMU_PMEVCNTR(12),
3622 PMU_PMEVCNTR(13),
3623 PMU_PMEVCNTR(14),
3624 PMU_PMEVCNTR(15),
3625 PMU_PMEVCNTR(16),
3626 PMU_PMEVCNTR(17),
3627 PMU_PMEVCNTR(18),
3628 PMU_PMEVCNTR(19),
3629 PMU_PMEVCNTR(20),
3630 PMU_PMEVCNTR(21),
3631 PMU_PMEVCNTR(22),
3632 PMU_PMEVCNTR(23),
3633 PMU_PMEVCNTR(24),
3634 PMU_PMEVCNTR(25),
3635 PMU_PMEVCNTR(26),
3636 PMU_PMEVCNTR(27),
3637 PMU_PMEVCNTR(28),
3638 PMU_PMEVCNTR(29),
3639 PMU_PMEVCNTR(30),
3640 /* PMEVTYPERn */
3641 PMU_PMEVTYPER(0),
3642 PMU_PMEVTYPER(1),
3643 PMU_PMEVTYPER(2),
3644 PMU_PMEVTYPER(3),
3645 PMU_PMEVTYPER(4),
3646 PMU_PMEVTYPER(5),
3647 PMU_PMEVTYPER(6),
3648 PMU_PMEVTYPER(7),
3649 PMU_PMEVTYPER(8),
3650 PMU_PMEVTYPER(9),
3651 PMU_PMEVTYPER(10),
3652 PMU_PMEVTYPER(11),
3653 PMU_PMEVTYPER(12),
3654 PMU_PMEVTYPER(13),
3655 PMU_PMEVTYPER(14),
3656 PMU_PMEVTYPER(15),
3657 PMU_PMEVTYPER(16),
3658 PMU_PMEVTYPER(17),
3659 PMU_PMEVTYPER(18),
3660 PMU_PMEVTYPER(19),
3661 PMU_PMEVTYPER(20),
3662 PMU_PMEVTYPER(21),
3663 PMU_PMEVTYPER(22),
3664 PMU_PMEVTYPER(23),
3665 PMU_PMEVTYPER(24),
3666 PMU_PMEVTYPER(25),
3667 PMU_PMEVTYPER(26),
3668 PMU_PMEVTYPER(27),
3669 PMU_PMEVTYPER(28),
3670 PMU_PMEVTYPER(29),
3671 PMU_PMEVTYPER(30),
3672 /* PMCCFILTR */
3673 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
3674
3675 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
3676 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
3677
3678 /* CCSIDR2 */
3679 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
3680
3681 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
3682 };
3683
3684 static const struct sys_reg_desc cp15_64_regs[] = {
3685 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
3686 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
3687 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
3688 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
3689 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
3690 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
3691 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
3692 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
3693 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
3694 };
3695
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)3696 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
3697 bool is_32)
3698 {
3699 unsigned int i;
3700
3701 for (i = 0; i < n; i++) {
3702 if (!is_32 && table[i].reg && !table[i].reset) {
3703 kvm_err("sys_reg table %pS entry %d (%s) lacks reset\n",
3704 &table[i], i, table[i].name);
3705 return false;
3706 }
3707
3708 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
3709 kvm_err("sys_reg table %pS entry %d (%s -> %s) out of order\n",
3710 &table[i], i, table[i - 1].name, table[i].name);
3711 return false;
3712 }
3713 }
3714
3715 return true;
3716 }
3717
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)3718 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
3719 {
3720 kvm_inject_undefined(vcpu);
3721 return 1;
3722 }
3723
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)3724 static void perform_access(struct kvm_vcpu *vcpu,
3725 struct sys_reg_params *params,
3726 const struct sys_reg_desc *r)
3727 {
3728 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
3729
3730 /* Check for regs disabled by runtime config */
3731 if (sysreg_hidden(vcpu, r)) {
3732 kvm_inject_undefined(vcpu);
3733 return;
3734 }
3735
3736 /*
3737 * Not having an accessor means that we have configured a trap
3738 * that we don't know how to handle. This certainly qualifies
3739 * as a gross bug that should be fixed right away.
3740 */
3741 BUG_ON(!r->access);
3742
3743 /* Skip instruction if instructed so */
3744 if (likely(r->access(vcpu, params, r)))
3745 kvm_incr_pc(vcpu);
3746 }
3747
3748 /*
3749 * emulate_cp -- tries to match a sys_reg access in a handling table, and
3750 * call the corresponding trap handler.
3751 *
3752 * @params: pointer to the descriptor of the access
3753 * @table: array of trap descriptors
3754 * @num: size of the trap descriptor array
3755 *
3756 * Return true if the access has been handled, false if not.
3757 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)3758 static bool emulate_cp(struct kvm_vcpu *vcpu,
3759 struct sys_reg_params *params,
3760 const struct sys_reg_desc *table,
3761 size_t num)
3762 {
3763 const struct sys_reg_desc *r;
3764
3765 if (!table)
3766 return false; /* Not handled */
3767
3768 r = find_reg(params, table, num);
3769
3770 if (r) {
3771 perform_access(vcpu, params, r);
3772 return true;
3773 }
3774
3775 /* Not handled */
3776 return false;
3777 }
3778
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3779 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
3780 struct sys_reg_params *params)
3781 {
3782 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
3783 int cp = -1;
3784
3785 switch (esr_ec) {
3786 case ESR_ELx_EC_CP15_32:
3787 case ESR_ELx_EC_CP15_64:
3788 cp = 15;
3789 break;
3790 case ESR_ELx_EC_CP14_MR:
3791 case ESR_ELx_EC_CP14_64:
3792 cp = 14;
3793 break;
3794 default:
3795 WARN_ON(1);
3796 }
3797
3798 print_sys_reg_msg(params,
3799 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
3800 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
3801 kvm_inject_undefined(vcpu);
3802 }
3803
3804 /**
3805 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
3806 * @vcpu: The VCPU pointer
3807 * @global: &struct sys_reg_desc
3808 * @nr_global: size of the @global array
3809 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)3810 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
3811 const struct sys_reg_desc *global,
3812 size_t nr_global)
3813 {
3814 struct sys_reg_params params;
3815 u64 esr = kvm_vcpu_get_esr(vcpu);
3816 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3817 int Rt2 = (esr >> 10) & 0x1f;
3818
3819 params.CRm = (esr >> 1) & 0xf;
3820 params.is_write = ((esr & 1) == 0);
3821
3822 params.Op0 = 0;
3823 params.Op1 = (esr >> 16) & 0xf;
3824 params.Op2 = 0;
3825 params.CRn = 0;
3826
3827 /*
3828 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
3829 * backends between AArch32 and AArch64, we get away with it.
3830 */
3831 if (params.is_write) {
3832 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
3833 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
3834 }
3835
3836 /*
3837 * If the table contains a handler, handle the
3838 * potential register operation in the case of a read and return
3839 * with success.
3840 */
3841 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
3842 /* Split up the value between registers for the read side */
3843 if (!params.is_write) {
3844 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
3845 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
3846 }
3847
3848 return 1;
3849 }
3850
3851 unhandled_cp_access(vcpu, ¶ms);
3852 return 1;
3853 }
3854
3855 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
3856
3857 /*
3858 * The CP10 ID registers are architecturally mapped to AArch64 feature
3859 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
3860 * from AArch32.
3861 */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)3862 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
3863 {
3864 u8 reg_id = (esr >> 10) & 0xf;
3865 bool valid;
3866
3867 params->is_write = ((esr & 1) == 0);
3868 params->Op0 = 3;
3869 params->Op1 = 0;
3870 params->CRn = 0;
3871 params->CRm = 3;
3872
3873 /* CP10 ID registers are read-only */
3874 valid = !params->is_write;
3875
3876 switch (reg_id) {
3877 /* MVFR0 */
3878 case 0b0111:
3879 params->Op2 = 0;
3880 break;
3881 /* MVFR1 */
3882 case 0b0110:
3883 params->Op2 = 1;
3884 break;
3885 /* MVFR2 */
3886 case 0b0101:
3887 params->Op2 = 2;
3888 break;
3889 default:
3890 valid = false;
3891 }
3892
3893 if (valid)
3894 return true;
3895
3896 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
3897 params->is_write ? "write" : "read", reg_id);
3898 return false;
3899 }
3900
3901 /**
3902 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
3903 * VFP Register' from AArch32.
3904 * @vcpu: The vCPU pointer
3905 *
3906 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
3907 * Work out the correct AArch64 system register encoding and reroute to the
3908 * AArch64 system register emulation.
3909 */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)3910 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
3911 {
3912 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3913 u64 esr = kvm_vcpu_get_esr(vcpu);
3914 struct sys_reg_params params;
3915
3916 /* UNDEF on any unhandled register access */
3917 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
3918 kvm_inject_undefined(vcpu);
3919 return 1;
3920 }
3921
3922 if (emulate_sys_reg(vcpu, ¶ms))
3923 vcpu_set_reg(vcpu, Rt, params.regval);
3924
3925 return 1;
3926 }
3927
3928 /**
3929 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
3930 * CRn=0, which corresponds to the AArch32 feature
3931 * registers.
3932 * @vcpu: the vCPU pointer
3933 * @params: the system register access parameters.
3934 *
3935 * Our cp15 system register tables do not enumerate the AArch32 feature
3936 * registers. Conveniently, our AArch64 table does, and the AArch32 system
3937 * register encoding can be trivially remapped into the AArch64 for the feature
3938 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
3939 *
3940 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
3941 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
3942 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
3943 * treat undefined registers in this range as RAZ.
3944 */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3945 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
3946 struct sys_reg_params *params)
3947 {
3948 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3949
3950 /* Treat impossible writes to RO registers as UNDEFINED */
3951 if (params->is_write) {
3952 unhandled_cp_access(vcpu, params);
3953 return 1;
3954 }
3955
3956 params->Op0 = 3;
3957
3958 /*
3959 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
3960 * Avoid conflicting with future expansion of AArch64 feature registers
3961 * and simply treat them as RAZ here.
3962 */
3963 if (params->CRm > 3)
3964 params->regval = 0;
3965 else if (!emulate_sys_reg(vcpu, params))
3966 return 1;
3967
3968 vcpu_set_reg(vcpu, Rt, params->regval);
3969 return 1;
3970 }
3971
3972 /**
3973 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
3974 * @vcpu: The VCPU pointer
3975 * @params: &struct sys_reg_params
3976 * @global: &struct sys_reg_desc
3977 * @nr_global: size of the @global array
3978 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)3979 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
3980 struct sys_reg_params *params,
3981 const struct sys_reg_desc *global,
3982 size_t nr_global)
3983 {
3984 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3985
3986 params->regval = vcpu_get_reg(vcpu, Rt);
3987
3988 if (emulate_cp(vcpu, params, global, nr_global)) {
3989 if (!params->is_write)
3990 vcpu_set_reg(vcpu, Rt, params->regval);
3991 return 1;
3992 }
3993
3994 unhandled_cp_access(vcpu, params);
3995 return 1;
3996 }
3997
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)3998 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
3999 {
4000 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
4001 }
4002
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)4003 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
4004 {
4005 struct sys_reg_params params;
4006
4007 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
4008
4009 /*
4010 * Certain AArch32 ID registers are handled by rerouting to the AArch64
4011 * system register table. Registers in the ID range where CRm=0 are
4012 * excluded from this scheme as they do not trivially map into AArch64
4013 * system register encodings.
4014 */
4015 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
4016 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
4017
4018 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
4019 }
4020
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)4021 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
4022 {
4023 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
4024 }
4025
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)4026 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
4027 {
4028 struct sys_reg_params params;
4029
4030 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
4031
4032 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
4033 }
4034
4035 /**
4036 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
4037 * @vcpu: The VCPU pointer
4038 * @params: Decoded system register parameters
4039 *
4040 * Return: true if the system register access was successful, false otherwise.
4041 */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)4042 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
4043 struct sys_reg_params *params)
4044 {
4045 const struct sys_reg_desc *r;
4046
4047 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4048 if (likely(r)) {
4049 perform_access(vcpu, params, r);
4050 return true;
4051 }
4052
4053 print_sys_reg_msg(params,
4054 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
4055 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
4056 kvm_inject_undefined(vcpu);
4057
4058 return false;
4059 }
4060
idregs_debug_find(struct kvm * kvm,u8 pos)4061 static const struct sys_reg_desc *idregs_debug_find(struct kvm *kvm, u8 pos)
4062 {
4063 unsigned long i, idreg_idx = 0;
4064
4065 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4066 const struct sys_reg_desc *r = &sys_reg_descs[i];
4067
4068 if (!is_vm_ftr_id_reg(reg_to_encoding(r)))
4069 continue;
4070
4071 if (idreg_idx == pos)
4072 return r;
4073
4074 idreg_idx++;
4075 }
4076
4077 return NULL;
4078 }
4079
idregs_debug_start(struct seq_file * s,loff_t * pos)4080 static void *idregs_debug_start(struct seq_file *s, loff_t *pos)
4081 {
4082 struct kvm *kvm = s->private;
4083 u8 *iter;
4084
4085 mutex_lock(&kvm->arch.config_lock);
4086
4087 iter = &kvm->arch.idreg_debugfs_iter;
4088 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags) &&
4089 *iter == (u8)~0) {
4090 *iter = *pos;
4091 if (!idregs_debug_find(kvm, *iter))
4092 iter = NULL;
4093 } else {
4094 iter = ERR_PTR(-EBUSY);
4095 }
4096
4097 mutex_unlock(&kvm->arch.config_lock);
4098
4099 return iter;
4100 }
4101
idregs_debug_next(struct seq_file * s,void * v,loff_t * pos)4102 static void *idregs_debug_next(struct seq_file *s, void *v, loff_t *pos)
4103 {
4104 struct kvm *kvm = s->private;
4105
4106 (*pos)++;
4107
4108 if (idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter + 1)) {
4109 kvm->arch.idreg_debugfs_iter++;
4110
4111 return &kvm->arch.idreg_debugfs_iter;
4112 }
4113
4114 return NULL;
4115 }
4116
idregs_debug_stop(struct seq_file * s,void * v)4117 static void idregs_debug_stop(struct seq_file *s, void *v)
4118 {
4119 struct kvm *kvm = s->private;
4120
4121 if (IS_ERR(v))
4122 return;
4123
4124 mutex_lock(&kvm->arch.config_lock);
4125
4126 kvm->arch.idreg_debugfs_iter = ~0;
4127
4128 mutex_unlock(&kvm->arch.config_lock);
4129 }
4130
idregs_debug_show(struct seq_file * s,void * v)4131 static int idregs_debug_show(struct seq_file *s, void *v)
4132 {
4133 const struct sys_reg_desc *desc;
4134 struct kvm *kvm = s->private;
4135
4136 desc = idregs_debug_find(kvm, kvm->arch.idreg_debugfs_iter);
4137
4138 if (!desc->name)
4139 return 0;
4140
4141 seq_printf(s, "%20s:\t%016llx\n",
4142 desc->name, kvm_read_vm_id_reg(kvm, reg_to_encoding(desc)));
4143
4144 return 0;
4145 }
4146
4147 static const struct seq_operations idregs_debug_sops = {
4148 .start = idregs_debug_start,
4149 .next = idregs_debug_next,
4150 .stop = idregs_debug_stop,
4151 .show = idregs_debug_show,
4152 };
4153
4154 DEFINE_SEQ_ATTRIBUTE(idregs_debug);
4155
kvm_sys_regs_create_debugfs(struct kvm * kvm)4156 void kvm_sys_regs_create_debugfs(struct kvm *kvm)
4157 {
4158 kvm->arch.idreg_debugfs_iter = ~0;
4159
4160 debugfs_create_file("idregs", 0444, kvm->debugfs_dentry, kvm,
4161 &idregs_debug_fops);
4162 }
4163
reset_vm_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4164 static void reset_vm_ftr_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *reg)
4165 {
4166 u32 id = reg_to_encoding(reg);
4167 struct kvm *kvm = vcpu->kvm;
4168
4169 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
4170 return;
4171
4172 kvm_set_vm_id_reg(kvm, id, reg->reset(vcpu, reg));
4173 }
4174
reset_vcpu_ftr_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * reg)4175 static void reset_vcpu_ftr_id_reg(struct kvm_vcpu *vcpu,
4176 const struct sys_reg_desc *reg)
4177 {
4178 if (kvm_vcpu_initialized(vcpu))
4179 return;
4180
4181 reg->reset(vcpu, reg);
4182 }
4183
4184 /**
4185 * kvm_reset_sys_regs - sets system registers to reset value
4186 * @vcpu: The VCPU pointer
4187 *
4188 * This function finds the right table above and sets the registers on the
4189 * virtual CPU struct to their architecturally defined reset values.
4190 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)4191 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
4192 {
4193 struct kvm *kvm = vcpu->kvm;
4194 unsigned long i;
4195
4196 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4197 const struct sys_reg_desc *r = &sys_reg_descs[i];
4198
4199 if (!r->reset)
4200 continue;
4201
4202 if (is_vm_ftr_id_reg(reg_to_encoding(r)))
4203 reset_vm_ftr_id_reg(vcpu, r);
4204 else if (is_vcpu_ftr_id_reg(reg_to_encoding(r)))
4205 reset_vcpu_ftr_id_reg(vcpu, r);
4206 else
4207 r->reset(vcpu, r);
4208 }
4209
4210 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
4211 }
4212
4213 /**
4214 * kvm_handle_sys_reg -- handles a system instruction or mrs/msr instruction
4215 * trap on a guest execution
4216 * @vcpu: The VCPU pointer
4217 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)4218 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
4219 {
4220 const struct sys_reg_desc *desc = NULL;
4221 struct sys_reg_params params;
4222 unsigned long esr = kvm_vcpu_get_esr(vcpu);
4223 int Rt = kvm_vcpu_sys_get_rt(vcpu);
4224 int sr_idx;
4225
4226 trace_kvm_handle_sys_reg(esr);
4227
4228 if (triage_sysreg_trap(vcpu, &sr_idx))
4229 return 1;
4230
4231 params = esr_sys64_to_params(esr);
4232 params.regval = vcpu_get_reg(vcpu, Rt);
4233
4234 /* System registers have Op0=={2,3}, as per DDI487 J.a C5.1.2 */
4235 if (params.Op0 == 2 || params.Op0 == 3)
4236 desc = &sys_reg_descs[sr_idx];
4237 else
4238 desc = &sys_insn_descs[sr_idx];
4239
4240 perform_access(vcpu, ¶ms, desc);
4241
4242 /* Read from system register? */
4243 if (!params.is_write &&
4244 (params.Op0 == 2 || params.Op0 == 3))
4245 vcpu_set_reg(vcpu, Rt, params.regval);
4246
4247 return 1;
4248 }
4249
4250 /******************************************************************************
4251 * Userspace API
4252 *****************************************************************************/
4253
index_to_params(u64 id,struct sys_reg_params * params)4254 static bool index_to_params(u64 id, struct sys_reg_params *params)
4255 {
4256 switch (id & KVM_REG_SIZE_MASK) {
4257 case KVM_REG_SIZE_U64:
4258 /* Any unused index bits means it's not valid. */
4259 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
4260 | KVM_REG_ARM_COPROC_MASK
4261 | KVM_REG_ARM64_SYSREG_OP0_MASK
4262 | KVM_REG_ARM64_SYSREG_OP1_MASK
4263 | KVM_REG_ARM64_SYSREG_CRN_MASK
4264 | KVM_REG_ARM64_SYSREG_CRM_MASK
4265 | KVM_REG_ARM64_SYSREG_OP2_MASK))
4266 return false;
4267 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
4268 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
4269 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
4270 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
4271 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
4272 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
4273 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
4274 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
4275 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
4276 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
4277 return true;
4278 default:
4279 return false;
4280 }
4281 }
4282
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)4283 const struct sys_reg_desc *get_reg_by_id(u64 id,
4284 const struct sys_reg_desc table[],
4285 unsigned int num)
4286 {
4287 struct sys_reg_params params;
4288
4289 if (!index_to_params(id, ¶ms))
4290 return NULL;
4291
4292 return find_reg(¶ms, table, num);
4293 }
4294
4295 /* Decode an index value, and find the sys_reg_desc entry. */
4296 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)4297 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
4298 const struct sys_reg_desc table[], unsigned int num)
4299
4300 {
4301 const struct sys_reg_desc *r;
4302
4303 /* We only do sys_reg for now. */
4304 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
4305 return NULL;
4306
4307 r = get_reg_by_id(id, table, num);
4308
4309 /* Not saved in the sys_reg array and not otherwise accessible? */
4310 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
4311 r = NULL;
4312
4313 return r;
4314 }
4315
4316 /*
4317 * These are the invariant sys_reg registers: we let the guest see the
4318 * host versions of these, so they're part of the guest state.
4319 *
4320 * A future CPU may provide a mechanism to present different values to
4321 * the guest, or a future kvm may trap them.
4322 */
4323
4324 #define FUNCTION_INVARIANT(reg) \
4325 static u64 reset_##reg(struct kvm_vcpu *v, \
4326 const struct sys_reg_desc *r) \
4327 { \
4328 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
4329 return ((struct sys_reg_desc *)r)->val; \
4330 }
4331
4332 FUNCTION_INVARIANT(midr_el1)
4333 FUNCTION_INVARIANT(revidr_el1)
4334 FUNCTION_INVARIANT(aidr_el1)
4335
4336 /* ->val is filled in by kvm_sys_reg_table_init() */
4337 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = {
4338 { SYS_DESC(SYS_MIDR_EL1), NULL, reset_midr_el1 },
4339 { SYS_DESC(SYS_REVIDR_EL1), NULL, reset_revidr_el1 },
4340 { SYS_DESC(SYS_AIDR_EL1), NULL, reset_aidr_el1 },
4341 };
4342
get_invariant_sys_reg(u64 id,u64 __user * uaddr)4343 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
4344 {
4345 const struct sys_reg_desc *r;
4346
4347 r = get_reg_by_id(id, invariant_sys_regs,
4348 ARRAY_SIZE(invariant_sys_regs));
4349 if (!r)
4350 return -ENOENT;
4351
4352 return put_user(r->val, uaddr);
4353 }
4354
set_invariant_sys_reg(u64 id,u64 __user * uaddr)4355 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
4356 {
4357 const struct sys_reg_desc *r;
4358 u64 val;
4359
4360 r = get_reg_by_id(id, invariant_sys_regs,
4361 ARRAY_SIZE(invariant_sys_regs));
4362 if (!r)
4363 return -ENOENT;
4364
4365 if (get_user(val, uaddr))
4366 return -EFAULT;
4367
4368 /* This is what we mean by invariant: you can't change it. */
4369 if (r->val != val)
4370 return -EINVAL;
4371
4372 return 0;
4373 }
4374
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4375 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4376 {
4377 u32 val;
4378 u32 __user *uval = uaddr;
4379
4380 /* Fail if we have unknown bits set. */
4381 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4382 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4383 return -ENOENT;
4384
4385 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4386 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4387 if (KVM_REG_SIZE(id) != 4)
4388 return -ENOENT;
4389 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4390 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4391 if (val >= CSSELR_MAX)
4392 return -ENOENT;
4393
4394 return put_user(get_ccsidr(vcpu, val), uval);
4395 default:
4396 return -ENOENT;
4397 }
4398 }
4399
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)4400 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
4401 {
4402 u32 val, newval;
4403 u32 __user *uval = uaddr;
4404
4405 /* Fail if we have unknown bits set. */
4406 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
4407 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
4408 return -ENOENT;
4409
4410 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
4411 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
4412 if (KVM_REG_SIZE(id) != 4)
4413 return -ENOENT;
4414 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
4415 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
4416 if (val >= CSSELR_MAX)
4417 return -ENOENT;
4418
4419 if (get_user(newval, uval))
4420 return -EFAULT;
4421
4422 return set_ccsidr(vcpu, val, newval);
4423 default:
4424 return -ENOENT;
4425 }
4426 }
4427
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4428 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4429 const struct sys_reg_desc table[], unsigned int num)
4430 {
4431 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4432 const struct sys_reg_desc *r;
4433 u64 val;
4434 int ret;
4435
4436 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4437 if (!r || sysreg_hidden(vcpu, r))
4438 return -ENOENT;
4439
4440 if (r->get_user) {
4441 ret = (r->get_user)(vcpu, r, &val);
4442 } else {
4443 val = __vcpu_sys_reg(vcpu, r->reg);
4444 ret = 0;
4445 }
4446
4447 if (!ret)
4448 ret = put_user(val, uaddr);
4449
4450 return ret;
4451 }
4452
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4453 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4454 {
4455 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4456 int err;
4457
4458 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4459 return demux_c15_get(vcpu, reg->id, uaddr);
4460
4461 err = get_invariant_sys_reg(reg->id, uaddr);
4462 if (err != -ENOENT)
4463 return err;
4464
4465 return kvm_sys_reg_get_user(vcpu, reg,
4466 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4467 }
4468
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)4469 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
4470 const struct sys_reg_desc table[], unsigned int num)
4471 {
4472 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
4473 const struct sys_reg_desc *r;
4474 u64 val;
4475 int ret;
4476
4477 if (get_user(val, uaddr))
4478 return -EFAULT;
4479
4480 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
4481 if (!r || sysreg_hidden(vcpu, r))
4482 return -ENOENT;
4483
4484 if (sysreg_user_write_ignore(vcpu, r))
4485 return 0;
4486
4487 if (r->set_user) {
4488 ret = (r->set_user)(vcpu, r, val);
4489 } else {
4490 __vcpu_sys_reg(vcpu, r->reg) = val;
4491 ret = 0;
4492 }
4493
4494 return ret;
4495 }
4496
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)4497 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
4498 {
4499 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
4500 int err;
4501
4502 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
4503 return demux_c15_set(vcpu, reg->id, uaddr);
4504
4505 err = set_invariant_sys_reg(reg->id, uaddr);
4506 if (err != -ENOENT)
4507 return err;
4508
4509 return kvm_sys_reg_set_user(vcpu, reg,
4510 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
4511 }
4512
num_demux_regs(void)4513 static unsigned int num_demux_regs(void)
4514 {
4515 return CSSELR_MAX;
4516 }
4517
write_demux_regids(u64 __user * uindices)4518 static int write_demux_regids(u64 __user *uindices)
4519 {
4520 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
4521 unsigned int i;
4522
4523 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
4524 for (i = 0; i < CSSELR_MAX; i++) {
4525 if (put_user(val | i, uindices))
4526 return -EFAULT;
4527 uindices++;
4528 }
4529 return 0;
4530 }
4531
sys_reg_to_index(const struct sys_reg_desc * reg)4532 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
4533 {
4534 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
4535 KVM_REG_ARM64_SYSREG |
4536 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
4537 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
4538 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
4539 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
4540 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
4541 }
4542
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)4543 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
4544 {
4545 if (!*uind)
4546 return true;
4547
4548 if (put_user(sys_reg_to_index(reg), *uind))
4549 return false;
4550
4551 (*uind)++;
4552 return true;
4553 }
4554
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)4555 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
4556 const struct sys_reg_desc *rd,
4557 u64 __user **uind,
4558 unsigned int *total)
4559 {
4560 /*
4561 * Ignore registers we trap but don't save,
4562 * and for which no custom user accessor is provided.
4563 */
4564 if (!(rd->reg || rd->get_user))
4565 return 0;
4566
4567 if (sysreg_hidden(vcpu, rd))
4568 return 0;
4569
4570 if (!copy_reg_to_user(rd, uind))
4571 return -EFAULT;
4572
4573 (*total)++;
4574 return 0;
4575 }
4576
4577 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)4578 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
4579 {
4580 const struct sys_reg_desc *i2, *end2;
4581 unsigned int total = 0;
4582 int err;
4583
4584 i2 = sys_reg_descs;
4585 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
4586
4587 while (i2 != end2) {
4588 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
4589 if (err)
4590 return err;
4591 }
4592 return total;
4593 }
4594
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)4595 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
4596 {
4597 return ARRAY_SIZE(invariant_sys_regs)
4598 + num_demux_regs()
4599 + walk_sys_regs(vcpu, (u64 __user *)NULL);
4600 }
4601
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)4602 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
4603 {
4604 unsigned int i;
4605 int err;
4606
4607 /* Then give them all the invariant registers' indices. */
4608 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
4609 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
4610 return -EFAULT;
4611 uindices++;
4612 }
4613
4614 err = walk_sys_regs(vcpu, uindices);
4615 if (err < 0)
4616 return err;
4617 uindices += err;
4618
4619 return write_demux_regids(uindices);
4620 }
4621
4622 #define KVM_ARM_FEATURE_ID_RANGE_INDEX(r) \
4623 KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(r), \
4624 sys_reg_Op1(r), \
4625 sys_reg_CRn(r), \
4626 sys_reg_CRm(r), \
4627 sys_reg_Op2(r))
4628
kvm_vm_ioctl_get_reg_writable_masks(struct kvm * kvm,struct reg_mask_range * range)4629 int kvm_vm_ioctl_get_reg_writable_masks(struct kvm *kvm, struct reg_mask_range *range)
4630 {
4631 const void *zero_page = page_to_virt(ZERO_PAGE(0));
4632 u64 __user *masks = (u64 __user *)range->addr;
4633
4634 /* Only feature id range is supported, reserved[13] must be zero. */
4635 if (range->range ||
4636 memcmp(range->reserved, zero_page, sizeof(range->reserved)))
4637 return -EINVAL;
4638
4639 /* Wipe the whole thing first */
4640 if (clear_user(masks, KVM_ARM_FEATURE_ID_RANGE_SIZE * sizeof(__u64)))
4641 return -EFAULT;
4642
4643 for (int i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
4644 const struct sys_reg_desc *reg = &sys_reg_descs[i];
4645 u32 encoding = reg_to_encoding(reg);
4646 u64 val;
4647
4648 if (!is_feature_id_reg(encoding) || !reg->set_user)
4649 continue;
4650
4651 if (!reg->val ||
4652 (is_aa32_id_reg(encoding) && !kvm_supports_32bit_el0())) {
4653 continue;
4654 }
4655 val = reg->val;
4656
4657 if (put_user(val, (masks + KVM_ARM_FEATURE_ID_RANGE_INDEX(encoding))))
4658 return -EFAULT;
4659 }
4660
4661 return 0;
4662 }
4663
vcpu_set_hcr(struct kvm_vcpu * vcpu)4664 static void vcpu_set_hcr(struct kvm_vcpu *vcpu)
4665 {
4666 struct kvm *kvm = vcpu->kvm;
4667
4668 if (has_vhe() || has_hvhe())
4669 vcpu->arch.hcr_el2 |= HCR_E2H;
4670 if (cpus_have_final_cap(ARM64_HAS_RAS_EXTN)) {
4671 /* route synchronous external abort exceptions to EL2 */
4672 vcpu->arch.hcr_el2 |= HCR_TEA;
4673 /* trap error record accesses */
4674 vcpu->arch.hcr_el2 |= HCR_TERR;
4675 }
4676
4677 if (cpus_have_final_cap(ARM64_HAS_STAGE2_FWB))
4678 vcpu->arch.hcr_el2 |= HCR_FWB;
4679
4680 if (cpus_have_final_cap(ARM64_HAS_EVT) &&
4681 !cpus_have_final_cap(ARM64_MISMATCHED_CACHE_TYPE) &&
4682 kvm_read_vm_id_reg(kvm, SYS_CTR_EL0) == read_sanitised_ftr_reg(SYS_CTR_EL0))
4683 vcpu->arch.hcr_el2 |= HCR_TID4;
4684 else
4685 vcpu->arch.hcr_el2 |= HCR_TID2;
4686
4687 if (vcpu_el1_is_32bit(vcpu))
4688 vcpu->arch.hcr_el2 &= ~HCR_RW;
4689
4690 if (kvm_has_mte(vcpu->kvm))
4691 vcpu->arch.hcr_el2 |= HCR_ATA;
4692
4693 /*
4694 * In the absence of FGT, we cannot independently trap TLBI
4695 * Range instructions. This isn't great, but trapping all
4696 * TLBIs would be far worse. Live with it...
4697 */
4698 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4699 vcpu->arch.hcr_el2 |= HCR_TTLBOS;
4700 }
4701
kvm_calculate_traps(struct kvm_vcpu * vcpu)4702 void kvm_calculate_traps(struct kvm_vcpu *vcpu)
4703 {
4704 struct kvm *kvm = vcpu->kvm;
4705
4706 mutex_lock(&kvm->arch.config_lock);
4707 vcpu_set_hcr(vcpu);
4708 vcpu_set_ich_hcr(vcpu);
4709
4710 if (cpus_have_final_cap(ARM64_HAS_HCX)) {
4711 /*
4712 * In general, all HCRX_EL2 bits are gated by a feature.
4713 * The only reason we can set SMPME without checking any
4714 * feature is that its effects are not directly observable
4715 * from the guest.
4716 */
4717 vcpu->arch.hcrx_el2 = HCRX_EL2_SMPME;
4718
4719 if (kvm_has_feat(kvm, ID_AA64ISAR2_EL1, MOPS, IMP))
4720 vcpu->arch.hcrx_el2 |= (HCRX_EL2_MSCEn | HCRX_EL2_MCE2);
4721
4722 if (kvm_has_feat(kvm, ID_AA64MMFR3_EL1, TCRX, IMP))
4723 vcpu->arch.hcrx_el2 |= HCRX_EL2_TCR2En;
4724
4725 if (kvm_has_fpmr(kvm))
4726 vcpu->arch.hcrx_el2 |= HCRX_EL2_EnFPM;
4727 }
4728
4729 if (test_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags))
4730 goto out;
4731
4732 kvm->arch.fgu[HFGxTR_GROUP] = (HFGxTR_EL2_nAMAIR2_EL1 |
4733 HFGxTR_EL2_nMAIR2_EL1 |
4734 HFGxTR_EL2_nS2POR_EL1 |
4735 HFGxTR_EL2_nACCDATA_EL1 |
4736 HFGxTR_EL2_nSMPRI_EL1_MASK |
4737 HFGxTR_EL2_nTPIDR2_EL0_MASK);
4738
4739 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, OS))
4740 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1OS|
4741 HFGITR_EL2_TLBIRVALE1OS |
4742 HFGITR_EL2_TLBIRVAAE1OS |
4743 HFGITR_EL2_TLBIRVAE1OS |
4744 HFGITR_EL2_TLBIVAALE1OS |
4745 HFGITR_EL2_TLBIVALE1OS |
4746 HFGITR_EL2_TLBIVAAE1OS |
4747 HFGITR_EL2_TLBIASIDE1OS |
4748 HFGITR_EL2_TLBIVAE1OS |
4749 HFGITR_EL2_TLBIVMALLE1OS);
4750
4751 if (!kvm_has_feat(kvm, ID_AA64ISAR0_EL1, TLB, RANGE))
4752 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_TLBIRVAALE1 |
4753 HFGITR_EL2_TLBIRVALE1 |
4754 HFGITR_EL2_TLBIRVAAE1 |
4755 HFGITR_EL2_TLBIRVAE1 |
4756 HFGITR_EL2_TLBIRVAALE1IS|
4757 HFGITR_EL2_TLBIRVALE1IS |
4758 HFGITR_EL2_TLBIRVAAE1IS |
4759 HFGITR_EL2_TLBIRVAE1IS |
4760 HFGITR_EL2_TLBIRVAALE1OS|
4761 HFGITR_EL2_TLBIRVALE1OS |
4762 HFGITR_EL2_TLBIRVAAE1OS |
4763 HFGITR_EL2_TLBIRVAE1OS);
4764
4765 if (!kvm_has_feat(kvm, ID_AA64ISAR2_EL1, ATS1A, IMP))
4766 kvm->arch.fgu[HFGITR_GROUP] |= HFGITR_EL2_ATS1E1A;
4767
4768 if (!kvm_has_feat(kvm, ID_AA64MMFR1_EL1, PAN, PAN2))
4769 kvm->arch.fgu[HFGITR_GROUP] |= (HFGITR_EL2_ATS1E1RP |
4770 HFGITR_EL2_ATS1E1WP);
4771
4772 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1PIE, IMP))
4773 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPIRE0_EL1 |
4774 HFGxTR_EL2_nPIR_EL1);
4775
4776 if (!kvm_has_feat(kvm, ID_AA64MMFR3_EL1, S1POE, IMP))
4777 kvm->arch.fgu[HFGxTR_GROUP] |= (HFGxTR_EL2_nPOR_EL1 |
4778 HFGxTR_EL2_nPOR_EL0);
4779
4780 if (!kvm_has_feat(kvm, ID_AA64PFR0_EL1, AMU, IMP))
4781 kvm->arch.fgu[HAFGRTR_GROUP] |= ~(HAFGRTR_EL2_RES0 |
4782 HAFGRTR_EL2_RES1);
4783
4784 set_bit(KVM_ARCH_FLAG_FGU_INITIALIZED, &kvm->arch.flags);
4785 out:
4786 mutex_unlock(&kvm->arch.config_lock);
4787 }
4788
4789 /*
4790 * Perform last adjustments to the ID registers that are implied by the
4791 * configuration outside of the ID regs themselves, as well as any
4792 * initialisation that directly depend on these ID registers (such as
4793 * RES0/RES1 behaviours). This is not the place to configure traps though.
4794 *
4795 * Because this can be called once per CPU, changes must be idempotent.
4796 */
kvm_finalize_sys_regs(struct kvm_vcpu * vcpu)4797 int kvm_finalize_sys_regs(struct kvm_vcpu *vcpu)
4798 {
4799 struct kvm *kvm = vcpu->kvm;
4800
4801 guard(mutex)(&kvm->arch.config_lock);
4802
4803 if (!(static_branch_unlikely(&kvm_vgic_global_state.gicv3_cpuif) &&
4804 irqchip_in_kernel(kvm) &&
4805 kvm->arch.vgic.vgic_model == KVM_DEV_TYPE_ARM_VGIC_V3)) {
4806 kvm->arch.id_regs[IDREG_IDX(SYS_ID_AA64PFR0_EL1)] &= ~ID_AA64PFR0_EL1_GIC_MASK;
4807 kvm->arch.id_regs[IDREG_IDX(SYS_ID_PFR1_EL1)] &= ~ID_PFR1_EL1_GIC_MASK;
4808 }
4809
4810 if (vcpu_has_nv(vcpu)) {
4811 int ret = kvm_init_nv_sysregs(kvm);
4812 if (ret)
4813 return ret;
4814 }
4815
4816 return 0;
4817 }
4818
kvm_sys_reg_table_init(void)4819 int __init kvm_sys_reg_table_init(void)
4820 {
4821 bool valid = true;
4822 unsigned int i;
4823 int ret = 0;
4824
4825 /* Make sure tables are unique and in order. */
4826 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
4827 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
4828 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
4829 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
4830 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
4831 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
4832 valid &= check_sysreg_table(sys_insn_descs, ARRAY_SIZE(sys_insn_descs), false);
4833
4834 if (!valid)
4835 return -EINVAL;
4836
4837 /* We abuse the reset function to overwrite the table itself. */
4838 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
4839 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
4840
4841 ret = populate_nv_trap_config();
4842
4843 for (i = 0; !ret && i < ARRAY_SIZE(sys_reg_descs); i++)
4844 ret = populate_sysreg_config(sys_reg_descs + i, i);
4845
4846 for (i = 0; !ret && i < ARRAY_SIZE(sys_insn_descs); i++)
4847 ret = populate_sysreg_config(sys_insn_descs + i, i);
4848
4849 return ret;
4850 }
4851