1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012,2013 - ARM Ltd 4 * Author: Marc Zyngier <marc.zyngier@arm.com> 5 * 6 * Derived from arch/arm/kvm/reset.c 7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University 8 * Author: Christoffer Dall <c.dall@virtualopensystems.com> 9 */ 10 11 #include <linux/errno.h> 12 #include <linux/kernel.h> 13 #include <linux/kvm_host.h> 14 #include <linux/kvm.h> 15 #include <linux/hw_breakpoint.h> 16 #include <linux/slab.h> 17 #include <linux/string.h> 18 #include <linux/types.h> 19 20 #include <kvm/arm_arch_timer.h> 21 22 #include <asm/cpufeature.h> 23 #include <asm/cputype.h> 24 #include <asm/fpsimd.h> 25 #include <asm/ptrace.h> 26 #include <asm/kvm_arm.h> 27 #include <asm/kvm_asm.h> 28 #include <asm/kvm_emulate.h> 29 #include <asm/kvm_mmu.h> 30 #include <asm/kvm_nested.h> 31 #include <asm/virt.h> 32 33 /* Maximum phys_shift supported for any VM on this host */ 34 static u32 __ro_after_init kvm_ipa_limit; 35 unsigned int __ro_after_init kvm_host_sve_max_vl; 36 37 /* 38 * ARMv8 Reset Values 39 */ 40 #define VCPU_RESET_PSTATE_EL1 (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \ 41 PSR_F_BIT | PSR_D_BIT) 42 43 #define VCPU_RESET_PSTATE_EL2 (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \ 44 PSR_F_BIT | PSR_D_BIT) 45 46 #define VCPU_RESET_PSTATE_SVC (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \ 47 PSR_AA32_I_BIT | PSR_AA32_F_BIT) 48 49 unsigned int __ro_after_init kvm_sve_max_vl; 50 kvm_arm_init_sve(void)51 int __init kvm_arm_init_sve(void) 52 { 53 if (system_supports_sve()) { 54 kvm_sve_max_vl = sve_max_virtualisable_vl(); 55 kvm_host_sve_max_vl = sve_max_vl(); 56 kvm_nvhe_sym(kvm_host_sve_max_vl) = kvm_host_sve_max_vl; 57 58 /* 59 * The get_sve_reg()/set_sve_reg() ioctl interface will need 60 * to be extended with multiple register slice support in 61 * order to support vector lengths greater than 62 * VL_ARCH_MAX: 63 */ 64 if (WARN_ON(kvm_sve_max_vl > VL_ARCH_MAX)) 65 kvm_sve_max_vl = VL_ARCH_MAX; 66 67 /* 68 * Don't even try to make use of vector lengths that 69 * aren't available on all CPUs, for now: 70 */ 71 if (kvm_sve_max_vl < sve_max_vl()) 72 pr_warn("KVM: SVE vector length for guests limited to %u bytes\n", 73 kvm_sve_max_vl); 74 } 75 76 return 0; 77 } 78 kvm_vcpu_enable_sve(struct kvm_vcpu * vcpu)79 static void kvm_vcpu_enable_sve(struct kvm_vcpu *vcpu) 80 { 81 vcpu->arch.sve_max_vl = kvm_sve_max_vl; 82 83 /* 84 * Userspace can still customize the vector lengths by writing 85 * KVM_REG_ARM64_SVE_VLS. Allocation is deferred until 86 * kvm_arm_vcpu_finalize(), which freezes the configuration. 87 */ 88 vcpu_set_flag(vcpu, GUEST_HAS_SVE); 89 } 90 91 /* 92 * Finalize vcpu's maximum SVE vector length, allocating 93 * vcpu->arch.sve_state as necessary. 94 */ kvm_vcpu_finalize_sve(struct kvm_vcpu * vcpu)95 static int kvm_vcpu_finalize_sve(struct kvm_vcpu *vcpu) 96 { 97 void *buf; 98 unsigned int vl; 99 size_t reg_sz; 100 int ret; 101 102 vl = vcpu->arch.sve_max_vl; 103 104 /* 105 * Responsibility for these properties is shared between 106 * kvm_arm_init_sve(), kvm_vcpu_enable_sve() and 107 * set_sve_vls(). Double-check here just to be sure: 108 */ 109 if (WARN_ON(!sve_vl_valid(vl) || vl > sve_max_virtualisable_vl() || 110 vl > VL_ARCH_MAX)) 111 return -EIO; 112 113 reg_sz = vcpu_sve_state_size(vcpu); 114 buf = kzalloc(reg_sz, GFP_KERNEL_ACCOUNT); 115 if (!buf) 116 return -ENOMEM; 117 118 ret = kvm_share_hyp(buf, buf + reg_sz); 119 if (ret) { 120 kfree(buf); 121 return ret; 122 } 123 124 vcpu->arch.sve_state = buf; 125 vcpu_set_flag(vcpu, VCPU_SVE_FINALIZED); 126 return 0; 127 } 128 kvm_arm_vcpu_finalize(struct kvm_vcpu * vcpu,int feature)129 int kvm_arm_vcpu_finalize(struct kvm_vcpu *vcpu, int feature) 130 { 131 switch (feature) { 132 case KVM_ARM_VCPU_SVE: 133 if (!vcpu_has_sve(vcpu)) 134 return -EINVAL; 135 136 if (kvm_arm_vcpu_sve_finalized(vcpu)) 137 return -EPERM; 138 139 return kvm_vcpu_finalize_sve(vcpu); 140 } 141 142 return -EINVAL; 143 } 144 kvm_arm_vcpu_is_finalized(struct kvm_vcpu * vcpu)145 bool kvm_arm_vcpu_is_finalized(struct kvm_vcpu *vcpu) 146 { 147 if (vcpu_has_sve(vcpu) && !kvm_arm_vcpu_sve_finalized(vcpu)) 148 return false; 149 150 return true; 151 } 152 kvm_arm_vcpu_destroy(struct kvm_vcpu * vcpu)153 void kvm_arm_vcpu_destroy(struct kvm_vcpu *vcpu) 154 { 155 void *sve_state = vcpu->arch.sve_state; 156 157 kvm_unshare_hyp(vcpu, vcpu + 1); 158 if (sve_state) 159 kvm_unshare_hyp(sve_state, sve_state + vcpu_sve_state_size(vcpu)); 160 kfree(sve_state); 161 kfree(vcpu->arch.ccsidr); 162 } 163 kvm_vcpu_reset_sve(struct kvm_vcpu * vcpu)164 static void kvm_vcpu_reset_sve(struct kvm_vcpu *vcpu) 165 { 166 if (vcpu_has_sve(vcpu)) 167 memset(vcpu->arch.sve_state, 0, vcpu_sve_state_size(vcpu)); 168 } 169 kvm_vcpu_enable_ptrauth(struct kvm_vcpu * vcpu)170 static void kvm_vcpu_enable_ptrauth(struct kvm_vcpu *vcpu) 171 { 172 vcpu_set_flag(vcpu, GUEST_HAS_PTRAUTH); 173 } 174 175 /** 176 * kvm_reset_vcpu - sets core registers and sys_regs to reset value 177 * @vcpu: The VCPU pointer 178 * 179 * This function sets the registers on the virtual CPU struct to their 180 * architecturally defined reset values, except for registers whose reset is 181 * deferred until kvm_arm_vcpu_finalize(). 182 * 183 * Note: This function can be called from two paths: The KVM_ARM_VCPU_INIT 184 * ioctl or as part of handling a request issued by another VCPU in the PSCI 185 * handling code. In the first case, the VCPU will not be loaded, and in the 186 * second case the VCPU will be loaded. Because this function operates purely 187 * on the memory-backed values of system registers, we want to do a full put if 188 * we were loaded (handling a request) and load the values back at the end of 189 * the function. Otherwise we leave the state alone. In both cases, we 190 * disable preemption around the vcpu reset as we would otherwise race with 191 * preempt notifiers which also call put/load. 192 */ kvm_reset_vcpu(struct kvm_vcpu * vcpu)193 void kvm_reset_vcpu(struct kvm_vcpu *vcpu) 194 { 195 struct vcpu_reset_state reset_state; 196 bool loaded; 197 u32 pstate; 198 199 spin_lock(&vcpu->arch.mp_state_lock); 200 reset_state = vcpu->arch.reset_state; 201 vcpu->arch.reset_state.reset = false; 202 spin_unlock(&vcpu->arch.mp_state_lock); 203 204 /* Reset PMU outside of the non-preemptible section */ 205 kvm_pmu_vcpu_reset(vcpu); 206 207 preempt_disable(); 208 loaded = (vcpu->cpu != -1); 209 if (loaded) 210 kvm_arch_vcpu_put(vcpu); 211 212 if (!kvm_arm_vcpu_sve_finalized(vcpu)) { 213 if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) 214 kvm_vcpu_enable_sve(vcpu); 215 } else { 216 kvm_vcpu_reset_sve(vcpu); 217 } 218 219 if (vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_ADDRESS) || 220 vcpu_has_feature(vcpu, KVM_ARM_VCPU_PTRAUTH_GENERIC)) 221 kvm_vcpu_enable_ptrauth(vcpu); 222 223 if (vcpu_el1_is_32bit(vcpu)) 224 pstate = VCPU_RESET_PSTATE_SVC; 225 else if (vcpu_has_nv(vcpu)) 226 pstate = VCPU_RESET_PSTATE_EL2; 227 else 228 pstate = VCPU_RESET_PSTATE_EL1; 229 230 /* Reset core registers */ 231 memset(vcpu_gp_regs(vcpu), 0, sizeof(*vcpu_gp_regs(vcpu))); 232 memset(&vcpu->arch.ctxt.fp_regs, 0, sizeof(vcpu->arch.ctxt.fp_regs)); 233 vcpu->arch.ctxt.spsr_abt = 0; 234 vcpu->arch.ctxt.spsr_und = 0; 235 vcpu->arch.ctxt.spsr_irq = 0; 236 vcpu->arch.ctxt.spsr_fiq = 0; 237 vcpu_gp_regs(vcpu)->pstate = pstate; 238 239 /* Reset system registers */ 240 kvm_reset_sys_regs(vcpu); 241 242 /* 243 * Additional reset state handling that PSCI may have imposed on us. 244 * Must be done after all the sys_reg reset. 245 */ 246 if (reset_state.reset) { 247 unsigned long target_pc = reset_state.pc; 248 249 /* Gracefully handle Thumb2 entry point */ 250 if (vcpu_mode_is_32bit(vcpu) && (target_pc & 1)) { 251 target_pc &= ~1UL; 252 vcpu_set_thumb(vcpu); 253 } 254 255 /* Propagate caller endianness */ 256 if (reset_state.be) 257 kvm_vcpu_set_be(vcpu); 258 259 *vcpu_pc(vcpu) = target_pc; 260 vcpu_set_reg(vcpu, 0, reset_state.r0); 261 } 262 263 /* Reset timer */ 264 kvm_timer_vcpu_reset(vcpu); 265 266 if (loaded) 267 kvm_arch_vcpu_load(vcpu, smp_processor_id()); 268 preempt_enable(); 269 } 270 kvm_get_pa_bits(struct kvm * kvm)271 u32 kvm_get_pa_bits(struct kvm *kvm) 272 { 273 /* Fixed limit until we can configure ID_AA64MMFR0.PARange */ 274 return kvm_ipa_limit; 275 } 276 get_kvm_ipa_limit(void)277 u32 get_kvm_ipa_limit(void) 278 { 279 return kvm_ipa_limit; 280 } 281 kvm_set_ipa_limit(void)282 int __init kvm_set_ipa_limit(void) 283 { 284 unsigned int parange; 285 u64 mmfr0; 286 287 mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1); 288 parange = cpuid_feature_extract_unsigned_field(mmfr0, 289 ID_AA64MMFR0_EL1_PARANGE_SHIFT); 290 /* 291 * IPA size beyond 48 bits for 4K and 16K page size is only supported 292 * when LPA2 is available. So if we have LPA2, enable it, else cap to 48 293 * bits, in case it's reported as larger on the system. 294 */ 295 if (!kvm_lpa2_is_enabled() && PAGE_SIZE != SZ_64K) 296 parange = min(parange, (unsigned int)ID_AA64MMFR0_EL1_PARANGE_48); 297 298 /* 299 * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at 300 * Stage-2. If not, things will stop very quickly. 301 */ 302 switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_TGRAN_2_SHIFT)) { 303 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE: 304 kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n"); 305 return -EINVAL; 306 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT: 307 kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n"); 308 break; 309 case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX: 310 kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n"); 311 break; 312 default: 313 kvm_err("Unsupported value for TGRAN_2, giving up\n"); 314 return -EINVAL; 315 } 316 317 kvm_ipa_limit = id_aa64mmfr0_parange_to_phys_shift(parange); 318 kvm_info("IPA Size Limit: %d bits%s\n", kvm_ipa_limit, 319 ((kvm_ipa_limit < KVM_PHYS_SHIFT) ? 320 " (Reduced IPA size, limited VM/VMM compatibility)" : "")); 321 322 return 0; 323 } 324