1 /* SPDX-License-Identifier: MIT */
2 /*
3 * Copyright (C) 2024 Advanced Micro Devices, Inc. All rights reserved.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
18 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
19 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
20 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * The above copyright notice and this permission notice (including the
23 * next paragraph) shall be included in all copies or substantial portions
24 * of the Software.
25 *
26 */
27
28 #include "amdgpu.h"
29 #include "isp_v4_1_0.h"
30
31 static const unsigned int isp_4_1_0_int_srcid[MAX_ISP410_INT_SRC] = {
32 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT9,
33 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT10,
34 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT11,
35 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT12,
36 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT13,
37 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT14,
38 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT15,
39 ISP_4_1__SRCID__ISP_RINGBUFFER_WPT16
40 };
41
isp_v4_1_0_hw_init(struct amdgpu_isp * isp)42 static int isp_v4_1_0_hw_init(struct amdgpu_isp *isp)
43 {
44 struct amdgpu_device *adev = isp->adev;
45 int idx, int_idx, num_res, r;
46 u64 isp_base;
47
48 if (adev->rmmio_size == 0 || adev->rmmio_size < 0x5289)
49 return -EINVAL;
50
51 isp_base = adev->rmmio_base;
52
53 isp->isp_cell = kcalloc(2, sizeof(struct mfd_cell), GFP_KERNEL);
54 if (!isp->isp_cell) {
55 r = -ENOMEM;
56 DRM_ERROR("%s: isp mfd cell alloc failed\n", __func__);
57 goto failure;
58 }
59
60 num_res = MAX_ISP410_MEM_RES + MAX_ISP410_SENSOR_RES + MAX_ISP410_INT_SRC;
61 isp->isp_res = kcalloc(num_res, sizeof(struct resource),
62 GFP_KERNEL);
63 if (!isp->isp_res) {
64 r = -ENOMEM;
65 DRM_ERROR("%s: isp mfd res alloc failed\n", __func__);
66 goto failure;
67 }
68
69 isp->isp_pdata = kzalloc(sizeof(*isp->isp_pdata), GFP_KERNEL);
70 if (!isp->isp_pdata) {
71 r = -ENOMEM;
72 DRM_ERROR("%s: isp platform data alloc failed\n", __func__);
73 goto failure;
74 }
75
76 /* initialize isp platform data */
77 isp->isp_pdata->adev = (void *)adev;
78 isp->isp_pdata->asic_type = adev->asic_type;
79 isp->isp_pdata->base_rmmio_size = adev->rmmio_size;
80
81 isp->isp_res[0].name = "isp_4_1_0_reg";
82 isp->isp_res[0].flags = IORESOURCE_MEM;
83 isp->isp_res[0].start = isp_base;
84 isp->isp_res[0].end = isp_base + ISP_REGS_OFFSET_END;
85
86 isp->isp_res[1].name = "isp_4_1_phy0_reg";
87 isp->isp_res[1].flags = IORESOURCE_MEM;
88 isp->isp_res[1].start = isp_base + ISP410_PHY0_OFFSET;
89 isp->isp_res[1].end = isp_base + ISP410_PHY0_OFFSET + ISP410_PHY0_SIZE;
90
91 isp->isp_res[2].name = "isp_gpio_sensor0_reg";
92 isp->isp_res[2].flags = IORESOURCE_MEM;
93 isp->isp_res[2].start = isp_base + ISP410_GPIO_SENSOR0_OFFSET;
94 isp->isp_res[2].end = isp_base + ISP410_GPIO_SENSOR0_OFFSET +
95 ISP410_GPIO_SENSOR0_SIZE;
96
97 for (idx = MAX_ISP410_MEM_RES + MAX_ISP410_SENSOR_RES, int_idx = 0;
98 idx < num_res; idx++, int_idx++) {
99 isp->isp_res[idx].name = "isp_4_1_0_irq";
100 isp->isp_res[idx].flags = IORESOURCE_IRQ;
101 isp->isp_res[idx].start =
102 amdgpu_irq_create_mapping(adev, isp_4_1_0_int_srcid[int_idx]);
103 isp->isp_res[idx].end =
104 isp->isp_res[idx].start;
105 }
106
107 isp->isp_cell[0].name = "amd_isp_capture";
108 isp->isp_cell[0].num_resources = num_res;
109 isp->isp_cell[0].resources = &isp->isp_res[0];
110 isp->isp_cell[0].platform_data = isp->isp_pdata;
111 isp->isp_cell[0].pdata_size = sizeof(struct isp_platform_data);
112
113 isp->isp_i2c_res = kcalloc(1, sizeof(struct resource),
114 GFP_KERNEL);
115 if (!isp->isp_i2c_res) {
116 r = -ENOMEM;
117 DRM_ERROR("%s: isp mfd res alloc failed\n", __func__);
118 goto failure;
119 }
120
121 isp->isp_i2c_res[0].name = "isp_i2c0_reg";
122 isp->isp_i2c_res[0].flags = IORESOURCE_MEM;
123 isp->isp_i2c_res[0].start = isp_base + ISP410_I2C0_OFFSET;
124 isp->isp_i2c_res[0].end = isp_base + ISP410_I2C0_OFFSET + ISP410_I2C0_SIZE;
125
126 isp->isp_cell[1].name = "amd_isp_i2c_designware";
127 isp->isp_cell[1].num_resources = 1;
128 isp->isp_cell[1].resources = &isp->isp_i2c_res[0];
129 isp->isp_cell[1].platform_data = isp->isp_pdata;
130 isp->isp_cell[1].pdata_size = sizeof(struct isp_platform_data);
131
132 r = mfd_add_hotplug_devices(isp->parent, isp->isp_cell, 2);
133 if (r) {
134 DRM_ERROR("%s: add mfd hotplug device failed\n", __func__);
135 goto failure;
136 }
137
138 return 0;
139
140 failure:
141
142 kfree(isp->isp_pdata);
143 kfree(isp->isp_res);
144 kfree(isp->isp_cell);
145 kfree(isp->isp_i2c_res);
146
147 return r;
148 }
149
isp_v4_1_0_hw_fini(struct amdgpu_isp * isp)150 static int isp_v4_1_0_hw_fini(struct amdgpu_isp *isp)
151 {
152 mfd_remove_devices(isp->parent);
153
154 kfree(isp->isp_res);
155 kfree(isp->isp_cell);
156 kfree(isp->isp_pdata);
157 kfree(isp->isp_i2c_res);
158
159 return 0;
160 }
161
162 static const struct isp_funcs isp_v4_1_0_funcs = {
163 .hw_init = isp_v4_1_0_hw_init,
164 .hw_fini = isp_v4_1_0_hw_fini,
165 };
166
isp_v4_1_0_set_isp_funcs(struct amdgpu_isp * isp)167 void isp_v4_1_0_set_isp_funcs(struct amdgpu_isp *isp)
168 {
169 isp->funcs = &isp_v4_1_0_funcs;
170 }
171