1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license.  When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2022 Intel Corporation
7 //
8 
9 #include <sound/pcm_params.h>
10 #include <sound/sof/ipc4/header.h>
11 #include "sof-audio.h"
12 #include "sof-priv.h"
13 #include "ops.h"
14 #include "ipc4-priv.h"
15 #include "ipc4-topology.h"
16 #include "ipc4-fw-reg.h"
17 
18 /**
19  * struct sof_ipc4_timestamp_info - IPC4 timestamp info
20  * @host_copier: the host copier of the pcm stream
21  * @dai_copier: the dai copier of the pcm stream
22  * @stream_start_offset: reported by fw in memory window (converted to frames)
23  * @stream_end_offset: reported by fw in memory window (converted to frames)
24  * @llp_offset: llp offset in memory window
25  * @boundary: wrap boundary should be used for the LLP frame counter
26  * @delay: Calculated and stored in pointer callback. The stored value is
27  *	   returned in the delay callback.
28  */
29 struct sof_ipc4_timestamp_info {
30 	struct sof_ipc4_copier *host_copier;
31 	struct sof_ipc4_copier *dai_copier;
32 	u64 stream_start_offset;
33 	u64 stream_end_offset;
34 	u32 llp_offset;
35 
36 	u64 boundary;
37 	snd_pcm_sframes_t delay;
38 };
39 
40 /**
41  * struct sof_ipc4_pcm_stream_priv - IPC4 specific private data
42  * @time_info: pointer to time info struct if it is supported, otherwise NULL
43  * @chain_dma_allocated: indicates the ChainDMA allocation state
44  */
45 struct sof_ipc4_pcm_stream_priv {
46 	struct sof_ipc4_timestamp_info *time_info;
47 
48 	bool chain_dma_allocated;
49 };
50 
51 static inline struct sof_ipc4_timestamp_info *
sof_ipc4_sps_to_time_info(struct snd_sof_pcm_stream * sps)52 sof_ipc4_sps_to_time_info(struct snd_sof_pcm_stream *sps)
53 {
54 	struct sof_ipc4_pcm_stream_priv *stream_priv = sps->private;
55 
56 	return stream_priv->time_info;
57 }
58 
sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev * sdev,u32 state,struct ipc4_pipeline_set_state_data * trigger_list)59 static int sof_ipc4_set_multi_pipeline_state(struct snd_sof_dev *sdev, u32 state,
60 					     struct ipc4_pipeline_set_state_data *trigger_list)
61 {
62 	struct sof_ipc4_msg msg = {{ 0 }};
63 	u32 primary, ipc_size;
64 
65 	/* trigger a single pipeline */
66 	if (trigger_list->count == 1)
67 		return sof_ipc4_set_pipeline_state(sdev, trigger_list->pipeline_instance_ids[0],
68 						   state);
69 
70 	primary = state;
71 	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
72 	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
73 	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
74 	msg.primary = primary;
75 
76 	/* trigger multiple pipelines with a single IPC */
77 	msg.extension = SOF_IPC4_GLB_PIPE_STATE_EXT_MULTI;
78 
79 	/* ipc_size includes the count and the pipeline IDs for the number of pipelines */
80 	ipc_size = sizeof(u32) * (trigger_list->count + 1);
81 	msg.data_size = ipc_size;
82 	msg.data_ptr = trigger_list;
83 
84 	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, ipc_size);
85 }
86 
sof_ipc4_set_pipeline_state(struct snd_sof_dev * sdev,u32 instance_id,u32 state)87 int sof_ipc4_set_pipeline_state(struct snd_sof_dev *sdev, u32 instance_id, u32 state)
88 {
89 	struct sof_ipc4_msg msg = {{ 0 }};
90 	u32 primary;
91 
92 	dev_dbg(sdev->dev, "ipc4 set pipeline instance %d state %d", instance_id, state);
93 
94 	primary = state;
95 	primary |= SOF_IPC4_GLB_PIPE_STATE_ID(instance_id);
96 	primary |= SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_SET_PIPELINE_STATE);
97 	primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
98 	primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
99 
100 	msg.primary = primary;
101 
102 	return sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
103 }
104 EXPORT_SYMBOL(sof_ipc4_set_pipeline_state);
105 
sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data * trigger_list,struct snd_sof_widget * pipe_widget,s8 * pipe_priority,bool ascend)106 static void sof_ipc4_add_pipeline_by_priority(struct ipc4_pipeline_set_state_data *trigger_list,
107 					      struct snd_sof_widget *pipe_widget,
108 					      s8 *pipe_priority, bool ascend)
109 {
110 	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
111 	int i, j;
112 
113 	for (i = 0; i < trigger_list->count; i++) {
114 		/* add pipeline from low priority to high */
115 		if (ascend && pipeline->priority < pipe_priority[i])
116 			break;
117 		/* add pipeline from high priority to low */
118 		else if (!ascend && pipeline->priority > pipe_priority[i])
119 			break;
120 	}
121 
122 	for (j = trigger_list->count - 1; j >= i; j--) {
123 		trigger_list->pipeline_instance_ids[j + 1] = trigger_list->pipeline_instance_ids[j];
124 		pipe_priority[j + 1] = pipe_priority[j];
125 	}
126 
127 	trigger_list->pipeline_instance_ids[i] = pipe_widget->instance_id;
128 	trigger_list->count++;
129 	pipe_priority[i] = pipeline->priority;
130 }
131 
132 static void
sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev * sdev,int state,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list,s8 * pipe_priority)133 sof_ipc4_add_pipeline_to_trigger_list(struct snd_sof_dev *sdev, int state,
134 				      struct snd_sof_pipeline *spipe,
135 				      struct ipc4_pipeline_set_state_data *trigger_list,
136 				      s8 *pipe_priority)
137 {
138 	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
139 	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
140 
141 	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
142 		return;
143 
144 	switch (state) {
145 	case SOF_IPC4_PIPE_RUNNING:
146 		/*
147 		 * Trigger pipeline if all PCMs containing it are paused or if it is RUNNING
148 		 * for the first time
149 		 */
150 		if (spipe->started_count == spipe->paused_count)
151 			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
152 							  false);
153 		break;
154 	case SOF_IPC4_PIPE_RESET:
155 		/* RESET if the pipeline is neither running nor paused */
156 		if (!spipe->started_count && !spipe->paused_count)
157 			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
158 							  true);
159 		break;
160 	case SOF_IPC4_PIPE_PAUSED:
161 		/* Pause the pipeline only when its started_count is 1 more than paused_count */
162 		if (spipe->paused_count == (spipe->started_count - 1))
163 			sof_ipc4_add_pipeline_by_priority(trigger_list, pipe_widget, pipe_priority,
164 							  true);
165 		break;
166 	default:
167 		break;
168 	}
169 }
170 
171 static void
sof_ipc4_update_pipeline_state(struct snd_sof_dev * sdev,int state,int cmd,struct snd_sof_pipeline * spipe,struct ipc4_pipeline_set_state_data * trigger_list)172 sof_ipc4_update_pipeline_state(struct snd_sof_dev *sdev, int state, int cmd,
173 			       struct snd_sof_pipeline *spipe,
174 			       struct ipc4_pipeline_set_state_data *trigger_list)
175 {
176 	struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
177 	struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
178 	int i;
179 
180 	if (pipeline->skip_during_fe_trigger && state != SOF_IPC4_PIPE_RESET)
181 		return;
182 
183 	/* set state for pipeline if it was just triggered */
184 	for (i = 0; i < trigger_list->count; i++) {
185 		if (trigger_list->pipeline_instance_ids[i] == pipe_widget->instance_id) {
186 			pipeline->state = state;
187 			break;
188 		}
189 	}
190 
191 	switch (state) {
192 	case SOF_IPC4_PIPE_PAUSED:
193 		switch (cmd) {
194 		case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
195 			/*
196 			 * increment paused_count if the PAUSED is the final state during
197 			 * the PAUSE trigger
198 			 */
199 			spipe->paused_count++;
200 			break;
201 		case SNDRV_PCM_TRIGGER_STOP:
202 		case SNDRV_PCM_TRIGGER_SUSPEND:
203 			/*
204 			 * decrement started_count if PAUSED is the final state during the
205 			 * STOP trigger
206 			 */
207 			spipe->started_count--;
208 			break;
209 		default:
210 			break;
211 		}
212 		break;
213 	case SOF_IPC4_PIPE_RUNNING:
214 		switch (cmd) {
215 		case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
216 			/* decrement paused_count for RELEASE */
217 			spipe->paused_count--;
218 			break;
219 		case SNDRV_PCM_TRIGGER_START:
220 		case SNDRV_PCM_TRIGGER_RESUME:
221 			/* increment started_count for START/RESUME */
222 			spipe->started_count++;
223 			break;
224 		default:
225 			break;
226 		}
227 		break;
228 	default:
229 		break;
230 	}
231 }
232 
233 /*
234  * The picture below represents the pipeline state machine wrt PCM actions corresponding to the
235  * triggers and ioctls
236  *				+---------------+
237  *				|               |
238  *				|    INIT       |
239  *				|               |
240  *				+-------+-------+
241  *					|
242  *					|
243  *					| START
244  *					|
245  *					|
246  * +----------------+		   +------v-------+		  +-------------+
247  * |                |   START     |              |   HW_FREE	  |             |
248  * |   RUNNING      <-------------+  PAUSED      +--------------> +   RESET     |
249  * |                |   PAUSE     |              |		  |             |
250  * +------+---------+   RELEASE   +---------+----+		  +-------------+
251  *	  |				     ^
252  *	  |				     |
253  *	  |				     |
254  *	  |				     |
255  *	  |		PAUSE		     |
256  *	  +---------------------------------+
257  *			STOP/SUSPEND
258  *
259  * Note that during system suspend, the suspend trigger is followed by a hw_free in
260  * sof_pcm_trigger(). So, the final state during suspend would be RESET.
261  * Also, since the SOF driver doesn't support full resume, streams would be restarted with the
262  * prepare ioctl before the START trigger.
263  */
264 
265 /*
266  * Chained DMA is a special case where there is no processing on
267  * DSP. The samples are just moved over by host side DMA to a single
268  * buffer on DSP and directly from there to link DMA. However, the
269  * model on SOF driver has two notional pipelines, one at host DAI,
270  * and another at link DAI. They both shall have the use_chain_dma
271  * attribute.
272  */
273 
sof_ipc4_chain_dma_trigger(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm,int direction,struct snd_sof_pcm_stream_pipeline_list * pipeline_list,int state,int cmd)274 static int sof_ipc4_chain_dma_trigger(struct snd_sof_dev *sdev,
275 				      struct snd_sof_pcm *spcm, int direction,
276 				      struct snd_sof_pcm_stream_pipeline_list *pipeline_list,
277 				      int state, int cmd)
278 {
279 	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
280 	struct sof_ipc4_pcm_stream_priv *stream_priv;
281 	bool allocate, enable, set_fifo_size;
282 	struct sof_ipc4_msg msg = {{ 0 }};
283 	int ret, i;
284 
285 	stream_priv = spcm->stream[direction].private;
286 
287 	switch (state) {
288 	case SOF_IPC4_PIPE_RUNNING: /* Allocate and start chained dma */
289 		allocate = true;
290 		enable = true;
291 		/*
292 		 * SOF assumes creation of a new stream from the presence of fifo_size
293 		 * in the message, so we must leave it out in pause release case.
294 		 */
295 		if (cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
296 			set_fifo_size = false;
297 		else
298 			set_fifo_size = true;
299 		break;
300 	case SOF_IPC4_PIPE_PAUSED: /* Disable chained DMA. */
301 		allocate = true;
302 		enable = false;
303 		set_fifo_size = false;
304 		break;
305 	case SOF_IPC4_PIPE_RESET: /* Disable and free chained DMA. */
306 
307 		/* ChainDMA can only be reset if it has been allocated */
308 		if (!stream_priv->chain_dma_allocated)
309 			return 0;
310 
311 		allocate = false;
312 		enable = false;
313 		set_fifo_size = false;
314 		break;
315 	default:
316 		dev_err(sdev->dev, "Unexpected state %d", state);
317 		return -EINVAL;
318 	}
319 
320 	msg.primary = SOF_IPC4_MSG_TYPE_SET(SOF_IPC4_GLB_CHAIN_DMA);
321 	msg.primary |= SOF_IPC4_MSG_DIR(SOF_IPC4_MSG_REQUEST);
322 	msg.primary |= SOF_IPC4_MSG_TARGET(SOF_IPC4_FW_GEN_MSG);
323 
324 	/*
325 	 * To set-up the DMA chain, the host DMA ID and SCS setting
326 	 * are retrieved from the host pipeline configuration. Likewise
327 	 * the link DMA ID and fifo_size are retrieved from the link
328 	 * pipeline configuration.
329 	 */
330 	for (i = 0; i < pipeline_list->count; i++) {
331 		struct snd_sof_pipeline *spipe = pipeline_list->pipelines[i];
332 		struct snd_sof_widget *pipe_widget = spipe->pipe_widget;
333 		struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
334 
335 		if (!pipeline->use_chain_dma) {
336 			dev_err(sdev->dev,
337 				"All pipelines in chained DMA stream should have use_chain_dma attribute set.");
338 			return -EINVAL;
339 		}
340 
341 		msg.primary |= pipeline->msg.primary;
342 
343 		/* Add fifo_size (actually DMA buffer size) field to the message */
344 		if (set_fifo_size)
345 			msg.extension |= pipeline->msg.extension;
346 	}
347 
348 	if (direction == SNDRV_PCM_STREAM_CAPTURE) {
349 		/*
350 		 * For ChainDMA the DMA ids are unique with the following mapping:
351 		 * playback:  0 - (num_playback_streams - 1)
352 		 * capture:   num_playback_streams - (num_playback_streams +
353 		 *				      num_capture_streams - 1)
354 		 *
355 		 * Add the num_playback_streams offset to the DMA ids stored in
356 		 * msg.primary in case capture
357 		 */
358 		msg.primary +=  SOF_IPC4_GLB_CHAIN_DMA_HOST_ID(ipc4_data->num_playback_streams);
359 		msg.primary +=  SOF_IPC4_GLB_CHAIN_DMA_LINK_ID(ipc4_data->num_playback_streams);
360 	}
361 
362 	if (allocate)
363 		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ALLOCATE_MASK;
364 
365 	if (enable)
366 		msg.primary |= SOF_IPC4_GLB_CHAIN_DMA_ENABLE_MASK;
367 
368 	ret = sof_ipc_tx_message_no_reply(sdev->ipc, &msg, 0);
369 	/* Update the ChainDMA allocation state */
370 	if (!ret)
371 		stream_priv->chain_dma_allocated = allocate;
372 
373 	return ret;
374 }
375 
sof_ipc4_trigger_pipelines(struct snd_soc_component * component,struct snd_pcm_substream * substream,int state,int cmd)376 static int sof_ipc4_trigger_pipelines(struct snd_soc_component *component,
377 				      struct snd_pcm_substream *substream, int state, int cmd)
378 {
379 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
380 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
381 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
382 	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
383 	struct ipc4_pipeline_set_state_data *trigger_list;
384 	struct snd_sof_widget *pipe_widget;
385 	struct sof_ipc4_pipeline *pipeline;
386 	struct snd_sof_pipeline *spipe;
387 	struct snd_sof_pcm *spcm;
388 	u8 *pipe_priority;
389 	int ret;
390 	int i;
391 
392 	dev_dbg(sdev->dev, "trigger cmd: %d state: %d\n", cmd, state);
393 
394 	spcm = snd_sof_find_spcm_dai(component, rtd);
395 	if (!spcm)
396 		return -EINVAL;
397 
398 	pipeline_list = &spcm->stream[substream->stream].pipeline_list;
399 
400 	/* nothing to trigger if the list is empty */
401 	if (!pipeline_list->pipelines || !pipeline_list->count)
402 		return 0;
403 
404 	spipe = pipeline_list->pipelines[0];
405 	pipe_widget = spipe->pipe_widget;
406 	pipeline = pipe_widget->private;
407 
408 	/*
409 	 * If use_chain_dma attribute is set we proceed to chained DMA
410 	 * trigger function that handles the rest for the substream.
411 	 */
412 	if (pipeline->use_chain_dma)
413 		return sof_ipc4_chain_dma_trigger(sdev, spcm, substream->stream,
414 						  pipeline_list, state, cmd);
415 
416 	/* allocate memory for the pipeline data */
417 	trigger_list = kzalloc(struct_size(trigger_list, pipeline_instance_ids,
418 					   pipeline_list->count), GFP_KERNEL);
419 	if (!trigger_list)
420 		return -ENOMEM;
421 
422 	pipe_priority = kzalloc(pipeline_list->count, GFP_KERNEL);
423 	if (!pipe_priority) {
424 		kfree(trigger_list);
425 		return -ENOMEM;
426 	}
427 
428 	mutex_lock(&ipc4_data->pipeline_state_mutex);
429 
430 	/*
431 	 * IPC4 requires pipelines to be triggered in order starting at the sink and
432 	 * walking all the way to the source. So traverse the pipeline_list in the order
433 	 * sink->source when starting PCM's and in the reverse order to pause/stop PCM's.
434 	 * Skip the pipelines that have their skip_during_fe_trigger flag set. If there is a fork
435 	 * in the pipeline, the order of triggering between the left/right paths will be
436 	 * indeterministic. But the sink->source trigger order sink->source would still be
437 	 * guaranteed for each fork independently.
438 	 */
439 	if (state == SOF_IPC4_PIPE_RUNNING || state == SOF_IPC4_PIPE_RESET)
440 		for (i = pipeline_list->count - 1; i >= 0; i--) {
441 			spipe = pipeline_list->pipelines[i];
442 			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
443 							      pipe_priority);
444 		}
445 	else
446 		for (i = 0; i < pipeline_list->count; i++) {
447 			spipe = pipeline_list->pipelines[i];
448 			sof_ipc4_add_pipeline_to_trigger_list(sdev, state, spipe, trigger_list,
449 							      pipe_priority);
450 		}
451 
452 	/* return if all pipelines are in the requested state already */
453 	if (!trigger_list->count) {
454 		ret = 0;
455 		goto free;
456 	}
457 
458 	/* no need to pause before reset or before pause release */
459 	if (state == SOF_IPC4_PIPE_RESET || cmd == SNDRV_PCM_TRIGGER_PAUSE_RELEASE)
460 		goto skip_pause_transition;
461 
462 	/*
463 	 * set paused state for pipelines if the final state is PAUSED or when the pipeline
464 	 * is set to RUNNING for the first time after the PCM is started.
465 	 */
466 	ret = sof_ipc4_set_multi_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, trigger_list);
467 	if (ret < 0) {
468 		dev_err(sdev->dev, "failed to pause all pipelines\n");
469 		goto free;
470 	}
471 
472 	/* update PAUSED state for all pipelines just triggered */
473 	for (i = 0; i < pipeline_list->count ; i++) {
474 		spipe = pipeline_list->pipelines[i];
475 		sof_ipc4_update_pipeline_state(sdev, SOF_IPC4_PIPE_PAUSED, cmd, spipe,
476 					       trigger_list);
477 	}
478 
479 	/* return if this is the final state */
480 	if (state == SOF_IPC4_PIPE_PAUSED) {
481 		struct sof_ipc4_timestamp_info *time_info;
482 
483 		/*
484 		 * Invalidate the stream_start_offset to make sure that it is
485 		 * going to be updated if the stream resumes
486 		 */
487 		time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
488 		if (time_info)
489 			time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
490 
491 		goto free;
492 	}
493 skip_pause_transition:
494 	/* else set the RUNNING/RESET state in the DSP */
495 	ret = sof_ipc4_set_multi_pipeline_state(sdev, state, trigger_list);
496 	if (ret < 0) {
497 		dev_err(sdev->dev, "failed to set final state %d for all pipelines\n", state);
498 		/*
499 		 * workaround: if the firmware is crashed while setting the
500 		 * pipelines to reset state we must ignore the error code and
501 		 * reset it to 0.
502 		 * Since the firmware is crashed we will not send IPC messages
503 		 * and we are going to see errors printed, but the state of the
504 		 * widgets will be correct for the next boot.
505 		 */
506 		if (sdev->fw_state != SOF_FW_CRASHED || state != SOF_IPC4_PIPE_RESET)
507 			goto free;
508 
509 		ret = 0;
510 	}
511 
512 	/* update RUNNING/RESET state for all pipelines that were just triggered */
513 	for (i = 0; i < pipeline_list->count; i++) {
514 		spipe = pipeline_list->pipelines[i];
515 		sof_ipc4_update_pipeline_state(sdev, state, cmd, spipe, trigger_list);
516 	}
517 
518 free:
519 	mutex_unlock(&ipc4_data->pipeline_state_mutex);
520 	kfree(trigger_list);
521 	kfree(pipe_priority);
522 	return ret;
523 }
524 
sof_ipc4_pcm_trigger(struct snd_soc_component * component,struct snd_pcm_substream * substream,int cmd)525 static int sof_ipc4_pcm_trigger(struct snd_soc_component *component,
526 				struct snd_pcm_substream *substream, int cmd)
527 {
528 	int state;
529 
530 	/* determine the pipeline state */
531 	switch (cmd) {
532 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
533 	case SNDRV_PCM_TRIGGER_RESUME:
534 	case SNDRV_PCM_TRIGGER_START:
535 		state = SOF_IPC4_PIPE_RUNNING;
536 		break;
537 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
538 	case SNDRV_PCM_TRIGGER_SUSPEND:
539 	case SNDRV_PCM_TRIGGER_STOP:
540 		state = SOF_IPC4_PIPE_PAUSED;
541 		break;
542 	default:
543 		dev_err(component->dev, "%s: unhandled trigger cmd %d\n", __func__, cmd);
544 		return -EINVAL;
545 	}
546 
547 	/* set the pipeline state */
548 	return sof_ipc4_trigger_pipelines(component, substream, state, cmd);
549 }
550 
sof_ipc4_pcm_hw_free(struct snd_soc_component * component,struct snd_pcm_substream * substream)551 static int sof_ipc4_pcm_hw_free(struct snd_soc_component *component,
552 				struct snd_pcm_substream *substream)
553 {
554 	/* command is not relevant with RESET, so just pass 0 */
555 	return sof_ipc4_trigger_pipelines(component, substream, SOF_IPC4_PIPE_RESET, 0);
556 }
557 
ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev * sdev,const char * link_name,struct snd_pcm_hw_params * params)558 static void ipc4_ssp_dai_config_pcm_params_match(struct snd_sof_dev *sdev, const char *link_name,
559 						 struct snd_pcm_hw_params *params)
560 {
561 	struct snd_sof_dai_link *slink;
562 	struct snd_sof_dai *dai;
563 	bool dai_link_found = false;
564 	int i;
565 
566 	list_for_each_entry(slink, &sdev->dai_link_list, list) {
567 		if (!strcmp(slink->link->name, link_name)) {
568 			dai_link_found = true;
569 			break;
570 		}
571 	}
572 
573 	if (!dai_link_found)
574 		return;
575 
576 	for (i = 0; i < slink->num_hw_configs; i++) {
577 		struct snd_soc_tplg_hw_config *hw_config = &slink->hw_configs[i];
578 
579 		if (params_rate(params) == le32_to_cpu(hw_config->fsync_rate)) {
580 			/* set current config for all DAI's with matching name */
581 			list_for_each_entry(dai, &sdev->dai_list, list)
582 				if (!strcmp(slink->link->name, dai->name))
583 					dai->current_config = le32_to_cpu(hw_config->id);
584 			break;
585 		}
586 	}
587 }
588 
589 /*
590  * Fixup DAI link parameters for sampling rate based on
591  * DAI copier configuration.
592  */
sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev * sdev,struct snd_pcm_hw_params * params,struct sof_ipc4_copier * ipc4_copier)593 static int sof_ipc4_pcm_dai_link_fixup_rate(struct snd_sof_dev *sdev,
594 					    struct snd_pcm_hw_params *params,
595 					    struct sof_ipc4_copier *ipc4_copier)
596 {
597 	struct sof_ipc4_pin_format *pin_fmts = ipc4_copier->available_fmt.input_pin_fmts;
598 	struct snd_interval *rate = hw_param_interval(params, SNDRV_PCM_HW_PARAM_RATE);
599 	int num_input_formats = ipc4_copier->available_fmt.num_input_formats;
600 	unsigned int fe_rate = params_rate(params);
601 	bool fe_be_rate_match = false;
602 	bool single_be_rate = true;
603 	unsigned int be_rate;
604 	int i;
605 
606 	/*
607 	 * Copier does not change sampling rate, so we
608 	 * need to only consider the input pin information.
609 	 */
610 	for (i = 0; i < num_input_formats; i++) {
611 		unsigned int val = pin_fmts[i].audio_fmt.sampling_frequency;
612 
613 		if (i == 0)
614 			be_rate = val;
615 		else if (val != be_rate)
616 			single_be_rate = false;
617 
618 		if (val == fe_rate) {
619 			fe_be_rate_match = true;
620 			break;
621 		}
622 	}
623 
624 	/*
625 	 * If rate is different than FE rate, topology must
626 	 * contain an SRC. But we do require topology to
627 	 * define a single rate in the DAI copier config in
628 	 * this case (FE rate may be variable).
629 	 */
630 	if (!fe_be_rate_match) {
631 		if (!single_be_rate) {
632 			dev_err(sdev->dev, "Unable to select sampling rate for DAI link\n");
633 			return -EINVAL;
634 		}
635 
636 		rate->min = be_rate;
637 		rate->max = rate->min;
638 	}
639 
640 	return 0;
641 }
642 
sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime * rtd,struct snd_pcm_hw_params * params)643 static int sof_ipc4_pcm_dai_link_fixup(struct snd_soc_pcm_runtime *rtd,
644 				       struct snd_pcm_hw_params *params)
645 {
646 	struct snd_soc_component *component = snd_soc_rtdcom_lookup(rtd, SOF_AUDIO_PCM_DRV_NAME);
647 	struct snd_sof_dai *dai = snd_sof_find_dai(component, rtd->dai_link->name);
648 	struct snd_mask *fmt = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
649 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
650 	struct snd_soc_dai *cpu_dai = snd_soc_rtd_to_cpu(rtd, 0);
651 	struct sof_ipc4_audio_format *ipc4_fmt;
652 	struct sof_ipc4_copier *ipc4_copier;
653 	bool single_bitdepth = false;
654 	u32 valid_bits = 0;
655 	int dir, ret;
656 
657 	if (!dai) {
658 		dev_err(component->dev, "%s: No DAI found with name %s\n", __func__,
659 			rtd->dai_link->name);
660 		return -EINVAL;
661 	}
662 
663 	ipc4_copier = dai->private;
664 	if (!ipc4_copier) {
665 		dev_err(component->dev, "%s: No private data found for DAI %s\n",
666 			__func__, rtd->dai_link->name);
667 		return -EINVAL;
668 	}
669 
670 	for_each_pcm_streams(dir) {
671 		struct snd_soc_dapm_widget *w = snd_soc_dai_get_widget(cpu_dai, dir);
672 
673 		if (w) {
674 			struct sof_ipc4_available_audio_format *available_fmt =
675 				&ipc4_copier->available_fmt;
676 			struct snd_sof_widget *swidget = w->dobj.private;
677 			struct snd_sof_widget *pipe_widget = swidget->spipe->pipe_widget;
678 			struct sof_ipc4_pipeline *pipeline = pipe_widget->private;
679 
680 			/* Chain DMA does not use copiers, so no fixup needed */
681 			if (pipeline->use_chain_dma)
682 				return 0;
683 
684 			if (dir == SNDRV_PCM_STREAM_PLAYBACK) {
685 				if (sof_ipc4_copier_is_single_bitdepth(sdev,
686 					available_fmt->output_pin_fmts,
687 					available_fmt->num_output_formats)) {
688 					ipc4_fmt = &available_fmt->output_pin_fmts->audio_fmt;
689 					single_bitdepth = true;
690 				}
691 			} else {
692 				if (sof_ipc4_copier_is_single_bitdepth(sdev,
693 					available_fmt->input_pin_fmts,
694 					available_fmt->num_input_formats)) {
695 					ipc4_fmt = &available_fmt->input_pin_fmts->audio_fmt;
696 					single_bitdepth = true;
697 				}
698 			}
699 		}
700 	}
701 
702 	ret = sof_ipc4_pcm_dai_link_fixup_rate(sdev, params, ipc4_copier);
703 	if (ret)
704 		return ret;
705 
706 	if (single_bitdepth) {
707 		snd_mask_none(fmt);
708 		valid_bits = SOF_IPC4_AUDIO_FORMAT_CFG_V_BIT_DEPTH(ipc4_fmt->fmt_cfg);
709 		dev_dbg(component->dev, "Set %s to %d bit format\n", dai->name, valid_bits);
710 	}
711 
712 	/* Set format if it is specified */
713 	switch (valid_bits) {
714 	case 16:
715 		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S16_LE);
716 		break;
717 	case 24:
718 		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S24_LE);
719 		break;
720 	case 32:
721 		snd_mask_set_format(fmt, SNDRV_PCM_FORMAT_S32_LE);
722 		break;
723 	default:
724 		break;
725 	}
726 
727 	switch (ipc4_copier->dai_type) {
728 	case SOF_DAI_INTEL_SSP:
729 		ipc4_ssp_dai_config_pcm_params_match(sdev, (char *)rtd->dai_link->name, params);
730 		break;
731 	default:
732 		break;
733 	}
734 
735 	return 0;
736 }
737 
sof_ipc4_pcm_free(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)738 static void sof_ipc4_pcm_free(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
739 {
740 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
741 	struct sof_ipc4_pcm_stream_priv *stream_priv;
742 	int stream;
743 
744 	for_each_pcm_streams(stream) {
745 		pipeline_list = &spcm->stream[stream].pipeline_list;
746 		kfree(pipeline_list->pipelines);
747 		pipeline_list->pipelines = NULL;
748 
749 		stream_priv = spcm->stream[stream].private;
750 		kfree(stream_priv->time_info);
751 		kfree(spcm->stream[stream].private);
752 		spcm->stream[stream].private = NULL;
753 	}
754 }
755 
sof_ipc4_pcm_setup(struct snd_sof_dev * sdev,struct snd_sof_pcm * spcm)756 static int sof_ipc4_pcm_setup(struct snd_sof_dev *sdev, struct snd_sof_pcm *spcm)
757 {
758 	struct snd_sof_pcm_stream_pipeline_list *pipeline_list;
759 	struct sof_ipc4_fw_data *ipc4_data = sdev->private;
760 	struct sof_ipc4_pcm_stream_priv *stream_priv;
761 	struct sof_ipc4_timestamp_info *time_info;
762 	bool support_info = true;
763 	u32 abi_version;
764 	u32 abi_offset;
765 	int stream;
766 
767 	abi_offset = offsetof(struct sof_ipc4_fw_registers, abi_ver);
768 	sof_mailbox_read(sdev, sdev->fw_info_box.offset + abi_offset, &abi_version,
769 			 sizeof(abi_version));
770 
771 	if (abi_version < SOF_IPC4_FW_REGS_ABI_VER)
772 		support_info = false;
773 
774 	/* For delay reporting the get_host_byte_counter callback is needed */
775 	if (!sof_ops(sdev) || !sof_ops(sdev)->get_host_byte_counter)
776 		support_info = false;
777 
778 	for_each_pcm_streams(stream) {
779 		pipeline_list = &spcm->stream[stream].pipeline_list;
780 
781 		/* allocate memory for max number of pipeline IDs */
782 		pipeline_list->pipelines = kcalloc(ipc4_data->max_num_pipelines,
783 						   sizeof(struct snd_sof_widget *), GFP_KERNEL);
784 		if (!pipeline_list->pipelines) {
785 			sof_ipc4_pcm_free(sdev, spcm);
786 			return -ENOMEM;
787 		}
788 
789 		stream_priv = kzalloc(sizeof(*stream_priv), GFP_KERNEL);
790 		if (!stream_priv) {
791 			sof_ipc4_pcm_free(sdev, spcm);
792 			return -ENOMEM;
793 		}
794 
795 		spcm->stream[stream].private = stream_priv;
796 
797 		if (!support_info)
798 			continue;
799 
800 		time_info = kzalloc(sizeof(*time_info), GFP_KERNEL);
801 		if (!time_info) {
802 			sof_ipc4_pcm_free(sdev, spcm);
803 			return -ENOMEM;
804 		}
805 
806 		stream_priv->time_info = time_info;
807 	}
808 
809 	return 0;
810 }
811 
sof_ipc4_build_time_info(struct snd_sof_dev * sdev,struct snd_sof_pcm_stream * sps)812 static void sof_ipc4_build_time_info(struct snd_sof_dev *sdev, struct snd_sof_pcm_stream *sps)
813 {
814 	struct sof_ipc4_copier *host_copier = NULL;
815 	struct sof_ipc4_copier *dai_copier = NULL;
816 	struct sof_ipc4_llp_reading_slot llp_slot;
817 	struct sof_ipc4_timestamp_info *time_info;
818 	struct snd_soc_dapm_widget *widget;
819 	struct snd_sof_dai *dai;
820 	int i;
821 
822 	/* find host & dai to locate info in memory window */
823 	for_each_dapm_widgets(sps->list, i, widget) {
824 		struct snd_sof_widget *swidget = widget->dobj.private;
825 
826 		if (!swidget)
827 			continue;
828 
829 		if (WIDGET_IS_AIF(swidget->widget->id)) {
830 			host_copier = swidget->private;
831 		} else if (WIDGET_IS_DAI(swidget->widget->id)) {
832 			dai = swidget->private;
833 			dai_copier = dai->private;
834 		}
835 	}
836 
837 	/* both host and dai copier must be valid for time_info */
838 	if (!host_copier || !dai_copier) {
839 		dev_err(sdev->dev, "host or dai copier are not found\n");
840 		return;
841 	}
842 
843 	time_info = sof_ipc4_sps_to_time_info(sps);
844 	time_info->host_copier = host_copier;
845 	time_info->dai_copier = dai_copier;
846 	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
847 					 llp_gpdma_reading_slots) + sdev->fw_info_box.offset;
848 
849 	/* find llp slot used by current dai */
850 	for (i = 0; i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS; i++) {
851 		sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
852 		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
853 			break;
854 
855 		time_info->llp_offset += sizeof(llp_slot);
856 	}
857 
858 	if (i < SOF_IPC4_MAX_LLP_GPDMA_READING_SLOTS)
859 		return;
860 
861 	/* if no llp gpdma slot is used, check aggregated sdw slot */
862 	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
863 					 llp_sndw_reading_slots) + sdev->fw_info_box.offset;
864 	for (i = 0; i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS; i++) {
865 		sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
866 		if (llp_slot.node_id == dai_copier->data.gtw_cfg.node_id)
867 			break;
868 
869 		time_info->llp_offset += sizeof(llp_slot);
870 	}
871 
872 	if (i < SOF_IPC4_MAX_LLP_SNDW_READING_SLOTS)
873 		return;
874 
875 	/* check EVAD slot */
876 	time_info->llp_offset = offsetof(struct sof_ipc4_fw_registers,
877 					 llp_evad_reading_slot) + sdev->fw_info_box.offset;
878 	sof_mailbox_read(sdev, time_info->llp_offset, &llp_slot, sizeof(llp_slot));
879 	if (llp_slot.node_id != dai_copier->data.gtw_cfg.node_id)
880 		time_info->llp_offset = 0;
881 }
882 
sof_ipc4_pcm_hw_params(struct snd_soc_component * component,struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_sof_platform_stream_params * platform_params)883 static int sof_ipc4_pcm_hw_params(struct snd_soc_component *component,
884 				  struct snd_pcm_substream *substream,
885 				  struct snd_pcm_hw_params *params,
886 				  struct snd_sof_platform_stream_params *platform_params)
887 {
888 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
889 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
890 	struct sof_ipc4_timestamp_info *time_info;
891 	struct snd_sof_pcm *spcm;
892 
893 	spcm = snd_sof_find_spcm_dai(component, rtd);
894 	if (!spcm)
895 		return -EINVAL;
896 
897 	time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
898 	/* delay calculation is not supported by current fw_reg ABI */
899 	if (!time_info)
900 		return 0;
901 
902 	time_info->stream_start_offset = SOF_IPC4_INVALID_STREAM_POSITION;
903 	time_info->llp_offset = 0;
904 
905 	sof_ipc4_build_time_info(sdev, &spcm->stream[substream->stream]);
906 
907 	return 0;
908 }
909 
sof_ipc4_get_stream_start_offset(struct snd_sof_dev * sdev,struct snd_pcm_substream * substream,struct snd_sof_pcm_stream * sps,struct sof_ipc4_timestamp_info * time_info)910 static int sof_ipc4_get_stream_start_offset(struct snd_sof_dev *sdev,
911 					    struct snd_pcm_substream *substream,
912 					    struct snd_sof_pcm_stream *sps,
913 					    struct sof_ipc4_timestamp_info *time_info)
914 {
915 	struct sof_ipc4_copier *host_copier = time_info->host_copier;
916 	struct sof_ipc4_copier *dai_copier = time_info->dai_copier;
917 	struct sof_ipc4_pipeline_registers ppl_reg;
918 	u32 dai_sample_size;
919 	u32 ch, node_index;
920 	u32 offset;
921 
922 	if (!host_copier || !dai_copier)
923 		return -EINVAL;
924 
925 	if (host_copier->data.gtw_cfg.node_id == SOF_IPC4_INVALID_NODE_ID)
926 		return -EINVAL;
927 
928 	node_index = SOF_IPC4_NODE_INDEX(host_copier->data.gtw_cfg.node_id);
929 	offset = offsetof(struct sof_ipc4_fw_registers, pipeline_regs) + node_index * sizeof(ppl_reg);
930 	sof_mailbox_read(sdev, sdev->fw_info_box.offset + offset, &ppl_reg, sizeof(ppl_reg));
931 	if (ppl_reg.stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION)
932 		return -EINVAL;
933 
934 	ch = dai_copier->data.out_format.fmt_cfg;
935 	ch = SOF_IPC4_AUDIO_FORMAT_CFG_CHANNELS_COUNT(ch);
936 	dai_sample_size = (dai_copier->data.out_format.bit_depth >> 3) * ch;
937 
938 	/* convert offsets to frame count */
939 	time_info->stream_start_offset = ppl_reg.stream_start_offset;
940 	do_div(time_info->stream_start_offset, dai_sample_size);
941 	time_info->stream_end_offset = ppl_reg.stream_end_offset;
942 	do_div(time_info->stream_end_offset, dai_sample_size);
943 
944 	/*
945 	 * Calculate the wrap boundary need to be used for delay calculation
946 	 * The host counter is in bytes, it will wrap earlier than the frames
947 	 * based link counter.
948 	 */
949 	time_info->boundary = div64_u64(~((u64)0),
950 					frames_to_bytes(substream->runtime, 1));
951 	/* Initialize the delay value to 0 (no delay) */
952 	time_info->delay = 0;
953 
954 	return 0;
955 }
956 
sof_ipc4_pcm_pointer(struct snd_soc_component * component,struct snd_pcm_substream * substream,snd_pcm_uframes_t * pointer)957 static int sof_ipc4_pcm_pointer(struct snd_soc_component *component,
958 				struct snd_pcm_substream *substream,
959 				snd_pcm_uframes_t *pointer)
960 {
961 	struct snd_sof_dev *sdev = snd_soc_component_get_drvdata(component);
962 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
963 	struct sof_ipc4_timestamp_info *time_info;
964 	struct sof_ipc4_llp_reading_slot llp;
965 	snd_pcm_uframes_t head_cnt, tail_cnt;
966 	struct snd_sof_pcm_stream *sps;
967 	u64 dai_cnt, host_cnt, host_ptr;
968 	struct snd_sof_pcm *spcm;
969 	int ret;
970 
971 	spcm = snd_sof_find_spcm_dai(component, rtd);
972 	if (!spcm)
973 		return -EOPNOTSUPP;
974 
975 	sps = &spcm->stream[substream->stream];
976 	time_info = sof_ipc4_sps_to_time_info(sps);
977 	if (!time_info)
978 		return -EOPNOTSUPP;
979 
980 	/*
981 	 * stream_start_offset is updated to memory window by FW based on
982 	 * pipeline statistics and it may be invalid if host query happens before
983 	 * the statistics is complete. And it will not change after the first initiailization.
984 	 */
985 	if (time_info->stream_start_offset == SOF_IPC4_INVALID_STREAM_POSITION) {
986 		ret = sof_ipc4_get_stream_start_offset(sdev, substream, sps, time_info);
987 		if (ret < 0)
988 			return -EOPNOTSUPP;
989 	}
990 
991 	/* For delay calculation we need the host counter */
992 	host_cnt = snd_sof_pcm_get_host_byte_counter(sdev, component, substream);
993 	host_ptr = host_cnt;
994 
995 	/* convert the host_cnt to frames */
996 	host_cnt = div64_u64(host_cnt, frames_to_bytes(substream->runtime, 1));
997 
998 	/*
999 	 * If the LLP counter is not reported by firmware in the SRAM window
1000 	 * then read the dai (link) counter via host accessible means if
1001 	 * available.
1002 	 */
1003 	if (!time_info->llp_offset) {
1004 		dai_cnt = snd_sof_pcm_get_dai_frame_counter(sdev, component, substream);
1005 		if (!dai_cnt)
1006 			return -EOPNOTSUPP;
1007 	} else {
1008 		sof_mailbox_read(sdev, time_info->llp_offset, &llp, sizeof(llp));
1009 		dai_cnt = ((u64)llp.reading.llp_u << 32) | llp.reading.llp_l;
1010 	}
1011 	dai_cnt += time_info->stream_end_offset;
1012 
1013 	/* In two cases dai dma counter is not accurate
1014 	 * (1) dai pipeline is started before host pipeline
1015 	 * (2) multiple streams mixed into one. Each stream has the same dai dma
1016 	 *     counter
1017 	 *
1018 	 * Firmware calculates correct stream_start_offset for all cases
1019 	 * including above two.
1020 	 * Driver subtracts stream_start_offset from dai dma counter to get
1021 	 * accurate one
1022 	 */
1023 
1024 	/*
1025 	 * On stream start the dai counter might not yet have reached the
1026 	 * stream_start_offset value which means that no frames have left the
1027 	 * DSP yet from the audio stream (on playback, capture streams have
1028 	 * offset of 0 as we start capturing right away).
1029 	 * In this case we need to adjust the distance between the counters by
1030 	 * increasing the host counter by (offset - dai_counter).
1031 	 * Otherwise the dai_counter needs to be adjusted to reflect the number
1032 	 * of valid frames passed on the DAI side.
1033 	 *
1034 	 * The delay is the difference between the counters on the two
1035 	 * sides of the DSP.
1036 	 */
1037 	if (dai_cnt < time_info->stream_start_offset) {
1038 		host_cnt += time_info->stream_start_offset - dai_cnt;
1039 		dai_cnt = 0;
1040 	} else {
1041 		dai_cnt -= time_info->stream_start_offset;
1042 	}
1043 
1044 	/* Wrap the dai counter at the boundary where the host counter wraps */
1045 	div64_u64_rem(dai_cnt, time_info->boundary, &dai_cnt);
1046 
1047 	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1048 		head_cnt = host_cnt;
1049 		tail_cnt = dai_cnt;
1050 	} else {
1051 		head_cnt = dai_cnt;
1052 		tail_cnt = host_cnt;
1053 	}
1054 
1055 	if (head_cnt < tail_cnt) {
1056 		time_info->delay = time_info->boundary - tail_cnt + head_cnt;
1057 		goto out;
1058 	}
1059 
1060 	time_info->delay =  head_cnt - tail_cnt;
1061 
1062 out:
1063 	/*
1064 	 * Convert the host byte counter to PCM pointer which wraps in buffer
1065 	 * and it is in frames
1066 	 */
1067 	div64_u64_rem(host_ptr, snd_pcm_lib_buffer_bytes(substream), &host_ptr);
1068 	*pointer = bytes_to_frames(substream->runtime, host_ptr);
1069 
1070 	return 0;
1071 }
1072 
sof_ipc4_pcm_delay(struct snd_soc_component * component,struct snd_pcm_substream * substream)1073 static snd_pcm_sframes_t sof_ipc4_pcm_delay(struct snd_soc_component *component,
1074 					    struct snd_pcm_substream *substream)
1075 {
1076 	struct snd_soc_pcm_runtime *rtd = snd_soc_substream_to_rtd(substream);
1077 	struct sof_ipc4_timestamp_info *time_info;
1078 	struct snd_sof_pcm *spcm;
1079 
1080 	spcm = snd_sof_find_spcm_dai(component, rtd);
1081 	if (!spcm)
1082 		return 0;
1083 
1084 	time_info = sof_ipc4_sps_to_time_info(&spcm->stream[substream->stream]);
1085 	/*
1086 	 * Report the stored delay value calculated in the pointer callback.
1087 	 * In the unlikely event that the calculation was skipped/aborted, the
1088 	 * default 0 delay returned.
1089 	 */
1090 	if (time_info)
1091 		return time_info->delay;
1092 
1093 	/* No delay information available, report 0 as delay */
1094 	return 0;
1095 
1096 }
1097 
1098 const struct sof_ipc_pcm_ops ipc4_pcm_ops = {
1099 	.hw_params = sof_ipc4_pcm_hw_params,
1100 	.trigger = sof_ipc4_pcm_trigger,
1101 	.hw_free = sof_ipc4_pcm_hw_free,
1102 	.dai_link_fixup = sof_ipc4_pcm_dai_link_fixup,
1103 	.pcm_setup = sof_ipc4_pcm_setup,
1104 	.pcm_free = sof_ipc4_pcm_free,
1105 	.pointer = sof_ipc4_pcm_pointer,
1106 	.delay = sof_ipc4_pcm_delay,
1107 	.ipc_first_on_start = true,
1108 	.platform_stop_during_hw_free = true,
1109 };
1110