1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 #ifndef _ASM_POWERPC_IO_H
3 #define _ASM_POWERPC_IO_H
4 #ifdef __KERNEL__
5
6 /*
7 */
8
9 /* Check of existence of legacy devices */
10 extern int check_legacy_ioport(unsigned long base_port);
11 #define I8042_DATA_REG 0x60
12 #define FDC_BASE 0x3f0
13
14 #if defined(CONFIG_PPC64) && defined(CONFIG_PCI)
15 extern struct pci_dev *isa_bridge_pcidev;
16 /*
17 * has legacy ISA devices ?
18 */
19 #define arch_has_dev_port() (isa_bridge_pcidev != NULL || isa_io_special)
20 #endif
21
22 #include <linux/device.h>
23 #include <linux/compiler.h>
24 #include <linux/mm.h>
25 #include <asm/page.h>
26 #include <asm/byteorder.h>
27 #include <asm/synch.h>
28 #include <asm/delay.h>
29 #include <asm/mmiowb.h>
30 #include <asm/mmu.h>
31
32 #define SIO_CONFIG_RA 0x398
33 #define SIO_CONFIG_RD 0x399
34
35 /* 32 bits uses slightly different variables for the various IO
36 * bases. Most of this file only uses _IO_BASE though which we
37 * define properly based on the platform
38 */
39 #ifndef CONFIG_PCI
40 #define _IO_BASE POISON_POINTER_DELTA
41 #define _ISA_MEM_BASE 0
42 #define PCI_DRAM_OFFSET 0
43 #elif defined(CONFIG_PPC32)
44 #define _IO_BASE isa_io_base
45 #define _ISA_MEM_BASE isa_mem_base
46 #define PCI_DRAM_OFFSET pci_dram_offset
47 #else
48 #define _IO_BASE pci_io_base
49 #define _ISA_MEM_BASE isa_mem_base
50 #define PCI_DRAM_OFFSET 0
51 #endif
52
53 extern unsigned long isa_io_base;
54 extern unsigned long pci_io_base;
55 extern unsigned long pci_dram_offset;
56
57 extern resource_size_t isa_mem_base;
58
59 /* Boolean set by platform if PIO accesses are suppored while _IO_BASE
60 * is not set or addresses cannot be translated to MMIO. This is typically
61 * set when the platform supports "special" PIO accesses via a non memory
62 * mapped mechanism, and allows things like the early udbg UART code to
63 * function.
64 */
65 extern bool isa_io_special;
66
67 #ifdef CONFIG_PPC32
68 #if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
69 #error CONFIG_PPC_INDIRECT_{PIO,MMIO} are not yet supported on 32 bits
70 #endif
71 #endif
72
73 /*
74 *
75 * Low level MMIO accessors
76 *
77 * This provides the non-bus specific accessors to MMIO. Those are PowerPC
78 * specific and thus shouldn't be used in generic code. The accessors
79 * provided here are:
80 *
81 * in_8, in_le16, in_be16, in_le32, in_be32, in_le64, in_be64
82 * out_8, out_le16, out_be16, out_le32, out_be32, out_le64, out_be64
83 * _insb, _insw_ns, _insl_ns, _outsb, _outsw_ns, _outsl_ns
84 *
85 * Those operate directly on a kernel virtual address. Note that the prototype
86 * for the out_* accessors has the arguments in opposite order from the usual
87 * linux PCI accessors. Unlike those, they take the address first and the value
88 * next.
89 *
90 * Note: I might drop the _ns suffix on the stream operations soon as it is
91 * simply normal for stream operations to not swap in the first place.
92 *
93 */
94
95 /* -mprefixed can generate offsets beyond range, fall back hack */
96 #ifdef CONFIG_PPC_KERNEL_PREFIXED
97 #define DEF_MMIO_IN_X(name, size, insn) \
98 static inline u##size name(const volatile u##size __iomem *addr) \
99 { \
100 u##size ret; \
101 __asm__ __volatile__("sync;"#insn" %0,0,%1;twi 0,%0,0;isync" \
102 : "=r" (ret) : "r" (addr) : "memory"); \
103 return ret; \
104 }
105
106 #define DEF_MMIO_OUT_X(name, size, insn) \
107 static inline void name(volatile u##size __iomem *addr, u##size val) \
108 { \
109 __asm__ __volatile__("sync;"#insn" %1,0,%0" \
110 : : "r" (addr), "r" (val) : "memory"); \
111 mmiowb_set_pending(); \
112 }
113
114 #define DEF_MMIO_IN_D(name, size, insn) \
115 static inline u##size name(const volatile u##size __iomem *addr) \
116 { \
117 u##size ret; \
118 __asm__ __volatile__("sync;"#insn" %0,0(%1);twi 0,%0,0;isync"\
119 : "=r" (ret) : "b" (addr) : "memory"); \
120 return ret; \
121 }
122
123 #define DEF_MMIO_OUT_D(name, size, insn) \
124 static inline void name(volatile u##size __iomem *addr, u##size val) \
125 { \
126 __asm__ __volatile__("sync;"#insn" %1,0(%0)" \
127 : : "b" (addr), "r" (val) : "memory"); \
128 mmiowb_set_pending(); \
129 }
130 #else
131 #define DEF_MMIO_IN_X(name, size, insn) \
132 static inline u##size name(const volatile u##size __iomem *addr) \
133 { \
134 u##size ret; \
135 __asm__ __volatile__("sync;"#insn" %0,%y1;twi 0,%0,0;isync" \
136 : "=r" (ret) : "Z" (*addr) : "memory"); \
137 return ret; \
138 }
139
140 #define DEF_MMIO_OUT_X(name, size, insn) \
141 static inline void name(volatile u##size __iomem *addr, u##size val) \
142 { \
143 __asm__ __volatile__("sync;"#insn" %1,%y0" \
144 : "=Z" (*addr) : "r" (val) : "memory"); \
145 mmiowb_set_pending(); \
146 }
147
148 #define DEF_MMIO_IN_D(name, size, insn) \
149 static inline u##size name(const volatile u##size __iomem *addr) \
150 { \
151 u##size ret; \
152 __asm__ __volatile__("sync;"#insn"%U1%X1 %0,%1;twi 0,%0,0;isync"\
153 : "=r" (ret) : "m<>" (*addr) : "memory"); \
154 return ret; \
155 }
156
157 #define DEF_MMIO_OUT_D(name, size, insn) \
158 static inline void name(volatile u##size __iomem *addr, u##size val) \
159 { \
160 __asm__ __volatile__("sync;"#insn"%U0%X0 %1,%0" \
161 : "=m<>" (*addr) : "r" (val) : "memory"); \
162 mmiowb_set_pending(); \
163 }
164 #endif
165
166 DEF_MMIO_IN_D(in_8, 8, lbz);
167 DEF_MMIO_OUT_D(out_8, 8, stb);
168
169 #ifdef __BIG_ENDIAN__
170 DEF_MMIO_IN_D(in_be16, 16, lhz);
171 DEF_MMIO_IN_D(in_be32, 32, lwz);
172 DEF_MMIO_IN_X(in_le16, 16, lhbrx);
173 DEF_MMIO_IN_X(in_le32, 32, lwbrx);
174
175 DEF_MMIO_OUT_D(out_be16, 16, sth);
176 DEF_MMIO_OUT_D(out_be32, 32, stw);
177 DEF_MMIO_OUT_X(out_le16, 16, sthbrx);
178 DEF_MMIO_OUT_X(out_le32, 32, stwbrx);
179 #else
180 DEF_MMIO_IN_X(in_be16, 16, lhbrx);
181 DEF_MMIO_IN_X(in_be32, 32, lwbrx);
182 DEF_MMIO_IN_D(in_le16, 16, lhz);
183 DEF_MMIO_IN_D(in_le32, 32, lwz);
184
185 DEF_MMIO_OUT_X(out_be16, 16, sthbrx);
186 DEF_MMIO_OUT_X(out_be32, 32, stwbrx);
187 DEF_MMIO_OUT_D(out_le16, 16, sth);
188 DEF_MMIO_OUT_D(out_le32, 32, stw);
189
190 #endif /* __BIG_ENDIAN */
191
192 #ifdef __powerpc64__
193
194 #ifdef __BIG_ENDIAN__
195 DEF_MMIO_OUT_D(out_be64, 64, std);
196 DEF_MMIO_IN_D(in_be64, 64, ld);
197
198 /* There is no asm instructions for 64 bits reverse loads and stores */
in_le64(const volatile u64 __iomem * addr)199 static inline u64 in_le64(const volatile u64 __iomem *addr)
200 {
201 return swab64(in_be64(addr));
202 }
203
out_le64(volatile u64 __iomem * addr,u64 val)204 static inline void out_le64(volatile u64 __iomem *addr, u64 val)
205 {
206 out_be64(addr, swab64(val));
207 }
208 #else
209 DEF_MMIO_OUT_D(out_le64, 64, std);
210 DEF_MMIO_IN_D(in_le64, 64, ld);
211
212 /* There is no asm instructions for 64 bits reverse loads and stores */
in_be64(const volatile u64 __iomem * addr)213 static inline u64 in_be64(const volatile u64 __iomem *addr)
214 {
215 return swab64(in_le64(addr));
216 }
217
out_be64(volatile u64 __iomem * addr,u64 val)218 static inline void out_be64(volatile u64 __iomem *addr, u64 val)
219 {
220 out_le64(addr, swab64(val));
221 }
222
223 #endif
224 #endif /* __powerpc64__ */
225
226 /*
227 * Low level IO stream instructions are defined out of line for now
228 */
229 extern void _insb(const volatile u8 __iomem *addr, void *buf, long count);
230 extern void _outsb(volatile u8 __iomem *addr,const void *buf,long count);
231 extern void _insw_ns(const volatile u16 __iomem *addr, void *buf, long count);
232 extern void _outsw_ns(volatile u16 __iomem *addr, const void *buf, long count);
233 extern void _insl_ns(const volatile u32 __iomem *addr, void *buf, long count);
234 extern void _outsl_ns(volatile u32 __iomem *addr, const void *buf, long count);
235
236 /* The _ns naming is historical and will be removed. For now, just #define
237 * the non _ns equivalent names
238 */
239 #define _insw _insw_ns
240 #define _insl _insl_ns
241 #define _outsw _outsw_ns
242 #define _outsl _outsl_ns
243
244
245 /*
246 * memset_io, memcpy_toio, memcpy_fromio base implementations are out of line
247 */
248
249 extern void _memset_io(volatile void __iomem *addr, int c, unsigned long n);
250 extern void _memcpy_fromio(void *dest, const volatile void __iomem *src,
251 unsigned long n);
252 extern void _memcpy_toio(volatile void __iomem *dest, const void *src,
253 unsigned long n);
254
255 /*
256 *
257 * PCI and standard ISA accessors
258 *
259 * Those are globally defined linux accessors for devices on PCI or ISA
260 * busses. They follow the Linux defined semantics. The current implementation
261 * for PowerPC is as close as possible to the x86 version of these, and thus
262 * provides fairly heavy weight barriers for the non-raw versions
263 *
264 * In addition, they support a hook mechanism when CONFIG_PPC_INDIRECT_MMIO
265 * or CONFIG_PPC_INDIRECT_PIO are set allowing the platform to provide its
266 * own implementation of some or all of the accessors.
267 */
268
269 /*
270 * Include the EEH definitions when EEH is enabled only so they don't get
271 * in the way when building for 32 bits
272 */
273 #ifdef CONFIG_EEH
274 #include <asm/eeh.h>
275 #endif
276
277 /* Shortcut to the MMIO argument pointer */
278 #define PCI_IO_ADDR volatile void __iomem *
279
280 /* Indirect IO address tokens:
281 *
282 * When CONFIG_PPC_INDIRECT_MMIO is set, the platform can provide hooks
283 * on all MMIOs. (Note that this is all 64 bits only for now)
284 *
285 * To help platforms who may need to differentiate MMIO addresses in
286 * their hooks, a bitfield is reserved for use by the platform near the
287 * top of MMIO addresses (not PIO, those have to cope the hard way).
288 *
289 * The highest address in the kernel virtual space are:
290 *
291 * d0003fffffffffff # with Hash MMU
292 * c00fffffffffffff # with Radix MMU
293 *
294 * The top 4 bits are reserved as the region ID on hash, leaving us 8 bits
295 * that can be used for the field.
296 *
297 * The direct IO mapping operations will then mask off those bits
298 * before doing the actual access, though that only happen when
299 * CONFIG_PPC_INDIRECT_MMIO is set, thus be careful when you use that
300 * mechanism
301 *
302 * For PIO, there is a separate CONFIG_PPC_INDIRECT_PIO which makes
303 * all PIO functions call through a hook.
304 */
305
306 #ifdef CONFIG_PPC_INDIRECT_MMIO
307 #define PCI_IO_IND_TOKEN_SHIFT 52
308 #define PCI_IO_IND_TOKEN_MASK (0xfful << PCI_IO_IND_TOKEN_SHIFT)
309 #define PCI_FIX_ADDR(addr) \
310 ((PCI_IO_ADDR)(((unsigned long)(addr)) & ~PCI_IO_IND_TOKEN_MASK))
311 #define PCI_GET_ADDR_TOKEN(addr) \
312 (((unsigned long)(addr) & PCI_IO_IND_TOKEN_MASK) >> \
313 PCI_IO_IND_TOKEN_SHIFT)
314 #define PCI_SET_ADDR_TOKEN(addr, token) \
315 do { \
316 unsigned long __a = (unsigned long)(addr); \
317 __a &= ~PCI_IO_IND_TOKEN_MASK; \
318 __a |= ((unsigned long)(token)) << PCI_IO_IND_TOKEN_SHIFT; \
319 (addr) = (void __iomem *)__a; \
320 } while(0)
321 #else
322 #define PCI_FIX_ADDR(addr) (addr)
323 #endif
324
325
326 /*
327 * Non ordered and non-swapping "raw" accessors
328 */
329
__raw_readb(const volatile void __iomem * addr)330 static inline unsigned char __raw_readb(const volatile void __iomem *addr)
331 {
332 return *(volatile unsigned char __force *)PCI_FIX_ADDR(addr);
333 }
334 #define __raw_readb __raw_readb
335
__raw_readw(const volatile void __iomem * addr)336 static inline unsigned short __raw_readw(const volatile void __iomem *addr)
337 {
338 return *(volatile unsigned short __force *)PCI_FIX_ADDR(addr);
339 }
340 #define __raw_readw __raw_readw
341
__raw_readl(const volatile void __iomem * addr)342 static inline unsigned int __raw_readl(const volatile void __iomem *addr)
343 {
344 return *(volatile unsigned int __force *)PCI_FIX_ADDR(addr);
345 }
346 #define __raw_readl __raw_readl
347
__raw_writeb(unsigned char v,volatile void __iomem * addr)348 static inline void __raw_writeb(unsigned char v, volatile void __iomem *addr)
349 {
350 *(volatile unsigned char __force *)PCI_FIX_ADDR(addr) = v;
351 }
352 #define __raw_writeb __raw_writeb
353
__raw_writew(unsigned short v,volatile void __iomem * addr)354 static inline void __raw_writew(unsigned short v, volatile void __iomem *addr)
355 {
356 *(volatile unsigned short __force *)PCI_FIX_ADDR(addr) = v;
357 }
358 #define __raw_writew __raw_writew
359
__raw_writel(unsigned int v,volatile void __iomem * addr)360 static inline void __raw_writel(unsigned int v, volatile void __iomem *addr)
361 {
362 *(volatile unsigned int __force *)PCI_FIX_ADDR(addr) = v;
363 }
364 #define __raw_writel __raw_writel
365
366 #ifdef __powerpc64__
__raw_readq(const volatile void __iomem * addr)367 static inline unsigned long __raw_readq(const volatile void __iomem *addr)
368 {
369 return *(volatile unsigned long __force *)PCI_FIX_ADDR(addr);
370 }
371 #define __raw_readq __raw_readq
372
__raw_writeq(unsigned long v,volatile void __iomem * addr)373 static inline void __raw_writeq(unsigned long v, volatile void __iomem *addr)
374 {
375 *(volatile unsigned long __force *)PCI_FIX_ADDR(addr) = v;
376 }
377 #define __raw_writeq __raw_writeq
378
__raw_writeq_be(unsigned long v,volatile void __iomem * addr)379 static inline void __raw_writeq_be(unsigned long v, volatile void __iomem *addr)
380 {
381 __raw_writeq((__force unsigned long)cpu_to_be64(v), addr);
382 }
383 #define __raw_writeq_be __raw_writeq_be
384
385 /*
386 * Real mode versions of the above. Those instructions are only supposed
387 * to be used in hypervisor real mode as per the architecture spec.
388 */
__raw_rm_writeb(u8 val,volatile void __iomem * paddr)389 static inline void __raw_rm_writeb(u8 val, volatile void __iomem *paddr)
390 {
391 __asm__ __volatile__(".machine push; \
392 .machine power6; \
393 stbcix %0,0,%1; \
394 .machine pop;"
395 : : "r" (val), "r" (paddr) : "memory");
396 }
397
__raw_rm_writew(u16 val,volatile void __iomem * paddr)398 static inline void __raw_rm_writew(u16 val, volatile void __iomem *paddr)
399 {
400 __asm__ __volatile__(".machine push; \
401 .machine power6; \
402 sthcix %0,0,%1; \
403 .machine pop;"
404 : : "r" (val), "r" (paddr) : "memory");
405 }
406
__raw_rm_writel(u32 val,volatile void __iomem * paddr)407 static inline void __raw_rm_writel(u32 val, volatile void __iomem *paddr)
408 {
409 __asm__ __volatile__(".machine push; \
410 .machine power6; \
411 stwcix %0,0,%1; \
412 .machine pop;"
413 : : "r" (val), "r" (paddr) : "memory");
414 }
415
__raw_rm_writeq(u64 val,volatile void __iomem * paddr)416 static inline void __raw_rm_writeq(u64 val, volatile void __iomem *paddr)
417 {
418 __asm__ __volatile__(".machine push; \
419 .machine power6; \
420 stdcix %0,0,%1; \
421 .machine pop;"
422 : : "r" (val), "r" (paddr) : "memory");
423 }
424
__raw_rm_writeq_be(u64 val,volatile void __iomem * paddr)425 static inline void __raw_rm_writeq_be(u64 val, volatile void __iomem *paddr)
426 {
427 __raw_rm_writeq((__force u64)cpu_to_be64(val), paddr);
428 }
429
__raw_rm_readb(volatile void __iomem * paddr)430 static inline u8 __raw_rm_readb(volatile void __iomem *paddr)
431 {
432 u8 ret;
433 __asm__ __volatile__(".machine push; \
434 .machine power6; \
435 lbzcix %0,0, %1; \
436 .machine pop;"
437 : "=r" (ret) : "r" (paddr) : "memory");
438 return ret;
439 }
440
__raw_rm_readw(volatile void __iomem * paddr)441 static inline u16 __raw_rm_readw(volatile void __iomem *paddr)
442 {
443 u16 ret;
444 __asm__ __volatile__(".machine push; \
445 .machine power6; \
446 lhzcix %0,0, %1; \
447 .machine pop;"
448 : "=r" (ret) : "r" (paddr) : "memory");
449 return ret;
450 }
451
__raw_rm_readl(volatile void __iomem * paddr)452 static inline u32 __raw_rm_readl(volatile void __iomem *paddr)
453 {
454 u32 ret;
455 __asm__ __volatile__(".machine push; \
456 .machine power6; \
457 lwzcix %0,0, %1; \
458 .machine pop;"
459 : "=r" (ret) : "r" (paddr) : "memory");
460 return ret;
461 }
462
__raw_rm_readq(volatile void __iomem * paddr)463 static inline u64 __raw_rm_readq(volatile void __iomem *paddr)
464 {
465 u64 ret;
466 __asm__ __volatile__(".machine push; \
467 .machine power6; \
468 ldcix %0,0, %1; \
469 .machine pop;"
470 : "=r" (ret) : "r" (paddr) : "memory");
471 return ret;
472 }
473 #endif /* __powerpc64__ */
474
475 /*
476 *
477 * PCI PIO and MMIO accessors.
478 *
479 *
480 * On 32 bits, PIO operations have a recovery mechanism in case they trigger
481 * machine checks (which they occasionally do when probing non existing
482 * IO ports on some platforms, like PowerMac and 8xx).
483 * I always found it to be of dubious reliability and I am tempted to get
484 * rid of it one of these days. So if you think it's important to keep it,
485 * please voice up asap. We never had it for 64 bits and I do not intend
486 * to port it over
487 */
488
489 #ifdef CONFIG_PPC32
490
491 #define __do_in_asm(name, op) \
492 static inline unsigned int name(unsigned int port) \
493 { \
494 unsigned int x; \
495 __asm__ __volatile__( \
496 "sync\n" \
497 "0:" op " %0,0,%1\n" \
498 "1: twi 0,%0,0\n" \
499 "2: isync\n" \
500 "3: nop\n" \
501 "4:\n" \
502 ".section .fixup,\"ax\"\n" \
503 "5: li %0,-1\n" \
504 " b 4b\n" \
505 ".previous\n" \
506 EX_TABLE(0b, 5b) \
507 EX_TABLE(1b, 5b) \
508 EX_TABLE(2b, 5b) \
509 EX_TABLE(3b, 5b) \
510 : "=&r" (x) \
511 : "r" (port + _IO_BASE) \
512 : "memory"); \
513 return x; \
514 }
515
516 #define __do_out_asm(name, op) \
517 static inline void name(unsigned int val, unsigned int port) \
518 { \
519 __asm__ __volatile__( \
520 "sync\n" \
521 "0:" op " %0,0,%1\n" \
522 "1: sync\n" \
523 "2:\n" \
524 EX_TABLE(0b, 2b) \
525 EX_TABLE(1b, 2b) \
526 : : "r" (val), "r" (port + _IO_BASE) \
527 : "memory"); \
528 }
529
530 __do_in_asm(_rec_inb, "lbzx")
531 __do_in_asm(_rec_inw, "lhbrx")
532 __do_in_asm(_rec_inl, "lwbrx")
533 __do_out_asm(_rec_outb, "stbx")
534 __do_out_asm(_rec_outw, "sthbrx")
535 __do_out_asm(_rec_outl, "stwbrx")
536
537 #endif /* CONFIG_PPC32 */
538
539 /* The "__do_*" operations below provide the actual "base" implementation
540 * for each of the defined accessors. Some of them use the out_* functions
541 * directly, some of them still use EEH, though we might change that in the
542 * future. Those macros below provide the necessary argument swapping and
543 * handling of the IO base for PIO.
544 *
545 * They are themselves used by the macros that define the actual accessors
546 * and can be used by the hooks if any.
547 *
548 * Note that PIO operations are always defined in terms of their corresonding
549 * MMIO operations. That allows platforms like iSeries who want to modify the
550 * behaviour of both to only hook on the MMIO version and get both. It's also
551 * possible to hook directly at the toplevel PIO operation if they have to
552 * be handled differently
553 */
554 #define __do_writeb(val, addr) out_8(PCI_FIX_ADDR(addr), val)
555 #define __do_writew(val, addr) out_le16(PCI_FIX_ADDR(addr), val)
556 #define __do_writel(val, addr) out_le32(PCI_FIX_ADDR(addr), val)
557 #define __do_writeq(val, addr) out_le64(PCI_FIX_ADDR(addr), val)
558 #define __do_writew_be(val, addr) out_be16(PCI_FIX_ADDR(addr), val)
559 #define __do_writel_be(val, addr) out_be32(PCI_FIX_ADDR(addr), val)
560 #define __do_writeq_be(val, addr) out_be64(PCI_FIX_ADDR(addr), val)
561
562 #ifdef CONFIG_EEH
563 #define __do_readb(addr) eeh_readb(PCI_FIX_ADDR(addr))
564 #define __do_readw(addr) eeh_readw(PCI_FIX_ADDR(addr))
565 #define __do_readl(addr) eeh_readl(PCI_FIX_ADDR(addr))
566 #define __do_readq(addr) eeh_readq(PCI_FIX_ADDR(addr))
567 #define __do_readw_be(addr) eeh_readw_be(PCI_FIX_ADDR(addr))
568 #define __do_readl_be(addr) eeh_readl_be(PCI_FIX_ADDR(addr))
569 #define __do_readq_be(addr) eeh_readq_be(PCI_FIX_ADDR(addr))
570 #else /* CONFIG_EEH */
571 #define __do_readb(addr) in_8(PCI_FIX_ADDR(addr))
572 #define __do_readw(addr) in_le16(PCI_FIX_ADDR(addr))
573 #define __do_readl(addr) in_le32(PCI_FIX_ADDR(addr))
574 #define __do_readq(addr) in_le64(PCI_FIX_ADDR(addr))
575 #define __do_readw_be(addr) in_be16(PCI_FIX_ADDR(addr))
576 #define __do_readl_be(addr) in_be32(PCI_FIX_ADDR(addr))
577 #define __do_readq_be(addr) in_be64(PCI_FIX_ADDR(addr))
578 #endif /* !defined(CONFIG_EEH) */
579
580 #ifdef CONFIG_PPC32
581 #define __do_outb(val, port) _rec_outb(val, port)
582 #define __do_outw(val, port) _rec_outw(val, port)
583 #define __do_outl(val, port) _rec_outl(val, port)
584 #define __do_inb(port) _rec_inb(port)
585 #define __do_inw(port) _rec_inw(port)
586 #define __do_inl(port) _rec_inl(port)
587 #else /* CONFIG_PPC32 */
588 #define __do_outb(val, port) writeb(val,(PCI_IO_ADDR)(_IO_BASE+port));
589 #define __do_outw(val, port) writew(val,(PCI_IO_ADDR)(_IO_BASE+port));
590 #define __do_outl(val, port) writel(val,(PCI_IO_ADDR)(_IO_BASE+port));
591 #define __do_inb(port) readb((PCI_IO_ADDR)(_IO_BASE + port));
592 #define __do_inw(port) readw((PCI_IO_ADDR)(_IO_BASE + port));
593 #define __do_inl(port) readl((PCI_IO_ADDR)(_IO_BASE + port));
594 #endif /* !CONFIG_PPC32 */
595
596 #ifdef CONFIG_EEH
597 #define __do_readsb(a, b, n) eeh_readsb(PCI_FIX_ADDR(a), (b), (n))
598 #define __do_readsw(a, b, n) eeh_readsw(PCI_FIX_ADDR(a), (b), (n))
599 #define __do_readsl(a, b, n) eeh_readsl(PCI_FIX_ADDR(a), (b), (n))
600 #else /* CONFIG_EEH */
601 #define __do_readsb(a, b, n) _insb(PCI_FIX_ADDR(a), (b), (n))
602 #define __do_readsw(a, b, n) _insw(PCI_FIX_ADDR(a), (b), (n))
603 #define __do_readsl(a, b, n) _insl(PCI_FIX_ADDR(a), (b), (n))
604 #endif /* !CONFIG_EEH */
605 #define __do_writesb(a, b, n) _outsb(PCI_FIX_ADDR(a),(b),(n))
606 #define __do_writesw(a, b, n) _outsw(PCI_FIX_ADDR(a),(b),(n))
607 #define __do_writesl(a, b, n) _outsl(PCI_FIX_ADDR(a),(b),(n))
608
609 #define __do_insb(p, b, n) readsb((PCI_IO_ADDR)(_IO_BASE+(p)), (b), (n))
610 #define __do_insw(p, b, n) readsw((PCI_IO_ADDR)(_IO_BASE+(p)), (b), (n))
611 #define __do_insl(p, b, n) readsl((PCI_IO_ADDR)(_IO_BASE+(p)), (b), (n))
612 #define __do_outsb(p, b, n) writesb((PCI_IO_ADDR)(_IO_BASE+(p)),(b),(n))
613 #define __do_outsw(p, b, n) writesw((PCI_IO_ADDR)(_IO_BASE+(p)),(b),(n))
614 #define __do_outsl(p, b, n) writesl((PCI_IO_ADDR)(_IO_BASE+(p)),(b),(n))
615
616 #define __do_memset_io(addr, c, n) \
617 _memset_io(PCI_FIX_ADDR(addr), c, n)
618 #define __do_memcpy_toio(dst, src, n) \
619 _memcpy_toio(PCI_FIX_ADDR(dst), src, n)
620
621 #ifdef CONFIG_EEH
622 #define __do_memcpy_fromio(dst, src, n) \
623 eeh_memcpy_fromio(dst, PCI_FIX_ADDR(src), n)
624 #else /* CONFIG_EEH */
625 #define __do_memcpy_fromio(dst, src, n) \
626 _memcpy_fromio(dst,PCI_FIX_ADDR(src),n)
627 #endif /* !CONFIG_EEH */
628
629 #ifdef CONFIG_PPC_INDIRECT_PIO
630 #define DEF_PCI_HOOK_pio(x) x
631 #else
632 #define DEF_PCI_HOOK_pio(x) NULL
633 #endif
634
635 #ifdef CONFIG_PPC_INDIRECT_MMIO
636 #define DEF_PCI_HOOK_mem(x) x
637 #else
638 #define DEF_PCI_HOOK_mem(x) NULL
639 #endif
640
641 /* Structure containing all the hooks */
642 extern struct ppc_pci_io {
643
644 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) ret (*name) at;
645 #define DEF_PCI_AC_NORET(name, at, al, space, aa) void (*name) at;
646
647 #include <asm/io-defs.h>
648
649 #undef DEF_PCI_AC_RET
650 #undef DEF_PCI_AC_NORET
651
652 } ppc_pci_io;
653
654 /* The inline wrappers */
655 #define DEF_PCI_AC_RET(name, ret, at, al, space, aa) \
656 static inline ret name at \
657 { \
658 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
659 return ppc_pci_io.name al; \
660 return __do_##name al; \
661 }
662
663 #define DEF_PCI_AC_NORET(name, at, al, space, aa) \
664 static inline void name at \
665 { \
666 if (DEF_PCI_HOOK_##space(ppc_pci_io.name) != NULL) \
667 ppc_pci_io.name al; \
668 else \
669 __do_##name al; \
670 }
671
672 #include <asm/io-defs.h>
673
674 #undef DEF_PCI_AC_RET
675 #undef DEF_PCI_AC_NORET
676
677 /* Some drivers check for the presence of readq & writeq with
678 * a #ifdef, so we make them happy here.
679 */
680 #define readb readb
681 #define readw readw
682 #define readl readl
683 #define writeb writeb
684 #define writew writew
685 #define writel writel
686 #define readsb readsb
687 #define readsw readsw
688 #define readsl readsl
689 #define writesb writesb
690 #define writesw writesw
691 #define writesl writesl
692 #define inb inb
693 #define inw inw
694 #define inl inl
695 #define outb outb
696 #define outw outw
697 #define outl outl
698 #define insb insb
699 #define insw insw
700 #define insl insl
701 #define outsb outsb
702 #define outsw outsw
703 #define outsl outsl
704 #ifdef __powerpc64__
705 #define readq readq
706 #define writeq writeq
707 #endif
708 #define memset_io memset_io
709 #define memcpy_fromio memcpy_fromio
710 #define memcpy_toio memcpy_toio
711
712 /*
713 * We don't do relaxed operations yet, at least not with this semantic
714 */
715 #define readb_relaxed(addr) readb(addr)
716 #define readw_relaxed(addr) readw(addr)
717 #define readl_relaxed(addr) readl(addr)
718 #define readq_relaxed(addr) readq(addr)
719 #define writeb_relaxed(v, addr) writeb(v, addr)
720 #define writew_relaxed(v, addr) writew(v, addr)
721 #define writel_relaxed(v, addr) writel(v, addr)
722 #define writeq_relaxed(v, addr) writeq(v, addr)
723
724 #ifndef CONFIG_GENERIC_IOMAP
725 /*
726 * Here comes the implementation of the IOMAP interfaces.
727 */
ioread16be(const void __iomem * addr)728 static inline unsigned int ioread16be(const void __iomem *addr)
729 {
730 return readw_be(addr);
731 }
732 #define ioread16be ioread16be
733
ioread32be(const void __iomem * addr)734 static inline unsigned int ioread32be(const void __iomem *addr)
735 {
736 return readl_be(addr);
737 }
738 #define ioread32be ioread32be
739
740 #ifdef __powerpc64__
ioread64_lo_hi(const void __iomem * addr)741 static inline u64 ioread64_lo_hi(const void __iomem *addr)
742 {
743 return readq(addr);
744 }
745 #define ioread64_lo_hi ioread64_lo_hi
746
ioread64_hi_lo(const void __iomem * addr)747 static inline u64 ioread64_hi_lo(const void __iomem *addr)
748 {
749 return readq(addr);
750 }
751 #define ioread64_hi_lo ioread64_hi_lo
752
ioread64be(const void __iomem * addr)753 static inline u64 ioread64be(const void __iomem *addr)
754 {
755 return readq_be(addr);
756 }
757 #define ioread64be ioread64be
758
ioread64be_lo_hi(const void __iomem * addr)759 static inline u64 ioread64be_lo_hi(const void __iomem *addr)
760 {
761 return readq_be(addr);
762 }
763 #define ioread64be_lo_hi ioread64be_lo_hi
764
ioread64be_hi_lo(const void __iomem * addr)765 static inline u64 ioread64be_hi_lo(const void __iomem *addr)
766 {
767 return readq_be(addr);
768 }
769 #define ioread64be_hi_lo ioread64be_hi_lo
770 #endif /* __powerpc64__ */
771
iowrite16be(u16 val,void __iomem * addr)772 static inline void iowrite16be(u16 val, void __iomem *addr)
773 {
774 writew_be(val, addr);
775 }
776 #define iowrite16be iowrite16be
777
iowrite32be(u32 val,void __iomem * addr)778 static inline void iowrite32be(u32 val, void __iomem *addr)
779 {
780 writel_be(val, addr);
781 }
782 #define iowrite32be iowrite32be
783
784 #ifdef __powerpc64__
iowrite64_lo_hi(u64 val,void __iomem * addr)785 static inline void iowrite64_lo_hi(u64 val, void __iomem *addr)
786 {
787 writeq(val, addr);
788 }
789 #define iowrite64_lo_hi iowrite64_lo_hi
790
iowrite64_hi_lo(u64 val,void __iomem * addr)791 static inline void iowrite64_hi_lo(u64 val, void __iomem *addr)
792 {
793 writeq(val, addr);
794 }
795 #define iowrite64_hi_lo iowrite64_hi_lo
796
iowrite64be(u64 val,void __iomem * addr)797 static inline void iowrite64be(u64 val, void __iomem *addr)
798 {
799 writeq_be(val, addr);
800 }
801 #define iowrite64be iowrite64be
802
iowrite64be_lo_hi(u64 val,void __iomem * addr)803 static inline void iowrite64be_lo_hi(u64 val, void __iomem *addr)
804 {
805 writeq_be(val, addr);
806 }
807 #define iowrite64be_lo_hi iowrite64be_lo_hi
808
iowrite64be_hi_lo(u64 val,void __iomem * addr)809 static inline void iowrite64be_hi_lo(u64 val, void __iomem *addr)
810 {
811 writeq_be(val, addr);
812 }
813 #define iowrite64be_hi_lo iowrite64be_hi_lo
814 #endif /* __powerpc64__ */
815
816 struct pci_dev;
817 void pci_iounmap(struct pci_dev *dev, void __iomem *addr);
818 #define pci_iounmap pci_iounmap
819 void __iomem *ioport_map(unsigned long port, unsigned int len);
820 #define ioport_map ioport_map
821 #endif
822
iosync(void)823 static inline void iosync(void)
824 {
825 __asm__ __volatile__ ("sync" : : : "memory");
826 }
827
828 /* Enforce in-order execution of data I/O.
829 * No distinction between read/write on PPC; use eieio for all three.
830 * Those are fairly week though. They don't provide a barrier between
831 * MMIO and cacheable storage nor do they provide a barrier vs. locks,
832 * they only provide barriers between 2 __raw MMIO operations and
833 * possibly break write combining.
834 */
835 #define iobarrier_rw() eieio()
836 #define iobarrier_r() eieio()
837 #define iobarrier_w() eieio()
838
839
840 /*
841 * output pause versions need a delay at least for the
842 * w83c105 ide controller in a p610.
843 */
844 #define inb_p(port) inb(port)
845 #define outb_p(val, port) (udelay(1), outb((val), (port)))
846 #define inw_p(port) inw(port)
847 #define outw_p(val, port) (udelay(1), outw((val), (port)))
848 #define inl_p(port) inl(port)
849 #define outl_p(val, port) (udelay(1), outl((val), (port)))
850
851
852 #define IO_SPACE_LIMIT ~(0UL)
853
854 /**
855 * ioremap - map bus memory into CPU space
856 * @address: bus address of the memory
857 * @size: size of the resource to map
858 *
859 * ioremap performs a platform specific sequence of operations to
860 * make bus memory CPU accessible via the readb/readw/readl/writeb/
861 * writew/writel functions and the other mmio helpers. The returned
862 * address is not guaranteed to be usable directly as a virtual
863 * address.
864 *
865 * We provide a few variations of it:
866 *
867 * * ioremap is the standard one and provides non-cacheable guarded mappings
868 * and can be hooked by the platform via ppc_md
869 *
870 * * ioremap_prot allows to specify the page flags as an argument and can
871 * also be hooked by the platform via ppc_md.
872 *
873 * * ioremap_wc enables write combining
874 *
875 * * ioremap_wt enables write through
876 *
877 * * ioremap_coherent maps coherent cached memory
878 *
879 * * iounmap undoes such a mapping and can be hooked
880 *
881 * * __ioremap_caller is the same as above but takes an explicit caller
882 * reference rather than using __builtin_return_address(0)
883 *
884 */
885 extern void __iomem *ioremap(phys_addr_t address, unsigned long size);
886 #define ioremap ioremap
887 #define ioremap_prot ioremap_prot
888 extern void __iomem *ioremap_wc(phys_addr_t address, unsigned long size);
889 #define ioremap_wc ioremap_wc
890
891 #ifdef CONFIG_PPC32
892 void __iomem *ioremap_wt(phys_addr_t address, unsigned long size);
893 #define ioremap_wt ioremap_wt
894 #endif
895
896 void __iomem *ioremap_coherent(phys_addr_t address, unsigned long size);
897 #define ioremap_cache(addr, size) \
898 ioremap_prot((addr), (size), pgprot_val(PAGE_KERNEL))
899
900 #define iounmap iounmap
901
902 void __iomem *ioremap_phb(phys_addr_t paddr, unsigned long size);
903
904 int early_ioremap_range(unsigned long ea, phys_addr_t pa,
905 unsigned long size, pgprot_t prot);
906
907 extern void __iomem *__ioremap_caller(phys_addr_t, unsigned long size,
908 pgprot_t prot, void *caller);
909
910 /*
911 * When CONFIG_PPC_INDIRECT_PIO is set, we use the generic iomap implementation
912 * which needs some additional definitions here. They basically allow PIO
913 * space overall to be 1GB. This will work as long as we never try to use
914 * iomap to map MMIO below 1GB which should be fine on ppc64
915 */
916 #define HAVE_ARCH_PIO_SIZE 1
917 #define PIO_OFFSET 0x00000000UL
918 #define PIO_MASK (FULL_IO_SIZE - 1)
919 #define PIO_RESERVED (FULL_IO_SIZE)
920
921 #define mmio_read16be(addr) readw_be(addr)
922 #define mmio_read32be(addr) readl_be(addr)
923 #define mmio_read64be(addr) readq_be(addr)
924 #define mmio_write16be(val, addr) writew_be(val, addr)
925 #define mmio_write32be(val, addr) writel_be(val, addr)
926 #define mmio_write64be(val, addr) writeq_be(val, addr)
927 #define mmio_insb(addr, dst, count) readsb(addr, dst, count)
928 #define mmio_insw(addr, dst, count) readsw(addr, dst, count)
929 #define mmio_insl(addr, dst, count) readsl(addr, dst, count)
930 #define mmio_outsb(addr, src, count) writesb(addr, src, count)
931 #define mmio_outsw(addr, src, count) writesw(addr, src, count)
932 #define mmio_outsl(addr, src, count) writesl(addr, src, count)
933
934 /**
935 * virt_to_phys - map virtual addresses to physical
936 * @address: address to remap
937 *
938 * The returned physical address is the physical (CPU) mapping for
939 * the memory address given. It is only valid to use this function on
940 * addresses directly mapped or allocated via kmalloc.
941 *
942 * This function does not give bus mappings for DMA transfers. In
943 * almost all conceivable cases a device driver should not be using
944 * this function
945 */
virt_to_phys(const volatile void * address)946 static inline unsigned long virt_to_phys(const volatile void * address)
947 {
948 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !virt_addr_valid(address));
949
950 return __pa((unsigned long)address);
951 }
952 #define virt_to_phys virt_to_phys
953
954 /**
955 * phys_to_virt - map physical address to virtual
956 * @address: address to remap
957 *
958 * The returned virtual address is a current CPU mapping for
959 * the memory address given. It is only valid to use this function on
960 * addresses that have a kernel mapping
961 *
962 * This function does not handle bus mappings for DMA transfers. In
963 * almost all conceivable cases a device driver should not be using
964 * this function
965 */
phys_to_virt(unsigned long address)966 static inline void * phys_to_virt(unsigned long address)
967 {
968 return (void *)__va(address);
969 }
970 #define phys_to_virt phys_to_virt
971
972 /*
973 * Change "struct page" to physical address.
974 */
page_to_phys(struct page * page)975 static inline phys_addr_t page_to_phys(struct page *page)
976 {
977 unsigned long pfn = page_to_pfn(page);
978
979 WARN_ON(IS_ENABLED(CONFIG_DEBUG_VIRTUAL) && !pfn_valid(pfn));
980
981 return PFN_PHYS(pfn);
982 }
983
984 /*
985 * 32 bits still uses virt_to_bus() for its implementation of DMA
986 * mappings se we have to keep it defined here. We also have some old
987 * drivers (shame shame shame) that use bus_to_virt() and haven't been
988 * fixed yet so I need to define it here.
989 */
990 #ifdef CONFIG_PPC32
991
virt_to_bus(volatile void * address)992 static inline unsigned long virt_to_bus(volatile void * address)
993 {
994 if (address == NULL)
995 return 0;
996 return __pa(address) + PCI_DRAM_OFFSET;
997 }
998 #define virt_to_bus virt_to_bus
999
bus_to_virt(unsigned long address)1000 static inline void * bus_to_virt(unsigned long address)
1001 {
1002 if (address == 0)
1003 return NULL;
1004 return __va(address - PCI_DRAM_OFFSET);
1005 }
1006 #define bus_to_virt bus_to_virt
1007
1008 #endif /* CONFIG_PPC32 */
1009
1010 /* access ports */
1011 #define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v))
1012 #define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v))
1013
1014 #define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v))
1015 #define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v))
1016
1017 #define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v))
1018 #define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v))
1019
1020 /* Clear and set bits in one shot. These macros can be used to clear and
1021 * set multiple bits in a register using a single read-modify-write. These
1022 * macros can also be used to set a multiple-bit bit pattern using a mask,
1023 * by specifying the mask in the 'clear' parameter and the new bit pattern
1024 * in the 'set' parameter.
1025 */
1026
1027 #define clrsetbits(type, addr, clear, set) \
1028 out_##type((addr), (in_##type(addr) & ~(clear)) | (set))
1029
1030 #ifdef __powerpc64__
1031 #define clrsetbits_be64(addr, clear, set) clrsetbits(be64, addr, clear, set)
1032 #define clrsetbits_le64(addr, clear, set) clrsetbits(le64, addr, clear, set)
1033 #endif
1034
1035 #define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set)
1036 #define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set)
1037
1038 #define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set)
1039 #define clrsetbits_le16(addr, clear, set) clrsetbits(le16, addr, clear, set)
1040
1041 #define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set)
1042
1043 #include <asm-generic/io.h>
1044
1045 #endif /* __KERNEL__ */
1046
1047 #endif /* _ASM_POWERPC_IO_H */
1048