1 /* 2 * Copyright © 2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/string_helpers.h> 26 27 #include <drm/drm_print.h> 28 #include <drm/intel/i915_pciids.h> 29 30 #include "gt/intel_gt_regs.h" 31 #include "i915_drv.h" 32 #include "i915_reg.h" 33 #include "i915_utils.h" 34 #include "intel_device_info.h" 35 36 #define PLATFORM_NAME(x) [INTEL_##x] = #x 37 static const char * const platform_names[] = { 38 PLATFORM_NAME(I830), 39 PLATFORM_NAME(I845G), 40 PLATFORM_NAME(I85X), 41 PLATFORM_NAME(I865G), 42 PLATFORM_NAME(I915G), 43 PLATFORM_NAME(I915GM), 44 PLATFORM_NAME(I945G), 45 PLATFORM_NAME(I945GM), 46 PLATFORM_NAME(G33), 47 PLATFORM_NAME(PINEVIEW), 48 PLATFORM_NAME(I965G), 49 PLATFORM_NAME(I965GM), 50 PLATFORM_NAME(G45), 51 PLATFORM_NAME(GM45), 52 PLATFORM_NAME(IRONLAKE), 53 PLATFORM_NAME(SANDYBRIDGE), 54 PLATFORM_NAME(IVYBRIDGE), 55 PLATFORM_NAME(VALLEYVIEW), 56 PLATFORM_NAME(HASWELL), 57 PLATFORM_NAME(BROADWELL), 58 PLATFORM_NAME(CHERRYVIEW), 59 PLATFORM_NAME(SKYLAKE), 60 PLATFORM_NAME(BROXTON), 61 PLATFORM_NAME(KABYLAKE), 62 PLATFORM_NAME(GEMINILAKE), 63 PLATFORM_NAME(COFFEELAKE), 64 PLATFORM_NAME(COMETLAKE), 65 PLATFORM_NAME(ICELAKE), 66 PLATFORM_NAME(ELKHARTLAKE), 67 PLATFORM_NAME(JASPERLAKE), 68 PLATFORM_NAME(TIGERLAKE), 69 PLATFORM_NAME(ROCKETLAKE), 70 PLATFORM_NAME(DG1), 71 PLATFORM_NAME(ALDERLAKE_S), 72 PLATFORM_NAME(ALDERLAKE_P), 73 PLATFORM_NAME(DG2), 74 PLATFORM_NAME(METEORLAKE), 75 }; 76 #undef PLATFORM_NAME 77 intel_platform_name(enum intel_platform platform)78 const char *intel_platform_name(enum intel_platform platform) 79 { 80 BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS); 81 82 if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) || 83 platform_names[platform] == NULL)) 84 return "<unknown>"; 85 86 return platform_names[platform]; 87 } 88 intel_device_info_print(const struct intel_device_info * info,const struct intel_runtime_info * runtime,struct drm_printer * p)89 void intel_device_info_print(const struct intel_device_info *info, 90 const struct intel_runtime_info *runtime, 91 struct drm_printer *p) 92 { 93 if (runtime->graphics.ip.rel) 94 drm_printf(p, "graphics version: %u.%02u\n", 95 runtime->graphics.ip.ver, 96 runtime->graphics.ip.rel); 97 else 98 drm_printf(p, "graphics version: %u\n", 99 runtime->graphics.ip.ver); 100 101 if (runtime->media.ip.rel) 102 drm_printf(p, "media version: %u.%02u\n", 103 runtime->media.ip.ver, 104 runtime->media.ip.rel); 105 else 106 drm_printf(p, "media version: %u\n", 107 runtime->media.ip.ver); 108 109 drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step)); 110 drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step)); 111 112 drm_printf(p, "gt: %d\n", info->gt); 113 drm_printf(p, "memory-regions: 0x%x\n", info->memory_regions); 114 drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes); 115 drm_printf(p, "platform: %s\n", intel_platform_name(info->platform)); 116 drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size); 117 drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type); 118 drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size); 119 120 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name)) 121 DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG); 122 #undef PRINT_FLAG 123 124 drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu)); 125 } 126 127 #define ID(id) (id) 128 129 static const u16 subplatform_ult_ids[] = { 130 INTEL_HSW_ULT_GT1_IDS(ID), 131 INTEL_HSW_ULT_GT2_IDS(ID), 132 INTEL_HSW_ULT_GT3_IDS(ID), 133 INTEL_BDW_ULT_GT1_IDS(ID), 134 INTEL_BDW_ULT_GT2_IDS(ID), 135 INTEL_BDW_ULT_GT3_IDS(ID), 136 INTEL_BDW_ULT_RSVD_IDS(ID), 137 INTEL_SKL_ULT_GT1_IDS(ID), 138 INTEL_SKL_ULT_GT2_IDS(ID), 139 INTEL_SKL_ULT_GT3_IDS(ID), 140 INTEL_KBL_ULT_GT1_IDS(ID), 141 INTEL_KBL_ULT_GT2_IDS(ID), 142 INTEL_KBL_ULT_GT3_IDS(ID), 143 INTEL_CFL_U_GT2_IDS(ID), 144 INTEL_CFL_U_GT3_IDS(ID), 145 INTEL_WHL_U_GT1_IDS(ID), 146 INTEL_WHL_U_GT2_IDS(ID), 147 INTEL_WHL_U_GT3_IDS(ID), 148 INTEL_CML_U_GT1_IDS(ID), 149 INTEL_CML_U_GT2_IDS(ID), 150 }; 151 152 static const u16 subplatform_ulx_ids[] = { 153 INTEL_HSW_ULX_GT1_IDS(ID), 154 INTEL_HSW_ULX_GT2_IDS(ID), 155 INTEL_BDW_ULX_GT1_IDS(ID), 156 INTEL_BDW_ULX_GT2_IDS(ID), 157 INTEL_BDW_ULX_GT3_IDS(ID), 158 INTEL_BDW_ULX_RSVD_IDS(ID), 159 INTEL_SKL_ULX_GT1_IDS(ID), 160 INTEL_SKL_ULX_GT2_IDS(ID), 161 INTEL_KBL_ULX_GT1_IDS(ID), 162 INTEL_KBL_ULX_GT2_IDS(ID), 163 INTEL_AML_KBL_GT2_IDS(ID), 164 INTEL_AML_CFL_GT2_IDS(ID), 165 }; 166 167 static const u16 subplatform_portf_ids[] = { 168 INTEL_ICL_PORT_F_IDS(ID), 169 }; 170 171 static const u16 subplatform_uy_ids[] = { 172 INTEL_TGL_GT2_IDS(ID), 173 }; 174 175 static const u16 subplatform_n_ids[] = { 176 INTEL_ADLN_IDS(ID), 177 }; 178 179 static const u16 subplatform_rpl_ids[] = { 180 INTEL_RPLS_IDS(ID), 181 INTEL_RPLU_IDS(ID), 182 INTEL_RPLP_IDS(ID), 183 }; 184 185 static const u16 subplatform_rplu_ids[] = { 186 INTEL_RPLU_IDS(ID), 187 }; 188 189 static const u16 subplatform_g10_ids[] = { 190 INTEL_DG2_G10_IDS(ID), 191 INTEL_ATS_M150_IDS(ID), 192 }; 193 194 static const u16 subplatform_g11_ids[] = { 195 INTEL_DG2_G11_IDS(ID), 196 INTEL_ATS_M75_IDS(ID), 197 }; 198 199 static const u16 subplatform_g12_ids[] = { 200 INTEL_DG2_G12_IDS(ID), 201 }; 202 203 static const u16 subplatform_arl_h_ids[] = { 204 INTEL_ARL_H_IDS(ID), 205 }; 206 207 static const u16 subplatform_arl_u_ids[] = { 208 INTEL_ARL_U_IDS(ID), 209 }; 210 211 static const u16 subplatform_arl_s_ids[] = { 212 INTEL_ARL_S_IDS(ID), 213 }; 214 find_devid(u16 id,const u16 * p,unsigned int num)215 static bool find_devid(u16 id, const u16 *p, unsigned int num) 216 { 217 for (; num; num--, p++) { 218 if (*p == id) 219 return true; 220 } 221 222 return false; 223 } 224 intel_device_info_subplatform_init(struct drm_i915_private * i915)225 static void intel_device_info_subplatform_init(struct drm_i915_private *i915) 226 { 227 const struct intel_device_info *info = INTEL_INFO(i915); 228 const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915); 229 const unsigned int pi = __platform_mask_index(rinfo, info->platform); 230 const unsigned int pb = __platform_mask_bit(rinfo, info->platform); 231 u16 devid = INTEL_DEVID(i915); 232 u32 mask = 0; 233 234 /* Make sure IS_<platform> checks are working. */ 235 RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb); 236 237 /* Find and mark subplatform bits based on the PCI device id. */ 238 if (find_devid(devid, subplatform_ult_ids, 239 ARRAY_SIZE(subplatform_ult_ids))) { 240 mask = BIT(INTEL_SUBPLATFORM_ULT); 241 } else if (find_devid(devid, subplatform_ulx_ids, 242 ARRAY_SIZE(subplatform_ulx_ids))) { 243 mask = BIT(INTEL_SUBPLATFORM_ULX); 244 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) { 245 /* ULX machines are also considered ULT. */ 246 mask |= BIT(INTEL_SUBPLATFORM_ULT); 247 } 248 } else if (find_devid(devid, subplatform_portf_ids, 249 ARRAY_SIZE(subplatform_portf_ids))) { 250 mask = BIT(INTEL_SUBPLATFORM_PORTF); 251 } else if (find_devid(devid, subplatform_uy_ids, 252 ARRAY_SIZE(subplatform_uy_ids))) { 253 mask = BIT(INTEL_SUBPLATFORM_UY); 254 } else if (find_devid(devid, subplatform_n_ids, 255 ARRAY_SIZE(subplatform_n_ids))) { 256 mask = BIT(INTEL_SUBPLATFORM_N); 257 } else if (find_devid(devid, subplatform_rpl_ids, 258 ARRAY_SIZE(subplatform_rpl_ids))) { 259 mask = BIT(INTEL_SUBPLATFORM_RPL); 260 if (find_devid(devid, subplatform_rplu_ids, 261 ARRAY_SIZE(subplatform_rplu_ids))) 262 mask |= BIT(INTEL_SUBPLATFORM_RPLU); 263 } else if (find_devid(devid, subplatform_g10_ids, 264 ARRAY_SIZE(subplatform_g10_ids))) { 265 mask = BIT(INTEL_SUBPLATFORM_G10); 266 } else if (find_devid(devid, subplatform_g11_ids, 267 ARRAY_SIZE(subplatform_g11_ids))) { 268 mask = BIT(INTEL_SUBPLATFORM_G11); 269 } else if (find_devid(devid, subplatform_g12_ids, 270 ARRAY_SIZE(subplatform_g12_ids))) { 271 mask = BIT(INTEL_SUBPLATFORM_G12); 272 } else if (find_devid(devid, subplatform_arl_h_ids, 273 ARRAY_SIZE(subplatform_arl_h_ids))) { 274 mask = BIT(INTEL_SUBPLATFORM_ARL_H); 275 } else if (find_devid(devid, subplatform_arl_u_ids, 276 ARRAY_SIZE(subplatform_arl_u_ids))) { 277 mask = BIT(INTEL_SUBPLATFORM_ARL_U); 278 } else if (find_devid(devid, subplatform_arl_s_ids, 279 ARRAY_SIZE(subplatform_arl_s_ids))) { 280 mask = BIT(INTEL_SUBPLATFORM_ARL_S); 281 } 282 283 GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK); 284 285 RUNTIME_INFO(i915)->platform_mask[pi] |= mask; 286 } 287 ip_ver_read(struct drm_i915_private * i915,u32 offset,struct intel_ip_version * ip)288 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip) 289 { 290 struct pci_dev *pdev = to_pci_dev(i915->drm.dev); 291 void __iomem *addr; 292 u32 val; 293 u8 expected_ver = ip->ver; 294 u8 expected_rel = ip->rel; 295 296 addr = pci_iomap_range(pdev, 0, offset, sizeof(u32)); 297 if (drm_WARN_ON(&i915->drm, !addr)) 298 return; 299 300 val = ioread32(addr); 301 pci_iounmap(pdev, addr); 302 303 ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val); 304 ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val); 305 ip->step = REG_FIELD_GET(GMD_ID_STEP, val); 306 307 /* Sanity check against expected versions from device info */ 308 if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel)) 309 drm_dbg(&i915->drm, 310 "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n", 311 ip->ver, ip->rel, offset, val, expected_ver, expected_rel); 312 } 313 314 /* 315 * Setup the graphics version for the current device. This must be done before 316 * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this 317 * function should be called very early in the driver initialization sequence. 318 * 319 * Regular MMIO access is not yet setup at the point this function is called so 320 * we peek at the appropriate MMIO offset directly. The GMD_ID register is 321 * part of an 'always on' power well by design, so we don't need to worry about 322 * forcewake while reading it. 323 */ intel_ipver_early_init(struct drm_i915_private * i915)324 static void intel_ipver_early_init(struct drm_i915_private *i915) 325 { 326 struct intel_runtime_info *runtime = RUNTIME_INFO(i915); 327 328 if (!HAS_GMD_ID(i915)) { 329 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12); 330 /* 331 * On older platforms, graphics and media share the same ip 332 * version and release. 333 */ 334 RUNTIME_INFO(i915)->media.ip = 335 RUNTIME_INFO(i915)->graphics.ip; 336 return; 337 } 338 339 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS), 340 &runtime->graphics.ip); 341 /* Wa_22012778468 */ 342 if (runtime->graphics.ip.ver == 0x0 && 343 INTEL_INFO(i915)->platform == INTEL_METEORLAKE) { 344 RUNTIME_INFO(i915)->graphics.ip.ver = 12; 345 RUNTIME_INFO(i915)->graphics.ip.rel = 70; 346 } 347 ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA), 348 &runtime->media.ip); 349 } 350 351 /** 352 * intel_device_info_runtime_init_early - initialize early runtime info 353 * @i915: the i915 device 354 * 355 * Determine early intel_device_info fields at runtime. This function needs 356 * to be called before the MMIO has been setup. 357 */ intel_device_info_runtime_init_early(struct drm_i915_private * i915)358 void intel_device_info_runtime_init_early(struct drm_i915_private *i915) 359 { 360 intel_ipver_early_init(i915); 361 intel_device_info_subplatform_init(i915); 362 } 363 364 /** 365 * intel_device_info_runtime_init - initialize runtime info 366 * @dev_priv: the i915 device 367 * 368 * Determine various intel_device_info fields at runtime. 369 * 370 * Use it when either: 371 * - it's judged too laborious to fill n static structures with the limit 372 * when a simple if statement does the job, 373 * - run-time checks (eg read fuse/strap registers) are needed. 374 * 375 * This function needs to be called: 376 * - after the MMIO has been setup as we are reading registers, 377 * - after the PCH has been detected, 378 * - before the first usage of the fields it can tweak. 379 */ intel_device_info_runtime_init(struct drm_i915_private * dev_priv)380 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv) 381 { 382 struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv); 383 384 BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES); 385 386 if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) { 387 drm_info(&dev_priv->drm, 388 "Disabling ppGTT for VT-d support\n"); 389 runtime->ppgtt_type = INTEL_PPGTT_NONE; 390 } 391 } 392 393 /* 394 * Set up device info and initial runtime info at driver create. 395 * 396 * Note: i915 is only an allocated blob of memory at this point. 397 */ intel_device_info_driver_create(struct drm_i915_private * i915,u16 device_id,const struct intel_device_info * match_info)398 void intel_device_info_driver_create(struct drm_i915_private *i915, 399 u16 device_id, 400 const struct intel_device_info *match_info) 401 { 402 struct intel_runtime_info *runtime; 403 404 /* Setup INTEL_INFO() */ 405 i915->__info = match_info; 406 407 /* Initialize initial runtime info from static const data and pdev. */ 408 runtime = RUNTIME_INFO(i915); 409 memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime)); 410 411 runtime->device_id = device_id; 412 } 413 intel_driver_caps_print(const struct intel_driver_caps * caps,struct drm_printer * p)414 void intel_driver_caps_print(const struct intel_driver_caps *caps, 415 struct drm_printer *p) 416 { 417 drm_printf(p, "Has logical contexts? %s\n", 418 str_yes_no(caps->has_logical_contexts)); 419 drm_printf(p, "scheduler: 0x%x\n", caps->scheduler); 420 } 421