1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/pci.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ih.h"
28
29 #include "oss/osssys_7_0_0_offset.h"
30 #include "oss/osssys_7_0_0_sh_mask.h"
31
32 #include "soc15_common.h"
33 #include "ih_v7_0.h"
34
35 #define MAX_REARM_RETRY 10
36
37 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev);
38
39 /**
40 * ih_v7_0_init_register_offset - Initialize register offset for ih rings
41 *
42 * @adev: amdgpu_device pointer
43 *
44 * Initialize register offset ih rings (IH_V7_0).
45 */
ih_v7_0_init_register_offset(struct amdgpu_device * adev)46 static void ih_v7_0_init_register_offset(struct amdgpu_device *adev)
47 {
48 struct amdgpu_ih_regs *ih_regs;
49
50 /* ih ring 2 is removed
51 * ih ring and ih ring 1 are available */
52 if (adev->irq.ih.ring_size) {
53 ih_regs = &adev->irq.ih.ih_regs;
54 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE);
55 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI);
56 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL);
57 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR);
58 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR);
59 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR);
60 ih_regs->ih_rb_wptr_addr_lo = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_LO);
61 ih_regs->ih_rb_wptr_addr_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_ADDR_HI);
62 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL;
63 }
64
65 if (adev->irq.ih1.ring_size) {
66 ih_regs = &adev->irq.ih1.ih_regs;
67 ih_regs->ih_rb_base = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_RING1);
68 ih_regs->ih_rb_base_hi = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_BASE_HI_RING1);
69 ih_regs->ih_rb_cntl = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_CNTL_RING1);
70 ih_regs->ih_rb_wptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_WPTR_RING1);
71 ih_regs->ih_rb_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_RB_RPTR_RING1);
72 ih_regs->ih_doorbell_rptr = SOC15_REG_OFFSET(OSSSYS, 0, regIH_DOORBELL_RPTR_RING1);
73 ih_regs->psp_reg_id = PSP_REG_IH_RB_CNTL_RING1;
74 }
75 }
76
77 /**
78 * force_update_wptr_for_self_int - Force update the wptr for self interrupt
79 *
80 * @adev: amdgpu_device pointer
81 * @threshold: threshold to trigger the wptr reporting
82 * @timeout: timeout to trigger the wptr reporting
83 * @enabled: Enable/disable timeout flush mechanism
84 *
85 * threshold input range: 0 ~ 15, default 0,
86 * real_threshold = 2^threshold
87 * timeout input range: 0 ~ 20, default 8,
88 * real_timeout = (2^timeout) * 1024 / (socclk_freq)
89 *
90 * Force update wptr for self interrupt ( >= SIENNA_CICHLID).
91 */
92 static void
force_update_wptr_for_self_int(struct amdgpu_device * adev,u32 threshold,u32 timeout,bool enabled)93 force_update_wptr_for_self_int(struct amdgpu_device *adev,
94 u32 threshold, u32 timeout, bool enabled)
95 {
96 u32 ih_cntl, ih_rb_cntl;
97
98 ih_cntl = RREG32_SOC15(OSSSYS, 0, regIH_CNTL2);
99 ih_rb_cntl = RREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1);
100
101 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
102 SELF_IV_FORCE_WPTR_UPDATE_TIMEOUT, timeout);
103 ih_cntl = REG_SET_FIELD(ih_cntl, IH_CNTL2,
104 SELF_IV_FORCE_WPTR_UPDATE_ENABLE, enabled);
105 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL_RING1,
106 RB_USED_INT_THRESHOLD, threshold);
107
108 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
109 if (psp_reg_program(&adev->psp, PSP_REG_IH_RB_CNTL_RING1, ih_rb_cntl))
110 return;
111 } else {
112 WREG32_SOC15(OSSSYS, 0, regIH_RB_CNTL_RING1, ih_rb_cntl);
113 }
114
115 WREG32_SOC15(OSSSYS, 0, regIH_CNTL2, ih_cntl);
116 }
117
118 /**
119 * ih_v7_0_toggle_ring_interrupts - toggle the interrupt ring buffer
120 *
121 * @adev: amdgpu_device pointer
122 * @ih: amdgpu_ih_ring pointet
123 * @enable: true - enable the interrupts, false - disable the interrupts
124 *
125 * Toggle the interrupt ring buffer (IH_V7_0)
126 */
ih_v7_0_toggle_ring_interrupts(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih,bool enable)127 static int ih_v7_0_toggle_ring_interrupts(struct amdgpu_device *adev,
128 struct amdgpu_ih_ring *ih,
129 bool enable)
130 {
131 struct amdgpu_ih_regs *ih_regs;
132 uint32_t tmp;
133
134 ih_regs = &ih->ih_regs;
135
136 tmp = RREG32(ih_regs->ih_rb_cntl);
137 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_ENABLE, (enable ? 1 : 0));
138 /* enable_intr field is only valid in ring0 */
139 if (ih == &adev->irq.ih)
140 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, ENABLE_INTR, (enable ? 1 : 0));
141
142 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
143 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp))
144 return -ETIMEDOUT;
145 } else {
146 WREG32(ih_regs->ih_rb_cntl, tmp);
147 }
148
149 if (enable) {
150 ih->enabled = true;
151 } else {
152 /* set rptr, wptr to 0 */
153 WREG32(ih_regs->ih_rb_rptr, 0);
154 WREG32(ih_regs->ih_rb_wptr, 0);
155 ih->enabled = false;
156 ih->rptr = 0;
157 }
158
159 return 0;
160 }
161
162 /**
163 * ih_v7_0_toggle_interrupts - Toggle all the available interrupt ring buffers
164 *
165 * @adev: amdgpu_device pointer
166 * @enable: enable or disable interrupt ring buffers
167 *
168 * Toggle all the available interrupt ring buffers (IH_V7_0).
169 */
ih_v7_0_toggle_interrupts(struct amdgpu_device * adev,bool enable)170 static int ih_v7_0_toggle_interrupts(struct amdgpu_device *adev, bool enable)
171 {
172 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
173 int i;
174 int r;
175
176 for (i = 0; i < ARRAY_SIZE(ih); i++) {
177 if (ih[i]->ring_size) {
178 r = ih_v7_0_toggle_ring_interrupts(adev, ih[i], enable);
179 if (r)
180 return r;
181 }
182 }
183
184 return 0;
185 }
186
ih_v7_0_rb_cntl(struct amdgpu_ih_ring * ih,uint32_t ih_rb_cntl)187 static uint32_t ih_v7_0_rb_cntl(struct amdgpu_ih_ring *ih, uint32_t ih_rb_cntl)
188 {
189 int rb_bufsz = order_base_2(ih->ring_size / 4);
190
191 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
192 MC_SPACE, ih->use_bus_addr ? 2 : 4);
193 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
194 WPTR_OVERFLOW_CLEAR, 1);
195 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
196 WPTR_OVERFLOW_ENABLE, 1);
197 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, RB_SIZE, rb_bufsz);
198 /* Ring Buffer write pointer writeback. If enabled, IH_RB_WPTR register
199 * value is written to memory
200 */
201 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL,
202 WPTR_WRITEBACK_ENABLE, 1);
203 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_SNOOP, 1);
204 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_RO, 0);
205 ih_rb_cntl = REG_SET_FIELD(ih_rb_cntl, IH_RB_CNTL, MC_VMID, 0);
206
207 return ih_rb_cntl;
208 }
209
ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring * ih)210 static uint32_t ih_v7_0_doorbell_rptr(struct amdgpu_ih_ring *ih)
211 {
212 u32 ih_doorbell_rtpr = 0;
213
214 if (ih->use_doorbell) {
215 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
216 IH_DOORBELL_RPTR, OFFSET,
217 ih->doorbell_index);
218 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
219 IH_DOORBELL_RPTR,
220 ENABLE, 1);
221 } else {
222 ih_doorbell_rtpr = REG_SET_FIELD(ih_doorbell_rtpr,
223 IH_DOORBELL_RPTR,
224 ENABLE, 0);
225 }
226 return ih_doorbell_rtpr;
227 }
228
229 /**
230 * ih_v7_0_enable_ring - enable an ih ring buffer
231 *
232 * @adev: amdgpu_device pointer
233 * @ih: amdgpu_ih_ring pointer
234 *
235 * Enable an ih ring buffer (IH_V7_0)
236 */
ih_v7_0_enable_ring(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)237 static int ih_v7_0_enable_ring(struct amdgpu_device *adev,
238 struct amdgpu_ih_ring *ih)
239 {
240 struct amdgpu_ih_regs *ih_regs;
241 uint32_t tmp;
242
243 ih_regs = &ih->ih_regs;
244
245 /* Ring Buffer base. [39:8] of 40-bit address of the beginning of the ring buffer*/
246 WREG32(ih_regs->ih_rb_base, ih->gpu_addr >> 8);
247 WREG32(ih_regs->ih_rb_base_hi, (ih->gpu_addr >> 40) & 0xff);
248
249 tmp = RREG32(ih_regs->ih_rb_cntl);
250 tmp = ih_v7_0_rb_cntl(ih, tmp);
251 if (ih == &adev->irq.ih)
252 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RPTR_REARM, !!adev->irq.msi_enabled);
253 if (ih == &adev->irq.ih1) {
254 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_ENABLE, 0);
255 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, RB_FULL_DRAIN_ENABLE, 1);
256 }
257
258 if (amdgpu_sriov_vf(adev) && amdgpu_sriov_reg_indirect_ih(adev)) {
259 if (psp_reg_program(&adev->psp, ih_regs->psp_reg_id, tmp)) {
260 DRM_ERROR("PSP program IH_RB_CNTL failed!\n");
261 return -ETIMEDOUT;
262 }
263 } else {
264 WREG32(ih_regs->ih_rb_cntl, tmp);
265 }
266
267 if (ih == &adev->irq.ih) {
268 /* set the ih ring 0 writeback address whether it's enabled or not */
269 WREG32(ih_regs->ih_rb_wptr_addr_lo, lower_32_bits(ih->wptr_addr));
270 WREG32(ih_regs->ih_rb_wptr_addr_hi, upper_32_bits(ih->wptr_addr) & 0xFFFF);
271 }
272
273 /* set rptr, wptr to 0 */
274 WREG32(ih_regs->ih_rb_wptr, 0);
275 WREG32(ih_regs->ih_rb_rptr, 0);
276
277 WREG32(ih_regs->ih_doorbell_rptr, ih_v7_0_doorbell_rptr(ih));
278
279 return 0;
280 }
281
282 /**
283 * ih_v7_0_irq_init - init and enable the interrupt ring
284 *
285 * @adev: amdgpu_device pointer
286 *
287 * Allocate a ring buffer for the interrupt controller,
288 * enable the RLC, disable interrupts, enable the IH
289 * ring buffer and enable it.
290 * Called at device load and reume.
291 * Returns 0 for success, errors for failure.
292 */
ih_v7_0_irq_init(struct amdgpu_device * adev)293 static int ih_v7_0_irq_init(struct amdgpu_device *adev)
294 {
295 struct amdgpu_ih_ring *ih[] = {&adev->irq.ih, &adev->irq.ih1};
296 u32 ih_chicken;
297 u32 tmp;
298 int ret;
299 int i;
300
301 /* disable irqs */
302 ret = ih_v7_0_toggle_interrupts(adev, false);
303 if (ret)
304 return ret;
305
306 adev->nbio.funcs->ih_control(adev);
307
308 if (unlikely((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
309 (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO))) {
310 if (ih[0]->use_bus_addr) {
311 ih_chicken = RREG32_SOC15(OSSSYS, 0, regIH_CHICKEN);
312 ih_chicken = REG_SET_FIELD(ih_chicken,
313 IH_CHICKEN, MC_SPACE_GPA_ENABLE, 1);
314 WREG32_SOC15(OSSSYS, 0, regIH_CHICKEN, ih_chicken);
315 }
316 }
317
318 for (i = 0; i < ARRAY_SIZE(ih); i++) {
319 if (ih[i]->ring_size) {
320 ret = ih_v7_0_enable_ring(adev, ih[i]);
321 if (ret)
322 return ret;
323 }
324 }
325
326 /* update doorbell range for ih ring 0 */
327 adev->nbio.funcs->ih_doorbell_range(adev, ih[0]->use_doorbell,
328 ih[0]->doorbell_index);
329
330 tmp = RREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL);
331 tmp = REG_SET_FIELD(tmp, IH_STORM_CLIENT_LIST_CNTL,
332 CLIENT18_IS_STORM_CLIENT, 1);
333 WREG32_SOC15(OSSSYS, 0, regIH_STORM_CLIENT_LIST_CNTL, tmp);
334
335 tmp = RREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL);
336 tmp = REG_SET_FIELD(tmp, IH_INT_FLOOD_CNTL, FLOOD_CNTL_ENABLE, 1);
337 WREG32_SOC15(OSSSYS, 0, regIH_INT_FLOOD_CNTL, tmp);
338
339 /* GC/MMHUB UTCL2 page fault interrupts are configured as
340 * MSI storm capable interrupts by deafult. The delay is
341 * used to avoid ISR being called too frequently
342 * when page fault happens on several continuous page
343 * and thus avoid MSI storm */
344 tmp = RREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL);
345 tmp = REG_SET_FIELD(tmp, IH_MSI_STORM_CTRL,
346 DELAY, 3);
347 WREG32_SOC15(OSSSYS, 0, regIH_MSI_STORM_CTRL, tmp);
348
349 /* Redirect the interrupts to IH RB1 for dGPU */
350 if (adev->irq.ih1.ring_size) {
351 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX);
352 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_INDEX, INDEX, 0);
353 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_INDEX, tmp);
354
355 tmp = RREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA);
356 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, CLIENT_ID, 0xa);
357 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA, SOURCE_ID, 0x0);
358 tmp = REG_SET_FIELD(tmp, IH_RING1_CLIENT_CFG_DATA,
359 SOURCE_ID_MATCH_ENABLE, 0x1);
360
361 WREG32_SOC15(OSSSYS, 0, regIH_RING1_CLIENT_CFG_DATA, tmp);
362 }
363
364 pci_set_master(adev->pdev);
365
366 /* enable interrupts */
367 ret = ih_v7_0_toggle_interrupts(adev, true);
368 if (ret)
369 return ret;
370 /* enable wptr force update for self int */
371 force_update_wptr_for_self_int(adev, 0, 8, true);
372
373 if (adev->irq.ih_soft.ring_size)
374 adev->irq.ih_soft.enabled = true;
375
376 return 0;
377 }
378
379 /**
380 * ih_v7_0_irq_disable - disable interrupts
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Disable interrupts on the hw.
385 */
ih_v7_0_irq_disable(struct amdgpu_device * adev)386 static void ih_v7_0_irq_disable(struct amdgpu_device *adev)
387 {
388 force_update_wptr_for_self_int(adev, 0, 8, false);
389 ih_v7_0_toggle_interrupts(adev, false);
390
391 /* Wait and acknowledge irq */
392 mdelay(1);
393 }
394
395 /**
396 * ih_v7_0_get_wptr() - get the IH ring buffer wptr
397 *
398 * @adev: amdgpu_device pointer
399 * @ih: IH ring buffer to fetch wptr
400 *
401 * Get the IH ring buffer wptr from either the register
402 * or the writeback memory buffer. Also check for
403 * ring buffer overflow and deal with it.
404 * Returns the value of the wptr.
405 */
ih_v7_0_get_wptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)406 static u32 ih_v7_0_get_wptr(struct amdgpu_device *adev,
407 struct amdgpu_ih_ring *ih)
408 {
409 u32 wptr, tmp;
410 struct amdgpu_ih_regs *ih_regs;
411
412 wptr = le32_to_cpu(*ih->wptr_cpu);
413 ih_regs = &ih->ih_regs;
414
415 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
416 goto out;
417
418 wptr = RREG32_NO_KIQ(ih_regs->ih_rb_wptr);
419 if (!REG_GET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW))
420 goto out;
421 wptr = REG_SET_FIELD(wptr, IH_RB_WPTR, RB_OVERFLOW, 0);
422
423 /* When a ring buffer overflow happen start parsing interrupt
424 * from the last not overwritten vector (wptr + 32). Hopefully
425 * this should allow us to catch up.
426 */
427 tmp = (wptr + 32) & ih->ptr_mask;
428 dev_warn(adev->dev, "IH ring buffer overflow "
429 "(0x%08X, 0x%08X, 0x%08X)\n",
430 wptr, ih->rptr, tmp);
431 ih->rptr = tmp;
432
433 tmp = RREG32_NO_KIQ(ih_regs->ih_rb_cntl);
434 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 1);
435 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
436
437 /* Unset the CLEAR_OVERFLOW bit immediately so new overflows
438 * can be detected.
439 */
440 tmp = REG_SET_FIELD(tmp, IH_RB_CNTL, WPTR_OVERFLOW_CLEAR, 0);
441 WREG32_NO_KIQ(ih_regs->ih_rb_cntl, tmp);
442 out:
443 return (wptr & ih->ptr_mask);
444 }
445
446 /**
447 * ih_v7_0_irq_rearm - rearm IRQ if lost
448 *
449 * @adev: amdgpu_device pointer
450 * @ih: IH ring to match
451 *
452 */
ih_v7_0_irq_rearm(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)453 static void ih_v7_0_irq_rearm(struct amdgpu_device *adev,
454 struct amdgpu_ih_ring *ih)
455 {
456 uint32_t v = 0;
457 uint32_t i = 0;
458 struct amdgpu_ih_regs *ih_regs;
459
460 ih_regs = &ih->ih_regs;
461
462 /* Rearm IRQ / re-write doorbell if doorbell write is lost */
463 for (i = 0; i < MAX_REARM_RETRY; i++) {
464 v = RREG32_NO_KIQ(ih_regs->ih_rb_rptr);
465 if ((v < ih->ring_size) && (v != ih->rptr))
466 WDOORBELL32(ih->doorbell_index, ih->rptr);
467 else
468 break;
469 }
470 }
471
472 /**
473 * ih_v7_0_set_rptr - set the IH ring buffer rptr
474 *
475 * @adev: amdgpu_device pointer
476 * @ih: IH ring buffer to set rptr
477 */
ih_v7_0_set_rptr(struct amdgpu_device * adev,struct amdgpu_ih_ring * ih)478 static void ih_v7_0_set_rptr(struct amdgpu_device *adev,
479 struct amdgpu_ih_ring *ih)
480 {
481 struct amdgpu_ih_regs *ih_regs;
482
483 if (ih->use_doorbell) {
484 /* XXX check if swapping is necessary on BE */
485 *ih->rptr_cpu = ih->rptr;
486 WDOORBELL32(ih->doorbell_index, ih->rptr);
487
488 if (amdgpu_sriov_vf(adev))
489 ih_v7_0_irq_rearm(adev, ih);
490 } else {
491 ih_regs = &ih->ih_regs;
492 WREG32(ih_regs->ih_rb_rptr, ih->rptr);
493 }
494 }
495
496 /**
497 * ih_v7_0_self_irq - dispatch work for ring 1
498 *
499 * @adev: amdgpu_device pointer
500 * @source: irq source
501 * @entry: IV with WPTR update
502 *
503 * Update the WPTR from the IV and schedule work to handle the entries.
504 */
ih_v7_0_self_irq(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)505 static int ih_v7_0_self_irq(struct amdgpu_device *adev,
506 struct amdgpu_irq_src *source,
507 struct amdgpu_iv_entry *entry)
508 {
509 uint32_t wptr = cpu_to_le32(entry->src_data[0]);
510
511 switch (entry->ring_id) {
512 case 1:
513 *adev->irq.ih1.wptr_cpu = wptr;
514 schedule_work(&adev->irq.ih1_work);
515 break;
516 default: break;
517 }
518 return 0;
519 }
520
521 static const struct amdgpu_irq_src_funcs ih_v7_0_self_irq_funcs = {
522 .process = ih_v7_0_self_irq,
523 };
524
ih_v7_0_set_self_irq_funcs(struct amdgpu_device * adev)525 static void ih_v7_0_set_self_irq_funcs(struct amdgpu_device *adev)
526 {
527 adev->irq.self_irq.num_types = 0;
528 adev->irq.self_irq.funcs = &ih_v7_0_self_irq_funcs;
529 }
530
ih_v7_0_early_init(void * handle)531 static int ih_v7_0_early_init(void *handle)
532 {
533 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
534
535 ih_v7_0_set_interrupt_funcs(adev);
536 ih_v7_0_set_self_irq_funcs(adev);
537 return 0;
538 }
539
ih_v7_0_sw_init(void * handle)540 static int ih_v7_0_sw_init(void *handle)
541 {
542 int r;
543 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
544 bool use_bus_addr;
545
546 r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_IH, 0,
547 &adev->irq.self_irq);
548
549 if (r)
550 return r;
551
552 /* use gpu virtual address for ih ring
553 * until ih_checken is programmed to allow
554 * use bus address for ih ring by psp bl */
555 use_bus_addr =
556 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
557 r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
558 if (r)
559 return r;
560
561 adev->irq.ih.use_doorbell = true;
562 adev->irq.ih.doorbell_index = adev->doorbell_index.ih << 1;
563
564 if (!(adev->flags & AMD_IS_APU)) {
565 r = amdgpu_ih_ring_init(adev, &adev->irq.ih1, IH_RING_SIZE,
566 use_bus_addr);
567 if (r)
568 return r;
569
570 adev->irq.ih1.use_doorbell = true;
571 adev->irq.ih1.doorbell_index = (adev->doorbell_index.ih + 1) << 1;
572 }
573
574 /* initialize ih control register offset */
575 ih_v7_0_init_register_offset(adev);
576
577 r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
578 if (r)
579 return r;
580
581 r = amdgpu_irq_init(adev);
582
583 return r;
584 }
585
ih_v7_0_sw_fini(void * handle)586 static int ih_v7_0_sw_fini(void *handle)
587 {
588 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
589
590 amdgpu_irq_fini_sw(adev);
591
592 return 0;
593 }
594
ih_v7_0_hw_init(void * handle)595 static int ih_v7_0_hw_init(void *handle)
596 {
597 int r;
598 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
599
600 r = ih_v7_0_irq_init(adev);
601 if (r)
602 return r;
603
604 return 0;
605 }
606
ih_v7_0_hw_fini(void * handle)607 static int ih_v7_0_hw_fini(void *handle)
608 {
609 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
610
611 ih_v7_0_irq_disable(adev);
612
613 return 0;
614 }
615
ih_v7_0_suspend(void * handle)616 static int ih_v7_0_suspend(void *handle)
617 {
618 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
619
620 return ih_v7_0_hw_fini(adev);
621 }
622
ih_v7_0_resume(void * handle)623 static int ih_v7_0_resume(void *handle)
624 {
625 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
626
627 return ih_v7_0_hw_init(adev);
628 }
629
ih_v7_0_is_idle(void * handle)630 static bool ih_v7_0_is_idle(void *handle)
631 {
632 /* todo */
633 return true;
634 }
635
ih_v7_0_wait_for_idle(void * handle)636 static int ih_v7_0_wait_for_idle(void *handle)
637 {
638 /* todo */
639 return -ETIMEDOUT;
640 }
641
ih_v7_0_soft_reset(void * handle)642 static int ih_v7_0_soft_reset(void *handle)
643 {
644 /* todo */
645 return 0;
646 }
647
ih_v7_0_update_clockgating_state(struct amdgpu_device * adev,bool enable)648 static void ih_v7_0_update_clockgating_state(struct amdgpu_device *adev,
649 bool enable)
650 {
651 uint32_t data, def, field_val;
652
653 if (adev->cg_flags & AMD_CG_SUPPORT_IH_CG) {
654 def = data = RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL);
655 field_val = enable ? 0 : 1;
656 data = REG_SET_FIELD(data, IH_CLK_CTRL,
657 DBUS_MUX_CLK_SOFT_OVERRIDE, field_val);
658 data = REG_SET_FIELD(data, IH_CLK_CTRL,
659 OSSSYS_SHARE_CLK_SOFT_OVERRIDE, field_val);
660 data = REG_SET_FIELD(data, IH_CLK_CTRL,
661 LIMIT_SMN_CLK_SOFT_OVERRIDE, field_val);
662 data = REG_SET_FIELD(data, IH_CLK_CTRL,
663 DYN_CLK_SOFT_OVERRIDE, field_val);
664 data = REG_SET_FIELD(data, IH_CLK_CTRL,
665 REG_CLK_SOFT_OVERRIDE, field_val);
666 if (def != data)
667 WREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL, data);
668 }
669
670 return;
671 }
672
ih_v7_0_set_clockgating_state(void * handle,enum amd_clockgating_state state)673 static int ih_v7_0_set_clockgating_state(void *handle,
674 enum amd_clockgating_state state)
675 {
676 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
677
678 ih_v7_0_update_clockgating_state(adev,
679 state == AMD_CG_STATE_GATE);
680 return 0;
681 }
682
ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device * adev,bool enable)683 static void ih_v7_0_update_ih_mem_power_gating(struct amdgpu_device *adev,
684 bool enable)
685 {
686 uint32_t ih_mem_pwr_cntl;
687
688 /* Disable ih sram power cntl before switch powergating mode */
689 ih_mem_pwr_cntl = RREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL);
690 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
691 IH_BUFFER_MEM_POWER_CTRL_EN, 0);
692 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
693
694 /* It is recommended to set mem powergating mode to DS mode */
695 if (enable) {
696 /* mem power mode */
697 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
698 IH_BUFFER_MEM_POWER_LS_EN, 0);
699 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
700 IH_BUFFER_MEM_POWER_DS_EN, 1);
701 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
702 IH_BUFFER_MEM_POWER_SD_EN, 0);
703 /* cam mem power mode */
704 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
705 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
706 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
707 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 1);
708 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
709 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
710 /* re-enable power cntl */
711 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
712 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
713 } else {
714 /* mem power mode */
715 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
716 IH_BUFFER_MEM_POWER_LS_EN, 0);
717 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
718 IH_BUFFER_MEM_POWER_DS_EN, 0);
719 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
720 IH_BUFFER_MEM_POWER_SD_EN, 0);
721 /* cam mem power mode */
722 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
723 IH_RETRY_INT_CAM_MEM_POWER_LS_EN, 0);
724 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
725 IH_RETRY_INT_CAM_MEM_POWER_DS_EN, 0);
726 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
727 IH_RETRY_INT_CAM_MEM_POWER_SD_EN, 0);
728 /* re-enable power cntl*/
729 ih_mem_pwr_cntl = REG_SET_FIELD(ih_mem_pwr_cntl, IH_MEM_POWER_CTRL,
730 IH_BUFFER_MEM_POWER_CTRL_EN, 1);
731 }
732
733 WREG32_SOC15(OSSSYS, 0, regIH_MEM_POWER_CTRL, ih_mem_pwr_cntl);
734 }
735
ih_v7_0_set_powergating_state(void * handle,enum amd_powergating_state state)736 static int ih_v7_0_set_powergating_state(void *handle,
737 enum amd_powergating_state state)
738 {
739 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
740 bool enable = (state == AMD_PG_STATE_GATE);
741
742 if (adev->pg_flags & AMD_PG_SUPPORT_IH_SRAM_PG)
743 ih_v7_0_update_ih_mem_power_gating(adev, enable);
744
745 return 0;
746 }
747
ih_v7_0_get_clockgating_state(void * handle,u64 * flags)748 static void ih_v7_0_get_clockgating_state(void *handle, u64 *flags)
749 {
750 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
751
752 if (!RREG32_SOC15(OSSSYS, 0, regIH_CLK_CTRL))
753 *flags |= AMD_CG_SUPPORT_IH_CG;
754
755 return;
756 }
757
758 static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
759 .name = "ih_v7_0",
760 .early_init = ih_v7_0_early_init,
761 .late_init = NULL,
762 .sw_init = ih_v7_0_sw_init,
763 .sw_fini = ih_v7_0_sw_fini,
764 .hw_init = ih_v7_0_hw_init,
765 .hw_fini = ih_v7_0_hw_fini,
766 .suspend = ih_v7_0_suspend,
767 .resume = ih_v7_0_resume,
768 .is_idle = ih_v7_0_is_idle,
769 .wait_for_idle = ih_v7_0_wait_for_idle,
770 .soft_reset = ih_v7_0_soft_reset,
771 .set_clockgating_state = ih_v7_0_set_clockgating_state,
772 .set_powergating_state = ih_v7_0_set_powergating_state,
773 .get_clockgating_state = ih_v7_0_get_clockgating_state,
774 .dump_ip_state = NULL,
775 .print_ip_state = NULL,
776 };
777
778 static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
779 .get_wptr = ih_v7_0_get_wptr,
780 .decode_iv = amdgpu_ih_decode_iv_helper,
781 .decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
782 .set_rptr = ih_v7_0_set_rptr
783 };
784
ih_v7_0_set_interrupt_funcs(struct amdgpu_device * adev)785 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev)
786 {
787 adev->irq.ih_funcs = &ih_v7_0_funcs;
788 }
789
790 const struct amdgpu_ip_block_version ih_v7_0_ip_block =
791 {
792 .type = AMD_IP_BLOCK_TYPE_IH,
793 .major = 7,
794 .minor = 0,
795 .rev = 0,
796 .funcs = &ih_v7_0_ip_funcs,
797 };
798