1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/module.h>
35 #include <linux/pci.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hnae3.h"
41 #include "hns_roce_common.h"
42 #include "hns_roce_device.h"
43 #include "hns_roce_hem.h"
44 #include "hns_roce_hw_v2.h"
45
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u32 port,const u8 * addr)46 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
47 const u8 *addr)
48 {
49 u8 phy_port;
50 u32 i;
51
52 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
53 return 0;
54
55 if (!memcmp(hr_dev->dev_addr[port], addr, ETH_ALEN))
56 return 0;
57
58 for (i = 0; i < ETH_ALEN; i++)
59 hr_dev->dev_addr[port][i] = addr[i];
60
61 phy_port = hr_dev->iboe.phy_port[port];
62 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
63 }
64
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)65 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
66 {
67 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
68 u32 port = attr->port_num - 1;
69 int ret;
70
71 if (port >= hr_dev->caps.num_ports)
72 return -EINVAL;
73
74 ret = hr_dev->hw->set_gid(hr_dev, attr->index, &attr->gid, attr);
75
76 return ret;
77 }
78
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)79 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
80 {
81 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
82 u32 port = attr->port_num - 1;
83 int ret;
84
85 if (port >= hr_dev->caps.num_ports)
86 return -EINVAL;
87
88 ret = hr_dev->hw->set_gid(hr_dev, attr->index, NULL, NULL);
89
90 return ret;
91 }
92
handle_en_event(struct hns_roce_dev * hr_dev,u32 port,unsigned long event)93 static int handle_en_event(struct hns_roce_dev *hr_dev, u32 port,
94 unsigned long event)
95 {
96 struct device *dev = hr_dev->dev;
97 struct net_device *netdev;
98 int ret = 0;
99
100 netdev = hr_dev->iboe.netdevs[port];
101 if (!netdev) {
102 dev_err(dev, "can't find netdev on port(%u)!\n", port);
103 return -ENODEV;
104 }
105
106 switch (event) {
107 case NETDEV_UP:
108 case NETDEV_CHANGE:
109 case NETDEV_REGISTER:
110 case NETDEV_CHANGEADDR:
111 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
112 break;
113 case NETDEV_DOWN:
114 /*
115 * In v1 engine, only support all ports closed together.
116 */
117 break;
118 default:
119 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
120 break;
121 }
122
123 return ret;
124 }
125
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)126 static int hns_roce_netdev_event(struct notifier_block *self,
127 unsigned long event, void *ptr)
128 {
129 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
130 struct hns_roce_ib_iboe *iboe = NULL;
131 struct hns_roce_dev *hr_dev = NULL;
132 int ret;
133 u32 port;
134
135 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
136 iboe = &hr_dev->iboe;
137
138 for (port = 0; port < hr_dev->caps.num_ports; port++) {
139 if (dev == iboe->netdevs[port]) {
140 ret = handle_en_event(hr_dev, port, event);
141 if (ret)
142 return NOTIFY_DONE;
143 break;
144 }
145 }
146
147 return NOTIFY_DONE;
148 }
149
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)150 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
151 {
152 int ret;
153 u8 i;
154
155 for (i = 0; i < hr_dev->caps.num_ports; i++) {
156 ret = hns_roce_set_mac(hr_dev, i,
157 hr_dev->iboe.netdevs[i]->dev_addr);
158 if (ret)
159 return ret;
160 }
161
162 return 0;
163 }
164
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)165 static int hns_roce_query_device(struct ib_device *ib_dev,
166 struct ib_device_attr *props,
167 struct ib_udata *uhw)
168 {
169 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
170
171 memset(props, 0, sizeof(*props));
172
173 props->fw_ver = hr_dev->caps.fw_ver;
174 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
175 props->max_mr_size = (u64)(~(0ULL));
176 props->page_size_cap = hr_dev->caps.page_size_cap;
177 props->vendor_id = hr_dev->vendor_id;
178 props->vendor_part_id = hr_dev->vendor_part_id;
179 props->hw_ver = hr_dev->hw_rev;
180 props->max_qp = hr_dev->caps.num_qps;
181 props->max_qp_wr = hr_dev->caps.max_wqes;
182 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
183 IB_DEVICE_RC_RNR_NAK_GEN;
184 props->max_send_sge = hr_dev->caps.max_sq_sg;
185 props->max_recv_sge = hr_dev->caps.max_rq_sg;
186 props->max_sge_rd = 1;
187 props->max_cq = hr_dev->caps.num_cqs;
188 props->max_cqe = hr_dev->caps.max_cqes;
189 props->max_mr = hr_dev->caps.num_mtpts;
190 props->max_pd = hr_dev->caps.num_pds;
191 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
192 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
193 props->atomic_cap = hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_ATOMIC ?
194 IB_ATOMIC_HCA : IB_ATOMIC_NONE;
195 props->max_pkeys = 1;
196 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
197 props->max_ah = INT_MAX;
198 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD;
199 props->cq_caps.max_cq_moderation_count = HNS_ROCE_MAX_CQ_COUNT;
200 if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
201 props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
202
203 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
204 props->max_srq = hr_dev->caps.num_srqs;
205 props->max_srq_wr = hr_dev->caps.max_srq_wrs;
206 props->max_srq_sge = hr_dev->caps.max_srq_sges;
207 }
208
209 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR &&
210 hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09) {
211 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
212 props->max_fast_reg_page_list_len = HNS_ROCE_FRMR_MAX_PA;
213 }
214
215 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
216 props->device_cap_flags |= IB_DEVICE_XRC;
217
218 return 0;
219 }
220
hns_roce_query_port(struct ib_device * ib_dev,u32 port_num,struct ib_port_attr * props)221 static int hns_roce_query_port(struct ib_device *ib_dev, u32 port_num,
222 struct ib_port_attr *props)
223 {
224 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
225 struct device *dev = hr_dev->dev;
226 struct net_device *net_dev;
227 unsigned long flags;
228 enum ib_mtu mtu;
229 u32 port;
230 int ret;
231
232 port = port_num - 1;
233
234 /* props being zeroed by the caller, avoid zeroing it here */
235
236 props->max_mtu = hr_dev->caps.max_mtu;
237 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
238 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
239 IB_PORT_VENDOR_CLASS_SUP |
240 IB_PORT_BOOT_MGMT_SUP;
241 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
242 props->pkey_tbl_len = 1;
243 ret = ib_get_eth_speed(ib_dev, port_num, &props->active_speed,
244 &props->active_width);
245 if (ret)
246 ibdev_warn(ib_dev, "failed to get speed, ret = %d.\n", ret);
247
248 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
249
250 net_dev = hr_dev->iboe.netdevs[port];
251 if (!net_dev) {
252 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
253 dev_err(dev, "find netdev %u failed!\n", port);
254 return -EINVAL;
255 }
256
257 mtu = iboe_get_mtu(net_dev->mtu);
258 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
259 props->state = netif_running(net_dev) && netif_carrier_ok(net_dev) ?
260 IB_PORT_ACTIVE :
261 IB_PORT_DOWN;
262 props->phys_state = props->state == IB_PORT_ACTIVE ?
263 IB_PORT_PHYS_STATE_LINK_UP :
264 IB_PORT_PHYS_STATE_DISABLED;
265
266 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
267
268 return 0;
269 }
270
hns_roce_get_link_layer(struct ib_device * device,u32 port_num)271 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
272 u32 port_num)
273 {
274 return IB_LINK_LAYER_ETHERNET;
275 }
276
hns_roce_query_pkey(struct ib_device * ib_dev,u32 port,u16 index,u16 * pkey)277 static int hns_roce_query_pkey(struct ib_device *ib_dev, u32 port, u16 index,
278 u16 *pkey)
279 {
280 if (index > 0)
281 return -EINVAL;
282
283 *pkey = PKEY_ID;
284
285 return 0;
286 }
287
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)288 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
289 struct ib_device_modify *props)
290 {
291 unsigned long flags;
292
293 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
294 return -EOPNOTSUPP;
295
296 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
297 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
298 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
299 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
300 }
301
302 return 0;
303 }
304
305 struct hns_user_mmap_entry *
hns_roce_user_mmap_entry_insert(struct ib_ucontext * ucontext,u64 address,size_t length,enum hns_roce_mmap_type mmap_type)306 hns_roce_user_mmap_entry_insert(struct ib_ucontext *ucontext, u64 address,
307 size_t length,
308 enum hns_roce_mmap_type mmap_type)
309 {
310 struct hns_user_mmap_entry *entry;
311 int ret;
312
313 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
314 if (!entry)
315 return NULL;
316
317 entry->address = address;
318 entry->mmap_type = mmap_type;
319
320 switch (mmap_type) {
321 /* pgoff 0 must be used by DB for compatibility */
322 case HNS_ROCE_MMAP_TYPE_DB:
323 ret = rdma_user_mmap_entry_insert_exact(
324 ucontext, &entry->rdma_entry, length, 0);
325 break;
326 case HNS_ROCE_MMAP_TYPE_DWQE:
327 ret = rdma_user_mmap_entry_insert_range(
328 ucontext, &entry->rdma_entry, length, 1,
329 U32_MAX);
330 break;
331 default:
332 ret = -EINVAL;
333 break;
334 }
335
336 if (ret) {
337 kfree(entry);
338 return NULL;
339 }
340
341 return entry;
342 }
343
hns_roce_dealloc_uar_entry(struct hns_roce_ucontext * context)344 static void hns_roce_dealloc_uar_entry(struct hns_roce_ucontext *context)
345 {
346 if (context->db_mmap_entry)
347 rdma_user_mmap_entry_remove(
348 &context->db_mmap_entry->rdma_entry);
349 }
350
hns_roce_alloc_uar_entry(struct ib_ucontext * uctx)351 static int hns_roce_alloc_uar_entry(struct ib_ucontext *uctx)
352 {
353 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
354 u64 address;
355
356 address = context->uar.pfn << PAGE_SHIFT;
357 context->db_mmap_entry = hns_roce_user_mmap_entry_insert(
358 uctx, address, PAGE_SIZE, HNS_ROCE_MMAP_TYPE_DB);
359 if (!context->db_mmap_entry)
360 return -ENOMEM;
361
362 return 0;
363 }
364
hns_roce_alloc_ucontext(struct ib_ucontext * uctx,struct ib_udata * udata)365 static int hns_roce_alloc_ucontext(struct ib_ucontext *uctx,
366 struct ib_udata *udata)
367 {
368 struct hns_roce_ucontext *context = to_hr_ucontext(uctx);
369 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
370 struct hns_roce_ib_alloc_ucontext_resp resp = {};
371 struct hns_roce_ib_alloc_ucontext ucmd = {};
372 int ret = -EAGAIN;
373
374 if (!hr_dev->active)
375 goto error_out;
376
377 resp.qp_tab_size = hr_dev->caps.num_qps;
378 resp.srq_tab_size = hr_dev->caps.num_srqs;
379
380 ret = ib_copy_from_udata(&ucmd, udata,
381 min(udata->inlen, sizeof(ucmd)));
382 if (ret)
383 goto error_out;
384
385 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
386 context->config = ucmd.config & HNS_ROCE_EXSGE_FLAGS;
387
388 if (context->config & HNS_ROCE_EXSGE_FLAGS) {
389 resp.config |= HNS_ROCE_RSP_EXSGE_FLAGS;
390 resp.max_inline_data = hr_dev->caps.max_sq_inline;
391 }
392
393 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
394 context->config |= ucmd.config & HNS_ROCE_RQ_INLINE_FLAGS;
395 if (context->config & HNS_ROCE_RQ_INLINE_FLAGS)
396 resp.config |= HNS_ROCE_RSP_RQ_INLINE_FLAGS;
397 }
398
399 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQE_INLINE) {
400 context->config |= ucmd.config & HNS_ROCE_CQE_INLINE_FLAGS;
401 if (context->config & HNS_ROCE_CQE_INLINE_FLAGS)
402 resp.config |= HNS_ROCE_RSP_CQE_INLINE_FLAGS;
403 }
404
405 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09)
406 resp.congest_type = hr_dev->caps.cong_cap;
407
408 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
409 if (ret)
410 goto error_out;
411
412 ret = hns_roce_alloc_uar_entry(uctx);
413 if (ret)
414 goto error_fail_uar_entry;
415
416 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
417 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
418 INIT_LIST_HEAD(&context->page_list);
419 mutex_init(&context->page_mutex);
420 }
421
422 resp.cqe_size = hr_dev->caps.cqe_sz;
423
424 ret = ib_copy_to_udata(udata, &resp,
425 min(udata->outlen, sizeof(resp)));
426 if (ret)
427 goto error_fail_copy_to_udata;
428
429 return 0;
430
431 error_fail_copy_to_udata:
432 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
433 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
434 mutex_destroy(&context->page_mutex);
435 hns_roce_dealloc_uar_entry(context);
436
437 error_fail_uar_entry:
438 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
439
440 error_out:
441 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_UCTX_ALLOC_ERR_CNT]);
442
443 return ret;
444 }
445
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)446 static void hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
447 {
448 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
449 struct hns_roce_dev *hr_dev = to_hr_dev(ibcontext->device);
450
451 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
452 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
453 mutex_destroy(&context->page_mutex);
454
455 hns_roce_dealloc_uar_entry(context);
456
457 ida_free(&hr_dev->uar_ida.ida, (int)context->uar.logic_idx);
458 }
459
hns_roce_mmap(struct ib_ucontext * uctx,struct vm_area_struct * vma)460 static int hns_roce_mmap(struct ib_ucontext *uctx, struct vm_area_struct *vma)
461 {
462 struct hns_roce_dev *hr_dev = to_hr_dev(uctx->device);
463 struct rdma_user_mmap_entry *rdma_entry;
464 struct hns_user_mmap_entry *entry;
465 phys_addr_t pfn;
466 pgprot_t prot;
467 int ret;
468
469 rdma_entry = rdma_user_mmap_entry_get_pgoff(uctx, vma->vm_pgoff);
470 if (!rdma_entry) {
471 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
472 return -EINVAL;
473 }
474
475 entry = to_hns_mmap(rdma_entry);
476 pfn = entry->address >> PAGE_SHIFT;
477
478 switch (entry->mmap_type) {
479 case HNS_ROCE_MMAP_TYPE_DB:
480 case HNS_ROCE_MMAP_TYPE_DWQE:
481 prot = pgprot_device(vma->vm_page_prot);
482 break;
483 default:
484 ret = -EINVAL;
485 goto out;
486 }
487
488 ret = rdma_user_mmap_io(uctx, vma, pfn, rdma_entry->npages * PAGE_SIZE,
489 prot, rdma_entry);
490
491 out:
492 rdma_user_mmap_entry_put(rdma_entry);
493 if (ret)
494 atomic64_inc(&hr_dev->dfx_cnt[HNS_ROCE_DFX_MMAP_ERR_CNT]);
495
496 return ret;
497 }
498
hns_roce_free_mmap(struct rdma_user_mmap_entry * rdma_entry)499 static void hns_roce_free_mmap(struct rdma_user_mmap_entry *rdma_entry)
500 {
501 struct hns_user_mmap_entry *entry = to_hns_mmap(rdma_entry);
502
503 kfree(entry);
504 }
505
hns_roce_port_immutable(struct ib_device * ib_dev,u32 port_num,struct ib_port_immutable * immutable)506 static int hns_roce_port_immutable(struct ib_device *ib_dev, u32 port_num,
507 struct ib_port_immutable *immutable)
508 {
509 struct ib_port_attr attr;
510 int ret;
511
512 ret = ib_query_port(ib_dev, port_num, &attr);
513 if (ret)
514 return ret;
515
516 immutable->pkey_tbl_len = attr.pkey_tbl_len;
517 immutable->gid_tbl_len = attr.gid_tbl_len;
518
519 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
520 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
521 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
522 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
523
524 return 0;
525 }
526
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)527 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
528 {
529 }
530
hns_roce_get_fw_ver(struct ib_device * device,char * str)531 static void hns_roce_get_fw_ver(struct ib_device *device, char *str)
532 {
533 u64 fw_ver = to_hr_dev(device)->caps.fw_ver;
534 unsigned int major, minor, sub_minor;
535
536 major = upper_32_bits(fw_ver);
537 minor = high_16_bits(lower_32_bits(fw_ver));
538 sub_minor = low_16_bits(fw_ver);
539
540 snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u.%04u", major, minor,
541 sub_minor);
542 }
543
544 #define HNS_ROCE_HW_CNT(ename, cname) \
545 [HNS_ROCE_HW_##ename##_CNT].name = cname
546
547 static const struct rdma_stat_desc hns_roce_port_stats_descs[] = {
548 HNS_ROCE_HW_CNT(RX_RC_PKT, "rx_rc_pkt"),
549 HNS_ROCE_HW_CNT(RX_UC_PKT, "rx_uc_pkt"),
550 HNS_ROCE_HW_CNT(RX_UD_PKT, "rx_ud_pkt"),
551 HNS_ROCE_HW_CNT(RX_XRC_PKT, "rx_xrc_pkt"),
552 HNS_ROCE_HW_CNT(RX_PKT, "rx_pkt"),
553 HNS_ROCE_HW_CNT(RX_ERR_PKT, "rx_err_pkt"),
554 HNS_ROCE_HW_CNT(RX_CNP_PKT, "rx_cnp_pkt"),
555 HNS_ROCE_HW_CNT(TX_RC_PKT, "tx_rc_pkt"),
556 HNS_ROCE_HW_CNT(TX_UC_PKT, "tx_uc_pkt"),
557 HNS_ROCE_HW_CNT(TX_UD_PKT, "tx_ud_pkt"),
558 HNS_ROCE_HW_CNT(TX_XRC_PKT, "tx_xrc_pkt"),
559 HNS_ROCE_HW_CNT(TX_PKT, "tx_pkt"),
560 HNS_ROCE_HW_CNT(TX_ERR_PKT, "tx_err_pkt"),
561 HNS_ROCE_HW_CNT(TX_CNP_PKT, "tx_cnp_pkt"),
562 HNS_ROCE_HW_CNT(TRP_GET_MPT_ERR_PKT, "trp_get_mpt_err_pkt"),
563 HNS_ROCE_HW_CNT(TRP_GET_IRRL_ERR_PKT, "trp_get_irrl_err_pkt"),
564 HNS_ROCE_HW_CNT(ECN_DB, "ecn_doorbell"),
565 HNS_ROCE_HW_CNT(RX_BUF, "rx_buffer"),
566 HNS_ROCE_HW_CNT(TRP_RX_SOF, "trp_rx_sof"),
567 HNS_ROCE_HW_CNT(CQ_CQE, "cq_cqe"),
568 HNS_ROCE_HW_CNT(CQ_POE, "cq_poe"),
569 HNS_ROCE_HW_CNT(CQ_NOTIFY, "cq_notify"),
570 };
571
hns_roce_alloc_hw_port_stats(struct ib_device * device,u32 port_num)572 static struct rdma_hw_stats *hns_roce_alloc_hw_port_stats(
573 struct ib_device *device, u32 port_num)
574 {
575 struct hns_roce_dev *hr_dev = to_hr_dev(device);
576
577 if (port_num > hr_dev->caps.num_ports) {
578 ibdev_err(device, "invalid port num.\n");
579 return NULL;
580 }
581
582 return rdma_alloc_hw_stats_struct(hns_roce_port_stats_descs,
583 ARRAY_SIZE(hns_roce_port_stats_descs),
584 RDMA_HW_STATS_DEFAULT_LIFESPAN);
585 }
586
hns_roce_get_hw_stats(struct ib_device * device,struct rdma_hw_stats * stats,u32 port,int index)587 static int hns_roce_get_hw_stats(struct ib_device *device,
588 struct rdma_hw_stats *stats,
589 u32 port, int index)
590 {
591 struct hns_roce_dev *hr_dev = to_hr_dev(device);
592 int num_counters = HNS_ROCE_HW_CNT_TOTAL;
593 int ret;
594
595 if (port == 0)
596 return 0;
597
598 if (port > hr_dev->caps.num_ports)
599 return -EINVAL;
600
601 ret = hr_dev->hw->query_hw_counter(hr_dev, stats->value, port,
602 &num_counters);
603 if (ret) {
604 ibdev_err(device, "failed to query hw counter, ret = %d\n",
605 ret);
606 return ret;
607 }
608
609 return num_counters;
610 }
611
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)612 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
613 {
614 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
615
616 hr_dev->active = false;
617 unregister_netdevice_notifier(&iboe->nb);
618 ib_unregister_device(&hr_dev->ib_dev);
619 }
620
621 static const struct ib_device_ops hns_roce_dev_ops = {
622 .owner = THIS_MODULE,
623 .driver_id = RDMA_DRIVER_HNS,
624 .uverbs_abi_ver = 1,
625 .uverbs_no_driver_id_binding = 1,
626
627 .get_dev_fw_str = hns_roce_get_fw_ver,
628 .add_gid = hns_roce_add_gid,
629 .alloc_pd = hns_roce_alloc_pd,
630 .alloc_ucontext = hns_roce_alloc_ucontext,
631 .create_ah = hns_roce_create_ah,
632 .create_user_ah = hns_roce_create_ah,
633 .create_cq = hns_roce_create_cq,
634 .create_qp = hns_roce_create_qp,
635 .dealloc_pd = hns_roce_dealloc_pd,
636 .dealloc_ucontext = hns_roce_dealloc_ucontext,
637 .del_gid = hns_roce_del_gid,
638 .dereg_mr = hns_roce_dereg_mr,
639 .destroy_ah = hns_roce_destroy_ah,
640 .destroy_cq = hns_roce_destroy_cq,
641 .disassociate_ucontext = hns_roce_disassociate_ucontext,
642 .get_dma_mr = hns_roce_get_dma_mr,
643 .get_link_layer = hns_roce_get_link_layer,
644 .get_port_immutable = hns_roce_port_immutable,
645 .mmap = hns_roce_mmap,
646 .mmap_free = hns_roce_free_mmap,
647 .modify_device = hns_roce_modify_device,
648 .modify_qp = hns_roce_modify_qp,
649 .query_ah = hns_roce_query_ah,
650 .query_device = hns_roce_query_device,
651 .query_pkey = hns_roce_query_pkey,
652 .query_port = hns_roce_query_port,
653 .reg_user_mr = hns_roce_reg_user_mr,
654
655 INIT_RDMA_OBJ_SIZE(ib_ah, hns_roce_ah, ibah),
656 INIT_RDMA_OBJ_SIZE(ib_cq, hns_roce_cq, ib_cq),
657 INIT_RDMA_OBJ_SIZE(ib_pd, hns_roce_pd, ibpd),
658 INIT_RDMA_OBJ_SIZE(ib_qp, hns_roce_qp, ibqp),
659 INIT_RDMA_OBJ_SIZE(ib_ucontext, hns_roce_ucontext, ibucontext),
660 };
661
662 static const struct ib_device_ops hns_roce_dev_hw_stats_ops = {
663 .alloc_hw_port_stats = hns_roce_alloc_hw_port_stats,
664 .get_hw_stats = hns_roce_get_hw_stats,
665 };
666
667 static const struct ib_device_ops hns_roce_dev_mr_ops = {
668 .rereg_user_mr = hns_roce_rereg_user_mr,
669 };
670
671 static const struct ib_device_ops hns_roce_dev_mw_ops = {
672 .alloc_mw = hns_roce_alloc_mw,
673 .dealloc_mw = hns_roce_dealloc_mw,
674
675 INIT_RDMA_OBJ_SIZE(ib_mw, hns_roce_mw, ibmw),
676 };
677
678 static const struct ib_device_ops hns_roce_dev_frmr_ops = {
679 .alloc_mr = hns_roce_alloc_mr,
680 .map_mr_sg = hns_roce_map_mr_sg,
681 };
682
683 static const struct ib_device_ops hns_roce_dev_srq_ops = {
684 .create_srq = hns_roce_create_srq,
685 .destroy_srq = hns_roce_destroy_srq,
686
687 INIT_RDMA_OBJ_SIZE(ib_srq, hns_roce_srq, ibsrq),
688 };
689
690 static const struct ib_device_ops hns_roce_dev_xrcd_ops = {
691 .alloc_xrcd = hns_roce_alloc_xrcd,
692 .dealloc_xrcd = hns_roce_dealloc_xrcd,
693
694 INIT_RDMA_OBJ_SIZE(ib_xrcd, hns_roce_xrcd, ibxrcd),
695 };
696
697 static const struct ib_device_ops hns_roce_dev_restrack_ops = {
698 .fill_res_cq_entry = hns_roce_fill_res_cq_entry,
699 .fill_res_cq_entry_raw = hns_roce_fill_res_cq_entry_raw,
700 .fill_res_qp_entry = hns_roce_fill_res_qp_entry,
701 .fill_res_qp_entry_raw = hns_roce_fill_res_qp_entry_raw,
702 .fill_res_mr_entry = hns_roce_fill_res_mr_entry,
703 .fill_res_mr_entry_raw = hns_roce_fill_res_mr_entry_raw,
704 .fill_res_srq_entry = hns_roce_fill_res_srq_entry,
705 .fill_res_srq_entry_raw = hns_roce_fill_res_srq_entry_raw,
706 };
707
hns_roce_register_device(struct hns_roce_dev * hr_dev)708 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
709 {
710 int ret;
711 struct hns_roce_ib_iboe *iboe = NULL;
712 struct ib_device *ib_dev = NULL;
713 struct device *dev = hr_dev->dev;
714 unsigned int i;
715
716 iboe = &hr_dev->iboe;
717 spin_lock_init(&iboe->lock);
718
719 ib_dev = &hr_dev->ib_dev;
720
721 ib_dev->node_type = RDMA_NODE_IB_CA;
722 ib_dev->dev.parent = dev;
723
724 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
725 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
726 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
727
728 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR)
729 ib_set_device_ops(ib_dev, &hns_roce_dev_mr_ops);
730
731 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_MW)
732 ib_set_device_ops(ib_dev, &hns_roce_dev_mw_ops);
733
734 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_FRMR)
735 ib_set_device_ops(ib_dev, &hns_roce_dev_frmr_ops);
736
737 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
738 ib_set_device_ops(ib_dev, &hns_roce_dev_srq_ops);
739 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_srq_ops);
740 }
741
742 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
743 ib_set_device_ops(ib_dev, &hns_roce_dev_xrcd_ops);
744
745 if (hr_dev->pci_dev->revision >= PCI_REVISION_ID_HIP09 &&
746 !hr_dev->is_vf)
747 ib_set_device_ops(ib_dev, &hns_roce_dev_hw_stats_ops);
748
749 ib_set_device_ops(ib_dev, hr_dev->hw->hns_roce_dev_ops);
750 ib_set_device_ops(ib_dev, &hns_roce_dev_ops);
751 ib_set_device_ops(ib_dev, &hns_roce_dev_restrack_ops);
752 for (i = 0; i < hr_dev->caps.num_ports; i++) {
753 if (!hr_dev->iboe.netdevs[i])
754 continue;
755
756 ret = ib_device_set_netdev(ib_dev, hr_dev->iboe.netdevs[i],
757 i + 1);
758 if (ret)
759 return ret;
760 }
761 dma_set_max_seg_size(dev, UINT_MAX);
762 ret = ib_register_device(ib_dev, "hns_%d", dev);
763 if (ret) {
764 dev_err(dev, "ib_register_device failed!\n");
765 return ret;
766 }
767
768 ret = hns_roce_setup_mtu_mac(hr_dev);
769 if (ret) {
770 dev_err(dev, "setup_mtu_mac failed!\n");
771 goto error_failed_setup_mtu_mac;
772 }
773
774 iboe->nb.notifier_call = hns_roce_netdev_event;
775 ret = register_netdevice_notifier(&iboe->nb);
776 if (ret) {
777 dev_err(dev, "register_netdevice_notifier failed!\n");
778 goto error_failed_setup_mtu_mac;
779 }
780
781 hr_dev->active = true;
782 return 0;
783
784 error_failed_setup_mtu_mac:
785 ib_unregister_device(ib_dev);
786
787 return ret;
788 }
789
hns_roce_init_hem(struct hns_roce_dev * hr_dev)790 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
791 {
792 struct device *dev = hr_dev->dev;
793 int ret;
794
795 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
796 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
797 hr_dev->caps.num_mtpts);
798 if (ret) {
799 dev_err(dev, "failed to init MTPT context memory, aborting.\n");
800 return ret;
801 }
802
803 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
804 HEM_TYPE_QPC, hr_dev->caps.qpc_sz,
805 hr_dev->caps.num_qps);
806 if (ret) {
807 dev_err(dev, "failed to init QP context memory, aborting.\n");
808 goto err_unmap_dmpt;
809 }
810
811 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
812 HEM_TYPE_IRRL,
813 hr_dev->caps.irrl_entry_sz *
814 hr_dev->caps.max_qp_init_rdma,
815 hr_dev->caps.num_qps);
816 if (ret) {
817 dev_err(dev, "failed to init irrl_table memory, aborting.\n");
818 goto err_unmap_qp;
819 }
820
821 if (hr_dev->caps.trrl_entry_sz) {
822 ret = hns_roce_init_hem_table(hr_dev,
823 &hr_dev->qp_table.trrl_table,
824 HEM_TYPE_TRRL,
825 hr_dev->caps.trrl_entry_sz *
826 hr_dev->caps.max_qp_dest_rdma,
827 hr_dev->caps.num_qps);
828 if (ret) {
829 dev_err(dev,
830 "failed to init trrl_table memory, aborting.\n");
831 goto err_unmap_irrl;
832 }
833 }
834
835 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
836 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
837 hr_dev->caps.num_cqs);
838 if (ret) {
839 dev_err(dev, "failed to init CQ context memory, aborting.\n");
840 goto err_unmap_trrl;
841 }
842
843 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
844 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->srq_table.table,
845 HEM_TYPE_SRQC,
846 hr_dev->caps.srqc_entry_sz,
847 hr_dev->caps.num_srqs);
848 if (ret) {
849 dev_err(dev,
850 "failed to init SRQ context memory, aborting.\n");
851 goto err_unmap_cq;
852 }
853 }
854
855 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL) {
856 ret = hns_roce_init_hem_table(hr_dev,
857 &hr_dev->qp_table.sccc_table,
858 HEM_TYPE_SCCC,
859 hr_dev->caps.sccc_sz,
860 hr_dev->caps.num_qps);
861 if (ret) {
862 dev_err(dev,
863 "failed to init SCC context memory, aborting.\n");
864 goto err_unmap_srq;
865 }
866 }
867
868 if (hr_dev->caps.qpc_timer_entry_sz) {
869 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qpc_timer_table,
870 HEM_TYPE_QPC_TIMER,
871 hr_dev->caps.qpc_timer_entry_sz,
872 hr_dev->caps.qpc_timer_bt_num);
873 if (ret) {
874 dev_err(dev,
875 "failed to init QPC timer memory, aborting.\n");
876 goto err_unmap_ctx;
877 }
878 }
879
880 if (hr_dev->caps.cqc_timer_entry_sz) {
881 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cqc_timer_table,
882 HEM_TYPE_CQC_TIMER,
883 hr_dev->caps.cqc_timer_entry_sz,
884 hr_dev->caps.cqc_timer_bt_num);
885 if (ret) {
886 dev_err(dev,
887 "failed to init CQC timer memory, aborting.\n");
888 goto err_unmap_qpc_timer;
889 }
890 }
891
892 if (hr_dev->caps.gmv_entry_sz) {
893 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->gmv_table,
894 HEM_TYPE_GMV,
895 hr_dev->caps.gmv_entry_sz,
896 hr_dev->caps.gmv_entry_num);
897 if (ret) {
898 dev_err(dev,
899 "failed to init gmv table memory, ret = %d\n",
900 ret);
901 goto err_unmap_cqc_timer;
902 }
903 }
904
905 return 0;
906
907 err_unmap_cqc_timer:
908 if (hr_dev->caps.cqc_timer_entry_sz)
909 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cqc_timer_table);
910
911 err_unmap_qpc_timer:
912 if (hr_dev->caps.qpc_timer_entry_sz)
913 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qpc_timer_table);
914
915 err_unmap_ctx:
916 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_FLOW_CTRL)
917 hns_roce_cleanup_hem_table(hr_dev,
918 &hr_dev->qp_table.sccc_table);
919 err_unmap_srq:
920 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
921 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->srq_table.table);
922
923 err_unmap_cq:
924 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->cq_table.table);
925
926 err_unmap_trrl:
927 if (hr_dev->caps.trrl_entry_sz)
928 hns_roce_cleanup_hem_table(hr_dev,
929 &hr_dev->qp_table.trrl_table);
930
931 err_unmap_irrl:
932 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
933
934 err_unmap_qp:
935 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
936
937 err_unmap_dmpt:
938 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
939
940 return ret;
941 }
942
hns_roce_teardown_hca(struct hns_roce_dev * hr_dev)943 static void hns_roce_teardown_hca(struct hns_roce_dev *hr_dev)
944 {
945 hns_roce_cleanup_bitmap(hr_dev);
946
947 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
948 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
949 mutex_destroy(&hr_dev->pgdir_mutex);
950 }
951
952 /**
953 * hns_roce_setup_hca - setup host channel adapter
954 * @hr_dev: pointer to hns roce device
955 * Return : int
956 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)957 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
958 {
959 struct device *dev = hr_dev->dev;
960 int ret;
961
962 spin_lock_init(&hr_dev->sm_lock);
963
964 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
965 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB) {
966 INIT_LIST_HEAD(&hr_dev->pgdir_list);
967 mutex_init(&hr_dev->pgdir_mutex);
968 }
969
970 hns_roce_init_uar_table(hr_dev);
971
972 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
973 if (ret) {
974 dev_err(dev, "failed to allocate priv_uar.\n");
975 goto err_uar_table_free;
976 }
977
978 ret = hns_roce_init_qp_table(hr_dev);
979 if (ret) {
980 dev_err(dev, "failed to init qp_table.\n");
981 goto err_uar_table_free;
982 }
983
984 hns_roce_init_pd_table(hr_dev);
985
986 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_XRC)
987 hns_roce_init_xrcd_table(hr_dev);
988
989 hns_roce_init_mr_table(hr_dev);
990
991 hns_roce_init_cq_table(hr_dev);
992
993 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ)
994 hns_roce_init_srq_table(hr_dev);
995
996 return 0;
997
998 err_uar_table_free:
999 ida_destroy(&hr_dev->uar_ida.ida);
1000 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_CQ_RECORD_DB ||
1001 hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_QP_RECORD_DB)
1002 mutex_destroy(&hr_dev->pgdir_mutex);
1003
1004 return ret;
1005 }
1006
check_and_get_armed_cq(struct list_head * cq_list,struct ib_cq * cq)1007 static void check_and_get_armed_cq(struct list_head *cq_list, struct ib_cq *cq)
1008 {
1009 struct hns_roce_cq *hr_cq = to_hr_cq(cq);
1010 unsigned long flags;
1011
1012 spin_lock_irqsave(&hr_cq->lock, flags);
1013 if (cq->comp_handler) {
1014 if (!hr_cq->is_armed) {
1015 hr_cq->is_armed = 1;
1016 list_add_tail(&hr_cq->node, cq_list);
1017 }
1018 }
1019 spin_unlock_irqrestore(&hr_cq->lock, flags);
1020 }
1021
hns_roce_handle_device_err(struct hns_roce_dev * hr_dev)1022 void hns_roce_handle_device_err(struct hns_roce_dev *hr_dev)
1023 {
1024 struct hns_roce_qp *hr_qp;
1025 struct hns_roce_cq *hr_cq;
1026 struct list_head cq_list;
1027 unsigned long flags_qp;
1028 unsigned long flags;
1029
1030 INIT_LIST_HEAD(&cq_list);
1031
1032 spin_lock_irqsave(&hr_dev->qp_list_lock, flags);
1033 list_for_each_entry(hr_qp, &hr_dev->qp_list, node) {
1034 spin_lock_irqsave(&hr_qp->sq.lock, flags_qp);
1035 if (hr_qp->sq.tail != hr_qp->sq.head)
1036 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.send_cq);
1037 spin_unlock_irqrestore(&hr_qp->sq.lock, flags_qp);
1038
1039 spin_lock_irqsave(&hr_qp->rq.lock, flags_qp);
1040 if ((!hr_qp->ibqp.srq) && (hr_qp->rq.tail != hr_qp->rq.head))
1041 check_and_get_armed_cq(&cq_list, hr_qp->ibqp.recv_cq);
1042 spin_unlock_irqrestore(&hr_qp->rq.lock, flags_qp);
1043 }
1044
1045 list_for_each_entry(hr_cq, &cq_list, node)
1046 hns_roce_cq_completion(hr_dev, hr_cq->cqn);
1047
1048 spin_unlock_irqrestore(&hr_dev->qp_list_lock, flags);
1049 }
1050
hns_roce_alloc_dfx_cnt(struct hns_roce_dev * hr_dev)1051 static int hns_roce_alloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1052 {
1053 hr_dev->dfx_cnt = kvcalloc(HNS_ROCE_DFX_CNT_TOTAL, sizeof(atomic64_t),
1054 GFP_KERNEL);
1055 if (!hr_dev->dfx_cnt)
1056 return -ENOMEM;
1057
1058 return 0;
1059 }
1060
hns_roce_dealloc_dfx_cnt(struct hns_roce_dev * hr_dev)1061 static void hns_roce_dealloc_dfx_cnt(struct hns_roce_dev *hr_dev)
1062 {
1063 kvfree(hr_dev->dfx_cnt);
1064 }
1065
hns_roce_init(struct hns_roce_dev * hr_dev)1066 int hns_roce_init(struct hns_roce_dev *hr_dev)
1067 {
1068 struct device *dev = hr_dev->dev;
1069 int ret;
1070
1071 hr_dev->is_reset = false;
1072
1073 ret = hns_roce_alloc_dfx_cnt(hr_dev);
1074 if (ret)
1075 return ret;
1076
1077 if (hr_dev->hw->cmq_init) {
1078 ret = hr_dev->hw->cmq_init(hr_dev);
1079 if (ret) {
1080 dev_err(dev, "init RoCE Command Queue failed!\n");
1081 goto error_failed_alloc_dfx_cnt;
1082 }
1083 }
1084
1085 ret = hr_dev->hw->hw_profile(hr_dev);
1086 if (ret) {
1087 dev_err(dev, "get RoCE engine profile failed!\n");
1088 goto error_failed_cmd_init;
1089 }
1090
1091 ret = hns_roce_cmd_init(hr_dev);
1092 if (ret) {
1093 dev_err(dev, "cmd init failed!\n");
1094 goto error_failed_cmd_init;
1095 }
1096
1097 /* EQ depends on poll mode, event mode depends on EQ */
1098 ret = hr_dev->hw->init_eq(hr_dev);
1099 if (ret) {
1100 dev_err(dev, "eq init failed!\n");
1101 goto error_failed_eq_table;
1102 }
1103
1104 if (hr_dev->cmd_mod) {
1105 ret = hns_roce_cmd_use_events(hr_dev);
1106 if (ret)
1107 dev_warn(dev,
1108 "Cmd event mode failed, set back to poll!\n");
1109 }
1110
1111 ret = hns_roce_init_hem(hr_dev);
1112 if (ret) {
1113 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
1114 goto error_failed_init_hem;
1115 }
1116
1117 ret = hns_roce_setup_hca(hr_dev);
1118 if (ret) {
1119 dev_err(dev, "setup hca failed!\n");
1120 goto error_failed_setup_hca;
1121 }
1122
1123 if (hr_dev->hw->hw_init) {
1124 ret = hr_dev->hw->hw_init(hr_dev);
1125 if (ret) {
1126 dev_err(dev, "hw_init failed!\n");
1127 goto error_failed_engine_init;
1128 }
1129 }
1130
1131 INIT_LIST_HEAD(&hr_dev->qp_list);
1132 spin_lock_init(&hr_dev->qp_list_lock);
1133 INIT_LIST_HEAD(&hr_dev->dip_list);
1134 spin_lock_init(&hr_dev->dip_list_lock);
1135
1136 ret = hns_roce_register_device(hr_dev);
1137 if (ret)
1138 goto error_failed_register_device;
1139
1140 hns_roce_register_debugfs(hr_dev);
1141
1142 return 0;
1143
1144 error_failed_register_device:
1145 if (hr_dev->hw->hw_exit)
1146 hr_dev->hw->hw_exit(hr_dev);
1147
1148 error_failed_engine_init:
1149 hns_roce_teardown_hca(hr_dev);
1150
1151 error_failed_setup_hca:
1152 hns_roce_cleanup_hem(hr_dev);
1153
1154 error_failed_init_hem:
1155 if (hr_dev->cmd_mod)
1156 hns_roce_cmd_use_polling(hr_dev);
1157 hr_dev->hw->cleanup_eq(hr_dev);
1158
1159 error_failed_eq_table:
1160 hns_roce_cmd_cleanup(hr_dev);
1161
1162 error_failed_cmd_init:
1163 if (hr_dev->hw->cmq_exit)
1164 hr_dev->hw->cmq_exit(hr_dev);
1165
1166 error_failed_alloc_dfx_cnt:
1167 hns_roce_dealloc_dfx_cnt(hr_dev);
1168
1169 return ret;
1170 }
1171
hns_roce_exit(struct hns_roce_dev * hr_dev)1172 void hns_roce_exit(struct hns_roce_dev *hr_dev)
1173 {
1174 hns_roce_unregister_debugfs(hr_dev);
1175 hns_roce_unregister_device(hr_dev);
1176
1177 if (hr_dev->hw->hw_exit)
1178 hr_dev->hw->hw_exit(hr_dev);
1179 hns_roce_teardown_hca(hr_dev);
1180 hns_roce_cleanup_hem(hr_dev);
1181
1182 if (hr_dev->cmd_mod)
1183 hns_roce_cmd_use_polling(hr_dev);
1184
1185 hr_dev->hw->cleanup_eq(hr_dev);
1186 hns_roce_cmd_cleanup(hr_dev);
1187 if (hr_dev->hw->cmq_exit)
1188 hr_dev->hw->cmq_exit(hr_dev);
1189 hns_roce_dealloc_dfx_cnt(hr_dev);
1190 }
1191
1192 MODULE_LICENSE("Dual BSD/GPL");
1193 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
1194 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
1195 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
1196 MODULE_DESCRIPTION("HNS RoCE Driver");
1197