1 /* 2 * Copyright (c) 2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #ifndef _HAL_9224_TX_H_ 20 #define _HAL_9224_TX_H_ 21 22 #include "tcl_data_cmd.h" 23 #include "phyrx_rssi_legacy.h" 24 #include "hal_internal.h" 25 #include "qdf_trace.h" 26 #include "hal_rx.h" 27 #include "hal_tx.h" 28 #include "hal_api_mon.h" 29 #include <hal_be_tx.h> 30 31 #define DSCP_TID_TABLE_SIZE 24 32 #define NUM_WORDS_PER_DSCP_TID_TABLE (DSCP_TID_TABLE_SIZE / 4) 33 #define HAL_TX_NUM_DSCP_REGISTER_SIZE 32 34 35 /** 36 * hal_tx_ppe2tcl_ring_halt_get_9224() - Get ring halt for the ppe2tcl ring 37 * @hal_soc: HAL SoC context 38 * 39 * Return: Ring halt status. 40 */ 41 static uint32_t hal_tx_ppe2tcl_ring_halt_get_9224(hal_soc_handle_t hal_soc) 42 { 43 uint32_t cmn_reg_addr; 44 uint32_t regval; 45 struct hal_soc *soc = (struct hal_soc *)hal_soc; 46 47 cmn_reg_addr = 48 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 49 50 /* Get RING_HALT status */ 51 regval = HAL_REG_READ(soc, cmn_reg_addr); 52 return (regval & 53 (1 << 54 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT)); 55 } 56 57 /** 58 * hal_tx_ppe2tcl_ring_halt_set_9224() - Enable ring halt for the ppe2tcl ring 59 * @hal_soc: HAL SoC context 60 * 61 * Return: none 62 */ 63 static void hal_tx_ppe2tcl_ring_halt_set_9224(hal_soc_handle_t hal_soc) 64 { 65 uint32_t cmn_reg_addr; 66 uint32_t regval; 67 struct hal_soc *soc = (struct hal_soc *)hal_soc; 68 69 cmn_reg_addr = 70 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 71 72 /* Enable RING_HALT */ 73 regval = HAL_REG_READ(soc, cmn_reg_addr); 74 regval |= 75 (1 << 76 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); 77 78 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 79 } 80 81 /** 82 * hal_tx_ppe2tcl_ring_halt_reset_9224() - Disable ring halt for the ppe2tcl 83 * ring 84 * @hal_soc: HAL SoC context 85 * 86 * Return: none 87 */ 88 static void hal_tx_ppe2tcl_ring_halt_reset_9224(hal_soc_handle_t hal_soc) 89 { 90 uint32_t cmn_reg_addr; 91 uint32_t regval; 92 struct hal_soc *soc = (struct hal_soc *)hal_soc; 93 94 cmn_reg_addr = 95 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 96 97 /* Disable RING_HALT */ 98 regval = HAL_REG_READ(soc, cmn_reg_addr); 99 regval &= ~(1 << 100 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_SHFT); 101 102 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 103 } 104 105 /** 106 * hal_tx_ppe2tcl_ring_halt_done_9224() - Check if ring halt is done 107 * for ppe2tcl ring 108 * @hal_soc: HAL SoC context 109 * 110 * Return: true if halt done 111 */ 112 static bool hal_tx_ppe2tcl_ring_halt_done_9224(hal_soc_handle_t hal_soc) 113 { 114 uint32_t cmn_reg_addr; 115 uint32_t regval; 116 struct hal_soc *soc = (struct hal_soc *)hal_soc; 117 118 cmn_reg_addr = 119 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR(MAC_TCL_REG_REG_BASE); 120 121 regval = HAL_REG_READ(soc, cmn_reg_addr); 122 regval &= (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_PPE2TCL1_RNG_HALT_STAT_SHFT); 123 124 return(!!regval); 125 } 126 127 /** 128 * hal_tx_set_dscp_tid_map_9224() - Configure default DSCP to TID map table 129 * @hal_soc: HAL SoC context 130 * @map: DSCP-TID mapping table 131 * @id: mapping table ID - 0-31 132 * 133 * DSCP are mapped to 8 TID values using TID values programmed 134 * in any of the 32 DSCP_TID_MAPS (id = 0-31). 135 * 136 * Return: none 137 */ 138 static void hal_tx_set_dscp_tid_map_9224(struct hal_soc *hal_soc, uint8_t *map, 139 uint8_t id) 140 { 141 int i; 142 uint32_t addr, cmn_reg_addr; 143 uint32_t value = 0, regval; 144 uint8_t val[DSCP_TID_TABLE_SIZE], cnt = 0; 145 146 struct hal_soc *soc = (struct hal_soc *)hal_soc; 147 148 if (id >= HAL_MAX_HW_DSCP_TID_V2_MAPS) 149 return; 150 151 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 152 MAC_TCL_REG_REG_BASE); 153 154 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 155 MAC_TCL_REG_REG_BASE, 156 id * NUM_WORDS_PER_DSCP_TID_TABLE); 157 158 /* Enable read/write access */ 159 regval = HAL_REG_READ(soc, cmn_reg_addr); 160 regval |= 161 (1 << 162 HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 163 164 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 165 166 /* Write 8 (24 bits) DSCP-TID mappings in each iteration */ 167 for (i = 0; i < 64; i += 8) { 168 value = (map[i] | 169 (map[i + 1] << 0x3) | 170 (map[i + 2] << 0x6) | 171 (map[i + 3] << 0x9) | 172 (map[i + 4] << 0xc) | 173 (map[i + 5] << 0xf) | 174 (map[i + 6] << 0x12) | 175 (map[i + 7] << 0x15)); 176 177 qdf_mem_copy(&val[cnt], (void *)&value, 3); 178 cnt += 3; 179 } 180 181 for (i = 0; i < DSCP_TID_TABLE_SIZE; i += 4) { 182 regval = *(uint32_t *)(val + i); 183 HAL_REG_WRITE(soc, addr, 184 (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 185 addr += 4; 186 } 187 188 /* Disable read/write access */ 189 regval = HAL_REG_READ(soc, cmn_reg_addr); 190 regval &= 191 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 192 193 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 194 } 195 196 /** 197 * hal_tx_update_dscp_tid_9224() - Update the dscp tid map table as updated 198 * by the user 199 * @soc: HAL SoC context 200 * @tid: TID 201 * @id: MAP ID 202 * @dscp: DSCP 203 * 204 * Return: void 205 */ 206 static void hal_tx_update_dscp_tid_9224(struct hal_soc *soc, uint8_t tid, 207 uint8_t id, uint8_t dscp) 208 { 209 uint32_t addr, addr1, cmn_reg_addr; 210 uint32_t start_value = 0, end_value = 0; 211 uint32_t regval; 212 uint8_t end_bits = 0; 213 uint8_t start_bits = 0; 214 uint32_t start_index, end_index; 215 216 cmn_reg_addr = HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_ADDR( 217 MAC_TCL_REG_REG_BASE); 218 219 addr = HWIO_TCL_R0_DSCP_TID_MAP_n_ADDR( 220 MAC_TCL_REG_REG_BASE, 221 id * NUM_WORDS_PER_DSCP_TID_TABLE); 222 223 start_index = dscp * HAL_TX_BITS_PER_TID; 224 end_index = (start_index + (HAL_TX_BITS_PER_TID - 1)) 225 % HAL_TX_NUM_DSCP_REGISTER_SIZE; 226 start_index = start_index % HAL_TX_NUM_DSCP_REGISTER_SIZE; 227 addr += (4 * ((dscp * HAL_TX_BITS_PER_TID) / 228 HAL_TX_NUM_DSCP_REGISTER_SIZE)); 229 230 if (end_index < start_index) { 231 end_bits = end_index + 1; 232 start_bits = HAL_TX_BITS_PER_TID - end_bits; 233 start_value = tid << start_index; 234 end_value = tid >> start_bits; 235 addr1 = addr + 4; 236 } else { 237 start_bits = HAL_TX_BITS_PER_TID - end_bits; 238 start_value = tid << start_index; 239 addr1 = 0; 240 } 241 242 /* Enable read/write access */ 243 regval = HAL_REG_READ(soc, cmn_reg_addr); 244 regval |= 245 (1 << HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_SHFT); 246 247 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 248 249 regval = HAL_REG_READ(soc, addr); 250 251 if (end_index < start_index) 252 regval &= (~0) >> start_bits; 253 else 254 regval &= ~(7 << start_index); 255 256 regval |= start_value; 257 258 HAL_REG_WRITE(soc, addr, (regval & HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 259 260 if (addr1) { 261 regval = HAL_REG_READ(soc, addr1); 262 regval &= (~0) << end_bits; 263 regval |= end_value; 264 265 HAL_REG_WRITE(soc, addr1, (regval & 266 HWIO_TCL_R0_DSCP_TID_MAP_n_RMSK)); 267 } 268 269 /* Disable read/write access */ 270 regval = HAL_REG_READ(soc, cmn_reg_addr); 271 regval &= 272 ~(HWIO_TCL_R0_CONS_RING_CMN_CTRL_REG_DSCP_TID_MAP_PROGRAM_EN_BMSK); 273 HAL_REG_WRITE(soc, cmn_reg_addr, regval); 274 } 275 276 #ifdef DP_TX_IMPLICIT_RBM_MAPPING 277 278 #define RBM_MAPPING_BMSK HWIO_TCL_R0_RBM_MAPPING0_SW2TCL1_RING_BMSK 279 #define RBM_MAPPING_SHFT HWIO_TCL_R0_RBM_MAPPING0_SW2TCL2_RING_SHFT 280 281 #define RBM_PPE2TCL_OFFSET \ 282 (HWIO_TCL_R0_RBM_MAPPING0_PPE2TCL1_RING_SHFT >> 2) 283 #define RBM_TCL_CMD_CREDIT_OFFSET \ 284 (HWIO_TCL_R0_RBM_MAPPING0_SW2TCL_CREDIT_RING_SHFT >> 2) 285 286 /** 287 * hal_tx_config_rbm_mapping_be_9224() - Update return buffer manager ring id 288 * @hal_soc_hdl: HAL SoC context 289 * @hal_ring_hdl: Source ring pointer 290 * @rbm_id: return buffer manager ring id 291 * 292 * Return: void 293 */ 294 static inline void 295 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 296 hal_ring_handle_t hal_ring_hdl, 297 uint8_t rbm_id) 298 { 299 struct hal_srng *srng = (struct hal_srng *)hal_ring_hdl; 300 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 301 uint32_t reg_addr = 0; 302 uint32_t reg_val = 0; 303 uint32_t val = 0; 304 uint8_t ring_num; 305 enum hal_ring_type ring_type; 306 307 ring_type = srng->ring_type; 308 ring_num = hal_soc->hw_srng_table[ring_type].start_ring_id; 309 ring_num = srng->ring_id - ring_num; 310 311 reg_addr = HWIO_TCL_R0_RBM_MAPPING0_ADDR(MAC_TCL_REG_REG_BASE); 312 313 if (ring_type == PPE2TCL) 314 ring_num = ring_num + RBM_PPE2TCL_OFFSET; 315 else if (ring_type == TCL_CMD_CREDIT) 316 ring_num = ring_num + RBM_TCL_CMD_CREDIT_OFFSET; 317 318 /* get current value stored in register address */ 319 val = HAL_REG_READ(hal_soc, reg_addr); 320 321 /* mask out other stored value */ 322 val &= (~(RBM_MAPPING_BMSK << (RBM_MAPPING_SHFT * ring_num))); 323 324 reg_val = val | ((RBM_MAPPING_BMSK & rbm_id) << 325 (RBM_MAPPING_SHFT * ring_num)); 326 327 /* write rbm mapped value to register address */ 328 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 329 } 330 #else 331 static inline void 332 hal_tx_config_rbm_mapping_be_9224(hal_soc_handle_t hal_soc_hdl, 333 hal_ring_handle_t hal_ring_hdl, 334 uint8_t rbm_id) 335 { 336 } 337 #endif 338 339 /** 340 * hal_tx_init_cmd_credit_ring_9224() - Initialize command/credit SRNG 341 * @hal_soc_hdl: Handle to HAL SoC structure 342 * @hal_ring_hdl: Handle to HAL SRNG structure 343 * 344 * Return: none 345 */ 346 static inline void 347 hal_tx_init_cmd_credit_ring_9224(hal_soc_handle_t hal_soc_hdl, 348 hal_ring_handle_t hal_ring_hdl) 349 { 350 } 351 352 /* TX MONITOR */ 353 #if defined(WLAN_PKT_CAPTURE_TX_2_0) && defined(TX_MONITOR_WORD_MASK) 354 355 #define TX_FES_SETUP_MASK 0x3 356 typedef struct tx_fes_setup_compact_9224 hal_tx_fes_setup_t; 357 struct tx_fes_setup_compact_9224 { 358 /* DWORD - 0 */ 359 uint32_t schedule_id; 360 /* DWORD - 1 */ 361 uint32_t reserved_1a : 7, // [0: 6] 362 transmit_start_reason : 3, // [7: 9] 363 reserved_1b : 13, // [10: 22] 364 number_of_users : 6, // [28: 23] 365 mu_type : 1, // [29] 366 reserved_1c : 2; // [30] 367 /* DWORD - 2 */ 368 uint32_t reserved_2a : 4, // [0: 3] 369 ndp_frame : 2, // [4: 5] 370 txbf : 1, // [6] 371 reserved_2b : 3, // [7: 9] 372 static_bandwidth : 3, // [12: 10] 373 reserved_2c : 1, // [13] 374 transmission_contains_mu_rts : 1, // [14] 375 reserved_2d : 17; // [15: 31] 376 /* DWORD - 3 */ 377 uint32_t reserved_3a : 15, // [0: 14] 378 mu_ndp : 1, // [15] 379 reserved_3b : 11, // [16: 26] 380 ndpa : 1, // [27] 381 reserved_3c : 4; // [28: 31] 382 }; 383 384 #define TX_PEER_ENTRY_MASK 0x103 385 typedef struct tx_peer_entry_compact_9224 hal_tx_peer_entry_t; 386 struct tx_peer_entry_compact_9224 { 387 /* DWORD - 0 */ 388 uint32_t mac_addr_a_31_0 : 32; 389 /* DWORD - 1 */ 390 uint32_t mac_addr_a_47_32 : 16, 391 mac_addr_b_15_0 : 16; 392 /* DWORD - 2 */ 393 uint32_t mac_addr_b_47_16 : 32; 394 /* DWORD - 3 */ 395 uint32_t reserved_3 : 32; 396 /* DWORD - 16 */ 397 uint32_t reserved_16 : 32; 398 /* DWORD - 17 */ 399 uint32_t multi_link_addr_crypto_enable : 1, 400 reserved_17_a : 15, 401 sw_peer_id : 16; 402 }; 403 404 #define TX_QUEUE_EXT_MASK 0x1 405 typedef struct tx_queue_ext_compact_9224 hal_tx_queue_ext_t; 406 struct tx_queue_ext_compact_9224 { 407 /* DWORD - 0 */ 408 uint32_t frame_ctl : 16, 409 qos_ctl : 16; 410 /* DWORD - 1 */ 411 uint32_t ampdu_flag : 1, 412 reserved_1 : 31; 413 }; 414 415 #define TX_MSDU_START_MASK 0x1 416 typedef struct tx_msdu_start_compact_9224 hal_tx_msdu_start_t; 417 struct tx_msdu_start_compact_9224 { 418 /* DWORD - 0 */ 419 uint32_t reserved_0 : 32; 420 /* DWORD - 1 */ 421 uint32_t reserved_1 : 32; 422 }; 423 424 #define TX_MPDU_START_MASK 0x3 425 typedef struct tx_mpdu_start_compact_9224 hal_tx_mpdu_start_t; 426 struct tx_mpdu_start_compact_9224 { 427 /* DWORD - 0 */ 428 uint32_t mpdu_length : 14, 429 frame_not_from_tqm : 1, 430 vht_control_present : 1, 431 mpdu_header_length : 8, 432 retry_count : 7, 433 wds : 1; 434 /* DWORD - 1 */ 435 uint32_t pn_31_0 : 32; 436 /* DWORD - 2 */ 437 uint32_t pn_47_32 : 16, 438 mpdu_sequence_number : 12, 439 raw_already_encrypted : 1, 440 frame_type : 2, 441 txdma_dropped_mpdu_warning : 1; 442 /* DWORD - 3 */ 443 uint32_t reserved_3 : 32; 444 }; 445 446 typedef struct rxpcu_user_setup_compact_9224 hal_rxpcu_user_setup_t; 447 struct rxpcu_user_setup_compact_9224 { 448 }; 449 450 #define TX_FES_STATUS_END_MASK 0x7 451 typedef struct tx_fes_status_end_compact_9224 hal_tx_fes_status_end_t; 452 struct tx_fes_status_end_compact_9224 { 453 /* DWORD - 0 */ 454 uint32_t reserved_0 : 32; 455 /* DWORD - 1 */ 456 struct { 457 uint16_t phytx_abort_reason : 8, 458 user_number : 6, 459 reserved_1a : 2; 460 } phytx_abort_request_info_details; 461 uint16_t reserved_1b : 12, 462 phytx_abort_request_info_valid : 1, 463 reserved_1c : 3; 464 /* DWORD - 2 */ 465 uint32_t start_of_frame_timestamp_15_0 : 16, 466 start_of_frame_timestamp_31_16 : 16; 467 /* DWORD - 3 */ 468 uint32_t end_of_frame_timestamp_15_0 : 16, 469 end_of_frame_timestamp_31_16 : 16; 470 /* DWORD - 4 */ 471 uint32_t terminate_ranging_sequence : 1, 472 reserved_4a : 7, 473 timing_status : 2, 474 response_type : 5, 475 r2r_end_status_to_follow : 1, 476 transmit_delay : 16; 477 /* DWORD - 5 */ 478 uint32_t reserved_5 : 32; 479 }; 480 481 #define RESPONSE_END_STATUS_MASK 0xD 482 typedef struct response_end_status_compact_9224 hal_response_end_status_t; 483 struct response_end_status_compact_9224 { 484 /* DWORD - 0 */ 485 uint32_t coex_bt_tx_while_wlan_tx : 1, 486 coex_wan_tx_while_wlan_tx : 1, 487 coex_wlan_tx_while_wlan_tx : 1, 488 global_data_underflow_warning : 1, 489 response_transmit_status : 4, 490 phytx_pkt_end_info_valid : 1, 491 phytx_abort_request_info_valid : 1, 492 generated_response : 3, 493 mba_user_count : 7, 494 mba_fake_bitmap_count : 7, 495 coex_based_tx_bw : 3, 496 trig_response_related : 1, 497 dpdtrain_done : 1; 498 /* DWORD - 1 */ 499 uint32_t reserved_1 : 32; 500 /* DWORD - 4 */ 501 uint32_t reserved_4 : 32; 502 /* DWORD - 5 */ 503 uint32_t start_of_frame_timestamp_15_0 : 16, 504 start_of_frame_timestamp_31_16 : 16; 505 /* DWORD - 6 */ 506 uint32_t end_of_frame_timestamp_15_0 : 16, 507 end_of_frame_timestamp_31_16 : 16; 508 /* DWORD - 7 */ 509 uint32_t reserved_7 : 32; 510 }; 511 512 #define TX_FES_STATUS_PROT_MASK 0x2 513 typedef struct tx_fes_status_prot_compact_9224 hal_tx_fes_status_prot_t; 514 struct tx_fes_status_prot_compact_9224 { 515 /* DWORD - 2 */ 516 uint32_t start_of_frame_timestamp_15_0 : 16, 517 start_of_frame_timestamp_31_16 : 16; 518 /* DWROD - 3 */ 519 uint32_t end_of_frame_timestamp_15_0 : 16, 520 end_of_frame_timestamp_31_16 : 16; 521 }; 522 523 #define PCU_PPDU_SETUP_INIT_MASK 0x1E800000 524 typedef struct pcu_ppdu_setup_init_compact_9224 hal_pcu_ppdu_setup_t; 525 struct pcu_ppdu_setup_init_compact_9224 { 526 /* DWORD - 46 */ 527 uint32_t reserved_46 : 32; 528 /* DWORD - 47 */ 529 uint32_t r2r_group_id : 6, 530 r2r_response_frame_type : 4, 531 r2r_sta_partial_aid : 11, 532 use_address_fields_for_protection : 1, 533 r2r_set_required_response_time : 1, 534 reserved_47 : 9; 535 /* DWORD - 50 */ 536 uint32_t reserved_50 : 32; 537 /* DWORD - 51 */ 538 uint32_t protection_frame_ad1_31_0 : 32; 539 /* DWORD - 52 */ 540 uint32_t protection_frame_ad1_47_32 : 16, 541 protection_frame_ad2_15_0 : 16; 542 /* DWORD - 53 */ 543 uint32_t protection_frame_ad2_47_16 : 32; 544 /* DWORD - 54 */ 545 uint32_t reserved_54 : 32; 546 /* DWORD - 55 */ 547 uint32_t protection_frame_ad3_31_0 : 32; 548 /* DWORD - 56 */ 549 uint32_t protection_frame_ad3_47_32 : 16, 550 protection_frame_ad4_15_0 : 16; 551 /* DWORD - 57 */ 552 uint32_t protection_frame_ad4_47_16 : 32; 553 }; 554 555 /** 556 * hal_txmon_get_word_mask_qcn9224() - api to get word mask for tx monitor 557 * @wmask: pointer to hal_txmon_word_mask_config_t 558 * 559 * Return: void 560 */ 561 static inline 562 void hal_txmon_get_word_mask_qcn9224(void *wmask) 563 { 564 hal_txmon_word_mask_config_t *word_mask = NULL; 565 566 word_mask = (hal_txmon_word_mask_config_t *)wmask; 567 568 word_mask->compaction_enable = 1; 569 word_mask->tx_fes_setup = TX_FES_SETUP_MASK; 570 word_mask->tx_peer_entry = TX_PEER_ENTRY_MASK; 571 word_mask->tx_queue_ext = TX_QUEUE_EXT_MASK; 572 word_mask->tx_msdu_start = TX_MSDU_START_MASK; 573 word_mask->pcu_ppdu_setup_init = PCU_PPDU_SETUP_INIT_MASK; 574 word_mask->tx_mpdu_start = TX_MPDU_START_MASK; 575 word_mask->rxpcu_user_setup = 0xFF; 576 word_mask->tx_fes_status_end = TX_FES_STATUS_END_MASK; 577 word_mask->response_end_status = RESPONSE_END_STATUS_MASK; 578 word_mask->tx_fes_status_prot = TX_FES_STATUS_PROT_MASK; 579 } 580 #endif 581 582 /** 583 * hal_tx_set_ppe_cmn_config_9224() - Set the PPE common config register 584 * @hal_soc_hdl: HAL SoC handle 585 * @cmn_cfg: Common PPE config 586 * 587 * Based on the PPE2TCL descriptor below errors, if the below register 588 * values are set then the packets are forward to Tx rule handler if 1'0b 589 * or to TCL exit base if 1'1b. 590 * 591 * Return: void 592 */ 593 static inline 594 void hal_tx_set_ppe_cmn_config_9224(hal_soc_handle_t hal_soc_hdl, 595 union hal_tx_cmn_config_ppe *cmn_cfg) 596 { 597 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 598 union hal_tx_cmn_config_ppe *cfg = 599 (union hal_tx_cmn_config_ppe *)cmn_cfg; 600 uint32_t reg_addr, reg_val = 0; 601 602 reg_addr = HWIO_TCL_R0_CMN_CONFIG_PPE_ADDR(MAC_TCL_REG_REG_BASE); 603 604 reg_val = HAL_REG_READ(soc, reg_addr); 605 606 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK; 607 reg_val |= 608 (cfg->drop_prec_err & 609 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_BMSK) << 610 HWIO_TCL_R0_CMN_CONFIG_PPE_DROP_PREC_ERR_EXCEPTION_SHFT; 611 612 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK; 613 reg_val |= 614 (cfg->fake_mac_hdr & 615 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_BMSK) << 616 HWIO_TCL_R0_CMN_CONFIG_PPE_FAKE_MAC_HDR_EXCEPTION_SHFT; 617 618 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK; 619 reg_val |= 620 (cfg->cpu_code_inv & 621 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_BMSK) << 622 HWIO_TCL_R0_CMN_CONFIG_PPE_CPU_CODE_VALID_EXCEPTION_SHFT; 623 624 reg_val &= ~HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK; 625 reg_val |= 626 (cfg->l3_l4_err & 627 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_BMSK) << 628 HWIO_TCL_R0_CMN_CONFIG_PPE_L3_L4_CSUM_ERR_EXCEPTION_SHFT; 629 630 HAL_REG_WRITE(soc, reg_addr, reg_val); 631 } 632 633 /** 634 * hal_tx_set_ppe_vp_entry_9224() - Set the PPE VP entry 635 * @hal_soc_hdl: HAL SoC handle 636 * @cfg: PPE VP config 637 * @ppe_vp_idx : PPE VP index to the table 638 * 639 * Return: void 640 */ 641 static inline 642 void hal_tx_set_ppe_vp_entry_9224(hal_soc_handle_t hal_soc_hdl, 643 union hal_tx_ppe_vp_config *cfg, 644 int ppe_vp_idx) 645 { 646 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 647 uint32_t reg_addr; 648 649 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 650 ppe_vp_idx); 651 652 HAL_REG_WRITE(soc, reg_addr, cfg->val); 653 } 654 655 /** 656 * hal_ppeds_cfg_ast_override_map_reg_9224() - Set the PPE index mapping table 657 * @hal_soc_hdl: HAL SoC context 658 * @idx: index into the table 659 * @idx_map: HAL PPE INDESX MAPPING config 660 * 661 * Return: void 662 */ 663 static inline void 664 hal_ppeds_cfg_ast_override_map_reg_9224(hal_soc_handle_t hal_soc_hdl, 665 uint8_t idx, 666 union hal_tx_ppe_idx_map_config *idx_map) 667 { 668 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 669 uint32_t reg_addr; 670 671 reg_addr = 672 HWIO_TCL_R0_PPE_INDEX_MAPPING_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 673 idx); 674 675 HAL_REG_WRITE(soc, reg_addr, idx_map->val); 676 } 677 678 /** 679 * hal_tx_set_ppe_pri2tid_map_9224() - Set PPE PRI to TID map 680 * @hal_soc_hdl: HAL SoC handle 681 * @val : PRI to TID value 682 * @map_no: Map number 683 * 684 * Return: void 685 */ 686 static inline 687 void hal_tx_set_ppe_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 688 uint32_t val, uint8_t map_no) 689 { 690 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 691 uint32_t reg_addr, reg_val = 0; 692 693 if (map_no == 0) 694 reg_addr = 695 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 696 else 697 reg_addr = 698 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 699 700 reg_val |= val; 701 HAL_REG_WRITE(soc, reg_addr, reg_val); 702 } 703 704 /** 705 * hal_tx_enable_pri2tid_map_9224() - Enable PRI to TID map 706 * @hal_soc_hdl: HAL SoC handle 707 * @val: PRI to TID value 708 * @ppe_vp_idx: Map number 709 * 710 * Return: void 711 */ 712 static inline 713 void hal_tx_enable_pri2tid_map_9224(hal_soc_handle_t hal_soc_hdl, 714 bool val, uint8_t ppe_vp_idx) 715 { 716 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 717 uint32_t reg_addr, reg_val = 0; 718 719 reg_addr = HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_ADDR(MAC_TCL_REG_REG_BASE, 720 ppe_vp_idx); 721 722 /* 723 * Drop precedence is enabled by default. 724 */ 725 reg_val = HAL_REG_READ(soc, reg_addr); 726 727 reg_val &= 728 ~HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK; 729 730 reg_val |= 731 (val & 732 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_BMSK) << 733 HWIO_TCL_R0_PPE_VP_CONFIG_TABLE_n_USE_PPE_INT_PRI_FOR_TID_SHFT; 734 735 HAL_REG_WRITE(soc, reg_addr, reg_val); 736 } 737 738 /** 739 * hal_tx_update_ppe_pri2tid_9224() - Update PPE PRI to TID 740 * @hal_soc_hdl: HAL SoC handle 741 * @pri: INT_PRI 742 * @tid: Wi-Fi TID 743 * 744 * Return: void 745 */ 746 static inline 747 void hal_tx_update_ppe_pri2tid_9224(hal_soc_handle_t hal_soc_hdl, 748 uint8_t pri, uint8_t tid) 749 { 750 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 751 uint32_t reg_addr, reg_val = 0, mask, shift; 752 753 /* 754 * INT_PRI 0..9 is in MAP0 register and INT_PRI 10..15 755 * is in MAP1 register. 756 */ 757 switch (pri) { 758 case 0 ... 9: 759 reg_addr = 760 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_ADDR(MAC_TCL_REG_REG_BASE); 761 mask = 762 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_BMSK << (0x3 * pri)); 763 shift = HWIO_TCL_R0_PPE_INT_PRI_TID_MAP0_INT_PRI_0_SHFT + (pri * 0x3); 764 break; 765 case 10 ... 15: 766 pri = pri - 10; 767 reg_addr = 768 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_ADDR(MAC_TCL_REG_REG_BASE); 769 mask = 770 (HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_BMSK << (0x3 * pri)); 771 shift = 772 HWIO_TCL_R0_PPE_INT_PRI_TID_MAP1_INT_PRI_10_SHFT + (pri * 0x3); 773 break; 774 default: 775 return; 776 } 777 778 reg_val = HAL_REG_READ(soc, reg_addr); 779 reg_val &= ~mask; 780 reg_val |= (pri << shift) & mask; 781 782 HAL_REG_WRITE(soc, reg_addr, reg_val); 783 } 784 #endif /* _HAL_9224_TX_H_ */ 785