1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_9_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \ 74 STATUS_HEADER_REO_STATUS_NUMBER 75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 76 STATUS_HEADER_TIMESTAMP 77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET 79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET 85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET 111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB 113 114 #define CE_WINDOW_ADDRESS_5018 \ 115 ((WFSS_CE_REG_BASE >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 116 117 #define UMAC_WINDOW_ADDRESS_5018 \ 118 ((SEQ_WCSS_UMAC_OFFSET >> WINDOW_SHIFT) & WINDOW_VALUE_MASK) 119 120 #define WINDOW_CONFIGURATION_VALUE_5018 \ 121 ((CE_WINDOW_ADDRESS_5018 << 6) |\ 122 (UMAC_WINDOW_ADDRESS_5018 << 12) | \ 123 WINDOW_ENABLE_BIT) 124 125 #define HOST_CE_MASK_VALUE 0xFF000000 126 127 #include "hal_5018_tx.h" 128 #include "hal_5018_rx.h" 129 #include <hal_generic_api.h> 130 #include "hal_li_rx.h" 131 #include "hal_li_api.h" 132 #include "hal_li_generic_api.h" 133 134 /** 135 * hal_rx_msdu_start_nss_get_5018() - API to get the NSS 136 * Interval from rx_msdu_start 137 * @buf: pointer to the start of RX PKT TLV header 138 * 139 * Return: uint32_t(nss) 140 */ 141 static uint32_t hal_rx_msdu_start_nss_get_5018(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 144 struct rx_msdu_start *msdu_start = 145 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 146 uint8_t mimo_ss_bitmap; 147 148 mimo_ss_bitmap = HAL_RX_MSDU_START_MIMO_SS_BITMAP(msdu_start); 149 150 return qdf_get_hweight8(mimo_ss_bitmap); 151 } 152 153 /** 154 * hal_rx_msdu_start_get_len_5018() - API to get the MSDU length 155 * from rx_msdu_start TLV 156 * @buf: pointer to the start of RX PKT TLV headers 157 * 158 * Return: (uint32_t)msdu length 159 */ 160 static uint32_t hal_rx_msdu_start_get_len_5018(uint8_t *buf) 161 { 162 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 163 struct rx_msdu_start *msdu_start = 164 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 165 uint32_t msdu_len; 166 167 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 168 169 return msdu_len; 170 } 171 172 /** 173 * hal_rx_mon_hw_desc_get_mpdu_status_5018() - Retrieve MPDU status 174 * 175 * @hw_desc_addr: Start address of Rx HW TLVs 176 * @rs: Status for monitor mode 177 * 178 * Return: void 179 */ 180 static void hal_rx_mon_hw_desc_get_mpdu_status_5018(void *hw_desc_addr, 181 struct mon_rx_status *rs) 182 { 183 struct rx_msdu_start *rx_msdu_start; 184 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 185 uint32_t reg_value; 186 const uint32_t sgi_hw_to_cdp[] = { 187 CDP_SGI_0_8_US, 188 CDP_SGI_0_4_US, 189 CDP_SGI_1_6_US, 190 CDP_SGI_3_2_US, 191 }; 192 193 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 194 195 HAL_RX_GET_MSDU_AGGREGATION(rx_desc, rs); 196 197 rs->ant_signal_db = HAL_RX_GET(rx_msdu_start, 198 RX_MSDU_START_5, USER_RSSI); 199 rs->is_stbc = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, STBC); 200 201 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, SGI); 202 rs->sgi = sgi_hw_to_cdp[reg_value]; 203 reg_value = HAL_RX_GET(rx_msdu_start, RX_MSDU_START_5, RECEPTION_TYPE); 204 rs->beamformed = (reg_value == HAL_RX_RECEPTION_TYPE_MU_MIMO) ? 1 : 0; 205 /* TODO: rs->beamformed should be set for SU beamforming also */ 206 } 207 208 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2) 209 /** 210 * hal_get_link_desc_size_5018() - API to get the link desc size 211 * 212 * Return: uint32_t 213 */ 214 static uint32_t hal_get_link_desc_size_5018(void) 215 { 216 return LINK_DESC_SIZE; 217 } 218 219 /** 220 * hal_rx_get_tlv_5018() - API to get the tlv 221 * @rx_tlv: TLV data extracted from the rx packet 222 * 223 * Return: uint8_t 224 */ 225 static uint8_t hal_rx_get_tlv_5018(void *rx_tlv) 226 { 227 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY_0, RECEIVE_BANDWIDTH); 228 } 229 230 /** 231 * hal_rx_mpdu_start_tlv_tag_valid_5018() - API to check if RX_MPDU_START 232 * tlv tag is valid 233 * 234 * @rx_tlv_hdr: start address of rx_pkt_tlvs 235 * 236 * Return: true if RX_MPDU_START is valid, else false. 237 */ 238 uint8_t hal_rx_mpdu_start_tlv_tag_valid_5018(void *rx_tlv_hdr) 239 { 240 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 241 uint32_t tlv_tag; 242 243 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv); 244 245 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 246 } 247 248 /** 249 * hal_rx_wbm_err_msdu_continuation_get_5018() - API to check if WBM 250 * msdu continuation bit is set 251 * 252 * @wbm_desc: wbm release ring descriptor 253 * 254 * Return: true if msdu continuation bit is set. 255 */ 256 uint8_t hal_rx_wbm_err_msdu_continuation_get_5018(void *wbm_desc) 257 { 258 uint32_t comp_desc = 259 *(uint32_t *)(((uint8_t *)wbm_desc) + 260 WBM_RELEASE_RING_3_MSDU_CONTINUATION_OFFSET); 261 262 return (comp_desc & WBM_RELEASE_RING_3_MSDU_CONTINUATION_MASK) >> 263 WBM_RELEASE_RING_3_MSDU_CONTINUATION_LSB; 264 } 265 266 static 267 void hal_compute_reo_remap_ix2_ix3_5018(uint32_t *ring, uint32_t num_rings, 268 uint32_t *remap1, uint32_t *remap2) 269 { 270 switch (num_rings) { 271 case 1: 272 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 273 HAL_REO_REMAP_IX2(ring[0], 17) | 274 HAL_REO_REMAP_IX2(ring[0], 18) | 275 HAL_REO_REMAP_IX2(ring[0], 19) | 276 HAL_REO_REMAP_IX2(ring[0], 20) | 277 HAL_REO_REMAP_IX2(ring[0], 21) | 278 HAL_REO_REMAP_IX2(ring[0], 22) | 279 HAL_REO_REMAP_IX2(ring[0], 23); 280 281 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 282 HAL_REO_REMAP_IX3(ring[0], 25) | 283 HAL_REO_REMAP_IX3(ring[0], 26) | 284 HAL_REO_REMAP_IX3(ring[0], 27) | 285 HAL_REO_REMAP_IX3(ring[0], 28) | 286 HAL_REO_REMAP_IX3(ring[0], 29) | 287 HAL_REO_REMAP_IX3(ring[0], 30) | 288 HAL_REO_REMAP_IX3(ring[0], 31); 289 break; 290 case 2: 291 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 292 HAL_REO_REMAP_IX2(ring[0], 17) | 293 HAL_REO_REMAP_IX2(ring[1], 18) | 294 HAL_REO_REMAP_IX2(ring[1], 19) | 295 HAL_REO_REMAP_IX2(ring[0], 20) | 296 HAL_REO_REMAP_IX2(ring[0], 21) | 297 HAL_REO_REMAP_IX2(ring[1], 22) | 298 HAL_REO_REMAP_IX2(ring[1], 23); 299 300 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 301 HAL_REO_REMAP_IX3(ring[0], 25) | 302 HAL_REO_REMAP_IX3(ring[1], 26) | 303 HAL_REO_REMAP_IX3(ring[1], 27) | 304 HAL_REO_REMAP_IX3(ring[0], 28) | 305 HAL_REO_REMAP_IX3(ring[0], 29) | 306 HAL_REO_REMAP_IX3(ring[1], 30) | 307 HAL_REO_REMAP_IX3(ring[1], 31); 308 break; 309 case 3: 310 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 311 HAL_REO_REMAP_IX2(ring[1], 17) | 312 HAL_REO_REMAP_IX2(ring[2], 18) | 313 HAL_REO_REMAP_IX2(ring[0], 19) | 314 HAL_REO_REMAP_IX2(ring[1], 20) | 315 HAL_REO_REMAP_IX2(ring[2], 21) | 316 HAL_REO_REMAP_IX2(ring[0], 22) | 317 HAL_REO_REMAP_IX2(ring[1], 23); 318 319 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 320 HAL_REO_REMAP_IX3(ring[0], 25) | 321 HAL_REO_REMAP_IX3(ring[1], 26) | 322 HAL_REO_REMAP_IX3(ring[2], 27) | 323 HAL_REO_REMAP_IX3(ring[0], 28) | 324 HAL_REO_REMAP_IX3(ring[1], 29) | 325 HAL_REO_REMAP_IX3(ring[2], 30) | 326 HAL_REO_REMAP_IX3(ring[0], 31); 327 break; 328 case 4: 329 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 330 HAL_REO_REMAP_IX2(ring[1], 17) | 331 HAL_REO_REMAP_IX2(ring[2], 18) | 332 HAL_REO_REMAP_IX2(ring[3], 19) | 333 HAL_REO_REMAP_IX2(ring[0], 20) | 334 HAL_REO_REMAP_IX2(ring[1], 21) | 335 HAL_REO_REMAP_IX2(ring[2], 22) | 336 HAL_REO_REMAP_IX2(ring[3], 23); 337 338 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 339 HAL_REO_REMAP_IX3(ring[1], 25) | 340 HAL_REO_REMAP_IX3(ring[2], 26) | 341 HAL_REO_REMAP_IX3(ring[3], 27) | 342 HAL_REO_REMAP_IX3(ring[0], 28) | 343 HAL_REO_REMAP_IX3(ring[1], 29) | 344 HAL_REO_REMAP_IX3(ring[2], 30) | 345 HAL_REO_REMAP_IX3(ring[3], 31); 346 break; 347 } 348 } 349 350 /** 351 * hal_rx_proc_phyrx_other_receive_info_tlv_5018() - API to get tlv info 352 * @rx_tlv_hdr: start address of rx_pkt_tlvs 353 * @ppdu_info_hdl: PPDU info handle to fill 354 * 355 * Return: uint32_t 356 */ 357 static inline 358 void hal_rx_proc_phyrx_other_receive_info_tlv_5018(void *rx_tlv_hdr, 359 void *ppdu_info_hdl) 360 { 361 } 362 363 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 364 static inline 365 void hal_rx_get_bb_info_5018(void *rx_tlv, 366 void *ppdu_info_hdl) 367 { 368 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 369 370 ppdu_info->cfr_info.bb_captured_channel = 371 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_CHANNEL); 372 373 ppdu_info->cfr_info.bb_captured_timeout = 374 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_TIMEOUT); 375 376 ppdu_info->cfr_info.bb_captured_reason = 377 HAL_RX_GET(rx_tlv, RXPCU_PPDU_END_INFO_3, BB_CAPTURED_REASON); 378 } 379 380 static inline 381 void hal_rx_get_rtt_info_5018(void *rx_tlv, 382 void *ppdu_info_hdl) 383 { 384 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl; 385 386 ppdu_info->cfr_info.rx_location_info_valid = 387 HAL_RX_GET(rx_tlv, PHYRX_PKT_END_13_RX_PKT_END_DETAILS, 388 RX_LOCATION_INFO_DETAILS_RX_LOCATION_INFO_VALID); 389 390 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 = 391 HAL_RX_GET(rx_tlv, 392 PHYRX_PKT_END_12_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 393 RTT_CHE_BUFFER_POINTER_LOW32); 394 395 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 = 396 HAL_RX_GET(rx_tlv, 397 PHYRX_PKT_END_11_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 398 RTT_CHE_BUFFER_POINTER_HIGH8); 399 400 ppdu_info->cfr_info.chan_capture_status = 401 HAL_RX_GET(rx_tlv, 402 PHYRX_PKT_END_13_RX_PKT_END_DETAILS_RX_LOCATION_INFO_DETAILS, 403 RESERVED_8); 404 } 405 #endif 406 407 /** 408 * hal_rx_dump_msdu_start_tlv_5018() - dump RX msdu_start TLV in structured 409 * human readable format. 410 * @pkttlvs: pointer to the pkttlvs. 411 * @dbg_level: log level. 412 * 413 * Return: void 414 */ 415 static void hal_rx_dump_msdu_start_tlv_5018(void *pkttlvs, 416 uint8_t dbg_level) 417 { 418 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; 419 struct rx_msdu_start *msdu_start = 420 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 421 422 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 423 "rx_msdu_start tlv - " 424 "rxpcu_mpdu_filter_in_category: %d " 425 "sw_frame_group_id: %d " 426 "phy_ppdu_id: %d " 427 "msdu_length: %d " 428 "ipsec_esp: %d " 429 "l3_offset: %d " 430 "ipsec_ah: %d " 431 "l4_offset: %d " 432 "msdu_number: %d " 433 "decap_format: %d " 434 "ipv4_proto: %d " 435 "ipv6_proto: %d " 436 "tcp_proto: %d " 437 "udp_proto: %d " 438 "ip_frag: %d " 439 "tcp_only_ack: %d " 440 "da_is_bcast_mcast: %d " 441 "ip4_protocol_ip6_next_header: %d " 442 "toeplitz_hash_2_or_4: %d " 443 "flow_id_toeplitz: %d " 444 "user_rssi: %d " 445 "pkt_type: %d " 446 "stbc: %d " 447 "sgi: %d " 448 "rate_mcs: %d " 449 "receive_bandwidth: %d " 450 "reception_type: %d " 451 "ppdu_start_timestamp: %d " 452 "sw_phy_meta_data: %d ", 453 msdu_start->rxpcu_mpdu_filter_in_category, 454 msdu_start->sw_frame_group_id, 455 msdu_start->phy_ppdu_id, 456 msdu_start->msdu_length, 457 msdu_start->ipsec_esp, 458 msdu_start->l3_offset, 459 msdu_start->ipsec_ah, 460 msdu_start->l4_offset, 461 msdu_start->msdu_number, 462 msdu_start->decap_format, 463 msdu_start->ipv4_proto, 464 msdu_start->ipv6_proto, 465 msdu_start->tcp_proto, 466 msdu_start->udp_proto, 467 msdu_start->ip_frag, 468 msdu_start->tcp_only_ack, 469 msdu_start->da_is_bcast_mcast, 470 msdu_start->ip4_protocol_ip6_next_header, 471 msdu_start->toeplitz_hash_2_or_4, 472 msdu_start->flow_id_toeplitz, 473 msdu_start->user_rssi, 474 msdu_start->pkt_type, 475 msdu_start->stbc, 476 msdu_start->sgi, 477 msdu_start->rate_mcs, 478 msdu_start->receive_bandwidth, 479 msdu_start->reception_type, 480 msdu_start->ppdu_start_timestamp, 481 msdu_start->sw_phy_meta_data); 482 } 483 484 /** 485 * hal_rx_dump_msdu_end_tlv_5018() - dump RX msdu_end TLV in structured 486 * human readable format. 487 * @pkttlvs: pointer to the pkttlvs. 488 * @dbg_level: log level. 489 * 490 * Return: void 491 */ 492 static void hal_rx_dump_msdu_end_tlv_5018(void *pkttlvs, 493 uint8_t dbg_level) 494 { 495 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)pkttlvs; 496 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 497 498 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level, 499 "rx_msdu_end tlv - " 500 "rxpcu_mpdu_filter_in_category: %d " 501 "sw_frame_group_id: %d " 502 "phy_ppdu_id: %d " 503 "ip_hdr_chksum: %d " 504 "reported_mpdu_length: %d " 505 "key_id_octet: %d " 506 "cce_super_rule: %d " 507 "cce_classify_not_done_truncat: %d " 508 "cce_classify_not_done_cce_dis: %d " 509 "rule_indication_31_0: %d " 510 "rule_indication_63_32: %d " 511 "da_offset: %d " 512 "sa_offset: %d " 513 "da_offset_valid: %d " 514 "sa_offset_valid: %d " 515 "ipv6_options_crc: %d " 516 "tcp_seq_number: %d " 517 "tcp_ack_number: %d " 518 "tcp_flag: %d " 519 "lro_eligible: %d " 520 "window_size: %d " 521 "tcp_udp_chksum: %d " 522 "sa_idx_timeout: %d " 523 "da_idx_timeout: %d " 524 "msdu_limit_error: %d " 525 "flow_idx_timeout: %d " 526 "flow_idx_invalid: %d " 527 "wifi_parser_error: %d " 528 "amsdu_parser_error: %d " 529 "sa_is_valid: %d " 530 "da_is_valid: %d " 531 "da_is_mcbc: %d " 532 "l3_header_padding: %d " 533 "first_msdu: %d " 534 "last_msdu: %d " 535 "sa_idx: %d " 536 "msdu_drop: %d " 537 "reo_destination_indication: %d " 538 "flow_idx: %d " 539 "fse_metadata: %d " 540 "cce_metadata: %d " 541 "sa_sw_peer_id: %d ", 542 msdu_end->rxpcu_mpdu_filter_in_category, 543 msdu_end->sw_frame_group_id, 544 msdu_end->phy_ppdu_id, 545 msdu_end->ip_hdr_chksum, 546 msdu_end->reported_mpdu_length, 547 msdu_end->key_id_octet, 548 msdu_end->cce_super_rule, 549 msdu_end->cce_classify_not_done_truncate, 550 msdu_end->cce_classify_not_done_cce_dis, 551 msdu_end->rule_indication_31_0, 552 msdu_end->rule_indication_63_32, 553 msdu_end->da_offset, 554 msdu_end->sa_offset, 555 msdu_end->da_offset_valid, 556 msdu_end->sa_offset_valid, 557 msdu_end->ipv6_options_crc, 558 msdu_end->tcp_seq_number, 559 msdu_end->tcp_ack_number, 560 msdu_end->tcp_flag, 561 msdu_end->lro_eligible, 562 msdu_end->window_size, 563 msdu_end->tcp_udp_chksum, 564 msdu_end->sa_idx_timeout, 565 msdu_end->da_idx_timeout, 566 msdu_end->msdu_limit_error, 567 msdu_end->flow_idx_timeout, 568 msdu_end->flow_idx_invalid, 569 msdu_end->wifi_parser_error, 570 msdu_end->amsdu_parser_error, 571 msdu_end->sa_is_valid, 572 msdu_end->da_is_valid, 573 msdu_end->da_is_mcbc, 574 msdu_end->l3_header_padding, 575 msdu_end->first_msdu, 576 msdu_end->last_msdu, 577 msdu_end->sa_idx, 578 msdu_end->msdu_drop, 579 msdu_end->reo_destination_indication, 580 msdu_end->flow_idx, 581 msdu_end->fse_metadata, 582 msdu_end->cce_metadata, 583 msdu_end->sa_sw_peer_id); 584 } 585 586 /** 587 * hal_rx_mpdu_start_tid_get_5018() - API to get tid from rx_msdu_start 588 * @buf: pointer to the start of RX PKT TLV header 589 * 590 * Return: uint32_t(tid value) 591 */ 592 static uint32_t hal_rx_mpdu_start_tid_get_5018(uint8_t *buf) 593 { 594 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 595 struct rx_mpdu_start *mpdu_start = 596 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 597 uint32_t tid; 598 599 tid = HAL_RX_MPDU_INFO_TID_GET(&mpdu_start->rx_mpdu_info_details); 600 601 return tid; 602 } 603 604 /** 605 * hal_rx_msdu_start_reception_type_get_5018() - API to get the reception type 606 * Interval from rx_msdu_start 607 * @buf: pointer to the start of RX PKT TLV header 608 * 609 * Return: uint32_t(reception_type) 610 */ 611 static uint32_t hal_rx_msdu_start_reception_type_get_5018(uint8_t *buf) 612 { 613 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 614 struct rx_msdu_start *msdu_start = 615 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 616 uint32_t reception_type; 617 618 reception_type = HAL_RX_MSDU_START_RECEPTION_TYPE_GET(msdu_start); 619 620 return reception_type; 621 } 622 623 /** 624 * hal_rx_msdu_end_da_idx_get_5018() - API to get da_idx from rx_msdu_end TLV 625 * @buf: pointer to the start of RX PKT TLV headers 626 * 627 * Return: da index 628 */ 629 static uint16_t hal_rx_msdu_end_da_idx_get_5018(uint8_t *buf) 630 { 631 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 632 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 633 uint16_t da_idx; 634 635 da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 636 637 return da_idx; 638 } 639 640 /** 641 * hal_rx_get_rx_fragment_number_5018() - API to retrieve rx fragment number 642 * @buf: Network buffer 643 * 644 * Return: rx fragment number 645 */ 646 static 647 uint8_t hal_rx_get_rx_fragment_number_5018(uint8_t *buf) 648 { 649 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 650 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 651 652 /* Return first 4 bits as fragment number */ 653 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 654 DOT11_SEQ_FRAG_MASK); 655 } 656 657 /** 658 * hal_rx_msdu_end_da_is_mcbc_get_5018() - API to check if pkt is MCBC 659 * from rx_msdu_end TLV 660 * @buf: pointer to the start of RX PKT TLV headers 661 * 662 * Return: da_is_mcbc 663 */ 664 static uint8_t 665 hal_rx_msdu_end_da_is_mcbc_get_5018(uint8_t *buf) 666 { 667 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 668 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 669 670 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 671 } 672 673 /** 674 * hal_rx_msdu_end_sa_is_valid_get_5018() - API to get_5018 the sa_is_valid 675 * bit from rx_msdu_end TLV 676 * @buf: pointer to the start of RX PKT TLV headers 677 * 678 * Return: sa_is_valid bit 679 */ 680 static uint8_t 681 hal_rx_msdu_end_sa_is_valid_get_5018(uint8_t *buf) 682 { 683 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 684 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 685 uint8_t sa_is_valid; 686 687 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 688 689 return sa_is_valid; 690 } 691 692 /** 693 * hal_rx_msdu_end_sa_idx_get_5018() - API to get_5018 the sa_idx from 694 * rx_msdu_end TLV 695 * @buf: pointer to the start of RX PKT TLV headers 696 * 697 * Return: sa_idx (SA AST index) 698 */ 699 static uint16_t hal_rx_msdu_end_sa_idx_get_5018(uint8_t *buf) 700 { 701 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 702 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 703 uint16_t sa_idx; 704 705 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 706 707 return sa_idx; 708 } 709 710 /** 711 * hal_rx_desc_is_first_msdu_5018() - Check if first msdu 712 * @hw_desc_addr: hardware descriptor address 713 * 714 * Return: 0 - success/ non-zero failure 715 */ 716 static uint32_t hal_rx_desc_is_first_msdu_5018(void *hw_desc_addr) 717 { 718 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 719 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 720 721 return HAL_RX_GET(msdu_end, RX_MSDU_END_10, FIRST_MSDU); 722 } 723 724 /** 725 * hal_rx_msdu_end_l3_hdr_padding_get_5018() - API to get_5018 the 726 * l3_header padding from 727 * rx_msdu_end TLV 728 * @buf: pointer to the start of RX PKT TLV headers 729 * 730 * Return: number of l3 header padding bytes 731 */ 732 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_5018(uint8_t *buf) 733 { 734 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 735 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 736 uint32_t l3_header_padding; 737 738 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 739 740 return l3_header_padding; 741 } 742 743 /** 744 * hal_rx_encryption_info_valid_5018() - Returns encryption type. 745 * @buf: rx_tlv_hdr of the received packet 746 * 747 * Return: encryption type 748 */ 749 inline uint32_t hal_rx_encryption_info_valid_5018(uint8_t *buf) 750 { 751 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 752 struct rx_mpdu_start *mpdu_start = 753 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 754 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 755 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 756 757 return encryption_info; 758 } 759 760 /** 761 * hal_rx_print_pn_5018() - Prints the PN of rx packet. 762 * @buf: rx_tlv_hdr of the received packet 763 * 764 * Return: void 765 */ 766 static void hal_rx_print_pn_5018(uint8_t *buf) 767 { 768 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 769 struct rx_mpdu_start *mpdu_start = 770 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 771 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 772 773 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 774 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 775 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 776 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 777 778 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 779 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 780 } 781 782 /** 783 * hal_rx_msdu_end_first_msdu_get_5018() - API to get first msdu status 784 * from rx_msdu_end TLV 785 * @buf: pointer to the start of RX PKT TLV headers 786 * 787 * Return: first_msdu 788 */ 789 static uint8_t hal_rx_msdu_end_first_msdu_get_5018(uint8_t *buf) 790 { 791 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 792 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 793 uint8_t first_msdu; 794 795 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 796 797 return first_msdu; 798 } 799 800 /** 801 * hal_rx_msdu_end_da_is_valid_get_5018() - API to check if da is valid 802 * from rx_msdu_end TLV 803 * @buf: pointer to the start of RX PKT TLV headers 804 * 805 * Return: da_is_valid 806 */ 807 static uint8_t hal_rx_msdu_end_da_is_valid_get_5018(uint8_t *buf) 808 { 809 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 810 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 811 uint8_t da_is_valid; 812 813 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 814 815 return da_is_valid; 816 } 817 818 /** 819 * hal_rx_msdu_end_last_msdu_get_5018() - API to get last msdu status 820 * from rx_msdu_end TLV 821 * @buf: pointer to the start of RX PKT TLV headers 822 * 823 * Return: last_msdu 824 */ 825 static uint8_t hal_rx_msdu_end_last_msdu_get_5018(uint8_t *buf) 826 { 827 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 828 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 829 uint8_t last_msdu; 830 831 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 832 833 return last_msdu; 834 } 835 836 /** 837 * hal_rx_get_mpdu_mac_ad4_valid_5018() - Retrieves if mpdu 4th addr is valid 838 * @buf: Network buffer 839 * 840 * Return: value of mpdu 4th address valid field 841 */ 842 inline bool hal_rx_get_mpdu_mac_ad4_valid_5018(uint8_t *buf) 843 { 844 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 845 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 846 bool ad4_valid = 0; 847 848 ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(rx_mpdu_info); 849 850 return ad4_valid; 851 } 852 853 /** 854 * hal_rx_mpdu_start_sw_peer_id_get_5018() - Retrieve sw peer_id 855 * @buf: network buffer 856 * 857 * Return: sw peer_id 858 */ 859 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_5018(uint8_t *buf) 860 { 861 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 862 struct rx_mpdu_start *mpdu_start = 863 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 864 865 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 866 &mpdu_start->rx_mpdu_info_details); 867 } 868 869 /** 870 * hal_rx_mpdu_get_to_ds_5018() - API to get the tods info from 871 * rx_mpdu_start 872 * @buf: pointer to the start of RX PKT TLV header 873 * 874 * Return: uint32_t(to_ds) 875 */ 876 static uint32_t hal_rx_mpdu_get_to_ds_5018(uint8_t *buf) 877 { 878 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 879 struct rx_mpdu_start *mpdu_start = 880 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 881 882 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 883 884 return HAL_RX_MPDU_GET_TODS(mpdu_info); 885 } 886 887 /** 888 * hal_rx_mpdu_get_fr_ds_5018() - API to get the from ds info from 889 * rx_mpdu_start 890 * @buf: pointer to the start of RX PKT TLV header 891 * 892 * Return: uint32_t(fr_ds) 893 */ 894 static uint32_t hal_rx_mpdu_get_fr_ds_5018(uint8_t *buf) 895 { 896 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 897 struct rx_mpdu_start *mpdu_start = 898 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 899 900 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 901 902 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 903 } 904 905 /** 906 * hal_rx_get_mpdu_frame_control_valid_5018() - Retrieves mpdu frame 907 * control valid 908 * @buf: Network buffer 909 * 910 * Return: value of frame control valid field 911 */ 912 static uint8_t hal_rx_get_mpdu_frame_control_valid_5018(uint8_t *buf) 913 { 914 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 915 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 916 917 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 918 } 919 920 /** 921 * hal_rx_get_mpdu_frame_control_field_5018() - Function to retrieve 922 * frame control field 923 * @buf: Network buffer 924 * 925 * Return: value of frame control field 926 */ 927 static uint16_t hal_rx_get_mpdu_frame_control_field_5018(uint8_t *buf) 928 { 929 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 930 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 931 uint16_t frame_ctrl = 0; 932 933 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 934 935 return frame_ctrl; 936 } 937 938 /** 939 * hal_rx_mpdu_get_addr1_5018() - API to check get address1 of the mpdu 940 * @buf: pointer to the start of RX PKT TLV headera 941 * @mac_addr: pointer to mac address 942 * 943 * Return: success/failure 944 */ 945 static QDF_STATUS hal_rx_mpdu_get_addr1_5018(uint8_t *buf, 946 uint8_t *mac_addr) 947 { 948 struct __attribute__((__packed__)) hal_addr1 { 949 uint32_t ad1_31_0; 950 uint16_t ad1_47_32; 951 }; 952 953 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 954 struct rx_mpdu_start *mpdu_start = 955 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 956 957 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 958 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 959 uint32_t mac_addr_ad1_valid; 960 961 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 962 963 if (mac_addr_ad1_valid) { 964 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 965 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 966 return QDF_STATUS_SUCCESS; 967 } 968 969 return QDF_STATUS_E_FAILURE; 970 } 971 972 /** 973 * hal_rx_mpdu_get_addr2_5018() - API to check get address2 of the mpdu 974 * in the packet 975 * @buf: pointer to the start of RX PKT TLV header 976 * @mac_addr: pointer to mac address 977 * 978 * Return: success/failure 979 */ 980 static QDF_STATUS hal_rx_mpdu_get_addr2_5018(uint8_t *buf, uint8_t *mac_addr) 981 { 982 struct __attribute__((__packed__)) hal_addr2 { 983 uint16_t ad2_15_0; 984 uint32_t ad2_47_16; 985 }; 986 987 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 988 struct rx_mpdu_start *mpdu_start = 989 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 990 991 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 992 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 993 uint32_t mac_addr_ad2_valid; 994 995 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 996 997 if (mac_addr_ad2_valid) { 998 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 999 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 1000 return QDF_STATUS_SUCCESS; 1001 } 1002 1003 return QDF_STATUS_E_FAILURE; 1004 } 1005 1006 /** 1007 * hal_rx_mpdu_get_addr3_5018() - API to get address3 of the mpdu 1008 * in the packet 1009 * @buf: pointer to the start of RX PKT TLV header 1010 * @mac_addr: pointer to mac address 1011 * 1012 * Return: success/failure 1013 */ 1014 static QDF_STATUS hal_rx_mpdu_get_addr3_5018(uint8_t *buf, uint8_t *mac_addr) 1015 { 1016 struct __attribute__((__packed__)) hal_addr3 { 1017 uint32_t ad3_31_0; 1018 uint16_t ad3_47_32; 1019 }; 1020 1021 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1022 struct rx_mpdu_start *mpdu_start = 1023 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1024 1025 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1026 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 1027 uint32_t mac_addr_ad3_valid; 1028 1029 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 1030 1031 if (mac_addr_ad3_valid) { 1032 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 1033 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 1034 return QDF_STATUS_SUCCESS; 1035 } 1036 1037 return QDF_STATUS_E_FAILURE; 1038 } 1039 1040 /** 1041 * hal_rx_mpdu_get_addr4_5018() - API to get address4 of the mpdu 1042 * in the packet 1043 * @buf: pointer to the start of RX PKT TLV header 1044 * @mac_addr: pointer to mac address 1045 * 1046 * Return: success/failure 1047 */ 1048 static QDF_STATUS hal_rx_mpdu_get_addr4_5018(uint8_t *buf, uint8_t *mac_addr) 1049 { 1050 struct __attribute__((__packed__)) hal_addr4 { 1051 uint32_t ad4_31_0; 1052 uint16_t ad4_47_32; 1053 }; 1054 1055 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1056 struct rx_mpdu_start *mpdu_start = 1057 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1058 1059 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 1060 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 1061 uint32_t mac_addr_ad4_valid; 1062 1063 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 1064 1065 if (mac_addr_ad4_valid) { 1066 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 1067 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 1068 return QDF_STATUS_SUCCESS; 1069 } 1070 1071 return QDF_STATUS_E_FAILURE; 1072 } 1073 1074 /** 1075 * hal_rx_get_mpdu_sequence_control_valid_5018() - Get mpdu sequence 1076 * control valid 1077 * @buf: Network buffer 1078 * 1079 * Return: value of sequence control valid field 1080 */ 1081 static uint8_t hal_rx_get_mpdu_sequence_control_valid_5018(uint8_t *buf) 1082 { 1083 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1084 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1085 1086 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 1087 } 1088 1089 /** 1090 * hal_rx_is_unicast_5018() - check packet is unicast frame or not. 1091 * @buf: pointer to rx pkt TLV. 1092 * 1093 * Return: true on unicast. 1094 */ 1095 static bool hal_rx_is_unicast_5018(uint8_t *buf) 1096 { 1097 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1098 struct rx_mpdu_start *mpdu_start = 1099 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1100 uint32_t grp_id; 1101 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1102 1103 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1104 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_OFFSET)), 1105 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_MASK, 1106 RX_MPDU_INFO_9_SW_FRAME_GROUP_ID_LSB)); 1107 1108 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 1109 } 1110 1111 /** 1112 * hal_rx_tid_get_5018() - get tid based on qos control valid. 1113 * @hal_soc_hdl: hal soc handle 1114 * @buf: pointer to rx pkt TLV. 1115 * 1116 * Return: tid 1117 */ 1118 static uint32_t hal_rx_tid_get_5018(hal_soc_handle_t hal_soc_hdl, uint8_t *buf) 1119 { 1120 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1121 struct rx_mpdu_start *mpdu_start = 1122 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1123 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 1124 uint8_t qos_control_valid = 1125 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 1126 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_OFFSET)), 1127 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_MASK, 1128 RX_MPDU_INFO_11_MPDU_QOS_CONTROL_VALID_LSB)); 1129 1130 if (qos_control_valid) 1131 return hal_rx_mpdu_start_tid_get_5018(buf); 1132 1133 return HAL_RX_NON_QOS_TID; 1134 } 1135 1136 /** 1137 * hal_rx_hw_desc_get_ppduid_get_5018() - retrieve ppdu id 1138 * @rx_tlv_hdr: rx tlv header 1139 * @rxdma_dst_ring_desc: rxdma HW descriptor 1140 * 1141 * Return: ppdu id 1142 */ 1143 static uint32_t hal_rx_hw_desc_get_ppduid_get_5018(void *rx_tlv_hdr, 1144 void *rxdma_dst_ring_desc) 1145 { 1146 struct reo_entrance_ring *reo_ent = rxdma_dst_ring_desc; 1147 1148 return HAL_RX_REO_ENT_PHY_PPDU_ID_GET(reo_ent); 1149 } 1150 1151 /** 1152 * hal_reo_status_get_header_5018() - Process reo desc info 1153 * @ring_desc: REO status ring descriptor 1154 * @b: tlv type info 1155 * @h1: Pointer to hal_reo_status_header where info to be stored 1156 * 1157 * Return - none. 1158 * 1159 */ 1160 static void hal_reo_status_get_header_5018(hal_ring_desc_t ring_desc, int b, 1161 void *h1) 1162 { 1163 uint32_t *d = (uint32_t *)ring_desc; 1164 uint32_t val1 = 0; 1165 struct hal_reo_status_header *h = 1166 (struct hal_reo_status_header *)h1; 1167 1168 /* Offsets of descriptor fields defined in HW headers start 1169 * from the field after TLV header 1170 */ 1171 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 1172 1173 switch (b) { 1174 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1175 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 1176 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1177 break; 1178 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1179 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 1180 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1181 break; 1182 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1183 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 1184 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1185 break; 1186 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1187 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 1188 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1189 break; 1190 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1191 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 1192 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1193 break; 1194 case HAL_REO_DESC_THRES_STATUS_TLV: 1195 val1 = 1196 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 1197 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1198 break; 1199 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1200 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 1201 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 1202 break; 1203 default: 1204 qdf_nofl_err("ERROR: Unknown tlv\n"); 1205 break; 1206 } 1207 h->cmd_num = 1208 HAL_GET_FIELD( 1209 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 1210 val1); 1211 h->exec_time = 1212 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1213 CMD_EXECUTION_TIME, val1); 1214 h->status = 1215 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 1216 REO_CMD_EXECUTION_STATUS, val1); 1217 switch (b) { 1218 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1219 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 1220 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1221 break; 1222 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1223 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 1224 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1225 break; 1226 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1227 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 1228 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1229 break; 1230 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1231 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 1232 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1233 break; 1234 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1235 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 1236 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1237 break; 1238 case HAL_REO_DESC_THRES_STATUS_TLV: 1239 val1 = 1240 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 1241 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1242 break; 1243 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1244 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 1245 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 1246 break; 1247 default: 1248 qdf_nofl_err("ERROR: Unknown tlv\n"); 1249 break; 1250 } 1251 h->tstamp = 1252 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 1253 } 1254 1255 /** 1256 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(): 1257 * Retrieve qos control valid bit from the tlv. 1258 * @buf: pointer to rx pkt TLV. 1259 * 1260 * Return: qos control value. 1261 */ 1262 static inline uint32_t 1263 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018(uint8_t *buf) 1264 { 1265 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1266 struct rx_mpdu_start *mpdu_start = 1267 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 1268 1269 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 1270 &mpdu_start->rx_mpdu_info_details); 1271 } 1272 1273 /** 1274 * hal_rx_msdu_end_sa_sw_peer_id_get_5018() - API to get the 1275 * sa_sw_peer_id from rx_msdu_end TLV 1276 * @buf: pointer to the start of RX PKT TLV headers 1277 * 1278 * Return: sa_sw_peer_id index 1279 */ 1280 static inline uint32_t 1281 hal_rx_msdu_end_sa_sw_peer_id_get_5018(uint8_t *buf) 1282 { 1283 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1284 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1285 1286 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1287 } 1288 1289 /** 1290 * hal_tx_desc_set_mesh_en_5018() - Set mesh_enable flag in Tx descriptor 1291 * @desc: Handle to Tx Descriptor 1292 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 1293 * enabling the interpretation of the 'Mesh Control Present' bit 1294 * (bit 8) of QoS Control (otherwise this bit is ignored), 1295 * For native WiFi frames, this indicates that a 'Mesh Control' field 1296 * is present between the header and the LLC. 1297 * 1298 * Return: void 1299 */ 1300 static inline 1301 void hal_tx_desc_set_mesh_en_5018(void *desc, uint8_t en) 1302 { 1303 HAL_SET_FLD(desc, TCL_DATA_CMD_5, MESH_ENABLE) |= 1304 HAL_TX_SM(TCL_DATA_CMD_5, MESH_ENABLE, en); 1305 } 1306 1307 static 1308 void *hal_rx_msdu0_buffer_addr_lsb_5018(void *link_desc_va) 1309 { 1310 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 1311 } 1312 1313 static 1314 void *hal_rx_msdu_desc_info_ptr_get_5018(void *msdu0) 1315 { 1316 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 1317 } 1318 1319 static 1320 void *hal_ent_mpdu_desc_info_5018(void *ent_ring_desc) 1321 { 1322 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 1323 } 1324 1325 static 1326 void *hal_dst_mpdu_desc_info_5018(void *dst_ring_desc) 1327 { 1328 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 1329 } 1330 1331 static 1332 uint8_t hal_rx_get_fc_valid_5018(uint8_t *buf) 1333 { 1334 return HAL_RX_GET_FC_VALID(buf); 1335 } 1336 1337 static uint8_t hal_rx_get_to_ds_flag_5018(uint8_t *buf) 1338 { 1339 return HAL_RX_GET_TO_DS_FLAG(buf); 1340 } 1341 1342 static uint8_t hal_rx_get_mac_addr2_valid_5018(uint8_t *buf) 1343 { 1344 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 1345 } 1346 1347 static uint8_t hal_rx_get_filter_category_5018(uint8_t *buf) 1348 { 1349 return HAL_RX_GET_FILTER_CATEGORY(buf); 1350 } 1351 1352 static uint32_t 1353 hal_rx_get_ppdu_id_5018(uint8_t *buf) 1354 { 1355 struct rx_mpdu_info *rx_mpdu_info; 1356 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 1357 1358 rx_mpdu_info = 1359 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 1360 1361 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 1362 } 1363 1364 /** 1365 * hal_reo_config_5018() - Set reo config parameters 1366 * @soc: hal soc handle 1367 * @reg_val: value to be set 1368 * @reo_params: reo parameters 1369 * 1370 * Return: void 1371 */ 1372 static void 1373 hal_reo_config_5018(struct hal_soc *soc, 1374 uint32_t reg_val, 1375 struct hal_reo_params *reo_params) 1376 { 1377 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 1378 } 1379 1380 /** 1381 * hal_rx_msdu_desc_info_get_ptr_5018() - Get msdu desc info ptr 1382 * @msdu_details_ptr: Pointer to msdu_details_ptr 1383 * 1384 * Return - Pointer to rx_msdu_desc_info structure. 1385 * 1386 */ 1387 static void *hal_rx_msdu_desc_info_get_ptr_5018(void *msdu_details_ptr) 1388 { 1389 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 1390 } 1391 1392 /** 1393 * hal_rx_link_desc_msdu0_ptr_5018 - Get pointer to rx_msdu details 1394 * @link_desc: Pointer to link desc 1395 * 1396 * Return - Pointer to rx_msdu_details structure 1397 * 1398 */ 1399 static void *hal_rx_link_desc_msdu0_ptr_5018(void *link_desc) 1400 { 1401 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 1402 } 1403 1404 /** 1405 * hal_rx_msdu_flow_idx_get_5018() - API to get flow index from 1406 * rx_msdu_end TLV 1407 * @buf: pointer to the start of RX PKT TLV headers 1408 * 1409 * Return: flow index value from MSDU END TLV 1410 */ 1411 static inline uint32_t hal_rx_msdu_flow_idx_get_5018(uint8_t *buf) 1412 { 1413 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1414 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1415 1416 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1417 } 1418 1419 /** 1420 * hal_rx_msdu_flow_idx_invalid_5018() - API to get flow index invalid 1421 * from rx_msdu_end TLV 1422 * @buf: pointer to the start of RX PKT TLV headers 1423 * 1424 * Return: flow index invalid value from MSDU END TLV 1425 */ 1426 static bool hal_rx_msdu_flow_idx_invalid_5018(uint8_t *buf) 1427 { 1428 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1429 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1430 1431 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1432 } 1433 1434 /** 1435 * hal_rx_msdu_flow_idx_timeout_5018() - API to get flow index timeout 1436 * from rx_msdu_end TLV 1437 * @buf: pointer to the start of RX PKT TLV headers 1438 * 1439 * Return: flow index timeout value from MSDU END TLV 1440 */ 1441 static bool hal_rx_msdu_flow_idx_timeout_5018(uint8_t *buf) 1442 { 1443 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1444 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1445 1446 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1447 } 1448 1449 /** 1450 * hal_rx_msdu_fse_metadata_get_5018() - API to get FSE metadata 1451 * from rx_msdu_end TLV 1452 * @buf: pointer to the start of RX PKT TLV headers 1453 * 1454 * Return: fse metadata value from MSDU END TLV 1455 */ 1456 static uint32_t hal_rx_msdu_fse_metadata_get_5018(uint8_t *buf) 1457 { 1458 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1459 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1460 1461 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 1462 } 1463 1464 /** 1465 * hal_rx_msdu_cce_metadata_get_5018() - API to get CCE metadata 1466 * from rx_msdu_end TLV 1467 * @buf: pointer to the start of RX PKT TLV headers 1468 * 1469 * Return: cce_metadata 1470 */ 1471 static uint16_t 1472 hal_rx_msdu_cce_metadata_get_5018(uint8_t *buf) 1473 { 1474 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1475 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1476 1477 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 1478 } 1479 1480 /** 1481 * hal_rx_msdu_get_flow_params_5018() - API to get flow index, flow index 1482 * invalid and flow index timeout from 1483 * rx_msdu_end TLV 1484 * @buf: pointer to the start of RX PKT TLV headers 1485 * @flow_invalid: pointer to return value of flow_idx_valid 1486 * @flow_timeout: pointer to return value of flow_idx_timeout 1487 * @flow_index: pointer to return value of flow_idx 1488 * 1489 * Return: none 1490 */ 1491 static inline void 1492 hal_rx_msdu_get_flow_params_5018(uint8_t *buf, 1493 bool *flow_invalid, 1494 bool *flow_timeout, 1495 uint32_t *flow_index) 1496 { 1497 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1498 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1499 1500 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1501 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1502 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1503 } 1504 1505 /** 1506 * hal_rx_tlv_get_tcp_chksum_5018() - API to get tcp checksum 1507 * @buf: rx_tlv_hdr 1508 * 1509 * Return: tcp checksum 1510 */ 1511 static uint16_t 1512 hal_rx_tlv_get_tcp_chksum_5018(uint8_t *buf) 1513 { 1514 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1515 } 1516 1517 /** 1518 * hal_rx_get_rx_sequence_5018() - Function to retrieve rx sequence number 1519 * @buf: Network buffer 1520 * 1521 * Return: rx sequence number 1522 */ 1523 static 1524 uint16_t hal_rx_get_rx_sequence_5018(uint8_t *buf) 1525 { 1526 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1527 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1528 1529 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1530 } 1531 1532 /** 1533 * hal_get_window_address_5018() - Function to get hp/tp address 1534 * @hal_soc: Pointer to hal_soc 1535 * @addr: address offset of register 1536 * 1537 * Return: modified address offset of register 1538 */ 1539 static inline qdf_iomem_t hal_get_window_address_5018(struct hal_soc *hal_soc, 1540 qdf_iomem_t addr) 1541 { 1542 uint32_t offset = addr - hal_soc->dev_base_addr; 1543 qdf_iomem_t new_offset; 1544 1545 /* 1546 * Check if offset lies within CE register range(0x08400000) 1547 * or UMAC/DP register range (0x00A00000). 1548 * If offset lies within CE register range, map it 1549 * into CE region. 1550 */ 1551 if (offset & HOST_CE_MASK_VALUE) { 1552 offset = offset - WFSS_CE_REG_BASE; 1553 new_offset = (hal_soc->dev_base_addr_ce + offset); 1554 1555 return new_offset; 1556 } else { 1557 /* 1558 * If offset lies within DP register range, 1559 * return the address as such 1560 */ 1561 return addr; 1562 } 1563 } 1564 1565 static inline void hal_write_window_register(struct hal_soc *hal_soc) 1566 { 1567 /* Write value into window configuration register */ 1568 qdf_iowrite32(hal_soc->dev_base_addr + WINDOW_REG_ADDRESS, 1569 WINDOW_CONFIGURATION_VALUE_5018); 1570 } 1571 1572 /** 1573 * hal_rx_msdu_packet_metadata_get_5018() - API to get the msdu 1574 * information from rx_msdu_end TLV 1575 * @buf: pointer to the start of RX PKT TLV headers 1576 * @msdu_pkt_metadata: pointer to the msdu info structure 1577 */ 1578 static void 1579 hal_rx_msdu_packet_metadata_get_5018(uint8_t *buf, 1580 void *msdu_pkt_metadata) 1581 { 1582 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1583 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1584 struct hal_rx_msdu_metadata *msdu_metadata = 1585 (struct hal_rx_msdu_metadata *)msdu_pkt_metadata; 1586 1587 msdu_metadata->l3_hdr_pad = 1588 HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 1589 msdu_metadata->sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 1590 msdu_metadata->da_idx = HAL_RX_MSDU_END_DA_IDX_GET(msdu_end); 1591 msdu_metadata->sa_sw_peer_id = 1592 HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 1593 } 1594 1595 /** 1596 * hal_rx_flow_setup_fse_5018() - Setup a flow search entry in HW FST 1597 * @rx_fst: Pointer to the Rx Flow Search Table 1598 * @table_offset: offset into the table where the flow is to be setup 1599 * @rx_flow: Flow Parameters 1600 * 1601 * Return: Success/Failure 1602 */ 1603 static void * 1604 hal_rx_flow_setup_fse_5018(uint8_t *rx_fst, uint32_t table_offset, 1605 uint8_t *rx_flow) 1606 { 1607 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1608 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1609 uint8_t *fse; 1610 bool fse_valid; 1611 1612 if (table_offset >= fst->max_entries) { 1613 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1614 "HAL FSE table offset %u exceeds max entries %u", 1615 table_offset, fst->max_entries); 1616 return NULL; 1617 } 1618 1619 fse = (uint8_t *)fst->base_vaddr + 1620 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1621 1622 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1623 1624 if (fse_valid) { 1625 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1626 "HAL FSE %pK already valid", fse); 1627 return NULL; 1628 } 1629 1630 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1631 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1632 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1633 1634 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1635 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1636 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1637 1638 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1639 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1640 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1641 1642 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1643 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1644 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1645 1646 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1647 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1648 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1649 1650 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1651 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1652 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1653 1654 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1655 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1656 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1657 1658 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1659 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1660 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1661 1662 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1663 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1664 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1665 (flow->tuple_info.dest_port)); 1666 1667 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1668 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1669 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1670 (flow->tuple_info.src_port)); 1671 1672 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1673 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1674 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1675 flow->tuple_info.l4_protocol); 1676 1677 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1678 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1679 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1680 flow->reo_destination_handler); 1681 1682 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1683 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1684 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1685 1686 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1687 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1688 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1689 flow->fse_metadata); 1690 1691 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION); 1692 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_INDICATION) |= 1693 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, 1694 REO_DESTINATION_INDICATION, 1695 flow->reo_destination_indication); 1696 1697 /* Reset all the other fields in FSE */ 1698 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1699 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, MSDU_DROP); 1700 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1701 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1702 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1703 1704 return fse; 1705 } 1706 1707 static void hal_hw_txrx_ops_attach_qca5018(struct hal_soc *hal_soc) 1708 { 1709 /* init and setup */ 1710 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1711 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1712 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1713 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1714 hal_soc->ops->hal_get_window_address = hal_get_window_address_5018; 1715 1716 /* tx */ 1717 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1718 hal_tx_desc_set_dscp_tid_table_id_5018; 1719 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5018; 1720 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5018; 1721 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_5018; 1722 hal_soc->ops->hal_tx_desc_set_buf_addr = 1723 hal_tx_desc_set_buf_addr_generic_li; 1724 hal_soc->ops->hal_tx_desc_set_search_type = 1725 hal_tx_desc_set_search_type_generic_li; 1726 hal_soc->ops->hal_tx_desc_set_search_index = 1727 hal_tx_desc_set_search_index_generic_li; 1728 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1729 hal_tx_desc_set_cache_set_num_generic_li; 1730 hal_soc->ops->hal_tx_comp_get_status = 1731 hal_tx_comp_get_status_generic_li; 1732 hal_soc->ops->hal_tx_comp_get_release_reason = 1733 hal_tx_comp_get_release_reason_generic_li; 1734 hal_soc->ops->hal_get_wbm_internal_error = 1735 hal_get_wbm_internal_error_generic_li; 1736 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_5018; 1737 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1738 hal_tx_init_cmd_credit_ring_5018; 1739 1740 /* rx */ 1741 hal_soc->ops->hal_rx_msdu_start_nss_get = 1742 hal_rx_msdu_start_nss_get_5018; 1743 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1744 hal_rx_mon_hw_desc_get_mpdu_status_5018; 1745 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5018; 1746 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1747 hal_rx_proc_phyrx_other_receive_info_tlv_5018; 1748 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5018; 1749 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1750 hal_rx_mpdu_start_tid_get_5018; 1751 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1752 hal_rx_msdu_start_reception_type_get_5018; 1753 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1754 hal_rx_msdu_end_da_idx_get_5018; 1755 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1756 hal_rx_msdu_desc_info_get_ptr_5018; 1757 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1758 hal_rx_link_desc_msdu0_ptr_5018; 1759 hal_soc->ops->hal_reo_status_get_header = 1760 hal_reo_status_get_header_5018; 1761 hal_soc->ops->hal_rx_status_get_tlv_info = 1762 hal_rx_status_get_tlv_info_generic_li; 1763 hal_soc->ops->hal_rx_wbm_err_info_get = 1764 hal_rx_wbm_err_info_get_generic_li; 1765 1766 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5018; 1767 hal_soc->ops->hal_rx_dump_rx_attention_tlv = 1768 hal_rx_dump_rx_attention_tlv_generic_li; 1769 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1770 hal_rx_dump_msdu_start_tlv_5018; 1771 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1772 hal_rx_dump_mpdu_start_tlv_generic_li; 1773 hal_soc->ops->hal_rx_dump_mpdu_end_tlv = 1774 hal_rx_dump_mpdu_end_tlv_generic_li; 1775 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv = 1776 hal_rx_dump_pkt_hdr_tlv_generic_li; 1777 1778 hal_soc->ops->hal_tx_set_pcp_tid_map = 1779 hal_tx_set_pcp_tid_map_generic_li; 1780 hal_soc->ops->hal_tx_update_pcp_tid_map = 1781 hal_tx_update_pcp_tid_generic_li; 1782 hal_soc->ops->hal_tx_set_tidmap_prty = 1783 hal_tx_update_tidmap_prty_generic_li; 1784 hal_soc->ops->hal_rx_get_rx_fragment_number = 1785 hal_rx_get_rx_fragment_number_5018; 1786 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1787 hal_rx_msdu_end_da_is_mcbc_get_5018; 1788 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1789 hal_rx_msdu_end_sa_is_valid_get_5018; 1790 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1791 hal_rx_msdu_end_sa_idx_get_5018; 1792 hal_soc->ops->hal_rx_desc_is_first_msdu = 1793 hal_rx_desc_is_first_msdu_5018; 1794 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1795 hal_rx_msdu_end_l3_hdr_padding_get_5018; 1796 hal_soc->ops->hal_rx_encryption_info_valid = 1797 hal_rx_encryption_info_valid_5018; 1798 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_5018; 1799 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1800 hal_rx_msdu_end_first_msdu_get_5018; 1801 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1802 hal_rx_msdu_end_da_is_valid_get_5018; 1803 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1804 hal_rx_msdu_end_last_msdu_get_5018; 1805 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1806 hal_rx_get_mpdu_mac_ad4_valid_5018; 1807 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1808 hal_rx_mpdu_start_sw_peer_id_get_5018; 1809 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1810 hal_rx_mpdu_peer_meta_data_get_li; 1811 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_5018; 1812 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_5018; 1813 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1814 hal_rx_get_mpdu_frame_control_valid_5018; 1815 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1816 hal_rx_get_mpdu_frame_control_field_5018; 1817 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_5018; 1818 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_5018; 1819 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_5018; 1820 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_5018; 1821 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1822 hal_rx_get_mpdu_sequence_control_valid_5018; 1823 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_5018; 1824 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_5018; 1825 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1826 hal_rx_hw_desc_get_ppduid_get_5018; 1827 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1828 hal_rx_mpdu_start_mpdu_qos_control_valid_get_5018; 1829 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1830 hal_rx_msdu_end_sa_sw_peer_id_get_5018; 1831 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1832 hal_rx_msdu0_buffer_addr_lsb_5018; 1833 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1834 hal_rx_msdu_desc_info_ptr_get_5018; 1835 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5018; 1836 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5018; 1837 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_5018; 1838 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_5018; 1839 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1840 hal_rx_get_mac_addr2_valid_5018; 1841 hal_soc->ops->hal_rx_get_filter_category = 1842 hal_rx_get_filter_category_5018; 1843 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_5018; 1844 hal_soc->ops->hal_reo_config = hal_reo_config_5018; 1845 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_5018; 1846 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1847 hal_rx_msdu_flow_idx_invalid_5018; 1848 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1849 hal_rx_msdu_flow_idx_timeout_5018; 1850 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1851 hal_rx_msdu_fse_metadata_get_5018; 1852 hal_soc->ops->hal_rx_msdu_cce_match_get = 1853 hal_rx_msdu_cce_match_get_li; 1854 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1855 hal_rx_msdu_cce_metadata_get_5018; 1856 hal_soc->ops->hal_rx_msdu_get_flow_params = 1857 hal_rx_msdu_get_flow_params_5018; 1858 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1859 hal_rx_tlv_get_tcp_chksum_5018; 1860 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_5018; 1861 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE) 1862 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5018; 1863 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5018; 1864 #endif 1865 /* rx - msdu fast path info fields */ 1866 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1867 hal_rx_msdu_packet_metadata_get_5018; 1868 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1869 hal_rx_mpdu_start_tlv_tag_valid_5018; 1870 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get = 1871 hal_rx_wbm_err_msdu_continuation_get_5018; 1872 1873 /* rx - TLV struct offsets */ 1874 hal_soc->ops->hal_rx_msdu_end_offset_get = hal_rx_msdu_end_offset_get_generic; 1875 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1876 hal_soc->ops->hal_rx_msdu_start_offset_get = hal_rx_msdu_start_offset_get_generic; 1877 hal_soc->ops->hal_rx_mpdu_start_offset_get = hal_rx_mpdu_start_offset_get_generic; 1878 hal_soc->ops->hal_rx_mpdu_end_offset_get = hal_rx_mpdu_end_offset_get_generic; 1879 #ifndef NO_RX_PKT_HDR_TLV 1880 hal_soc->ops->hal_rx_pkt_tlv_offset_get = hal_rx_pkt_tlv_offset_get_generic; 1881 #endif 1882 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5018; 1883 hal_soc->ops->hal_rx_flow_get_tuple_info = 1884 hal_rx_flow_get_tuple_info_li; 1885 hal_soc->ops->hal_rx_flow_delete_entry = 1886 hal_rx_flow_delete_entry_li; 1887 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1888 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = hal_compute_reo_remap_ix2_ix3_5018; 1889 hal_soc->ops->hal_setup_link_idle_list = 1890 hal_setup_link_idle_list_generic_li; 1891 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1892 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1893 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1894 hal_rx_tlv_decrypt_err_get_li; 1895 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1896 hal_rx_tlv_get_pkt_capture_flags_li; 1897 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1898 hal_rx_mpdu_info_ampdu_flag_get_li; 1899 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1900 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1901 hal_rx_msdu_start_get_len_5018; 1902 }; 1903 1904 struct hal_hw_srng_config hw_srng_table_5018[] = { 1905 /* TODO: max_rings can populated by querying HW capabilities */ 1906 { /* REO_DST */ 1907 .start_ring_id = HAL_SRNG_REO2SW1, 1908 .max_rings = 4, 1909 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1910 .lmac_ring = FALSE, 1911 .ring_dir = HAL_SRNG_DST_RING, 1912 .reg_start = { 1913 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1914 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1915 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1916 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1917 }, 1918 .reg_size = { 1919 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1920 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1921 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1922 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1923 }, 1924 .max_size = 1925 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1926 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1927 }, 1928 { /* REO_EXCEPTION */ 1929 /* Designating REO2TCL ring as exception ring. This ring is 1930 * similar to other REO2SW rings though it is named as REO2TCL. 1931 * Any of theREO2SW rings can be used as exception ring. 1932 */ 1933 .start_ring_id = HAL_SRNG_REO2TCL, 1934 .max_rings = 1, 1935 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1936 .lmac_ring = FALSE, 1937 .ring_dir = HAL_SRNG_DST_RING, 1938 .reg_start = { 1939 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1940 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1941 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1942 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1943 }, 1944 /* Single ring - provide ring size if multiple rings of this 1945 * type are supported 1946 */ 1947 .reg_size = {}, 1948 .max_size = 1949 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1950 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1951 }, 1952 { /* REO_REINJECT */ 1953 .start_ring_id = HAL_SRNG_SW2REO, 1954 .max_rings = 1, 1955 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1956 .lmac_ring = FALSE, 1957 .ring_dir = HAL_SRNG_SRC_RING, 1958 .reg_start = { 1959 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1960 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1961 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1962 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1963 }, 1964 /* Single ring - provide ring size if multiple rings of this 1965 * type are supported 1966 */ 1967 .reg_size = {}, 1968 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1969 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1970 }, 1971 { /* REO_CMD */ 1972 .start_ring_id = HAL_SRNG_REO_CMD, 1973 .max_rings = 1, 1974 .entry_size = (sizeof(struct tlv_32_hdr) + 1975 sizeof(struct reo_get_queue_stats)) >> 2, 1976 .lmac_ring = FALSE, 1977 .ring_dir = HAL_SRNG_SRC_RING, 1978 .reg_start = { 1979 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1980 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1981 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1982 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1983 }, 1984 /* Single ring - provide ring size if multiple rings of this 1985 * type are supported 1986 */ 1987 .reg_size = {}, 1988 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1989 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1990 }, 1991 { /* REO_STATUS */ 1992 .start_ring_id = HAL_SRNG_REO_STATUS, 1993 .max_rings = 1, 1994 .entry_size = (sizeof(struct tlv_32_hdr) + 1995 sizeof(struct reo_get_queue_stats_status)) >> 2, 1996 .lmac_ring = FALSE, 1997 .ring_dir = HAL_SRNG_DST_RING, 1998 .reg_start = { 1999 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 2000 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2001 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 2002 SEQ_WCSS_UMAC_REO_REG_OFFSET), 2003 }, 2004 /* Single ring - provide ring size if multiple rings of this 2005 * type are supported 2006 */ 2007 .reg_size = {}, 2008 .max_size = 2009 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2010 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2011 }, 2012 { /* TCL_DATA */ 2013 .start_ring_id = HAL_SRNG_SW2TCL1, 2014 .max_rings = 3, 2015 .entry_size = (sizeof(struct tlv_32_hdr) + 2016 sizeof(struct tcl_data_cmd)) >> 2, 2017 .lmac_ring = FALSE, 2018 .ring_dir = HAL_SRNG_SRC_RING, 2019 .reg_start = { 2020 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 2021 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2022 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 2023 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2024 }, 2025 .reg_size = { 2026 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 2027 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 2028 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 2029 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 2030 }, 2031 .max_size = 2032 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 2033 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 2034 }, 2035 { /* TCL_CMD */ 2036 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 2037 .max_rings = 1, 2038 .entry_size = (sizeof(struct tlv_32_hdr) + 2039 sizeof(struct tcl_data_cmd)) >> 2, 2040 .lmac_ring = FALSE, 2041 .ring_dir = HAL_SRNG_SRC_RING, 2042 .reg_start = { 2043 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR( 2044 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2045 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR( 2046 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2047 }, 2048 /* Single ring - provide ring size if multiple rings of this 2049 * type are supported 2050 */ 2051 .reg_size = {}, 2052 .max_size = 2053 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >> 2054 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT, 2055 }, 2056 { /* TCL_STATUS */ 2057 .start_ring_id = HAL_SRNG_TCL_STATUS, 2058 .max_rings = 1, 2059 .entry_size = (sizeof(struct tlv_32_hdr) + 2060 sizeof(struct tcl_status_ring)) >> 2, 2061 .lmac_ring = FALSE, 2062 .ring_dir = HAL_SRNG_DST_RING, 2063 .reg_start = { 2064 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 2065 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2066 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 2067 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 2068 }, 2069 /* Single ring - provide ring size if multiple rings of this 2070 * type are supported 2071 */ 2072 .reg_size = {}, 2073 .max_size = 2074 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 2075 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 2076 }, 2077 { /* CE_SRC */ 2078 .start_ring_id = HAL_SRNG_CE_0_SRC, 2079 .max_rings = 12, 2080 .entry_size = sizeof(struct ce_src_desc) >> 2, 2081 .lmac_ring = FALSE, 2082 .ring_dir = HAL_SRNG_SRC_RING, 2083 .reg_start = { 2084 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2085 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2086 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2087 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 2088 }, 2089 .reg_size = { 2090 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2091 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2092 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 2093 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 2094 }, 2095 .max_size = 2096 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2097 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2098 }, 2099 { /* CE_DST */ 2100 .start_ring_id = HAL_SRNG_CE_0_DST, 2101 .max_rings = 12, 2102 .entry_size = 8 >> 2, 2103 /*TODO: entry_size above should actually be 2104 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 2105 * of struct ce_dst_desc in HW header files 2106 */ 2107 .lmac_ring = FALSE, 2108 .ring_dir = HAL_SRNG_SRC_RING, 2109 .reg_start = { 2110 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 2111 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2112 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 2113 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2114 }, 2115 .reg_size = { 2116 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2117 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2118 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2119 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2120 }, 2121 .max_size = 2122 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 2123 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 2124 }, 2125 { /* CE_DST_STATUS */ 2126 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 2127 .max_rings = 12, 2128 .entry_size = sizeof(struct ce_stat_desc) >> 2, 2129 .lmac_ring = FALSE, 2130 .ring_dir = HAL_SRNG_DST_RING, 2131 .reg_start = { 2132 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 2133 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2134 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 2135 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 2136 }, 2137 /* TODO: check destination status ring registers */ 2138 .reg_size = { 2139 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2140 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2141 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 2142 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 2143 }, 2144 .max_size = 2145 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 2146 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 2147 }, 2148 { /* WBM_IDLE_LINK */ 2149 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 2150 .max_rings = 1, 2151 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 2152 .lmac_ring = FALSE, 2153 .ring_dir = HAL_SRNG_SRC_RING, 2154 .reg_start = { 2155 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2156 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2157 }, 2158 /* Single ring - provide ring size if multiple rings of this 2159 * type are supported 2160 */ 2161 .reg_size = {}, 2162 .max_size = 2163 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 2164 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 2165 }, 2166 { /* SW2WBM_RELEASE */ 2167 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 2168 .max_rings = 1, 2169 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2170 .lmac_ring = FALSE, 2171 .ring_dir = HAL_SRNG_SRC_RING, 2172 .reg_start = { 2173 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2174 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2175 }, 2176 /* Single ring - provide ring size if multiple rings of this 2177 * type are supported 2178 */ 2179 .reg_size = {}, 2180 .max_size = 2181 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2182 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2183 }, 2184 { /* WBM2SW_RELEASE */ 2185 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 2186 .max_rings = 5, 2187 .entry_size = sizeof(struct wbm_release_ring) >> 2, 2188 .lmac_ring = FALSE, 2189 .ring_dir = HAL_SRNG_DST_RING, 2190 .reg_start = { 2191 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2192 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2193 }, 2194 .reg_size = { 2195 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2196 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2197 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 2198 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 2199 }, 2200 .max_size = 2201 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 2202 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 2203 }, 2204 { /* RXDMA_BUF */ 2205 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 2206 #ifdef IPA_OFFLOAD 2207 .max_rings = 3, 2208 #else 2209 .max_rings = 2, 2210 #endif 2211 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2212 .lmac_ring = TRUE, 2213 .ring_dir = HAL_SRNG_SRC_RING, 2214 /* reg_start is not set because LMAC rings are not accessed 2215 * from host 2216 */ 2217 .reg_start = {}, 2218 .reg_size = {}, 2219 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2220 }, 2221 { /* RXDMA_DST */ 2222 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 2223 .max_rings = 1, 2224 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2225 .lmac_ring = TRUE, 2226 .ring_dir = HAL_SRNG_DST_RING, 2227 /* reg_start is not set because LMAC rings are not accessed 2228 * from host 2229 */ 2230 .reg_start = {}, 2231 .reg_size = {}, 2232 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2233 }, 2234 { /* RXDMA_MONITOR_BUF */ 2235 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 2236 .max_rings = 1, 2237 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2238 .lmac_ring = TRUE, 2239 .ring_dir = HAL_SRNG_SRC_RING, 2240 /* reg_start is not set because LMAC rings are not accessed 2241 * from host 2242 */ 2243 .reg_start = {}, 2244 .reg_size = {}, 2245 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2246 }, 2247 { /* RXDMA_MONITOR_STATUS */ 2248 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 2249 .max_rings = 1, 2250 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2251 .lmac_ring = TRUE, 2252 .ring_dir = HAL_SRNG_SRC_RING, 2253 /* reg_start is not set because LMAC rings are not accessed 2254 * from host 2255 */ 2256 .reg_start = {}, 2257 .reg_size = {}, 2258 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2259 }, 2260 { /* RXDMA_MONITOR_DST */ 2261 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 2262 .max_rings = 1, 2263 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 2264 .lmac_ring = TRUE, 2265 .ring_dir = HAL_SRNG_DST_RING, 2266 /* reg_start is not set because LMAC rings are not accessed 2267 * from host 2268 */ 2269 .reg_start = {}, 2270 .reg_size = {}, 2271 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2272 }, 2273 { /* RXDMA_MONITOR_DESC */ 2274 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 2275 .max_rings = 1, 2276 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 2277 .lmac_ring = TRUE, 2278 .ring_dir = HAL_SRNG_SRC_RING, 2279 /* reg_start is not set because LMAC rings are not accessed 2280 * from host 2281 */ 2282 .reg_start = {}, 2283 .reg_size = {}, 2284 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2285 }, 2286 { /* DIR_BUF_RX_DMA_SRC */ 2287 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 2288 /* one ring for spectral and one ring for cfr */ 2289 .max_rings = 2, 2290 .entry_size = 2, 2291 .lmac_ring = TRUE, 2292 .ring_dir = HAL_SRNG_SRC_RING, 2293 /* reg_start is not set because LMAC rings are not accessed 2294 * from host 2295 */ 2296 .reg_start = {}, 2297 .reg_size = {}, 2298 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2299 }, 2300 #ifdef WLAN_FEATURE_CIF_CFR 2301 { /* WIFI_POS_SRC */ 2302 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 2303 .max_rings = 1, 2304 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 2305 .lmac_ring = TRUE, 2306 .ring_dir = HAL_SRNG_SRC_RING, 2307 /* reg_start is not set because LMAC rings are not accessed 2308 * from host 2309 */ 2310 .reg_start = {}, 2311 .reg_size = {}, 2312 .max_size = HAL_RXDMA_MAX_RING_SIZE, 2313 }, 2314 #endif 2315 { /* REO2PPE */ 0}, 2316 { /* PPE2TCL */ 0}, 2317 { /* PPE_RELEASE */ 0}, 2318 { /* TX_MONITOR_BUF */ 0}, 2319 { /* TX_MONITOR_DST */ 0}, 2320 { /* SW2RXDMA_NEW */ 0}, 2321 { /* SW2RXDMA_LINK_RELEASE */ 0}, 2322 }; 2323 2324 /** 2325 * hal_qca5018_attach()- Attach 5018 target specific hal_soc ops, 2326 * offset and srng table 2327 * @hal_soc: hal_soc handle 2328 * 2329 * Return: void 2330 */ 2331 void hal_qca5018_attach(struct hal_soc *hal_soc) 2332 { 2333 hal_soc->hw_srng_table = hw_srng_table_5018; 2334 2335 hal_srng_hw_reg_offset_init_generic(hal_soc); 2336 hal_hw_txrx_default_ops_attach_li(hal_soc); 2337 hal_hw_txrx_ops_attach_qca5018(hal_soc); 2338 } 2339