1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 #include "hal_li_hw_headers.h" 20 #include "hal_internal.h" 21 #include "hal_api.h" 22 #include "target_type.h" 23 #include "wcss_version.h" 24 #include "qdf_module.h" 25 #include "hal_flow.h" 26 #include "rx_flow_search_entry.h" 27 #include "hal_rx_flow_info.h" 28 29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \ 30 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET 31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \ 32 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK 33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \ 34 RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB 35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \ 36 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_OFFSET 37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \ 38 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_MASK 39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \ 40 RXPCU_PPDU_END_INFO_10_PHYRX_ABORT_REQUEST_INFO_PHYRX_ABORT_REQUEST_INFO_DETAILS_LSB 41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \ 42 PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET 43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \ 44 PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET 45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \ 46 PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET 47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \ 48 PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET 49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \ 50 PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET 51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \ 52 PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET 53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \ 54 PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET 55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \ 56 PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET 57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \ 58 PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET 59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \ 60 PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET 61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \ 62 PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET 63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \ 64 RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET 65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 66 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \ 68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \ 72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET 73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \ 74 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER 75 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSE \ 76 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET 77 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \ 78 RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET 79 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 80 TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 81 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \ 82 TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET 83 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \ 84 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET 85 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \ 86 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB 87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \ 88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK 89 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \ 90 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB 91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \ 92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK 93 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \ 94 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB 95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \ 96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK 97 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \ 98 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB 99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \ 100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK 101 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \ 102 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB 103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \ 104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK 105 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \ 106 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK 107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \ 108 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET 109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \ 110 WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB 111 112 #include "hal_8074v1_tx.h" 113 #include "hal_8074v1_rx.h" 114 #include <hal_generic_api.h> 115 #include "hal_li_rx.h" 116 #include "hal_li_tx.h" 117 #include "hal_li_api.h" 118 #include "hal_li_generic_api.h" 119 120 /** 121 * hal_get_window_address_8074() - Function to get hp/tp address 122 * @hal_soc: Pointer to hal_soc 123 * @addr: address offset of register 124 * 125 * Return: modified address offset of register 126 */ 127 static inline qdf_iomem_t hal_get_window_address_8074(struct hal_soc *hal_soc, 128 qdf_iomem_t addr) 129 { 130 return addr; 131 } 132 133 /** 134 * hal_rx_get_rx_fragment_number_8074v1() - Function to retrieve 135 * rx fragment number 136 * @buf: Network buffer 137 * 138 * Return: rx fragment number 139 */ 140 static 141 uint8_t hal_rx_get_rx_fragment_number_8074v1(uint8_t *buf) 142 { 143 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 144 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 145 146 /* Return first 4 bits as fragment number */ 147 return (HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) & 148 DOT11_SEQ_FRAG_MASK); 149 } 150 151 /** 152 * hal_rx_msdu_end_da_is_mcbc_get_8074v1() - API to check if pkt is MCBC 153 * from rx_msdu_end TLV 154 * @buf: pointer to the start of RX PKT TLV headers 155 * 156 * Return: da_is_mcbc 157 */ 158 static uint8_t 159 hal_rx_msdu_end_da_is_mcbc_get_8074v1(uint8_t *buf) 160 { 161 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 162 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 163 164 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end); 165 } 166 167 /** 168 * hal_rx_msdu_end_sa_is_valid_get_8074v1() - API to get_8074v1 the 169 * sa_is_valid bit from 170 * rx_msdu_end TLV 171 * @buf: pointer to the start of RX PKT TLV headers 172 * 173 * Return: sa_is_valid bit 174 */ 175 static uint8_t 176 hal_rx_msdu_end_sa_is_valid_get_8074v1(uint8_t *buf) 177 { 178 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 179 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 180 uint8_t sa_is_valid; 181 182 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end); 183 184 return sa_is_valid; 185 } 186 187 /** 188 * hal_rx_msdu_end_sa_idx_get_8074v1() - API to get_8074v1 the sa_idx from 189 * rx_msdu_end TLV 190 * @buf: pointer to the start of RX PKT TLV headers 191 * 192 * Return: sa_idx (SA AST index) 193 */ 194 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v1(uint8_t *buf) 195 { 196 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 197 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 198 uint16_t sa_idx; 199 200 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end); 201 202 return sa_idx; 203 } 204 205 /** 206 * hal_rx_desc_is_first_msdu_8074v1() - Check if first msdu 207 * @hw_desc_addr: hardware descriptor address 208 * 209 * Return: 0 - success/ non-zero failure 210 */ 211 static uint32_t hal_rx_desc_is_first_msdu_8074v1(void *hw_desc_addr) 212 { 213 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr; 214 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end; 215 216 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU); 217 } 218 219 /** 220 * hal_rx_msdu_end_l3_hdr_padding_get_8074v1() - API to get_8074v1 the 221 * l3_header padding from 222 * rx_msdu_end TLV 223 * @buf: pointer to the start of RX PKT TLV headers 224 * 225 * Return: number of l3 header padding bytes 226 */ 227 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v1(uint8_t *buf) 228 { 229 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 230 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 231 uint32_t l3_header_padding; 232 233 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end); 234 235 return l3_header_padding; 236 } 237 238 /** 239 * hal_rx_encryption_info_valid_8074v1() - Returns encryption type. 240 * @buf: rx_tlv_hdr of the received packet 241 * 242 * Return: encryption type 243 */ 244 static uint32_t hal_rx_encryption_info_valid_8074v1(uint8_t *buf) 245 { 246 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 247 struct rx_mpdu_start *mpdu_start = 248 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 249 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 250 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info); 251 252 return encryption_info; 253 } 254 255 /** 256 * hal_rx_print_pn_8074v1() - Prints the PN of rx packet. 257 * @buf: rx_tlv_hdr of the received packet 258 * 259 * Return: void 260 */ 261 static void hal_rx_print_pn_8074v1(uint8_t *buf) 262 { 263 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 264 struct rx_mpdu_start *mpdu_start = 265 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 266 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 267 268 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info); 269 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info); 270 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info); 271 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info); 272 273 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x", 274 pn_127_96, pn_95_64, pn_63_32, pn_31_0); 275 } 276 277 /** 278 * hal_rx_msdu_end_first_msdu_get_8074v1() - API to get first msdu status 279 * from rx_msdu_end TLV 280 * @buf: pointer to the start of RX PKT TLV headers 281 * 282 * Return: first_msdu 283 */ 284 static uint8_t 285 hal_rx_msdu_end_first_msdu_get_8074v1(uint8_t *buf) 286 { 287 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 288 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 289 uint8_t first_msdu; 290 291 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end); 292 293 return first_msdu; 294 } 295 296 /** 297 * hal_rx_msdu_end_da_is_valid_get_8074v1() - API to check if da is valid from 298 * rx_msdu_end TLV 299 * @buf: pointer to the start of RX PKT TLV headers 300 * 301 * Return: da_is_valid 302 */ 303 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v1(uint8_t *buf) 304 { 305 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 306 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 307 uint8_t da_is_valid; 308 309 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end); 310 311 return da_is_valid; 312 } 313 314 /** 315 * hal_rx_msdu_end_last_msdu_get_8074v1() - API to get last msdu status from 316 * rx_msdu_end TLV 317 * @buf: pointer to the start of RX PKT TLV headers 318 * 319 * Return: last_msdu 320 */ 321 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v1(uint8_t *buf) 322 { 323 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 324 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 325 uint8_t last_msdu; 326 327 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end); 328 329 return last_msdu; 330 } 331 332 /** 333 * hal_rx_get_mpdu_mac_ad4_valid_8074v1() - Retrieves if mpdu 4th addr is valid 334 * @buf: Network buffer 335 * 336 * Return: value of mpdu 4th address valid field 337 */ 338 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v1(uint8_t *buf) 339 { 340 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 341 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 342 bool ad4_valid = 0; 343 344 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info); 345 346 return ad4_valid; 347 } 348 349 /** 350 * hal_rx_mpdu_start_sw_peer_id_get_8074v1() - Retrieve sw peer_id 351 * @buf: network buffer 352 * 353 * Return: sw peer_id 354 */ 355 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v1(uint8_t *buf) 356 { 357 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 358 struct rx_mpdu_start *mpdu_start = 359 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 360 361 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET( 362 &mpdu_start->rx_mpdu_info_details); 363 } 364 365 /** 366 * hal_rx_mpdu_get_to_ds_8074v1() - API to get the tods info from rx_mpdu_start 367 * @buf: pointer to the start of RX PKT TLV header 368 * 369 * Return: uint32_t(to_ds) 370 */ 371 372 static uint32_t hal_rx_mpdu_get_to_ds_8074v1(uint8_t *buf) 373 { 374 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 375 struct rx_mpdu_start *mpdu_start = 376 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 377 378 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 379 380 return HAL_RX_MPDU_GET_TODS(mpdu_info); 381 } 382 383 /** 384 * hal_rx_mpdu_get_fr_ds_8074v1() - API to get the from ds info from 385 * rx_mpdu_start 386 * @buf: pointer to the start of RX PKT TLV header 387 * 388 * Return: uint32_t(fr_ds) 389 */ 390 static uint32_t hal_rx_mpdu_get_fr_ds_8074v1(uint8_t *buf) 391 { 392 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 393 struct rx_mpdu_start *mpdu_start = 394 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 395 396 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 397 398 return HAL_RX_MPDU_GET_FROMDS(mpdu_info); 399 } 400 401 /** 402 * hal_rx_get_mpdu_frame_control_valid_8074v1() - Retrieves mpdu frame control 403 * valid 404 * @buf: Network buffer 405 * 406 * Return: value of frame control valid field 407 */ 408 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v1(uint8_t *buf) 409 { 410 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 411 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 412 413 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info); 414 } 415 416 /** 417 * hal_rx_get_mpdu_frame_control_field_8074v1() - Function to retrieve frame 418 * control field 419 * @buf: Network buffer 420 * 421 * Return: value of frame control field 422 * 423 */ 424 static uint16_t hal_rx_get_mpdu_frame_control_field_8074v1(uint8_t *buf) 425 { 426 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 427 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 428 uint16_t frame_ctrl = 0; 429 430 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info); 431 432 return frame_ctrl; 433 } 434 435 /** 436 * hal_rx_mpdu_get_addr1_8074v1() - API to check get address1 of the mpdu 437 * @buf: pointer to the start of RX PKT TLV headera 438 * @mac_addr: pointer to mac address 439 * 440 * Return: success/failure 441 */ 442 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v1(uint8_t *buf, 443 uint8_t *mac_addr) 444 { 445 struct __attribute__((__packed__)) hal_addr1 { 446 uint32_t ad1_31_0; 447 uint16_t ad1_47_32; 448 }; 449 450 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 451 struct rx_mpdu_start *mpdu_start = 452 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 453 454 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 455 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr; 456 uint32_t mac_addr_ad1_valid; 457 458 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info); 459 460 if (mac_addr_ad1_valid) { 461 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info); 462 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info); 463 return QDF_STATUS_SUCCESS; 464 } 465 466 return QDF_STATUS_E_FAILURE; 467 } 468 469 /** 470 * hal_rx_mpdu_get_addr2_8074v1() - API to check get address2 of the mpdu 471 * in the packet 472 * @buf: pointer to the start of RX PKT TLV header 473 * @mac_addr: pointer to mac address 474 * 475 * Return: success/failure 476 */ 477 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v1(uint8_t *buf, uint8_t *mac_addr) 478 { 479 struct __attribute__((__packed__)) hal_addr2 { 480 uint16_t ad2_15_0; 481 uint32_t ad2_47_16; 482 }; 483 484 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 485 struct rx_mpdu_start *mpdu_start = 486 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 487 488 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 489 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr; 490 uint32_t mac_addr_ad2_valid; 491 492 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info); 493 494 if (mac_addr_ad2_valid) { 495 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info); 496 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info); 497 return QDF_STATUS_SUCCESS; 498 } 499 500 return QDF_STATUS_E_FAILURE; 501 } 502 503 /** 504 * hal_rx_mpdu_get_addr3_8074v1() - API to get address3 of the mpdu 505 * in the packet 506 * @buf: pointer to the start of RX PKT TLV header 507 * @mac_addr: pointer to mac address 508 * 509 * Return: success/failure 510 */ 511 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v1(uint8_t *buf, uint8_t *mac_addr) 512 { 513 struct __attribute__((__packed__)) hal_addr3 { 514 uint32_t ad3_31_0; 515 uint16_t ad3_47_32; 516 }; 517 518 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 519 struct rx_mpdu_start *mpdu_start = 520 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 521 522 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 523 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr; 524 uint32_t mac_addr_ad3_valid; 525 526 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info); 527 528 if (mac_addr_ad3_valid) { 529 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info); 530 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info); 531 return QDF_STATUS_SUCCESS; 532 } 533 534 return QDF_STATUS_E_FAILURE; 535 } 536 537 /** 538 * hal_rx_mpdu_get_addr4_8074v1() - API to get address4 of the mpdu 539 * in the packet 540 * @buf: pointer to the start of RX PKT TLV header 541 * @mac_addr: pointer to mac address 542 * 543 * Return: success/failure 544 */ 545 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v1(uint8_t *buf, uint8_t *mac_addr) 546 { 547 struct __attribute__((__packed__)) hal_addr4 { 548 uint32_t ad4_31_0; 549 uint16_t ad4_47_32; 550 }; 551 552 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 553 struct rx_mpdu_start *mpdu_start = 554 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 555 556 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details; 557 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr; 558 uint32_t mac_addr_ad4_valid; 559 560 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info); 561 562 if (mac_addr_ad4_valid) { 563 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info); 564 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info); 565 return QDF_STATUS_SUCCESS; 566 } 567 568 return QDF_STATUS_E_FAILURE; 569 } 570 571 /** 572 * hal_rx_get_mpdu_sequence_control_valid_8074v1() - Get mpdu sequence control 573 * valid 574 * @buf: Network buffer 575 * 576 * Return: value of sequence control valid field 577 */ 578 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v1(uint8_t *buf) 579 { 580 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 581 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 582 583 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info); 584 } 585 586 /** 587 * hal_rx_is_unicast_8074v1() - check packet is unicast frame or not. 588 * @buf: pointer to rx pkt TLV. 589 * 590 * Return: true on unicast. 591 */ 592 static bool hal_rx_is_unicast_8074v1(uint8_t *buf) 593 { 594 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 595 struct rx_mpdu_start *mpdu_start = 596 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 597 uint32_t grp_id; 598 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 599 600 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 601 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)), 602 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK, 603 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB)); 604 605 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false; 606 } 607 608 /** 609 * hal_rx_tid_get_8074v1() - get tid based on qos control valid. 610 * @hal_soc_hdl: HAL SoC handle 611 * @buf: pointer to rx pkt TLV. 612 * 613 * Return: tid 614 */ 615 static uint32_t hal_rx_tid_get_8074v1(hal_soc_handle_t hal_soc_hdl, 616 uint8_t *buf) 617 { 618 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 619 struct rx_mpdu_start *mpdu_start = 620 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 621 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details; 622 uint8_t qos_control_valid = 623 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info), 624 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)), 625 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK, 626 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB)); 627 628 if (qos_control_valid) 629 return hal_rx_mpdu_start_tid_get_8074(buf); 630 631 return HAL_RX_NON_QOS_TID; 632 } 633 634 /** 635 * hal_rx_hw_desc_get_ppduid_get_8074v1() - retrieve ppdu id 636 * @rx_tlv_hdr: Rx tlv header 637 * @rxdma_dst_ring_desc: Rx HW descriptor 638 * 639 * Return: ppdu id 640 */ 641 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v1(void *rx_tlv_hdr, 642 void *rxdma_dst_ring_desc) 643 { 644 struct rx_mpdu_info *rx_mpdu_info; 645 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 646 647 rx_mpdu_info = 648 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 649 650 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID); 651 } 652 653 /** 654 * hal_reo_status_get_header_8074v1() - Process reo desc info 655 * @ring_desc: REO status ring descriptor 656 * @b: tlv type info 657 * @h1: Pointer to hal_reo_status_header where info to be stored 658 * 659 * Return - none. 660 * 661 */ 662 static void hal_reo_status_get_header_8074v1(hal_ring_desc_t ring_desc, int b, 663 void *h1) 664 { 665 uint32_t *d = (uint32_t *)ring_desc; 666 uint32_t val1 = 0; 667 struct hal_reo_status_header *h = 668 (struct hal_reo_status_header *)h1; 669 670 /* Offsets of descriptor fields defined in HW headers start 671 * from the field after TLV header 672 */ 673 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr)); 674 675 switch (b) { 676 case HAL_REO_QUEUE_STATS_STATUS_TLV: 677 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0, 678 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 679 break; 680 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 681 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0, 682 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 683 break; 684 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 685 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0, 686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 687 break; 688 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 689 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0, 690 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 691 break; 692 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 693 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0, 694 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 695 break; 696 case HAL_REO_DESC_THRES_STATUS_TLV: 697 val1 = 698 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0, 699 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 700 break; 701 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 702 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0, 703 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)]; 704 break; 705 default: 706 qdf_nofl_err("ERROR: Unknown tlv\n"); 707 break; 708 } 709 h->cmd_num = 710 HAL_GET_FIELD( 711 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER, 712 val1); 713 h->exec_time = 714 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 715 CMD_EXECUTION_TIME, val1); 716 h->status = 717 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0, 718 REO_CMD_EXECUTION_STATUS, val1); 719 switch (b) { 720 case HAL_REO_QUEUE_STATS_STATUS_TLV: 721 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1, 722 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 723 break; 724 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 725 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1, 726 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 727 break; 728 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 729 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1, 730 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 731 break; 732 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 733 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1, 734 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 735 break; 736 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 737 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1, 738 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 739 break; 740 case HAL_REO_DESC_THRES_STATUS_TLV: 741 val1 = 742 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1, 743 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 744 break; 745 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 746 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1, 747 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)]; 748 break; 749 default: 750 qdf_nofl_err("ERROR: Unknown tlv\n"); 751 break; 752 } 753 h->tstamp = 754 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1); 755 } 756 757 /** 758 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1() - 759 * Retrieve qos control valid bit from the tlv. 760 * @buf: pointer to rx pkt TLV. 761 * 762 * Return: qos control value. 763 */ 764 static inline uint32_t 765 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1(uint8_t *buf) 766 { 767 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 768 struct rx_mpdu_start *mpdu_start = 769 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start; 770 771 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET( 772 &mpdu_start->rx_mpdu_info_details); 773 } 774 775 /** 776 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v1() - API to get the sa_sw_peer_id 777 * from rx_msdu_end TLV 778 * @buf: pointer to the start of RX PKT TLV headers 779 * 780 * Return: sa_sw_peer_id index 781 */ 782 static inline uint32_t 783 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1(uint8_t *buf) 784 { 785 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 786 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 787 788 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end); 789 } 790 791 /** 792 * hal_tx_desc_set_mesh_en_8074v1() - Set mesh_enable flag in Tx descriptor 793 * @desc: Handle to Tx Descriptor 794 * @en: For raw WiFi frames, this indicates transmission to a mesh STA, 795 * enabling the interpretation of the 'Mesh Control Present' bit 796 * (bit 8) of QoS Control (otherwise this bit is ignored), 797 * For native WiFi frames, this indicates that a 'Mesh Control' field 798 * is present between the header and the LLC. 799 * 800 * Return: void 801 */ 802 static inline 803 void hal_tx_desc_set_mesh_en_8074v1(void *desc, uint8_t en) 804 { 805 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |= 806 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en); 807 } 808 809 static 810 void *hal_rx_msdu0_buffer_addr_lsb_8074v1(void *link_desc_va) 811 { 812 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va); 813 } 814 815 static 816 void *hal_rx_msdu_desc_info_ptr_get_8074v1(void *msdu0) 817 { 818 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0); 819 } 820 821 static 822 void *hal_ent_mpdu_desc_info_8074v1(void *ent_ring_desc) 823 { 824 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc); 825 } 826 827 static 828 void *hal_dst_mpdu_desc_info_8074v1(void *dst_ring_desc) 829 { 830 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc); 831 } 832 833 static 834 uint8_t hal_rx_get_fc_valid_8074v1(uint8_t *buf) 835 { 836 return HAL_RX_GET_FC_VALID(buf); 837 } 838 839 static uint8_t hal_rx_get_to_ds_flag_8074v1(uint8_t *buf) 840 { 841 return HAL_RX_GET_TO_DS_FLAG(buf); 842 } 843 844 static uint8_t hal_rx_get_mac_addr2_valid_8074v1(uint8_t *buf) 845 { 846 return HAL_RX_GET_MAC_ADDR2_VALID(buf); 847 } 848 849 static uint8_t hal_rx_get_filter_category_8074v1(uint8_t *buf) 850 { 851 return HAL_RX_GET_FILTER_CATEGORY(buf); 852 } 853 854 static uint32_t 855 hal_rx_get_ppdu_id_8074v1(uint8_t *buf) 856 { 857 struct rx_mpdu_info *rx_mpdu_info; 858 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf; 859 860 rx_mpdu_info = 861 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details; 862 863 return HAL_RX_GET_PPDU_ID(rx_mpdu_info); 864 } 865 866 /** 867 * hal_reo_config_8074v1() - Set reo config parameters 868 * @soc: hal soc handle 869 * @reg_val: value to be set 870 * @reo_params: reo parameters 871 * 872 * Return: void 873 */ 874 static void 875 hal_reo_config_8074v1(struct hal_soc *soc, 876 uint32_t reg_val, 877 struct hal_reo_params *reo_params) 878 { 879 HAL_REO_R0_CONFIG(soc, reg_val, reo_params); 880 } 881 882 /** 883 * hal_rx_msdu_desc_info_get_ptr_8074v1() - Get msdu desc info ptr 884 * @msdu_details_ptr: Pointer to msdu_details_ptr 885 * 886 * Return - Pointer to rx_msdu_desc_info structure. 887 * 888 */ 889 static void *hal_rx_msdu_desc_info_get_ptr_8074v1(void *msdu_details_ptr) 890 { 891 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr); 892 } 893 894 /** 895 * hal_rx_link_desc_msdu0_ptr_8074v1() - Get pointer to rx_msdu details 896 * @link_desc: Pointer to link desc 897 * 898 * Return - Pointer to rx_msdu_details structure 899 * 900 */ 901 static void *hal_rx_link_desc_msdu0_ptr_8074v1(void *link_desc) 902 { 903 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc); 904 } 905 906 /** 907 * hal_rx_msdu_flow_idx_get_8074v1() - API to get flow index from 908 * rx_msdu_end TLV 909 * @buf: pointer to the start of RX PKT TLV headers 910 * 911 * Return: flow index value from MSDU END TLV 912 */ 913 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v1(uint8_t *buf) 914 { 915 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 916 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 917 918 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 919 } 920 921 /** 922 * hal_rx_msdu_flow_idx_invalid_8074v1() - API to get flow index invalid 923 * from rx_msdu_end TLV 924 * @buf: pointer to the start of RX PKT TLV headers 925 * 926 * Return: flow index invalid value from MSDU END TLV 927 */ 928 static bool hal_rx_msdu_flow_idx_invalid_8074v1(uint8_t *buf) 929 { 930 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 931 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 932 933 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 934 } 935 936 /** 937 * hal_rx_msdu_flow_idx_timeout_8074v1() - API to get flow index timeout 938 * from rx_msdu_end TLV 939 * @buf: pointer to the start of RX PKT TLV headers 940 * 941 * Return: flow index timeout value from MSDU END TLV 942 */ 943 static bool hal_rx_msdu_flow_idx_timeout_8074v1(uint8_t *buf) 944 { 945 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 946 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 947 948 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 949 } 950 951 /** 952 * hal_rx_msdu_fse_metadata_get_8074v1() - API to get FSE metadata 953 * from rx_msdu_end TLV 954 * @buf: pointer to the start of RX PKT TLV headers 955 * 956 * Return: fse metadata value from MSDU END TLV 957 */ 958 static uint32_t hal_rx_msdu_fse_metadata_get_8074v1(uint8_t *buf) 959 { 960 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 961 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 962 963 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end); 964 } 965 966 /** 967 * hal_rx_msdu_cce_metadata_get_8074v1() - API to get CCE metadata 968 * from rx_msdu_end TLV 969 * @buf: pointer to the start of RX PKT TLV headers 970 * 971 * Return: cce_metadata 972 */ 973 static uint16_t 974 hal_rx_msdu_cce_metadata_get_8074v1(uint8_t *buf) 975 { 976 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 977 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 978 979 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end); 980 } 981 982 /** 983 * hal_rx_msdu_get_flow_params_8074v1() - API to get flow index, flow index 984 * invalid and flow index timeout from 985 * rx_msdu_end TLV 986 * @buf: pointer to the start of RX PKT TLV headers 987 * @flow_invalid: pointer to return value of flow_idx_valid 988 * @flow_timeout: pointer to return value of flow_idx_timeout 989 * @flow_index: pointer to return value of flow_idx 990 * 991 * Return: none 992 */ 993 static inline void 994 hal_rx_msdu_get_flow_params_8074v1(uint8_t *buf, 995 bool *flow_invalid, 996 bool *flow_timeout, 997 uint32_t *flow_index) 998 { 999 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 1000 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 1001 1002 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end); 1003 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end); 1004 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end); 1005 } 1006 1007 /** 1008 * hal_rx_tlv_get_tcp_chksum_8074v1() - API to get tcp checksum 1009 * @buf: rx_tlv_hdr 1010 * 1011 * Return: tcp checksum 1012 */ 1013 static uint16_t 1014 hal_rx_tlv_get_tcp_chksum_8074v1(uint8_t *buf) 1015 { 1016 return HAL_RX_TLV_GET_TCP_CHKSUM(buf); 1017 } 1018 1019 /** 1020 * hal_rx_get_rx_sequence_8074v1() - Function to retrieve rx sequence number 1021 * @buf: Network buffer 1022 * 1023 * Return: rx sequence number 1024 */ 1025 static 1026 uint16_t hal_rx_get_rx_sequence_8074v1(uint8_t *buf) 1027 { 1028 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf); 1029 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs); 1030 1031 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info); 1032 } 1033 1034 /** 1035 * hal_rx_mpdu_start_tlv_tag_valid_8074v1() - API to check if RX_MPDU_START 1036 * tlv tag is valid 1037 * @rx_tlv_hdr: start address of rx_pkt_tlvs 1038 * 1039 * Return: true if RX_MPDU_START is valid, else false. 1040 */ 1041 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v1(void *rx_tlv_hdr) 1042 { 1043 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr; 1044 uint32_t tlv_tag; 1045 1046 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE( 1047 &rx_desc->mpdu_start_tlv); 1048 1049 return tlv_tag == WIFIRX_MPDU_START_E ? true : false; 1050 } 1051 1052 /** 1053 * hal_rx_flow_setup_fse_8074v1() - Setup a flow search entry in HW FST 1054 * @rx_fst: Pointer to the Rx Flow Search Table 1055 * @table_offset: offset into the table where the flow is to be setup 1056 * @rx_flow: Flow Parameters 1057 * 1058 * Return: Success/Failure 1059 */ 1060 static void * 1061 hal_rx_flow_setup_fse_8074v1(uint8_t *rx_fst, uint32_t table_offset, 1062 uint8_t *rx_flow) 1063 { 1064 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 1065 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow; 1066 uint8_t *fse; 1067 bool fse_valid; 1068 1069 if (table_offset >= fst->max_entries) { 1070 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR, 1071 "HAL FSE table offset %u exceeds max entries %u", 1072 table_offset, fst->max_entries); 1073 return NULL; 1074 } 1075 1076 fse = (uint8_t *)fst->base_vaddr + 1077 (table_offset * HAL_RX_FST_ENTRY_SIZE); 1078 1079 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1080 1081 if (fse_valid) { 1082 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG, 1083 "HAL FSE %pK already valid", fse); 1084 return NULL; 1085 } 1086 1087 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) = 1088 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96, 1089 qdf_htonl(flow->tuple_info.src_ip_127_96)); 1090 1091 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) = 1092 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64, 1093 qdf_htonl(flow->tuple_info.src_ip_95_64)); 1094 1095 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) = 1096 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32, 1097 qdf_htonl(flow->tuple_info.src_ip_63_32)); 1098 1099 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) = 1100 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0, 1101 qdf_htonl(flow->tuple_info.src_ip_31_0)); 1102 1103 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) = 1104 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96, 1105 qdf_htonl(flow->tuple_info.dest_ip_127_96)); 1106 1107 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) = 1108 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64, 1109 qdf_htonl(flow->tuple_info.dest_ip_95_64)); 1110 1111 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) = 1112 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32, 1113 qdf_htonl(flow->tuple_info.dest_ip_63_32)); 1114 1115 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) = 1116 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0, 1117 qdf_htonl(flow->tuple_info.dest_ip_31_0)); 1118 1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT); 1120 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |= 1121 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT, 1122 (flow->tuple_info.dest_port)); 1123 1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT); 1125 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |= 1126 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT, 1127 (flow->tuple_info.src_port)); 1128 1129 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL); 1130 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |= 1131 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL, 1132 flow->tuple_info.l4_protocol); 1133 1134 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER); 1135 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |= 1136 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER, 1137 flow->reo_destination_handler); 1138 1139 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID); 1140 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |= 1141 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1); 1142 1143 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA); 1144 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) = 1145 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA, 1146 flow->fse_metadata); 1147 1148 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION); 1149 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |= 1150 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11, 1151 REO_DESTINATION_INDICATION, 1152 flow->reo_destination_indication); 1153 1154 /* Reset all the other fields in FSE */ 1155 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9); 1156 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP); 1157 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11); 1158 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT); 1159 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT); 1160 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP); 1161 1162 return fse; 1163 } 1164 1165 static 1166 void hal_compute_reo_remap_ix2_ix3_8074v1(uint32_t *ring, uint32_t num_rings, 1167 uint32_t *remap1, uint32_t *remap2) 1168 { 1169 switch (num_rings) { 1170 case 1: 1171 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1172 HAL_REO_REMAP_IX2(ring[0], 17) | 1173 HAL_REO_REMAP_IX2(ring[0], 18) | 1174 HAL_REO_REMAP_IX2(ring[0], 19) | 1175 HAL_REO_REMAP_IX2(ring[0], 20) | 1176 HAL_REO_REMAP_IX2(ring[0], 21) | 1177 HAL_REO_REMAP_IX2(ring[0], 22) | 1178 HAL_REO_REMAP_IX2(ring[0], 23); 1179 1180 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1181 HAL_REO_REMAP_IX3(ring[0], 25) | 1182 HAL_REO_REMAP_IX3(ring[0], 26) | 1183 HAL_REO_REMAP_IX3(ring[0], 27) | 1184 HAL_REO_REMAP_IX3(ring[0], 28) | 1185 HAL_REO_REMAP_IX3(ring[0], 29) | 1186 HAL_REO_REMAP_IX3(ring[0], 30) | 1187 HAL_REO_REMAP_IX3(ring[0], 31); 1188 break; 1189 case 2: 1190 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1191 HAL_REO_REMAP_IX2(ring[0], 17) | 1192 HAL_REO_REMAP_IX2(ring[1], 18) | 1193 HAL_REO_REMAP_IX2(ring[1], 19) | 1194 HAL_REO_REMAP_IX2(ring[0], 20) | 1195 HAL_REO_REMAP_IX2(ring[0], 21) | 1196 HAL_REO_REMAP_IX2(ring[1], 22) | 1197 HAL_REO_REMAP_IX2(ring[1], 23); 1198 1199 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1200 HAL_REO_REMAP_IX3(ring[0], 25) | 1201 HAL_REO_REMAP_IX3(ring[1], 26) | 1202 HAL_REO_REMAP_IX3(ring[1], 27) | 1203 HAL_REO_REMAP_IX3(ring[0], 28) | 1204 HAL_REO_REMAP_IX3(ring[0], 29) | 1205 HAL_REO_REMAP_IX3(ring[1], 30) | 1206 HAL_REO_REMAP_IX3(ring[1], 31); 1207 break; 1208 case 3: 1209 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1210 HAL_REO_REMAP_IX2(ring[1], 17) | 1211 HAL_REO_REMAP_IX2(ring[2], 18) | 1212 HAL_REO_REMAP_IX2(ring[0], 19) | 1213 HAL_REO_REMAP_IX2(ring[1], 20) | 1214 HAL_REO_REMAP_IX2(ring[2], 21) | 1215 HAL_REO_REMAP_IX2(ring[0], 22) | 1216 HAL_REO_REMAP_IX2(ring[1], 23); 1217 1218 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) | 1219 HAL_REO_REMAP_IX3(ring[0], 25) | 1220 HAL_REO_REMAP_IX3(ring[1], 26) | 1221 HAL_REO_REMAP_IX3(ring[2], 27) | 1222 HAL_REO_REMAP_IX3(ring[0], 28) | 1223 HAL_REO_REMAP_IX3(ring[1], 29) | 1224 HAL_REO_REMAP_IX3(ring[2], 30) | 1225 HAL_REO_REMAP_IX3(ring[0], 31); 1226 break; 1227 case 4: 1228 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) | 1229 HAL_REO_REMAP_IX2(ring[1], 17) | 1230 HAL_REO_REMAP_IX2(ring[2], 18) | 1231 HAL_REO_REMAP_IX2(ring[3], 19) | 1232 HAL_REO_REMAP_IX2(ring[0], 20) | 1233 HAL_REO_REMAP_IX2(ring[1], 21) | 1234 HAL_REO_REMAP_IX2(ring[2], 22) | 1235 HAL_REO_REMAP_IX2(ring[3], 23); 1236 1237 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) | 1238 HAL_REO_REMAP_IX3(ring[1], 25) | 1239 HAL_REO_REMAP_IX3(ring[2], 26) | 1240 HAL_REO_REMAP_IX3(ring[3], 27) | 1241 HAL_REO_REMAP_IX3(ring[0], 28) | 1242 HAL_REO_REMAP_IX3(ring[1], 29) | 1243 HAL_REO_REMAP_IX3(ring[2], 30) | 1244 HAL_REO_REMAP_IX3(ring[3], 31); 1245 break; 1246 } 1247 } 1248 1249 static void hal_hw_txrx_ops_attach_qca8074(struct hal_soc *hal_soc) 1250 { 1251 1252 /* init and setup */ 1253 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic; 1254 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic; 1255 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic; 1256 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li; 1257 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074; 1258 1259 /* tx */ 1260 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id = 1261 hal_tx_desc_set_dscp_tid_table_id_8074; 1262 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074; 1263 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074; 1264 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074; 1265 hal_soc->ops->hal_tx_desc_set_buf_addr = 1266 hal_tx_desc_set_buf_addr_generic_li; 1267 hal_soc->ops->hal_tx_desc_set_search_type = 1268 hal_tx_desc_set_search_type_generic_li; 1269 hal_soc->ops->hal_tx_desc_set_search_index = 1270 hal_tx_desc_set_search_index_generic_li; 1271 hal_soc->ops->hal_tx_desc_set_cache_set_num = 1272 hal_tx_desc_set_cache_set_num_generic_li; 1273 hal_soc->ops->hal_tx_comp_get_status = 1274 hal_tx_comp_get_status_generic_li; 1275 hal_soc->ops->hal_tx_comp_get_release_reason = 1276 hal_tx_comp_get_release_reason_generic_li; 1277 hal_soc->ops->hal_get_wbm_internal_error = 1278 hal_get_wbm_internal_error_generic_li; 1279 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v1; 1280 hal_soc->ops->hal_tx_init_cmd_credit_ring = 1281 hal_tx_init_cmd_credit_ring_8074v1; 1282 1283 /* rx */ 1284 hal_soc->ops->hal_rx_msdu_start_nss_get = 1285 hal_rx_msdu_start_nss_get_8074; 1286 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status = 1287 hal_rx_mon_hw_desc_get_mpdu_status_8074; 1288 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074; 1289 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv = 1290 hal_rx_proc_phyrx_other_receive_info_tlv_8074; 1291 1292 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_8074; 1293 hal_soc->ops->hal_rx_dump_rx_attention_tlv = 1294 hal_rx_dump_rx_attention_tlv_generic_li; 1295 hal_soc->ops->hal_rx_dump_msdu_start_tlv = 1296 hal_rx_dump_msdu_start_tlv_8074; 1297 hal_soc->ops->hal_rx_dump_mpdu_start_tlv = 1298 hal_rx_dump_mpdu_start_tlv_generic_li; 1299 hal_soc->ops->hal_rx_dump_mpdu_end_tlv = 1300 hal_rx_dump_mpdu_end_tlv_generic_li; 1301 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv = 1302 hal_rx_dump_pkt_hdr_tlv_generic_li; 1303 1304 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074; 1305 hal_soc->ops->hal_rx_mpdu_start_tid_get = 1306 hal_rx_mpdu_start_tid_get_8074; 1307 hal_soc->ops->hal_rx_msdu_start_reception_type_get = 1308 hal_rx_msdu_start_reception_type_get_8074; 1309 hal_soc->ops->hal_rx_msdu_end_da_idx_get = 1310 hal_rx_msdu_end_da_idx_get_8074; 1311 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr = 1312 hal_rx_msdu_desc_info_get_ptr_8074v1; 1313 hal_soc->ops->hal_rx_link_desc_msdu0_ptr = 1314 hal_rx_link_desc_msdu0_ptr_8074v1; 1315 hal_soc->ops->hal_reo_status_get_header = 1316 hal_reo_status_get_header_8074v1; 1317 hal_soc->ops->hal_rx_status_get_tlv_info = 1318 hal_rx_status_get_tlv_info_generic_li; 1319 hal_soc->ops->hal_rx_wbm_err_info_get = 1320 hal_rx_wbm_err_info_get_generic_li; 1321 1322 hal_soc->ops->hal_tx_set_pcp_tid_map = 1323 hal_tx_set_pcp_tid_map_generic_li; 1324 hal_soc->ops->hal_tx_update_pcp_tid_map = 1325 hal_tx_update_pcp_tid_generic_li; 1326 hal_soc->ops->hal_tx_set_tidmap_prty = 1327 hal_tx_update_tidmap_prty_generic_li; 1328 hal_soc->ops->hal_rx_get_rx_fragment_number = 1329 hal_rx_get_rx_fragment_number_8074v1; 1330 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get = 1331 hal_rx_msdu_end_da_is_mcbc_get_8074v1; 1332 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get = 1333 hal_rx_msdu_end_sa_is_valid_get_8074v1; 1334 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = 1335 hal_rx_msdu_end_sa_idx_get_8074v1; 1336 hal_soc->ops->hal_rx_desc_is_first_msdu = 1337 hal_rx_desc_is_first_msdu_8074v1; 1338 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get = 1339 hal_rx_msdu_end_l3_hdr_padding_get_8074v1; 1340 hal_soc->ops->hal_rx_encryption_info_valid = 1341 hal_rx_encryption_info_valid_8074v1; 1342 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v1; 1343 hal_soc->ops->hal_rx_msdu_end_first_msdu_get = 1344 hal_rx_msdu_end_first_msdu_get_8074v1; 1345 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get = 1346 hal_rx_msdu_end_da_is_valid_get_8074v1; 1347 hal_soc->ops->hal_rx_msdu_end_last_msdu_get = 1348 hal_rx_msdu_end_last_msdu_get_8074v1; 1349 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid = 1350 hal_rx_get_mpdu_mac_ad4_valid_8074v1; 1351 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get = 1352 hal_rx_mpdu_start_sw_peer_id_get_8074v1; 1353 hal_soc->ops->hal_rx_tlv_peer_meta_data_get = 1354 hal_rx_mpdu_peer_meta_data_get_li; 1355 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v1; 1356 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v1; 1357 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid = 1358 hal_rx_get_mpdu_frame_control_valid_8074v1; 1359 hal_soc->ops->hal_rx_get_frame_ctrl_field = 1360 hal_rx_get_mpdu_frame_control_field_8074v1; 1361 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v1; 1362 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v1; 1363 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v1; 1364 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v1; 1365 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid = 1366 hal_rx_get_mpdu_sequence_control_valid_8074v1; 1367 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v1; 1368 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v1; 1369 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get = 1370 hal_rx_hw_desc_get_ppduid_get_8074v1; 1371 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get = 1372 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v1; 1373 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get = 1374 hal_rx_msdu_end_sa_sw_peer_id_get_8074v1; 1375 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb = 1376 hal_rx_msdu0_buffer_addr_lsb_8074v1; 1377 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get = 1378 hal_rx_msdu_desc_info_ptr_get_8074v1; 1379 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v1; 1380 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v1; 1381 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v1; 1382 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v1; 1383 hal_soc->ops->hal_rx_get_mac_addr2_valid = 1384 hal_rx_get_mac_addr2_valid_8074v1; 1385 hal_soc->ops->hal_rx_get_filter_category = 1386 hal_rx_get_filter_category_8074v1; 1387 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v1; 1388 hal_soc->ops->hal_reo_config = hal_reo_config_8074v1; 1389 hal_soc->ops->hal_rx_msdu_flow_idx_get = 1390 hal_rx_msdu_flow_idx_get_8074v1; 1391 hal_soc->ops->hal_rx_msdu_flow_idx_invalid = 1392 hal_rx_msdu_flow_idx_invalid_8074v1; 1393 hal_soc->ops->hal_rx_msdu_flow_idx_timeout = 1394 hal_rx_msdu_flow_idx_timeout_8074v1; 1395 hal_soc->ops->hal_rx_msdu_fse_metadata_get = 1396 hal_rx_msdu_fse_metadata_get_8074v1; 1397 hal_soc->ops->hal_rx_msdu_cce_match_get = 1398 hal_rx_msdu_cce_match_get_li; 1399 hal_soc->ops->hal_rx_msdu_cce_metadata_get = 1400 hal_rx_msdu_cce_metadata_get_8074v1; 1401 hal_soc->ops->hal_rx_msdu_get_flow_params = 1402 hal_rx_msdu_get_flow_params_8074v1; 1403 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = 1404 hal_rx_tlv_get_tcp_chksum_8074v1; 1405 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v1; 1406 /* rx - msdu fast path info fields */ 1407 hal_soc->ops->hal_rx_msdu_packet_metadata_get = 1408 hal_rx_msdu_packet_metadata_get_generic_li; 1409 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid = 1410 hal_rx_mpdu_start_tlv_tag_valid_8074v1; 1411 1412 /* rx - TLV struct offsets */ 1413 hal_soc->ops->hal_rx_msdu_end_offset_get = 1414 hal_rx_msdu_end_offset_get_generic; 1415 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic; 1416 hal_soc->ops->hal_rx_msdu_start_offset_get = 1417 hal_rx_msdu_start_offset_get_generic; 1418 hal_soc->ops->hal_rx_mpdu_start_offset_get = 1419 hal_rx_mpdu_start_offset_get_generic; 1420 hal_soc->ops->hal_rx_mpdu_end_offset_get = 1421 hal_rx_mpdu_end_offset_get_generic; 1422 #ifndef NO_RX_PKT_HDR_TLV 1423 hal_soc->ops->hal_rx_pkt_tlv_offset_get = 1424 hal_rx_pkt_tlv_offset_get_generic; 1425 #endif 1426 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v1; 1427 hal_soc->ops->hal_rx_flow_get_tuple_info = 1428 hal_rx_flow_get_tuple_info_li; 1429 hal_soc->ops->hal_rx_flow_delete_entry = 1430 hal_rx_flow_delete_entry_li; 1431 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li; 1432 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 = 1433 hal_compute_reo_remap_ix2_ix3_8074v1; 1434 hal_soc->ops->hal_setup_link_idle_list = 1435 hal_setup_link_idle_list_generic_li; 1436 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li; 1437 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li; 1438 hal_soc->ops->hal_rx_tlv_decrypt_err_get = 1439 hal_rx_tlv_decrypt_err_get_li; 1440 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags = 1441 hal_rx_tlv_get_pkt_capture_flags_li; 1442 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get = 1443 hal_rx_mpdu_info_ampdu_flag_get_li; 1444 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL; 1445 }; 1446 1447 struct hal_hw_srng_config hw_srng_table_8074[] = { 1448 /* TODO: max_rings can populated by querying HW capabilities */ 1449 { /* REO_DST */ 1450 .start_ring_id = HAL_SRNG_REO2SW1, 1451 .max_rings = 4, 1452 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1453 .lmac_ring = FALSE, 1454 .ring_dir = HAL_SRNG_DST_RING, 1455 .reg_start = { 1456 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR( 1457 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1458 HWIO_REO_R2_REO2SW1_RING_HP_ADDR( 1459 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1460 }, 1461 .reg_size = { 1462 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) - 1463 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0), 1464 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) - 1465 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0), 1466 }, 1467 .max_size = 1468 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >> 1469 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT, 1470 }, 1471 { /* REO_EXCEPTION */ 1472 /* Designating REO2TCL ring as exception ring. This ring is 1473 * similar to other REO2SW rings though it is named as REO2TCL. 1474 * Any of theREO2SW rings can be used as exception ring. 1475 */ 1476 .start_ring_id = HAL_SRNG_REO2TCL, 1477 .max_rings = 1, 1478 .entry_size = sizeof(struct reo_destination_ring) >> 2, 1479 .lmac_ring = FALSE, 1480 .ring_dir = HAL_SRNG_DST_RING, 1481 .reg_start = { 1482 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR( 1483 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1484 HWIO_REO_R2_REO2TCL_RING_HP_ADDR( 1485 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1486 }, 1487 /* Single ring - provide ring size if multiple rings of this 1488 * type are supported 1489 */ 1490 .reg_size = {}, 1491 .max_size = 1492 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >> 1493 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT, 1494 }, 1495 { /* REO_REINJECT */ 1496 .start_ring_id = HAL_SRNG_SW2REO, 1497 .max_rings = 1, 1498 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1499 .lmac_ring = FALSE, 1500 .ring_dir = HAL_SRNG_SRC_RING, 1501 .reg_start = { 1502 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR( 1503 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1504 HWIO_REO_R2_SW2REO_RING_HP_ADDR( 1505 SEQ_WCSS_UMAC_REO_REG_OFFSET) 1506 }, 1507 /* Single ring - provide ring size if multiple rings of this 1508 * type are supported 1509 */ 1510 .reg_size = {}, 1511 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >> 1512 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT, 1513 }, 1514 { /* REO_CMD */ 1515 .start_ring_id = HAL_SRNG_REO_CMD, 1516 .max_rings = 1, 1517 .entry_size = (sizeof(struct tlv_32_hdr) + 1518 sizeof(struct reo_get_queue_stats)) >> 2, 1519 .lmac_ring = FALSE, 1520 .ring_dir = HAL_SRNG_SRC_RING, 1521 .reg_start = { 1522 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR( 1523 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1524 HWIO_REO_R2_REO_CMD_RING_HP_ADDR( 1525 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1526 }, 1527 /* Single ring - provide ring size if multiple rings of this 1528 * type are supported 1529 */ 1530 .reg_size = {}, 1531 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1532 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1533 }, 1534 { /* REO_STATUS */ 1535 .start_ring_id = HAL_SRNG_REO_STATUS, 1536 .max_rings = 1, 1537 .entry_size = (sizeof(struct tlv_32_hdr) + 1538 sizeof(struct reo_get_queue_stats_status)) >> 2, 1539 .lmac_ring = FALSE, 1540 .ring_dir = HAL_SRNG_DST_RING, 1541 .reg_start = { 1542 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR( 1543 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1544 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR( 1545 SEQ_WCSS_UMAC_REO_REG_OFFSET), 1546 }, 1547 /* Single ring - provide ring size if multiple rings of this 1548 * type are supported 1549 */ 1550 .reg_size = {}, 1551 .max_size = 1552 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1553 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1554 }, 1555 { /* TCL_DATA */ 1556 .start_ring_id = HAL_SRNG_SW2TCL1, 1557 .max_rings = 3, 1558 .entry_size = (sizeof(struct tlv_32_hdr) + 1559 sizeof(struct tcl_data_cmd)) >> 2, 1560 .lmac_ring = FALSE, 1561 .ring_dir = HAL_SRNG_SRC_RING, 1562 .reg_start = { 1563 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR( 1564 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1565 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR( 1566 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1567 }, 1568 .reg_size = { 1569 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) - 1570 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0), 1571 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) - 1572 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0), 1573 }, 1574 .max_size = 1575 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >> 1576 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT, 1577 }, 1578 { /* TCL_CMD */ 1579 .start_ring_id = HAL_SRNG_SW2TCL_CMD, 1580 .max_rings = 1, 1581 .entry_size = (sizeof(struct tlv_32_hdr) + 1582 sizeof(struct tcl_data_cmd)) >> 2, 1583 .lmac_ring = FALSE, 1584 .ring_dir = HAL_SRNG_SRC_RING, 1585 .reg_start = { 1586 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR( 1587 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1588 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR( 1589 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1590 }, 1591 /* Single ring - provide ring size if multiple rings of this 1592 * type are supported 1593 */ 1594 .reg_size = {}, 1595 .max_size = 1596 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >> 1597 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT, 1598 }, 1599 { /* TCL_STATUS */ 1600 .start_ring_id = HAL_SRNG_TCL_STATUS, 1601 .max_rings = 1, 1602 .entry_size = (sizeof(struct tlv_32_hdr) + 1603 sizeof(struct tcl_status_ring)) >> 2, 1604 .lmac_ring = FALSE, 1605 .ring_dir = HAL_SRNG_DST_RING, 1606 .reg_start = { 1607 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR( 1608 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1609 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR( 1610 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET), 1611 }, 1612 /* Single ring - provide ring size if multiple rings of this 1613 * type are supported 1614 */ 1615 .reg_size = {}, 1616 .max_size = 1617 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >> 1618 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT, 1619 }, 1620 { /* CE_SRC */ 1621 .start_ring_id = HAL_SRNG_CE_0_SRC, 1622 .max_rings = 12, 1623 .entry_size = sizeof(struct ce_src_desc) >> 2, 1624 .lmac_ring = FALSE, 1625 .ring_dir = HAL_SRNG_SRC_RING, 1626 .reg_start = { 1627 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1628 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1629 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1630 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET), 1631 }, 1632 .reg_size = { 1633 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1635 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET - 1636 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET, 1637 }, 1638 .max_size = 1639 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1640 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1641 }, 1642 { /* CE_DST */ 1643 .start_ring_id = HAL_SRNG_CE_0_DST, 1644 .max_rings = 12, 1645 .entry_size = 8 >> 2, 1646 /*TODO: entry_size above should actually be 1647 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition 1648 * of struct ce_dst_desc in HW header files 1649 */ 1650 .lmac_ring = FALSE, 1651 .ring_dir = HAL_SRNG_SRC_RING, 1652 .reg_start = { 1653 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR( 1654 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1655 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR( 1656 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1657 }, 1658 .reg_size = { 1659 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1660 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1661 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1662 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1663 }, 1664 .max_size = 1665 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >> 1666 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT, 1667 }, 1668 { /* CE_DST_STATUS */ 1669 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS, 1670 .max_rings = 12, 1671 .entry_size = sizeof(struct ce_stat_desc) >> 2, 1672 .lmac_ring = FALSE, 1673 .ring_dir = HAL_SRNG_DST_RING, 1674 .reg_start = { 1675 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR( 1676 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1677 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR( 1678 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET), 1679 }, 1680 /* TODO: check destination status ring registers */ 1681 .reg_size = { 1682 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1683 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1684 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET - 1685 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET, 1686 }, 1687 .max_size = 1688 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >> 1689 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT, 1690 }, 1691 { /* WBM_IDLE_LINK */ 1692 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK, 1693 .max_rings = 1, 1694 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2, 1695 .lmac_ring = FALSE, 1696 .ring_dir = HAL_SRNG_SRC_RING, 1697 .reg_start = { 1698 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1699 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1700 }, 1701 /* Single ring - provide ring size if multiple rings of this 1702 * type are supported 1703 */ 1704 .reg_size = {}, 1705 .max_size = 1706 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >> 1707 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT, 1708 }, 1709 { /* SW2WBM_RELEASE */ 1710 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE, 1711 .max_rings = 1, 1712 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1713 .lmac_ring = FALSE, 1714 .ring_dir = HAL_SRNG_SRC_RING, 1715 .reg_start = { 1716 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1717 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1718 }, 1719 /* Single ring - provide ring size if multiple rings of this 1720 * type are supported 1721 */ 1722 .reg_size = {}, 1723 .max_size = 1724 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1725 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1726 }, 1727 { /* WBM2SW_RELEASE */ 1728 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE, 1729 .max_rings = 4, 1730 .entry_size = sizeof(struct wbm_release_ring) >> 2, 1731 .lmac_ring = FALSE, 1732 .ring_dir = HAL_SRNG_DST_RING, 1733 .reg_start = { 1734 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1735 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1736 }, 1737 .reg_size = { 1738 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1739 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1740 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) - 1741 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET), 1742 }, 1743 .max_size = 1744 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >> 1745 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT, 1746 }, 1747 { /* RXDMA_BUF */ 1748 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0, 1749 #ifdef IPA_OFFLOAD 1750 .max_rings = 3, 1751 #else 1752 .max_rings = 2, 1753 #endif 1754 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1755 .lmac_ring = TRUE, 1756 .ring_dir = HAL_SRNG_SRC_RING, 1757 /* reg_start is not set because LMAC rings are not accessed 1758 * from host 1759 */ 1760 .reg_start = {}, 1761 .reg_size = {}, 1762 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1763 }, 1764 { /* RXDMA_DST */ 1765 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0, 1766 .max_rings = 1, 1767 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1768 .lmac_ring = TRUE, 1769 .ring_dir = HAL_SRNG_DST_RING, 1770 /* reg_start is not set because LMAC rings are not accessed 1771 * from host 1772 */ 1773 .reg_start = {}, 1774 .reg_size = {}, 1775 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1776 }, 1777 { /* RXDMA_MONITOR_BUF */ 1778 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF, 1779 .max_rings = 1, 1780 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1781 .lmac_ring = TRUE, 1782 .ring_dir = HAL_SRNG_SRC_RING, 1783 /* reg_start is not set because LMAC rings are not accessed 1784 * from host 1785 */ 1786 .reg_start = {}, 1787 .reg_size = {}, 1788 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1789 }, 1790 { /* RXDMA_MONITOR_STATUS */ 1791 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF, 1792 .max_rings = 1, 1793 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1794 .lmac_ring = TRUE, 1795 .ring_dir = HAL_SRNG_SRC_RING, 1796 /* reg_start is not set because LMAC rings are not accessed 1797 * from host 1798 */ 1799 .reg_start = {}, 1800 .reg_size = {}, 1801 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1802 }, 1803 { /* RXDMA_MONITOR_DST */ 1804 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1, 1805 .max_rings = 1, 1806 .entry_size = sizeof(struct reo_entrance_ring) >> 2, 1807 .lmac_ring = TRUE, 1808 .ring_dir = HAL_SRNG_DST_RING, 1809 /* reg_start is not set because LMAC rings are not accessed 1810 * from host 1811 */ 1812 .reg_start = {}, 1813 .reg_size = {}, 1814 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1815 }, 1816 { /* RXDMA_MONITOR_DESC */ 1817 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC, 1818 .max_rings = 1, 1819 .entry_size = sizeof(struct wbm_buffer_ring) >> 2, 1820 .lmac_ring = TRUE, 1821 .ring_dir = HAL_SRNG_SRC_RING, 1822 /* reg_start is not set because LMAC rings are not accessed 1823 * from host 1824 */ 1825 .reg_start = {}, 1826 .reg_size = {}, 1827 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1828 }, 1829 { /* DIR_BUF_RX_DMA_SRC */ 1830 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING, 1831 .max_rings = 1, 1832 .entry_size = 2, 1833 .lmac_ring = TRUE, 1834 .ring_dir = HAL_SRNG_SRC_RING, 1835 /* reg_start is not set because LMAC rings are not accessed 1836 * from host 1837 */ 1838 .reg_start = {}, 1839 .reg_size = {}, 1840 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1841 }, 1842 #ifdef WLAN_FEATURE_CIF_CFR 1843 { /* WIFI_POS_SRC */ 1844 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING, 1845 .max_rings = 1, 1846 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2, 1847 .lmac_ring = TRUE, 1848 .ring_dir = HAL_SRNG_SRC_RING, 1849 /* reg_start is not set because LMAC rings are not accessed 1850 * from host 1851 */ 1852 .reg_start = {}, 1853 .reg_size = {}, 1854 .max_size = HAL_RXDMA_MAX_RING_SIZE, 1855 }, 1856 #endif 1857 { /* REO2PPE */ 0}, 1858 { /* PPE2TCL */ 0}, 1859 { /* PPE_RELEASE */ 0}, 1860 { /* TX_MONITOR_BUF */ 0}, 1861 { /* TX_MONITOR_DST */ 0}, 1862 { /* SW2RXDMA_NEW */ 0}, 1863 { /* SW2RXDMA_LINK_RELEASE */ 0}, 1864 }; 1865 1866 /** 1867 * hal_qca8074_attach() - Attach 8074 target specific hal_soc ops, 1868 * offset and srng table 1869 * @hal_soc: HAL SoC context 1870 */ 1871 void hal_qca8074_attach(struct hal_soc *hal_soc) 1872 { 1873 hal_soc->hw_srng_table = hw_srng_table_8074; 1874 hal_srng_hw_reg_offset_init_generic(hal_soc); 1875 hal_hw_txrx_default_ops_attach_li(hal_soc); 1876 hal_hw_txrx_ops_attach_qca8074(hal_soc); 1877 } 1878