1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #ifndef _HAL_BE_GENERIC_API_H_ 21 #define _HAL_BE_GENERIC_API_H_ 22 23 #include <hal_be_hw_headers.h> 24 #include "hal_be_tx.h" 25 #include "hal_be_reo.h" 26 #include <hal_api_mon.h> 27 #include <hal_generic_api.h> 28 #include "txmon_tlvs.h" 29 30 /* 31 * Debug macro to print the TLV header tag 32 */ 33 #define SHOW_DEFINED(x) do {} while (0) 34 35 #if defined(WLAN_PKT_CAPTURE_TX_2_0) && !defined(TX_MONITOR_WORD_MASK) 36 typedef struct tx_fes_setup hal_tx_fes_setup_t; 37 typedef struct tx_peer_entry hal_tx_peer_entry_t; 38 typedef struct tx_queue_extension hal_tx_queue_ext_t; 39 typedef struct tx_msdu_start hal_tx_msdu_start_t; 40 typedef struct tx_mpdu_start hal_tx_mpdu_start_t; 41 typedef struct tx_fes_status_end hal_tx_fes_status_end_t; 42 typedef struct response_end_status hal_response_end_status_t; 43 typedef struct tx_fes_status_prot hal_tx_fes_status_prot_t; 44 typedef struct pcu_ppdu_setup_init hal_pcu_ppdu_setup_t; 45 #endif 46 47 #if defined(WLAN_FEATURE_TSF_AUTO_REPORT) || defined(WLAN_CONFIG_TX_DELAY) 48 static inline void 49 hal_tx_comp_get_buffer_timestamp_be(void *desc, 50 struct hal_tx_completion_status *ts) 51 { 52 ts->buffer_timestamp = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 53 BUFFER_TIMESTAMP); 54 } 55 #else /* !(WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY) */ 56 static inline void 57 hal_tx_comp_get_buffer_timestamp_be(void *desc, 58 struct hal_tx_completion_status *ts) 59 { 60 } 61 #endif /* WLAN_FEATURE_TSF_AUTO_REPORT || WLAN_CONFIG_TX_DELAY */ 62 63 /** 64 * hal_tx_comp_get_status_generic_be() - TQM Release reason 65 * @desc: WBM descriptor 66 * @ts1: completion ring Tx status 67 * @hal: hal_soc 68 * 69 * This function will parse the WBM completion descriptor and populate in 70 * HAL structure 71 * 72 * Return: none 73 */ 74 static inline void 75 hal_tx_comp_get_status_generic_be(void *desc, void *ts1, 76 struct hal_soc *hal) 77 { 78 uint8_t rate_stats_valid = 0; 79 uint32_t rate_stats = 0; 80 struct hal_tx_completion_status *ts = 81 (struct hal_tx_completion_status *)ts1; 82 83 ts->ppdu_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 84 TQM_STATUS_NUMBER); 85 ts->ack_frame_rssi = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 86 ACK_FRAME_RSSI); 87 ts->first_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 88 FIRST_MSDU); 89 ts->last_msdu = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 90 LAST_MSDU); 91 #if 0 92 // TODO - This has to be calculated form first and last msdu 93 ts->msdu_part_of_amsdu = HAL_TX_DESC_GET(desc, 94 WBM2SW_COMPLETION_RING_TX, 95 MSDU_PART_OF_AMSDU); 96 #endif 97 98 ts->peer_id = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 99 SW_PEER_ID); 100 ts->tid = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, TID); 101 ts->transmit_cnt = HAL_TX_DESC_GET(desc, WBM2SW_COMPLETION_RING_TX, 102 TRANSMIT_COUNT); 103 104 rate_stats = HAL_TX_DESC_GET(desc, HAL_TX_COMP, TX_RATE_STATS); 105 106 rate_stats_valid = HAL_TX_MS(TX_RATE_STATS_INFO, 107 TX_RATE_STATS_INFO_VALID, rate_stats); 108 109 ts->valid = rate_stats_valid; 110 111 if (rate_stats_valid) { 112 ts->bw = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_BW, 113 rate_stats); 114 ts->pkt_type = HAL_TX_MS(TX_RATE_STATS_INFO, 115 TRANSMIT_PKT_TYPE, rate_stats); 116 ts->stbc = HAL_TX_MS(TX_RATE_STATS_INFO, 117 TRANSMIT_STBC, rate_stats); 118 ts->ldpc = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_LDPC, 119 rate_stats); 120 ts->sgi = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_SGI, 121 rate_stats); 122 ts->mcs = HAL_TX_MS(TX_RATE_STATS_INFO, TRANSMIT_MCS, 123 rate_stats); 124 ts->ofdma = HAL_TX_MS(TX_RATE_STATS_INFO, OFDMA_TRANSMISSION, 125 rate_stats); 126 ts->tones_in_ru = HAL_TX_MS(TX_RATE_STATS_INFO, TONES_IN_RU, 127 rate_stats); 128 } 129 130 ts->release_src = hal_tx_comp_get_buffer_source_generic_be(desc); 131 ts->status = hal_tx_comp_get_release_reason( 132 desc, 133 hal_soc_to_hal_soc_handle(hal)); 134 135 ts->tsf = HAL_TX_DESC_GET(desc, UNIFIED_WBM_RELEASE_RING_6, 136 TX_RATE_STATS_INFO_TX_RATE_STATS); 137 hal_tx_comp_get_buffer_timestamp_be(desc, ts); 138 } 139 140 /** 141 * hal_tx_set_pcp_tid_map_generic_be() - Configure default PCP to TID map table 142 * @soc: HAL SoC context 143 * @map: PCP-TID mapping table 144 * 145 * PCP are mapped to 8 TID values using TID values programmed 146 * in one set of mapping registers PCP_TID_MAP_<0 to 6> 147 * The mapping register has TID mapping for 8 PCP values 148 * 149 * Return: none 150 */ 151 static void hal_tx_set_pcp_tid_map_generic_be(struct hal_soc *soc, uint8_t *map) 152 { 153 uint32_t addr, value; 154 155 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 156 MAC_TCL_REG_REG_BASE); 157 158 value = (map[0] | 159 (map[1] << HWIO_TCL_R0_PCP_TID_MAP_PCP_1_SHFT) | 160 (map[2] << HWIO_TCL_R0_PCP_TID_MAP_PCP_2_SHFT) | 161 (map[3] << HWIO_TCL_R0_PCP_TID_MAP_PCP_3_SHFT) | 162 (map[4] << HWIO_TCL_R0_PCP_TID_MAP_PCP_4_SHFT) | 163 (map[5] << HWIO_TCL_R0_PCP_TID_MAP_PCP_5_SHFT) | 164 (map[6] << HWIO_TCL_R0_PCP_TID_MAP_PCP_6_SHFT) | 165 (map[7] << HWIO_TCL_R0_PCP_TID_MAP_PCP_7_SHFT)); 166 167 HAL_REG_WRITE(soc, addr, (value & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 168 } 169 170 /** 171 * hal_tx_update_pcp_tid_generic_be() - Update the pcp tid map table with 172 * value received from user-space 173 * @soc: HAL SoC context 174 * @pcp: pcp value 175 * @tid : tid value 176 * 177 * Return: void 178 */ 179 static void 180 hal_tx_update_pcp_tid_generic_be(struct hal_soc *soc, 181 uint8_t pcp, uint8_t tid) 182 { 183 uint32_t addr, value, regval; 184 185 addr = HWIO_TCL_R0_PCP_TID_MAP_ADDR( 186 MAC_TCL_REG_REG_BASE); 187 188 value = (uint32_t)tid << (HAL_TX_BITS_PER_TID * pcp); 189 190 /* Read back previous PCP TID config and update 191 * with new config. 192 */ 193 regval = HAL_REG_READ(soc, addr); 194 regval &= ~(HAL_TX_TID_BITS_MASK << (HAL_TX_BITS_PER_TID * pcp)); 195 regval |= value; 196 197 HAL_REG_WRITE(soc, addr, 198 (regval & HWIO_TCL_R0_PCP_TID_MAP_RMSK)); 199 } 200 201 /** 202 * hal_tx_update_tidmap_prty_generic_be() - Update the tid map priority 203 * @soc: HAL SoC context 204 * @value: priority value 205 * 206 * Return: void 207 */ 208 static 209 void hal_tx_update_tidmap_prty_generic_be(struct hal_soc *soc, uint8_t value) 210 { 211 uint32_t addr; 212 213 addr = HWIO_TCL_R0_TID_MAP_PRTY_ADDR( 214 MAC_TCL_REG_REG_BASE); 215 216 HAL_REG_WRITE(soc, addr, 217 (value & HWIO_TCL_R0_TID_MAP_PRTY_RMSK)); 218 } 219 220 /** 221 * hal_rx_get_tlv_size_generic_be() - Get rx packet tlv size 222 * @rx_pkt_tlv_size: TLV size for regular RX packets 223 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 224 * 225 * Return: size of rx pkt tlv before the actual data 226 */ 227 static void hal_rx_get_tlv_size_generic_be(uint16_t *rx_pkt_tlv_size, 228 uint16_t *rx_mon_pkt_tlv_size) 229 { 230 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 231 /* For now mon pkt tlv is same as rx pkt tlv */ 232 *rx_mon_pkt_tlv_size = MON_RX_PKT_TLVS_LEN; 233 } 234 235 /** 236 * hal_rx_flow_get_tuple_info_be() - Setup a flow search entry in HW FST 237 * @rx_fst: Pointer to the Rx Flow Search Table 238 * @hal_hash: HAL 5 tuple hash 239 * @flow_tuple_info: 5-tuple info of the flow returned to the caller 240 * 241 * Return: Success/Failure 242 */ 243 static void * 244 hal_rx_flow_get_tuple_info_be(uint8_t *rx_fst, uint32_t hal_hash, 245 uint8_t *flow_tuple_info) 246 { 247 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst; 248 void *hal_fse = NULL; 249 struct hal_flow_tuple_info *tuple_info 250 = (struct hal_flow_tuple_info *)flow_tuple_info; 251 252 hal_fse = (uint8_t *)fst->base_vaddr + 253 (hal_hash * HAL_RX_FST_ENTRY_SIZE); 254 255 if (!hal_fse || !tuple_info) 256 return NULL; 257 258 if (!HAL_GET_FLD(hal_fse, RX_FLOW_SEARCH_ENTRY, VALID)) 259 return NULL; 260 261 tuple_info->src_ip_127_96 = 262 qdf_ntohl(HAL_GET_FLD(hal_fse, 263 RX_FLOW_SEARCH_ENTRY, 264 SRC_IP_127_96)); 265 tuple_info->src_ip_95_64 = 266 qdf_ntohl(HAL_GET_FLD(hal_fse, 267 RX_FLOW_SEARCH_ENTRY, 268 SRC_IP_95_64)); 269 tuple_info->src_ip_63_32 = 270 qdf_ntohl(HAL_GET_FLD(hal_fse, 271 RX_FLOW_SEARCH_ENTRY, 272 SRC_IP_63_32)); 273 tuple_info->src_ip_31_0 = 274 qdf_ntohl(HAL_GET_FLD(hal_fse, 275 RX_FLOW_SEARCH_ENTRY, 276 SRC_IP_31_0)); 277 tuple_info->dest_ip_127_96 = 278 qdf_ntohl(HAL_GET_FLD(hal_fse, 279 RX_FLOW_SEARCH_ENTRY, 280 DEST_IP_127_96)); 281 tuple_info->dest_ip_95_64 = 282 qdf_ntohl(HAL_GET_FLD(hal_fse, 283 RX_FLOW_SEARCH_ENTRY, 284 DEST_IP_95_64)); 285 tuple_info->dest_ip_63_32 = 286 qdf_ntohl(HAL_GET_FLD(hal_fse, 287 RX_FLOW_SEARCH_ENTRY, 288 DEST_IP_63_32)); 289 tuple_info->dest_ip_31_0 = 290 qdf_ntohl(HAL_GET_FLD(hal_fse, 291 RX_FLOW_SEARCH_ENTRY, 292 DEST_IP_31_0)); 293 tuple_info->dest_port = HAL_GET_FLD(hal_fse, 294 RX_FLOW_SEARCH_ENTRY, 295 DEST_PORT); 296 tuple_info->src_port = HAL_GET_FLD(hal_fse, 297 RX_FLOW_SEARCH_ENTRY, 298 SRC_PORT); 299 tuple_info->l4_protocol = HAL_GET_FLD(hal_fse, 300 RX_FLOW_SEARCH_ENTRY, 301 L4_PROTOCOL); 302 303 return hal_fse; 304 } 305 306 /** 307 * hal_rx_flow_delete_entry_be() - Setup a flow search entry in HW FST 308 * @rx_fst: Pointer to the Rx Flow Search Table 309 * @hal_rx_fse: Pointer to the Rx Flow that is to be deleted from the FST 310 * 311 * Return: Success/Failure 312 */ 313 static QDF_STATUS 314 hal_rx_flow_delete_entry_be(uint8_t *rx_fst, void *hal_rx_fse) 315 { 316 uint8_t *fse = (uint8_t *)hal_rx_fse; 317 318 if (!HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID)) 319 return QDF_STATUS_E_NOENT; 320 321 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID); 322 323 return QDF_STATUS_SUCCESS; 324 } 325 326 /** 327 * hal_rx_fst_get_fse_size_be() - Retrieve the size of each entry in Rx FST 328 * 329 * Return: size of each entry/flow in Rx FST 330 */ 331 static inline uint32_t 332 hal_rx_fst_get_fse_size_be(void) 333 { 334 return HAL_RX_FST_ENTRY_SIZE; 335 } 336 337 /* 338 * TX MONITOR 339 */ 340 341 #ifdef WLAN_PKT_CAPTURE_TX_2_0 342 /** 343 * hal_txmon_is_mon_buf_addr_tlv_generic_be() - api to find mon buffer tlv 344 * @tx_tlv_hdr: pointer to TLV header 345 * 346 * Return: bool based on tlv tag matches monitor buffer address tlv 347 */ 348 static inline bool 349 hal_txmon_is_mon_buf_addr_tlv_generic_be(void *tx_tlv_hdr) 350 { 351 uint32_t tlv_tag; 352 353 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 354 355 if (WIFIMON_BUFFER_ADDR_E == tlv_tag) 356 return true; 357 358 return false; 359 } 360 361 /** 362 * hal_txmon_populate_packet_info_generic_be() - api to populate packet info 363 * @tx_tlv: pointer to TLV header 364 * @packet_info: place holder for packet info 365 * 366 * Return: Address to void 367 */ 368 static inline void 369 hal_txmon_populate_packet_info_generic_be(void *tx_tlv, void *packet_info) 370 { 371 struct hal_mon_packet_info *pkt_info; 372 struct mon_buffer_addr *addr = (struct mon_buffer_addr *)tx_tlv; 373 374 pkt_info = (struct hal_mon_packet_info *)packet_info; 375 pkt_info->sw_cookie = (((uint64_t)addr->buffer_virt_addr_63_32 << 32) | 376 (addr->buffer_virt_addr_31_0)); 377 pkt_info->dma_length = addr->dma_length + 1; 378 pkt_info->msdu_continuation = addr->msdu_continuation; 379 pkt_info->truncated = addr->truncated; 380 } 381 382 /** 383 * hal_txmon_parse_tx_fes_setup() - parse tx_fes_setup tlv 384 * 385 * @tx_tlv: pointer to tx_fes_setup tlv header 386 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 387 * 388 * Return: void 389 */ 390 static inline void 391 hal_txmon_parse_tx_fes_setup(void *tx_tlv, 392 struct hal_tx_ppdu_info *tx_ppdu_info) 393 { 394 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 395 396 tx_ppdu_info->num_users = tx_fes_setup->number_of_users; 397 if (tx_ppdu_info->num_users == 0) 398 tx_ppdu_info->num_users = 1; 399 400 TXMON_HAL(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 401 TXMON_HAL_STATUS(tx_ppdu_info, ppdu_id) = tx_fes_setup->schedule_id; 402 } 403 404 /** 405 * hal_txmon_get_num_users() - get num users from tx_fes_setup tlv 406 * 407 * @tx_tlv: pointer to tx_fes_setup tlv header 408 * 409 * Return: number of users 410 */ 411 static inline uint8_t 412 hal_txmon_get_num_users(void *tx_tlv) 413 { 414 hal_tx_fes_setup_t *tx_fes_setup = (hal_tx_fes_setup_t *)tx_tlv; 415 416 return tx_fes_setup->number_of_users; 417 } 418 419 /** 420 * hal_txmon_parse_tx_fes_status_end() - parse tx_fes_status_end tlv 421 * 422 * @tx_tlv: pointer to tx_fes_status_end tlv header 423 * @ppdu_info: pointer to hal_tx_ppdu_info 424 * @tx_status_info: pointer to hal_tx_status_info 425 * 426 * Return: void 427 */ 428 static inline void 429 hal_txmon_parse_tx_fes_status_end(void *tx_tlv, 430 struct hal_tx_ppdu_info *ppdu_info, 431 struct hal_tx_status_info *tx_status_info) 432 { 433 hal_tx_fes_status_end_t *tx_fes_end = (hal_tx_fes_status_end_t *)tx_tlv; 434 435 if (tx_fes_end->phytx_abort_request_info_valid) { 436 TXMON_STATUS_INFO(tx_status_info, phy_abort_reason) = 437 tx_fes_end->phytx_abort_request_info_details.phytx_abort_reason; 438 TXMON_STATUS_INFO(tx_status_info, phy_abort_user_number) = 439 tx_fes_end->phytx_abort_request_info_details.user_number; 440 } 441 442 TXMON_STATUS_INFO(tx_status_info, 443 response_type) = tx_fes_end->response_type; 444 TXMON_STATUS_INFO(tx_status_info, 445 r2r_to_follow) = tx_fes_end->r2r_end_status_to_follow; 446 /* update phy timestamp to ppdu timestamp */ 447 TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) = 448 (tx_fes_end->start_of_frame_timestamp_15_0 | 449 tx_fes_end->start_of_frame_timestamp_31_16 << 450 HAL_TX_LSB(TX_FES_STATUS_END, START_OF_FRAME_TIMESTAMP_31_16)); 451 } 452 453 /** 454 * hal_txmon_parse_response_end_status() - parse response_end_status tlv 455 * 456 * @tx_tlv: pointer to response_end_status tlv header 457 * @ppdu_info: pointer to hal_tx_ppdu_info 458 * @tx_status_info: pointer to hal_tx_status_info 459 * 460 * Return: void 461 */ 462 static inline void 463 hal_txmon_parse_response_end_status(void *tx_tlv, 464 struct hal_tx_ppdu_info *ppdu_info, 465 struct hal_tx_status_info *tx_status_info) 466 { 467 hal_response_end_status_t *resp_end_status = NULL; 468 469 resp_end_status = (hal_response_end_status_t *)tx_tlv; 470 TXMON_HAL_STATUS(ppdu_info, bw) = resp_end_status->coex_based_tx_bw; 471 TXMON_STATUS_INFO(tx_status_info, generated_response) = 472 resp_end_status->generated_response; 473 TXMON_STATUS_INFO(tx_status_info, mba_count) = 474 resp_end_status->mba_user_count; 475 TXMON_STATUS_INFO(tx_status_info, mba_fake_bitmap_count) = 476 resp_end_status->mba_fake_bitmap_count; 477 TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) = 478 (resp_end_status->start_of_frame_timestamp_15_0 | 479 (resp_end_status->start_of_frame_timestamp_31_16 << 16)); 480 } 481 482 /** 483 * hal_txmon_parse_pcu_ppdu_setup_init() - parse pcu_ppdu_setup_init tlv 484 * 485 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 486 * @data_status_info: pointer to data hal_tx_status_info 487 * @prot_status_info: pointer to protection hal_tx_status_info 488 * 489 * Return: void 490 */ 491 static inline void 492 hal_txmon_parse_pcu_ppdu_setup_init(void *tx_tlv, 493 struct hal_tx_status_info *data_status_info, 494 struct hal_tx_status_info *prot_status_info) 495 { 496 hal_pcu_ppdu_setup_t *pcu_init = (hal_pcu_ppdu_setup_t *)tx_tlv; 497 498 prot_status_info->protection_addr = 499 pcu_init->use_address_fields_for_protection; 500 /* protection frame address 1 */ 501 *(uint32_t *)&prot_status_info->addr1[0] = 502 pcu_init->protection_frame_ad1_31_0; 503 *(uint16_t *)&prot_status_info->addr1[4] = 504 pcu_init->protection_frame_ad1_47_32; 505 /* protection frame address 2 */ 506 *(uint32_t *)&prot_status_info->addr2[0] = 507 pcu_init->protection_frame_ad2_15_0; 508 *(uint32_t *)&prot_status_info->addr2[2] = 509 pcu_init->protection_frame_ad2_47_16; 510 /* protection frame address 3 */ 511 *(uint32_t *)&prot_status_info->addr3[0] = 512 pcu_init->protection_frame_ad3_31_0; 513 *(uint16_t *)&prot_status_info->addr3[4] = 514 pcu_init->protection_frame_ad3_47_32; 515 /* protection frame address 4 */ 516 *(uint32_t *)&prot_status_info->addr4[0] = 517 pcu_init->protection_frame_ad4_15_0; 518 *(uint32_t *)&prot_status_info->addr4[2] = 519 pcu_init->protection_frame_ad4_47_16; 520 } 521 522 /** 523 * hal_txmon_parse_peer_entry() - parse peer entry tlv 524 * 525 * @tx_tlv: pointer to peer_entry tlv header 526 * @user_id: user_id 527 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 528 * @tx_status_info: pointer to hal_tx_status_info 529 * 530 * Return: void 531 */ 532 static inline void 533 hal_txmon_parse_peer_entry(void *tx_tlv, 534 uint8_t user_id, 535 struct hal_tx_ppdu_info *tx_ppdu_info, 536 struct hal_tx_status_info *tx_status_info) 537 { 538 hal_tx_peer_entry_t *peer_entry = (hal_tx_peer_entry_t *)tx_tlv; 539 540 *(uint32_t *)&tx_status_info->addr1[0] = 541 peer_entry->mac_addr_a_31_0; 542 *(uint16_t *)&tx_status_info->addr1[4] = 543 peer_entry->mac_addr_a_47_32; 544 *(uint32_t *)&tx_status_info->addr2[0] = 545 peer_entry->mac_addr_b_15_0; 546 *(uint32_t *)&tx_status_info->addr2[2] = 547 peer_entry->mac_addr_b_47_16; 548 TXMON_HAL_USER(tx_ppdu_info, user_id, sw_peer_id) = 549 peer_entry->sw_peer_id; 550 } 551 552 /** 553 * hal_txmon_parse_queue_exten() - parse queue exten tlv 554 * 555 * @tx_tlv: pointer to queue exten tlv header 556 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 557 * 558 * Return: void 559 */ 560 static inline void 561 hal_txmon_parse_queue_exten(void *tx_tlv, 562 struct hal_tx_ppdu_info *tx_ppdu_info) 563 { 564 hal_tx_queue_ext_t *queue_ext = (hal_tx_queue_ext_t *)tx_tlv; 565 566 TXMON_HAL_STATUS(tx_ppdu_info, frame_control) = queue_ext->frame_ctl; 567 TXMON_HAL_STATUS(tx_ppdu_info, frame_control_info_valid) = true; 568 } 569 570 /** 571 * hal_txmon_parse_mpdu_start() - parse mpdu start tlv 572 * 573 * @tx_tlv: pointer to mpdu start tlv header 574 * @user_id: user id 575 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 576 * 577 * Return: void 578 */ 579 static inline void 580 hal_txmon_parse_mpdu_start(void *tx_tlv, uint8_t user_id, 581 struct hal_tx_ppdu_info *tx_ppdu_info) 582 { 583 hal_tx_mpdu_start_t *mpdu_start = (hal_tx_mpdu_start_t *)tx_tlv; 584 585 TXMON_HAL_USER(tx_ppdu_info, user_id, start_seq) = 586 mpdu_start->mpdu_sequence_number; 587 TXMON_HAL(tx_ppdu_info, cur_usr_idx) = user_id; 588 } 589 590 /** 591 * hal_txmon_parse_msdu_start() - parse msdu start tlv 592 * 593 * @tx_tlv: pointer to msdu start tlv header 594 * @user_id: user id 595 * @tx_ppdu_info: pointer to hal_tx_ppdu_info 596 * 597 * Return: void 598 */ 599 static inline void 600 hal_txmon_parse_msdu_start(void *tx_tlv, uint8_t user_id, 601 struct hal_tx_ppdu_info *tx_ppdu_info) 602 { 603 } 604 605 /** 606 * hal_txmon_parse_tx_fes_status_prot() - parse tx_fes_status_prot tlv 607 * 608 * @tx_tlv: pointer to pcu_ppdu_setup_init tlv header 609 * @ppdu_info: pointer to hal_tx_ppdu_info 610 * @tx_status_info: pointer to hal_tx_status_info 611 * 612 * Return: void 613 */ 614 static inline void 615 hal_txmon_parse_tx_fes_status_prot(void *tx_tlv, 616 struct hal_tx_ppdu_info *ppdu_info, 617 struct hal_tx_status_info *tx_status_info) 618 { 619 hal_tx_fes_status_prot_t *fes_prot = (hal_tx_fes_status_prot_t *)tx_tlv; 620 621 TXMON_HAL_STATUS(ppdu_info, ppdu_timestamp) = 622 (fes_prot->start_of_frame_timestamp_15_0 | 623 fes_prot->start_of_frame_timestamp_31_16 << 15); 624 } 625 626 /** 627 * get_ru_offset_from_start_index() - api to get ru offset from ru index 628 * 629 * @ru_size: RU size 630 * @start_idx: Start index 631 * 632 * Return: uint8_t ru allocation offset 633 */ 634 static inline 635 uint8_t get_ru_offset_from_start_index(uint8_t ru_size, uint8_t start_idx) 636 { 637 uint8_t ru_alloc_offset[HAL_MAX_DL_MU_USERS][HAL_MAX_RU_INDEX] = { 638 {0, 0, 0, 0, 0, 0, 0}, 639 {1, 0, 0, 0, 0, 0, 0}, 640 {2, 1, 0, 0, 0, 0, 0}, 641 {3, 1, 0, 0, 0, 0, 0}, 642 {4, 0, 0, 0, 0, 0, 0}, 643 {5, 2, 1, 0, 0, 0, 0}, 644 {6, 2, 1, 0, 0, 0, 0}, 645 {7, 3, 1, 0, 0, 0, 0}, 646 {8, 3, 1, 0, 0, 0, 0}, 647 {9, 4, 2, 1, 0, 0, 0}, 648 {10, 4, 2, 1, 0, 0, 0}, 649 {11, 5, 2, 1, 0, 0, 0}, 650 {12, 5, 2, 1, 0, 0, 0}, 651 {13, 0, 0, 1, 0, 0, 0}, 652 {14, 6, 3, 1, 0, 0, 0}, 653 {15, 6, 3, 1, 0, 0, 0}, 654 {16, 7, 3, 1, 0, 0, 0}, 655 {17, 7, 3, 1, 0, 0, 0}, 656 {18, 0, 0, 0, 0, 0, 0}, 657 {19, 8, 4, 2, 1, 0, 0}, 658 {20, 8, 4, 2, 1, 0, 0}, 659 {21, 9, 4, 2, 1, 0, 0}, 660 {22, 9, 4, 2, 1, 0, 0}, 661 {23, 0, 0, 2, 1, 0, 0}, 662 {24, 10, 5, 2, 1, 0, 0}, 663 {25, 10, 5, 2, 1, 0, 0}, 664 {26, 11, 5, 2, 1, 0, 0}, 665 {27, 11, 5, 2, 1, 0, 0}, 666 {28, 12, 6, 3, 1, 0, 0}, 667 {29, 12, 6, 3, 1, 0, 0}, 668 {30, 13, 6, 3, 1, 0, 0}, 669 {31, 13, 6, 3, 1, 0, 0}, 670 {32, 0, 0, 3, 1, 0, 0}, 671 {33, 14, 7, 3, 1, 0, 0}, 672 {34, 14, 7, 3, 1, 0, 0}, 673 {35, 15, 7, 3, 1, 0, 0}, 674 {36, 15, 7, 3, 1, 0, 0}, 675 }; 676 677 if (start_idx >= HAL_MAX_UL_MU_USERS || ru_size >= HAL_MAX_RU_INDEX) 678 return 0; 679 680 return ru_alloc_offset[start_idx][ru_size]; 681 } 682 683 /** 684 * hal_txmon_parse_fw2sw() - parse firmware to software tlv 685 * 686 * @tx_tlv: pointer to firmware to software tlvmpdu start tlv header 687 * @type: place where this tlv is generated 688 * @status_info: pointer to hal_tx_status_info 689 * 690 * Return: void 691 */ 692 static inline void 693 hal_txmon_parse_fw2sw(void *tx_tlv, uint8_t type, 694 struct hal_tx_status_info *status_info) 695 { 696 uint32_t *msg = (uint32_t *)tx_tlv; 697 698 switch (type) { 699 case TXMON_FW2SW_TYPE_FES_SETUP: 700 { 701 uint32_t schedule_id; 702 uint16_t c_freq1; 703 uint16_t c_freq2; 704 uint16_t freq_mhz; 705 uint8_t phy_mode; 706 707 c_freq1 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ1_GET(*msg); 708 c_freq2 = TXMON_FW2SW_MON_FES_SETUP_BAND_CENTER_FREQ2_GET(*msg); 709 710 msg++; 711 phy_mode = TXMON_FW2SW_MON_FES_SETUP_PHY_MODE_GET(*msg); 712 freq_mhz = TXMON_FW2SW_MON_FES_SETUP_MHZ_GET(*msg); 713 714 msg++; 715 schedule_id = TXMON_FW2SW_MON_FES_SETUP_SCHEDULE_ID_GET(*msg); 716 717 TXMON_STATUS_INFO(status_info, band_center_freq1) = c_freq1; 718 TXMON_STATUS_INFO(status_info, band_center_freq2) = c_freq2; 719 TXMON_STATUS_INFO(status_info, freq) = freq_mhz; 720 TXMON_STATUS_INFO(status_info, phy_mode) = phy_mode; 721 TXMON_STATUS_INFO(status_info, schedule_id) = schedule_id; 722 723 break; 724 } 725 case TXMON_FW2SW_TYPE_FES_SETUP_USER: 726 { 727 break; 728 } 729 case TXMON_FW2SW_TYPE_FES_SETUP_EXT: 730 { 731 break; 732 } 733 }; 734 } 735 736 /** 737 * hal_txmon_parse_u_sig_hdr() - parse u_sig header information from tlv 738 * 739 * @tx_tlv: pointer to mactx_u_sig_eht_su_mu/tb tlv 740 * @ppdu_info: pointer to hal_tx_ppdu_info 741 * 742 * Return: void 743 */ 744 static inline void 745 hal_txmon_parse_u_sig_hdr(void *tx_tlv, struct hal_tx_ppdu_info *ppdu_info) 746 { 747 struct hal_mon_usig_hdr *usig = (struct hal_mon_usig_hdr *)tx_tlv; 748 struct hal_mon_usig_cmn *usig_1 = &usig->usig_1; 749 uint8_t bad_usig_crc; 750 751 bad_usig_crc = HAL_TX_DESC_GET_64(tx_tlv, 752 MACTX_U_SIG_EHT_SU_MU_MACTX_U_SIG_EHT_SU_MU_INFO_DETAILS, 753 CRC) ? 0 : 1; 754 755 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 756 QDF_MON_STATUS_USIG_PHY_VERSION_KNOWN | 757 QDF_MON_STATUS_USIG_BW_KNOWN | 758 QDF_MON_STATUS_USIG_UL_DL_KNOWN | 759 QDF_MON_STATUS_USIG_BSS_COLOR_KNOWN | 760 QDF_MON_STATUS_USIG_TXOP_KNOWN; 761 762 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 763 (usig_1->phy_version << 764 QDF_MON_STATUS_USIG_PHY_VERSION_SHIFT); 765 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 766 (usig_1->bw << QDF_MON_STATUS_USIG_BW_SHIFT); 767 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 768 (usig_1->ul_dl << QDF_MON_STATUS_USIG_UL_DL_SHIFT); 769 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 770 (usig_1->bss_color << 771 QDF_MON_STATUS_USIG_BSS_COLOR_SHIFT); 772 TXMON_HAL_STATUS(ppdu_info, usig_common) |= 773 (usig_1->txop << QDF_MON_STATUS_USIG_TXOP_SHIFT); 774 TXMON_HAL_STATUS(ppdu_info, usig_common) |= bad_usig_crc; 775 TXMON_HAL_STATUS(ppdu_info, bw) = usig_1->bw; 776 777 TXMON_HAL_STATUS(ppdu_info, usig_flags) = 1; 778 } 779 780 /** 781 * hal_txmon_populate_he_data_per_user() - populate he data per user 782 * 783 * @usr: pointer to hal_txmon_user_desc_per_user 784 * @user_id: user index 785 * @ppdu_info: pointer to hal_tx_ppdu_info 786 * 787 * Return: void 788 */ 789 static inline void 790 hal_txmon_populate_he_data_per_user(struct hal_txmon_user_desc_per_user *usr, 791 uint32_t user_id, 792 struct hal_tx_ppdu_info *ppdu_info) 793 { 794 uint32_t he_data1 = TXMON_HAL_USER(ppdu_info, user_id, he_data1); 795 uint32_t he_data2 = TXMON_HAL_USER(ppdu_info, user_id, he_data2); 796 uint32_t he_data3 = TXMON_HAL_USER(ppdu_info, user_id, he_data3); 797 uint32_t he_data5 = TXMON_HAL_USER(ppdu_info, user_id, he_data5); 798 uint32_t he_data6 = TXMON_HAL_USER(ppdu_info, user_id, he_data6); 799 800 /* populate */ 801 /* BEAM CHANGE */ 802 he_data1 |= QDF_MON_STATUS_HE_BEAM_CHANGE_KNOWN; 803 he_data1 |= QDF_MON_STATUS_TXBF_KNOWN; 804 he_data5 |= (!!usr->user_bf_type << QDF_MON_STATUS_TXBF_SHIFT); 805 he_data3 |= (!!usr->user_bf_type << QDF_MON_STATUS_BEAM_CHANGE_SHIFT); 806 807 /* UL/DL known */ 808 he_data1 |= QDF_MON_STATUS_HE_DL_UL_KNOWN; 809 he_data3 |= (1 << QDF_MON_STATUS_DL_UL_SHIFT); 810 811 /* MCS */ 812 he_data1 |= QDF_MON_STATUS_HE_MCS_KNOWN; 813 he_data3 |= (usr->mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT); 814 /* DCM */ 815 he_data1 |= QDF_MON_STATUS_HE_DCM_KNOWN; 816 he_data3 |= (usr->dcm << QDF_MON_STATUS_DCM_SHIFT); 817 /* LDPC EXTRA SYMB */ 818 he_data1 |= QDF_MON_STATUS_HE_LDPC_EXTRA_SYMBOL_KNOWN; 819 he_data3 |= (usr->ldpc_extra_symbol << 820 QDF_MON_STATUS_LDPC_EXTRA_SYMBOL_SHIFT); 821 /* RU offset and RU */ 822 he_data2 |= QDF_MON_STATUS_RU_ALLOCATION_OFFSET_KNOWN; 823 he_data2 |= (get_ru_offset_from_start_index(usr->ru_size, 824 usr->ru_start_index) << 825 QDF_MON_STATUS_RU_ALLOCATION_SHIFT); 826 /* Data BW and RU allocation */ 827 if (usr->ru_size < HAL_MAX_RU_INDEX) { 828 /* update bandwidth if it is full bandwidth */ 829 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 830 he_data5 = (he_data5 & 0xFFF0) | (4 + usr->ru_size); 831 } 832 833 he_data6 |= (usr->nss & 0xF); 834 TXMON_HAL_USER(ppdu_info, user_id, mcs) = usr->mcs; 835 836 /* update stack variable to ppdu_info */ 837 TXMON_HAL_USER(ppdu_info, user_id, he_data1) = he_data1; 838 TXMON_HAL_USER(ppdu_info, user_id, he_data2) = he_data2; 839 TXMON_HAL_USER(ppdu_info, user_id, he_data3) = he_data3; 840 TXMON_HAL_USER(ppdu_info, user_id, he_data5) = he_data5; 841 TXMON_HAL_USER(ppdu_info, user_id, he_data6) = he_data6; 842 } 843 844 /** 845 * hal_txmon_get_user_desc_per_user() - get mactx user desc per user from tlv 846 * 847 * @tx_tlv: pointer to mactx_user_desc_per_user tlv 848 * @usr: pointer to hal_txmon_user_desc_per_user 849 * 850 * Return: void 851 */ 852 static inline void 853 hal_txmon_get_user_desc_per_user(void *tx_tlv, 854 struct hal_txmon_user_desc_per_user *usr) 855 { 856 usr->psdu_length = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 857 PSDU_LENGTH); 858 usr->ru_start_index = HAL_TX_DESC_GET_64(tx_tlv, 859 MACTX_USER_DESC_PER_USER, 860 RU_START_INDEX); 861 usr->ru_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 862 RU_SIZE); 863 usr->ofdma_mu_mimo_enabled = 864 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 865 OFDMA_MU_MIMO_ENABLED); 866 usr->nss = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 867 NSS) + 1; 868 usr->stream_offset = HAL_TX_DESC_GET_64(tx_tlv, 869 MACTX_USER_DESC_PER_USER, 870 STREAM_OFFSET); 871 usr->mcs = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, MCS); 872 usr->dcm = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, DCM); 873 usr->fec_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 874 FEC_TYPE); 875 usr->user_bf_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 876 USER_BF_TYPE); 877 usr->drop_user_cbf = HAL_TX_DESC_GET_64(tx_tlv, 878 MACTX_USER_DESC_PER_USER, 879 DROP_USER_CBF); 880 usr->ldpc_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv, 881 MACTX_USER_DESC_PER_USER, 882 LDPC_EXTRA_SYMBOL); 883 usr->force_extra_symbol = HAL_TX_DESC_GET_64(tx_tlv, 884 MACTX_USER_DESC_PER_USER, 885 FORCE_EXTRA_SYMBOL); 886 usr->sw_peer_id = HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_PER_USER, 887 SW_PEER_ID); 888 } 889 890 /** 891 * hal_txmon_populate_eht_sig_per_user() - populate eht sig user information 892 * 893 * @usr: pointer to hal_txmon_user_desc_per_user 894 * @user_id: user index 895 * @ppdu_info: pointer to hal_tx_ppdu_info 896 * 897 * Return: void 898 */ 899 static inline void 900 hal_txmon_populate_eht_sig_per_user(struct hal_txmon_user_desc_per_user *usr, 901 uint32_t user_id, 902 struct hal_tx_ppdu_info *ppdu_info) 903 { 904 uint32_t eht_known = 0; 905 uint32_t eht_data[6] = {0}; 906 uint8_t i = 0; 907 908 eht_known = QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_KNOWN; 909 910 eht_data[0] |= (usr->ldpc_extra_symbol << 911 QDF_MON_STATUS_EHT_LDPC_EXTRA_SYMBOL_SEG_SHIFT); 912 913 TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known; 914 915 for (i = 0; i < 6; i++) 916 TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i]; 917 } 918 919 /** 920 * hal_txmon_parse_user_desc_per_user() - parse mactx user desc per user 921 * 922 * @tx_tlv: pointer to mactx_user_desc_per_user tlv 923 * @user_id: user index 924 * @ppdu_info: pointer to hal_tx_ppdu_info 925 * 926 * Return: void 927 */ 928 static inline void 929 hal_txmon_parse_user_desc_per_user(void *tx_tlv, uint32_t user_id, 930 struct hal_tx_ppdu_info *ppdu_info) 931 { 932 struct hal_txmon_user_desc_per_user usr_info = {0}; 933 934 hal_txmon_get_user_desc_per_user(tx_tlv, &usr_info); 935 936 /* based on preamble type populate user desc user info */ 937 if (TXMON_HAL_STATUS(ppdu_info, he_flags)) 938 hal_txmon_populate_he_data_per_user(&usr_info, 939 user_id, ppdu_info); 940 941 hal_txmon_populate_eht_sig_per_user(&usr_info, user_id, ppdu_info); 942 } 943 944 /** 945 * hal_txmon_get_user_desc_common() - update hal_txmon_usr_desc_common from tlv 946 * 947 * @tx_tlv: pointer to mactx_user_desc_common tlv 948 * @usr_common: pointer to hal_txmon_usr_desc_common 949 * 950 * Return: void 951 */ 952 static inline void 953 hal_txmon_get_user_desc_common(void *tx_tlv, 954 struct hal_txmon_usr_desc_common *usr_common) 955 { 956 usr_common->ltf_size = 957 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, LTF_SIZE); 958 usr_common->pkt_extn_pe = 959 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 960 PACKET_EXTENSION_PE_DISAMBIGUITY); 961 usr_common->a_factor = 962 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 963 PACKET_EXTENSION_A_FACTOR); 964 usr_common->center_ru_0 = 965 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_0); 966 usr_common->center_ru_1 = 967 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, CENTER_RU_1); 968 usr_common->num_ltf_symbols = 969 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 970 NUM_LTF_SYMBOLS); 971 usr_common->doppler_indication = 972 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 973 DOPPLER_INDICATION); 974 usr_common->spatial_reuse = 975 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 976 SPATIAL_REUSE); 977 978 usr_common->ru_channel_0[0] = 979 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 980 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_0); 981 usr_common->ru_channel_0[1] = 982 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 983 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_1); 984 usr_common->ru_channel_0[2] = 985 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 986 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_2); 987 usr_common->ru_channel_0[3] = 988 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 989 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND0_3); 990 usr_common->ru_channel_0[4] = 991 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 992 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_0); 993 usr_common->ru_channel_0[5] = 994 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 995 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_1); 996 usr_common->ru_channel_0[6] = 997 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 998 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_2); 999 usr_common->ru_channel_0[7] = 1000 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1001 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND0_3); 1002 1003 usr_common->ru_channel_1[0] = 1004 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1005 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_0); 1006 usr_common->ru_channel_1[1] = 1007 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1008 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_1); 1009 usr_common->ru_channel_1[2] = 1010 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1011 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_2); 1012 usr_common->ru_channel_1[3] = 1013 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1014 RU_ALLOCATION_0123_DETAILS_RU_ALLOCATION_BAND1_3); 1015 usr_common->ru_channel_1[4] = 1016 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1017 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_0); 1018 usr_common->ru_channel_1[5] = 1019 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1020 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_1); 1021 usr_common->ru_channel_1[6] = 1022 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1023 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_2); 1024 usr_common->ru_channel_1[7] = 1025 HAL_TX_DESC_GET_64(tx_tlv, MACTX_USER_DESC_COMMON, 1026 RU_ALLOCATION_4567_DETAILS_RU_ALLOCATION_BAND1_3); 1027 } 1028 1029 /** 1030 * hal_txmon_populate_he_data_common() - populate he data common information 1031 * 1032 * @usr_common: pointer to hal_txmon_usr_desc_common 1033 * @user_id: user index 1034 * @ppdu_info: pointer to hal_tx_ppdu_info 1035 * 1036 * Return: void 1037 */ 1038 static inline void 1039 hal_txmon_populate_he_data_common(struct hal_txmon_usr_desc_common *usr_common, 1040 uint32_t user_id, 1041 struct hal_tx_ppdu_info *ppdu_info) 1042 { 1043 /* HE data 1 */ 1044 TXMON_HAL_USER(ppdu_info, 1045 user_id, he_data1) |= QDF_MON_STATUS_HE_DOPPLER_KNOWN; 1046 1047 /* HE data 2 */ 1048 TXMON_HAL_USER(ppdu_info, user_id, 1049 he_data2) |= (QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 1050 QDF_MON_STATUS_LTF_SYMBOLS_KNOWN); 1051 1052 /* HE data 5 */ 1053 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 1054 (usr_common->pkt_extn_pe << 1055 QDF_MON_STATUS_PE_DISAMBIGUITY_SHIFT) | 1056 (usr_common->a_factor << QDF_MON_STATUS_PRE_FEC_PAD_SHIFT) | 1057 ((1 + usr_common->ltf_size) << 1058 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT) | 1059 (usr_common->num_ltf_symbols << 1060 QDF_MON_STATUS_HE_LTF_SYM_SHIFT); 1061 1062 /* HE data 6 */ 1063 TXMON_HAL_USER(ppdu_info, user_id, 1064 he_data6) |= (usr_common->doppler_indication << 1065 QDF_MON_STATUS_DOPPLER_SHIFT); 1066 } 1067 1068 /** 1069 * hal_txmon_populate_he_mu_common() - populate he mu common information 1070 * 1071 * @usr_common: pointer to hal_txmon_usr_desc_common 1072 * @user_id: user index 1073 * @ppdu_info: pointer to hal_tx_ppdu_info 1074 * 1075 * Return: void 1076 */ 1077 static inline void 1078 hal_txmon_populate_he_mu_common(struct hal_txmon_usr_desc_common *usr_common, 1079 uint32_t user_id, 1080 struct hal_tx_ppdu_info *ppdu_info) 1081 { 1082 uint16_t he_mu_flag_1 = 0; 1083 uint16_t he_mu_flag_2 = 0; 1084 uint16_t i = 0; 1085 1086 he_mu_flag_1 |= (QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 1087 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 1088 ((usr_common->center_ru_0 << 1089 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_SHIFT) & 1090 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_VALUE)); 1091 he_mu_flag_2 |= ((usr_common->center_ru_1 << 1092 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_SHIFT) & 1093 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_VALUE); 1094 1095 for (i = 0; i < usr_common->num_users; i++) { 1096 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 1097 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 1098 1099 /* channel 1 */ 1100 TXMON_HAL_USER(ppdu_info, i, he_RU[0]) = 1101 usr_common->ru_channel_0[0]; 1102 TXMON_HAL_USER(ppdu_info, i, he_RU[1]) = 1103 usr_common->ru_channel_0[1]; 1104 TXMON_HAL_USER(ppdu_info, i, he_RU[2]) = 1105 usr_common->ru_channel_0[2]; 1106 TXMON_HAL_USER(ppdu_info, i, he_RU[3]) = 1107 usr_common->ru_channel_0[3]; 1108 /* channel 2 */ 1109 TXMON_HAL_USER(ppdu_info, i, he_RU[4]) = 1110 usr_common->ru_channel_1[0]; 1111 TXMON_HAL_USER(ppdu_info, i, he_RU[5]) = 1112 usr_common->ru_channel_1[1]; 1113 TXMON_HAL_USER(ppdu_info, i, he_RU[6]) = 1114 usr_common->ru_channel_1[2]; 1115 TXMON_HAL_USER(ppdu_info, i, he_RU[7]) = 1116 usr_common->ru_channel_1[3]; 1117 } 1118 } 1119 1120 /** 1121 * hal_txmon_populate_eht_sig_common() - populate eht sig common information 1122 * 1123 * @usr_common: pointer to hal_txmon_usr_desc_common 1124 * @user_id: user index 1125 * @ppdu_info: pointer to hal_tx_ppdu_info 1126 * 1127 * Return: void 1128 */ 1129 static inline void 1130 hal_txmon_populate_eht_sig_common(struct hal_txmon_usr_desc_common *usr_common, 1131 uint32_t user_id, 1132 struct hal_tx_ppdu_info *ppdu_info) 1133 { 1134 uint32_t eht_known = 0; 1135 uint32_t eht_data[9] = {0}; 1136 uint8_t num_ru_allocation_known = 0; 1137 uint8_t i = 0; 1138 1139 eht_known = (QDF_MON_STATUS_EHT_SPATIAL_REUSE_KNOWN | 1140 QDF_MON_STATUS_EHT_EHT_LTF_KNOWN | 1141 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_KNOWN | 1142 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_KNOWN | 1143 QDF_MON_STATUS_EHT_DISREARD_KNOWN); 1144 1145 eht_data[0] |= (usr_common->spatial_reuse << 1146 QDF_MON_STATUS_EHT_SPATIAL_REUSE_SHIFT); 1147 eht_data[0] |= (usr_common->num_ltf_symbols << 1148 QDF_MON_STATUS_EHT_EHT_LTF_SHIFT); 1149 eht_data[0] |= (usr_common->a_factor << 1150 QDF_MON_STATUS_EHT_PRE_FEC_PADDING_FACTOR_SHIFT); 1151 eht_data[0] |= (usr_common->pkt_extn_pe << 1152 QDF_MON_STATUS_EHT_PE_DISAMBIGUITY_SHIFT); 1153 eht_data[0] |= (0xF << QDF_MON_STATUS_EHT_DISREGARD_SHIFT); 1154 1155 switch (TXMON_HAL_STATUS(ppdu_info, bw)) { 1156 case HAL_EHT_BW_320_2: 1157 case HAL_EHT_BW_320_1: 1158 num_ru_allocation_known += 4; 1159 1160 eht_data[3] |= (usr_common->ru_channel_0[7] << 1161 QDF_MON_STATUS_EHT_RU_ALLOCATION2_6_SHIFT); 1162 eht_data[3] |= (usr_common->ru_channel_0[6] << 1163 QDF_MON_STATUS_EHT_RU_ALLOCATION2_5_SHIFT); 1164 eht_data[3] |= (usr_common->ru_channel_0[5] << 1165 QDF_MON_STATUS_EHT_RU_ALLOCATION2_4_SHIFT); 1166 eht_data[2] |= (usr_common->ru_channel_0[4] << 1167 QDF_MON_STATUS_EHT_RU_ALLOCATION2_3_SHIFT); 1168 fallthrough; 1169 case HAL_EHT_BW_160: 1170 num_ru_allocation_known += 2; 1171 1172 eht_data[2] |= (usr_common->ru_channel_0[3] << 1173 QDF_MON_STATUS_EHT_RU_ALLOCATION2_2_SHIFT); 1174 eht_data[2] |= (usr_common->ru_channel_0[2] << 1175 QDF_MON_STATUS_EHT_RU_ALLOCATION2_1_SHIFT); 1176 fallthrough; 1177 case HAL_EHT_BW_80: 1178 num_ru_allocation_known += 1; 1179 1180 eht_data[1] |= (usr_common->ru_channel_0[1] << 1181 QDF_MON_STATUS_EHT_RU_ALLOCATION1_2_SHIFT); 1182 fallthrough; 1183 case HAL_EHT_BW_40: 1184 case HAL_EHT_BW_20: 1185 num_ru_allocation_known += 1; 1186 1187 eht_data[1] |= (usr_common->ru_channel_0[0] << 1188 QDF_MON_STATUS_EHT_RU_ALLOCATION1_1_SHIFT); 1189 break; 1190 default: 1191 break; 1192 } 1193 1194 eht_known |= (num_ru_allocation_known << 1195 QDF_MON_STATUS_EHT_NUM_KNOWN_RU_ALLOCATIONS_SHIFT); 1196 1197 TXMON_HAL_STATUS(ppdu_info, eht_known) |= eht_known; 1198 1199 for (i = 0; i < 4; i++) 1200 TXMON_HAL_STATUS(ppdu_info, eht_data[i]) |= eht_data[i]; 1201 } 1202 1203 /** 1204 * hal_txmon_parse_user_desc_common() - parse mactx user desc common tlv 1205 * 1206 * @tx_tlv: pointer to mactx_user_desc_common tlv 1207 * @user_id: user index 1208 * @ppdu_info: pointer to hal_tx_ppdu_info 1209 * 1210 * Return: void 1211 */ 1212 static inline void 1213 hal_txmon_parse_user_desc_common(void *tx_tlv, uint32_t user_id, 1214 struct hal_tx_ppdu_info *ppdu_info) 1215 { 1216 struct hal_txmon_usr_desc_common usr_common = {0}; 1217 1218 usr_common.num_users = TXMON_HAL(ppdu_info, num_users); 1219 hal_txmon_get_user_desc_common(tx_tlv, &usr_common); 1220 1221 TXMON_HAL_STATUS(ppdu_info, 1222 he_mu_flags) = IS_MULTI_USERS(usr_common.num_users); 1223 1224 switch (TXMON_HAL_STATUS(ppdu_info, preamble_type)) { 1225 case TXMON_PKT_TYPE_11AX: 1226 if (TXMON_HAL_STATUS(ppdu_info, he_flags)) 1227 hal_txmon_populate_he_data_common(&usr_common, 1228 user_id, ppdu_info); 1229 if (TXMON_HAL_STATUS(ppdu_info, he_mu_flags)) 1230 hal_txmon_populate_he_mu_common(&usr_common, 1231 user_id, ppdu_info); 1232 break; 1233 case TXMON_PKT_TYPE_11BE: 1234 hal_txmon_populate_eht_sig_common(&usr_common, 1235 user_id, ppdu_info); 1236 break; 1237 } 1238 } 1239 1240 /** 1241 * hal_txmon_parse_eht_sig_non_mumimo_user_info() - parse eht sig non mumimo tlv 1242 * 1243 * @tx_tlv: pointer to hal_eht_sig_non_mu_mimo_user_info 1244 * @user_id: user index 1245 * @ppdu_info: pointer to hal_tx_ppdu_info 1246 * 1247 * Return: void 1248 */ 1249 static inline void 1250 hal_txmon_parse_eht_sig_non_mumimo_user_info(void *tx_tlv, uint32_t user_id, 1251 struct hal_tx_ppdu_info *ppdu_info) 1252 { 1253 struct hal_eht_sig_non_mu_mimo_user_info *user_info; 1254 uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid); 1255 1256 user_info = (struct hal_eht_sig_non_mu_mimo_user_info *)tx_tlv; 1257 1258 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1259 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1260 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1261 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1262 QDF_MON_STATUS_EHT_USER_NSS_KNOWN | 1263 QDF_MON_STATUS_EHT_USER_BEAMFORMING_KNOWN; 1264 1265 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1266 (user_info->sta_id << 1267 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1268 1269 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1270 (user_info->mcs << 1271 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1272 1273 TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs; 1274 1275 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1276 (user_info->nss << 1277 QDF_MON_STATUS_EHT_USER_NSS_SHIFT); 1278 1279 TXMON_HAL_STATUS(ppdu_info, nss) = user_info->nss + 1; 1280 1281 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1282 (user_info->beamformed << 1283 QDF_MON_STATUS_EHT_USER_BEAMFORMING_SHIFT); 1284 1285 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1286 (user_info->coding << 1287 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1288 1289 /* TODO: CRC */ 1290 1291 TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1; 1292 } 1293 1294 /** 1295 * hal_txmon_parse_eht_sig_mumimo_user_info() - parse eht sig mumimo tlv 1296 * 1297 * @tx_tlv: pointer to hal_eht_sig_mu_mimo_user_info 1298 * @user_id: user index 1299 * @ppdu_info: pointer to hal_tx_ppdu_info 1300 * 1301 * Return: void 1302 */ 1303 static inline void 1304 hal_txmon_parse_eht_sig_mumimo_user_info(void *tx_tlv, uint32_t user_id, 1305 struct hal_tx_ppdu_info *ppdu_info) 1306 { 1307 struct hal_eht_sig_mu_mimo_user_info *user_info; 1308 uint32_t idx = TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid); 1309 1310 user_info = (struct hal_eht_sig_mu_mimo_user_info *)tx_tlv; 1311 1312 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1313 QDF_MON_STATUS_EHT_USER_STA_ID_KNOWN | 1314 QDF_MON_STATUS_EHT_USER_MCS_KNOWN | 1315 QDF_MON_STATUS_EHT_USER_CODING_KNOWN | 1316 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_KNOWN; 1317 1318 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1319 (user_info->sta_id << 1320 QDF_MON_STATUS_EHT_USER_STA_ID_SHIFT); 1321 1322 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1323 (user_info->mcs << 1324 QDF_MON_STATUS_EHT_USER_MCS_SHIFT); 1325 1326 TXMON_HAL_STATUS(ppdu_info, mcs) = user_info->mcs; 1327 1328 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1329 (user_info->coding << 1330 QDF_MON_STATUS_EHT_USER_CODING_SHIFT); 1331 1332 TXMON_HAL_STATUS(ppdu_info, eht_user_info[idx]) |= 1333 (user_info->spatial_coding << 1334 QDF_MON_STATUS_EHT_USER_SPATIAL_CONFIG_SHIFT); 1335 /* TODO: CRC */ 1336 1337 TXMON_HAL_STATUS(ppdu_info, num_eht_user_info_valid) += 1; 1338 } 1339 1340 /** 1341 * hal_txmon_status_get_num_users_generic_be() - api to get num users 1342 * from start of fes window 1343 * 1344 * @tx_tlv_hdr: pointer to TLV header 1345 * @num_users: reference to number of user 1346 * 1347 * Return: status 1348 */ 1349 static inline uint32_t 1350 hal_txmon_status_get_num_users_generic_be(void *tx_tlv_hdr, uint8_t *num_users) 1351 { 1352 uint32_t tlv_tag, user_id, tlv_len; 1353 uint32_t tlv_status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 1354 void *tx_tlv; 1355 1356 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 1357 user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr); 1358 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr); 1359 1360 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 1361 /* window starts with either initiator or response */ 1362 switch (tlv_tag) { 1363 case WIFITX_FES_SETUP_E: 1364 { 1365 *num_users = hal_txmon_get_num_users(tx_tlv); 1366 if (*num_users == 0) 1367 *num_users = 1; 1368 1369 tlv_status = HAL_MON_TX_FES_SETUP; 1370 break; 1371 } 1372 case WIFIRX_RESPONSE_REQUIRED_INFO_E: 1373 { 1374 *num_users = HAL_TX_DESC_GET_64(tx_tlv, 1375 RX_RESPONSE_REQUIRED_INFO, 1376 RESPONSE_STA_COUNT); 1377 if (*num_users == 0) 1378 *num_users = 1; 1379 tlv_status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 1380 break; 1381 } 1382 }; 1383 1384 return tlv_status; 1385 } 1386 1387 #ifdef MONITOR_TLV_RECORDING_ENABLE 1388 static inline void 1389 hal_tx_tlv_record_set_data_ppdu_info(struct hal_tx_ppdu_info *ppdu_info) 1390 { 1391 ppdu_info->tx_tlv_info.is_data_ppdu_info = 1; 1392 } 1393 #else 1394 static inline void 1395 hal_tx_tlv_record_set_data_ppdu_info(struct hal_tx_ppdu_info *ppdu_info) 1396 { 1397 } 1398 #endif 1399 /** 1400 * hal_txmon_get_word_mask_generic_be() - api to get word mask for tx monitor 1401 * @wmask: pointer to hal_txmon_word_mask_config_t 1402 * 1403 * Return: void 1404 */ 1405 static inline 1406 void hal_txmon_get_word_mask_generic_be(void *wmask) 1407 { 1408 hal_txmon_word_mask_config_t *word_mask = NULL; 1409 1410 word_mask = (hal_txmon_word_mask_config_t *)wmask; 1411 qdf_mem_set(word_mask, sizeof(hal_txmon_word_mask_config_t), 0xFF); 1412 word_mask->compaction_enable = 0; 1413 } 1414 1415 /** 1416 * hal_tx_get_ppdu_info() - api to get tx ppdu info 1417 * @data_info: populate dp_ppdu_info data 1418 * @prot_info: populate dp_ppdu_info protection 1419 * @tlv_tag: Tag 1420 * 1421 * Return: dp_tx_ppdu_info pointer 1422 */ 1423 static inline void * 1424 hal_tx_get_ppdu_info(void *data_info, void *prot_info, uint32_t tlv_tag) 1425 { 1426 struct hal_tx_ppdu_info *prot_ppdu_info = prot_info; 1427 1428 switch (tlv_tag) { 1429 case WIFITX_FES_SETUP_E:/* DOWNSTREAM */ 1430 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 1431 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM */ 1432 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM */ 1433 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM */ 1434 case WIFITX_MPDU_START_E:/* DOWNSTREAM */ 1435 case WIFITX_MSDU_START_E:/* DOWNSTREAM */ 1436 case WIFITX_DATA_E:/* DOWNSTREAM */ 1437 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 1438 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 1439 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 1440 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 1441 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 1442 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 1443 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 1444 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 1445 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 1446 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 1447 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 1448 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 1449 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 1450 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 1451 case WIFITX_FES_STATUS_START_PPDU_E:/* UPSTREAM */ 1452 { 1453 hal_tx_tlv_record_set_data_ppdu_info(data_info); 1454 return data_info; 1455 } 1456 } 1457 1458 /* 1459 * check current prot_tlv_status is start protection 1460 * check current tlv_tag is either start protection or end protection 1461 */ 1462 if (TXMON_HAL(prot_ppdu_info, 1463 prot_tlv_status) == WIFITX_FES_STATUS_START_PROT_E) { 1464 return prot_info; 1465 } else if (tlv_tag == WIFITX_FES_STATUS_PROT_E || 1466 tlv_tag == WIFITX_FES_STATUS_START_PROT_E) { 1467 TXMON_HAL(prot_ppdu_info, prot_tlv_status) = tlv_tag; 1468 return prot_info; 1469 } 1470 1471 hal_tx_tlv_record_set_data_ppdu_info(data_info); 1472 return data_info; 1473 } 1474 1475 #ifdef MONITOR_TLV_RECORDING_ENABLE 1476 static inline void 1477 hal_tx_record_tlv_info(struct hal_tx_ppdu_info *ppdu_info, 1478 uint32_t tlv_tag) 1479 { 1480 ppdu_info->tx_tlv_info.tlv_tag = tlv_tag; 1481 switch (tlv_tag) { 1482 case WIFITX_FES_SETUP_E: 1483 case WIFITXPCU_BUFFER_STATUS_E: 1484 case WIFIPCU_PPDU_SETUP_INIT_E: 1485 case WIFISCH_CRITICAL_TLV_REFERENCE_E: 1486 case WIFITX_PEER_ENTRY_E: 1487 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E: 1488 case WIFITX_QUEUE_EXTENSION_E: 1489 case WIFITX_FES_SETUP_COMPLETE_E: 1490 case WIFIFW2SW_MON_E: 1491 case WIFISCHEDULER_END_E: 1492 case WIFITQM_MPDU_GLOBAL_START_E: 1493 ppdu_info->tx_tlv_info.tlv_category = CATEGORY_PPDU_START; 1494 break; 1495 1496 case WIFITX_MPDU_START_E: 1497 case WIFITX_MSDU_START_E: 1498 case WIFITX_DATA_E: 1499 case WIFITX_MSDU_END_E: 1500 case WIFITX_MPDU_END_E: 1501 ppdu_info->tx_tlv_info.tlv_category = CATEGORY_MPDU; 1502 break; 1503 1504 case WIFITX_LAST_MPDU_FETCHED_E: 1505 case WIFITX_LAST_MPDU_END_E: 1506 case WIFIPDG_TX_REQ_E: 1507 case WIFITX_FES_STATUS_START_PPDU_E: 1508 case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E: 1509 case WIFIMACTX_L_SIG_A_E: 1510 case WIFITXPCU_PREAMBLE_DONE_E: 1511 case WIFIMACTX_USER_DESC_COMMON_E: 1512 case WIFIMACTX_SERVICE_E: 1513 case WIFITXDMA_STOP_REQUEST_E: 1514 case WIFITXPCU_USER_BUFFER_STATUS_E: 1515 case WIFITX_FES_STATUS_USER_PPDU_E: 1516 case WIFITX_MPDU_COUNT_TRANSFER_END_E: 1517 case WIFIRX_START_PARAM_E: 1518 case WIFITX_FES_STATUS_ACK_OR_BA_E: 1519 case WIFITX_FES_STATUS_USER_RESPONSE_E: 1520 case WIFITX_FES_STATUS_END_E: 1521 case WIFITX_FES_STATUS_PROT_E: 1522 case WIFIMACTX_PHY_DESC_E: 1523 case WIFIMACTX_HE_SIG_A_SU_E: 1524 ppdu_info->tx_tlv_info.tlv_category = CATEGORY_PPDU_END; 1525 break; 1526 } 1527 } 1528 #else 1529 static inline void 1530 hal_tx_record_tlv_info(struct hal_tx_ppdu_info *ppdu_info, 1531 uint32_t tlv_tag) 1532 { 1533 } 1534 #endif 1535 1536 /** 1537 * hal_txmon_status_parse_tlv_generic_be() - api to parse status tlv. 1538 * @data_ppdu_info: hal_txmon data ppdu info 1539 * @prot_ppdu_info: hal_txmon prot ppdu info 1540 * @data_status_info: pointer to data status info 1541 * @prot_status_info: pointer to prot status info 1542 * @tx_tlv_hdr: fragment of tx_tlv_hdr 1543 * @status_frag: qdf_frag_t buffer 1544 * 1545 * Return: status 1546 */ 1547 static inline uint32_t 1548 hal_txmon_status_parse_tlv_generic_be(void *data_ppdu_info, 1549 void *prot_ppdu_info, 1550 void *data_status_info, 1551 void *prot_status_info, 1552 void *tx_tlv_hdr, 1553 qdf_frag_t status_frag) 1554 { 1555 struct hal_tx_ppdu_info *ppdu_info; 1556 struct hal_tx_status_info *tx_status_info; 1557 struct hal_mon_packet_info *packet_info = NULL; 1558 uint32_t tlv_tag, user_id, tlv_len, tlv_user_id; 1559 uint32_t status = HAL_MON_TX_STATUS_PPDU_NOT_DONE; 1560 void *tx_tlv; 1561 1562 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(tx_tlv_hdr); 1563 tlv_user_id = HAL_RX_GET_USER_TLV32_USERID(tx_tlv_hdr); 1564 tlv_len = HAL_RX_GET_USER_TLV32_LEN(tx_tlv_hdr); 1565 1566 tx_tlv = (uint8_t *)tx_tlv_hdr + HAL_RX_TLV64_HDR_SIZE; 1567 1568 /* parse tlv and populate tx_ppdu_info */ 1569 ppdu_info = hal_tx_get_ppdu_info(data_ppdu_info, 1570 prot_ppdu_info, tlv_tag); 1571 tx_status_info = (ppdu_info->is_data ? data_status_info : 1572 prot_status_info); 1573 1574 user_id = (tlv_user_id > ppdu_info->num_users ? 0 : tlv_user_id); 1575 hal_tx_record_tlv_info(ppdu_info, tlv_tag); 1576 1577 switch (tlv_tag) { 1578 /* start of initiator FES window */ 1579 case WIFITX_FES_SETUP_E:/* DOWNSTREAM - COMPACTION */ 1580 { 1581 /* initiator PPDU window start */ 1582 hal_txmon_parse_tx_fes_setup(tx_tlv, ppdu_info); 1583 1584 status = HAL_MON_TX_FES_SETUP; 1585 SHOW_DEFINED(WIFITX_FES_SETUP_E); 1586 break; 1587 } 1588 /* end of initiator FES window */ 1589 case WIFITX_FES_STATUS_END_E:/* UPSTREAM - COMPACTION */ 1590 { 1591 hal_txmon_parse_tx_fes_status_end(tx_tlv, ppdu_info, 1592 tx_status_info); 1593 1594 status = HAL_MON_TX_FES_STATUS_END; 1595 SHOW_DEFINED(WIFITX_FES_STATUS_END_E); 1596 break; 1597 } 1598 /* response window open */ 1599 case WIFIRX_RESPONSE_REQUIRED_INFO_E:/* UPSTREAM */ 1600 { 1601 /* response PPDU window start */ 1602 uint32_t ppdu_id = 0; 1603 uint8_t reception_type = 0; 1604 uint8_t response_sta_count = 0; 1605 1606 status = HAL_MON_RX_RESPONSE_REQUIRED_INFO; 1607 1608 ppdu_id = HAL_TX_DESC_GET_64(tx_tlv, 1609 RX_RESPONSE_REQUIRED_INFO, 1610 PHY_PPDU_ID); 1611 reception_type = 1612 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 1613 SU_OR_UPLINK_MU_RECEPTION); 1614 response_sta_count = 1615 HAL_TX_DESC_GET_64(tx_tlv, RX_RESPONSE_REQUIRED_INFO, 1616 RESPONSE_STA_COUNT); 1617 1618 /* get mac address */ 1619 *(uint32_t *)&tx_status_info->addr1[0] = 1620 HAL_TX_DESC_GET_64(tx_tlv, 1621 RX_RESPONSE_REQUIRED_INFO, 1622 ADDR1_31_0); 1623 *(uint32_t *)&tx_status_info->addr1[4] = 1624 HAL_TX_DESC_GET_64(tx_tlv, 1625 RX_RESPONSE_REQUIRED_INFO, 1626 ADDR1_47_32); 1627 *(uint32_t *)&tx_status_info->addr2[0] = 1628 HAL_TX_DESC_GET_64(tx_tlv, 1629 RX_RESPONSE_REQUIRED_INFO, 1630 ADDR2_15_0); 1631 *(uint32_t *)&tx_status_info->addr2[2] = 1632 HAL_TX_DESC_GET_64(tx_tlv, 1633 RX_RESPONSE_REQUIRED_INFO, 1634 ADDR2_47_16); 1635 1636 TXMON_HAL(ppdu_info, ppdu_id) = ppdu_id; 1637 TXMON_HAL_STATUS(ppdu_info, ppdu_id) = ppdu_id; 1638 1639 if (response_sta_count == 0) 1640 response_sta_count = 1; 1641 TXMON_HAL(ppdu_info, num_users) = response_sta_count; 1642 1643 if (reception_type) 1644 TXMON_STATUS_INFO(tx_status_info, 1645 transmission_type) = 1646 TXMON_SU_TRANSMISSION; 1647 else 1648 TXMON_STATUS_INFO(tx_status_info, 1649 transmission_type) = 1650 TXMON_MU_TRANSMISSION; 1651 1652 SHOW_DEFINED(WIFIRX_RESPONSE_REQUIRED_INFO_E); 1653 break; 1654 } 1655 /* Response window close */ 1656 case WIFIRESPONSE_END_STATUS_E:/* UPSTREAM - COMPACTION */ 1657 { 1658 /* response PPDU window end */ 1659 hal_txmon_parse_response_end_status(tx_tlv, ppdu_info, 1660 tx_status_info); 1661 1662 status = HAL_MON_RESPONSE_END_STATUS_INFO; 1663 SHOW_DEFINED(WIFIRESPONSE_END_STATUS_E); 1664 break; 1665 } 1666 case WIFITX_FLUSH_E:/* DOWNSTREAM */ 1667 { 1668 SHOW_DEFINED(WIFITX_FLUSH_E); 1669 break; 1670 } 1671 /* Downstream tlv */ 1672 case WIFIPCU_PPDU_SETUP_INIT_E:/* DOWNSTREAM - COMPACTION */ 1673 { 1674 hal_txmon_parse_pcu_ppdu_setup_init(tx_tlv, data_status_info, 1675 prot_status_info); 1676 status = HAL_MON_TX_PCU_PPDU_SETUP_INIT; 1677 SHOW_DEFINED(WIFIPCU_PPDU_SETUP_INIT_E); 1678 break; 1679 } 1680 case WIFITX_PEER_ENTRY_E:/* DOWNSTREAM - COMPACTION */ 1681 { 1682 hal_txmon_parse_peer_entry(tx_tlv, user_id, 1683 ppdu_info, tx_status_info); 1684 SHOW_DEFINED(WIFITX_PEER_ENTRY_E); 1685 break; 1686 } 1687 case WIFITX_QUEUE_EXTENSION_E:/* DOWNSTREAM - COMPACTION */ 1688 { 1689 status = HAL_MON_TX_QUEUE_EXTENSION; 1690 hal_txmon_parse_queue_exten(tx_tlv, ppdu_info); 1691 1692 SHOW_DEFINED(WIFITX_QUEUE_EXTENSION_E); 1693 break; 1694 } 1695 /* payload and data frame handling */ 1696 case WIFITX_MPDU_START_E:/* DOWNSTREAM - COMPACTION */ 1697 { 1698 hal_txmon_parse_mpdu_start(tx_tlv, user_id, ppdu_info); 1699 1700 status = HAL_MON_TX_MPDU_START; 1701 SHOW_DEFINED(WIFITX_MPDU_START_E); 1702 break; 1703 } 1704 case WIFITX_MSDU_START_E:/* DOWNSTREAM - COMPACTION */ 1705 { 1706 hal_txmon_parse_msdu_start(tx_tlv, user_id, ppdu_info); 1707 /* we expect frame to be 802.11 frame type */ 1708 status = HAL_MON_TX_MSDU_START; 1709 SHOW_DEFINED(WIFITX_MSDU_START_E); 1710 break; 1711 } 1712 case WIFITX_DATA_E:/* DOWNSTREAM */ 1713 { 1714 status = HAL_MON_TX_DATA; 1715 /* 1716 * TODO: do we need a conversion api to convert 1717 * user_id from hw to get host user_index 1718 */ 1719 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1720 TXMON_STATUS_INFO(tx_status_info, 1721 buffer) = (void *)status_frag; 1722 TXMON_STATUS_INFO(tx_status_info, 1723 offset) = ((void *)tx_tlv - 1724 (void *)status_frag); 1725 TXMON_STATUS_INFO(tx_status_info, 1726 length) = tlv_len; 1727 1728 /* 1729 * reference of the status buffer will be held in 1730 * dp_tx_update_ppdu_info_status() 1731 */ 1732 SHOW_DEFINED(WIFITX_DATA_E); 1733 break; 1734 } 1735 case WIFIMON_BUFFER_ADDR_E:/* DOWNSTREAM */ 1736 { 1737 packet_info = &ppdu_info->packet_info; 1738 status = HAL_MON_TX_BUFFER_ADDR; 1739 /* 1740 * TODO: do we need a conversion api to convert 1741 * user_id from hw to get host user_index 1742 */ 1743 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1744 1745 hal_txmon_populate_packet_info_generic_be(tx_tlv, packet_info); 1746 1747 SHOW_DEFINED(WIFIMON_BUFFER_ADDR_E); 1748 break; 1749 } 1750 case WIFITX_MPDU_END_E:/* DOWNSTREAM */ 1751 { 1752 /* no tlv content */ 1753 SHOW_DEFINED(WIFITX_MPDU_END_E); 1754 break; 1755 } 1756 case WIFITX_MSDU_END_E:/* DOWNSTREAM */ 1757 { 1758 /* no tlv content */ 1759 SHOW_DEFINED(WIFITX_MSDU_END_E); 1760 break; 1761 } 1762 case WIFITX_LAST_MPDU_FETCHED_E:/* DOWNSTREAM */ 1763 { 1764 /* no tlv content */ 1765 SHOW_DEFINED(WIFITX_LAST_MPDU_FETCHED_E); 1766 break; 1767 } 1768 case WIFITX_LAST_MPDU_END_E:/* DOWNSTREAM */ 1769 { 1770 /* no tlv content */ 1771 SHOW_DEFINED(WIFITX_LAST_MPDU_END_E); 1772 break; 1773 } 1774 case WIFICOEX_TX_REQ_E:/* DOWNSTREAM */ 1775 { 1776 /* 1777 * transmitting power 1778 * minimum transmitting power 1779 * desired nss 1780 * tx chain mask 1781 * desired bw 1782 * duration of transmit and response 1783 * 1784 * since most of the field we are deriving from other tlv 1785 * we don't need to enable this in our tlv. 1786 */ 1787 SHOW_DEFINED(WIFICOEX_TX_REQ_E); 1788 break; 1789 } 1790 case WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E:/* DOWNSTREAM */ 1791 { 1792 /* user tlv */ 1793 /* 1794 * All Tx monitor will have 802.11 hdr 1795 * we don't need to enable this TLV 1796 */ 1797 SHOW_DEFINED(WIFITX_RAW_OR_NATIVE_FRAME_SETUP_E); 1798 break; 1799 } 1800 case WIFINDP_PREAMBLE_DONE_E:/* DOWNSTREAM */ 1801 { 1802 /* 1803 * no tlv content 1804 * 1805 * TLV that indicates to TXPCU that preamble phase for the NDP 1806 * frame transmission is now over 1807 */ 1808 SHOW_DEFINED(WIFINDP_PREAMBLE_DONE_E); 1809 break; 1810 } 1811 case WIFISCH_CRITICAL_TLV_REFERENCE_E:/* DOWNSTREAM */ 1812 { 1813 /* 1814 * no tlv content 1815 * 1816 * TLV indicates to the SCH that all timing critical TLV 1817 * has been passed on to the transmit path 1818 */ 1819 SHOW_DEFINED(WIFISCH_CRITICAL_TLV_REFERENCE_E); 1820 break; 1821 } 1822 case WIFITX_LOOPBACK_SETUP_E:/* DOWNSTREAM */ 1823 { 1824 /* 1825 * Loopback specific setup info - not needed for Tx monitor 1826 */ 1827 SHOW_DEFINED(WIFITX_LOOPBACK_SETUP_E); 1828 break; 1829 } 1830 case WIFITX_FES_SETUP_COMPLETE_E:/* DOWNSTREAM */ 1831 { 1832 /* 1833 * no tlv content 1834 * 1835 * TLV indicates that other modules besides the scheduler can 1836 * now also start generating TLV's 1837 * prevent colliding or generating TLV's out of order 1838 */ 1839 SHOW_DEFINED(WIFITX_FES_SETUP_COMPLETE_E); 1840 break; 1841 } 1842 case WIFITQM_MPDU_GLOBAL_START_E:/* DOWNSTREAM */ 1843 { 1844 /* 1845 * no tlv content 1846 * 1847 * TLV indicates to SCH that a burst of MPDU info will 1848 * start to come in over the TLV 1849 */ 1850 SHOW_DEFINED(WIFITQM_MPDU_GLOBAL_START_E); 1851 break; 1852 } 1853 case WIFITX_WUR_DATA_E:/* DOWNSTREAM */ 1854 { 1855 SHOW_DEFINED(WIFITX_WUR_DATA_E); 1856 break; 1857 } 1858 case WIFISCHEDULER_END_E:/* DOWNSTREAM */ 1859 { 1860 /* 1861 * no tlv content 1862 * 1863 * TLV indicates END of all TLV's within the scheduler TLV 1864 */ 1865 SHOW_DEFINED(WIFISCHEDULER_END_E); 1866 break; 1867 } 1868 1869 /* Upstream tlv */ 1870 case WIFIPDG_TX_REQ_E: 1871 { 1872 SHOW_DEFINED(WIFIPDG_TX_REQ_E); 1873 break; 1874 } 1875 case WIFITX_FES_STATUS_START_E: 1876 { 1877 /* 1878 * TLV indicating that first transmission on the medium 1879 */ 1880 uint8_t medium_prot_type = 0; 1881 1882 status = HAL_MON_TX_FES_STATUS_START; 1883 1884 medium_prot_type = HAL_TX_DESC_GET_64(tx_tlv, 1885 TX_FES_STATUS_START, 1886 MEDIUM_PROT_TYPE); 1887 1888 ppdu_info = (struct hal_tx_ppdu_info *)prot_ppdu_info; 1889 /* update what type of medium protection frame */ 1890 TXMON_STATUS_INFO(tx_status_info, 1891 medium_prot_type) = medium_prot_type; 1892 SHOW_DEFINED(WIFITX_FES_STATUS_START_E); 1893 break; 1894 } 1895 case WIFITX_FES_STATUS_PROT_E:/* UPSTREAM - COMPACTION */ 1896 { 1897 hal_txmon_parse_tx_fes_status_prot(tx_tlv, ppdu_info, 1898 tx_status_info); 1899 1900 status = HAL_MON_TX_FES_STATUS_PROT; 1901 TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag; 1902 1903 SHOW_DEFINED(WIFITX_FES_STATUS_PROT_E); 1904 break; 1905 } 1906 case WIFITX_FES_STATUS_START_PROT_E: 1907 { 1908 uint64_t tsft_64; 1909 uint32_t response_type; 1910 status = HAL_MON_TX_FES_STATUS_START_PROT; 1911 TXMON_HAL(ppdu_info, prot_tlv_status) = tlv_tag; 1912 /* timestamp */ 1913 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1914 TX_FES_STATUS_START_PROT, 1915 PROT_TIMESTAMP_LOWER_32); 1916 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1917 TX_FES_STATUS_START_PROT, 1918 PROT_TIMESTAMP_UPPER_32) << 32); 1919 1920 response_type = HAL_TX_DESC_GET_64(tx_tlv, 1921 TX_FES_STATUS_START_PROT, 1922 RESPONSE_TYPE); 1923 1924 TXMON_STATUS_INFO(tx_status_info, 1925 response_type) = response_type; 1926 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1927 1928 SHOW_DEFINED(WIFITX_FES_STATUS_START_PROT_E); 1929 break; 1930 } 1931 case WIFIPROT_TX_END_E: 1932 { 1933 /* 1934 * no tlv content 1935 * 1936 * generated by TXPCU the moment that protection frame 1937 * transmission has finished on the medium 1938 */ 1939 SHOW_DEFINED(WIFIPROT_TX_END_E); 1940 break; 1941 } 1942 case WIFITX_FES_STATUS_START_PPDU_E: 1943 { 1944 uint64_t tsft_64; 1945 uint8_t ndp_frame; 1946 1947 status = HAL_MON_TX_FES_STATUS_START_PPDU; 1948 tsft_64 = HAL_TX_DESC_GET_64(tx_tlv, 1949 TX_FES_STATUS_START_PPDU, 1950 PPDU_TIMESTAMP_LOWER_32); 1951 tsft_64 |= (HAL_TX_DESC_GET_64(tx_tlv, 1952 TX_FES_STATUS_START_PPDU, 1953 PPDU_TIMESTAMP_UPPER_32) << 32); 1954 1955 ndp_frame = HAL_TX_DESC_GET_64(tx_tlv, 1956 TX_FES_STATUS_START_PPDU, 1957 NDP_FRAME); 1958 1959 TXMON_STATUS_INFO(tx_status_info, ndp_frame) = ndp_frame; 1960 TXMON_HAL_STATUS(ppdu_info, tsft) = tsft_64; 1961 1962 SHOW_DEFINED(WIFITX_FES_STATUS_START_PPDU_E); 1963 break; 1964 } 1965 case WIFITX_FES_STATUS_USER_PPDU_E: 1966 { 1967 /* user tlv */ 1968 uint16_t duration; 1969 uint8_t transmitted_tid; 1970 1971 duration = HAL_TX_DESC_GET_64(tx_tlv, 1972 TX_FES_STATUS_USER_PPDU, 1973 DURATION); 1974 transmitted_tid = HAL_TX_DESC_GET_64(tx_tlv, 1975 TX_FES_STATUS_USER_PPDU, 1976 TRANSMITTED_TID); 1977 1978 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 1979 TXMON_HAL_USER(ppdu_info, user_id, tid) = transmitted_tid; 1980 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 1981 1982 status = HAL_MON_TX_FES_STATUS_USER_PPDU; 1983 SHOW_DEFINED(WIFITX_FES_STATUS_USER_PPDU_E); 1984 break; 1985 } 1986 case WIFIPPDU_TX_END_E: 1987 { 1988 /* 1989 * no tlv content 1990 * 1991 * generated by TXPCU the moment that PPDU transmission has 1992 * finished on the medium 1993 */ 1994 SHOW_DEFINED(WIFIPPDU_TX_END_E); 1995 break; 1996 } 1997 1998 case WIFITX_FES_STATUS_USER_RESPONSE_E: 1999 { 2000 /* 2001 * TLV contains the FES transmit result of the each 2002 * of the MAC users. TLV are forwarded to HWSCH 2003 */ 2004 SHOW_DEFINED(WIFITX_FES_STATUS_USER_RESPONSE_E); 2005 break; 2006 } 2007 case WIFITX_FES_STATUS_ACK_OR_BA_E: 2008 { 2009 /* user tlv */ 2010 /* 2011 * TLV generated by RXPCU and provide information related to 2012 * the received BA or ACK frame 2013 */ 2014 SHOW_DEFINED(WIFITX_FES_STATUS_ACK_OR_BA_E); 2015 break; 2016 } 2017 case WIFITX_FES_STATUS_1K_BA_E: 2018 { 2019 /* user tlv */ 2020 /* 2021 * TLV generated by RXPCU and providing information related 2022 * to the received BA frame in case of 512/1024 bitmaps 2023 */ 2024 SHOW_DEFINED(WIFITX_FES_STATUS_1K_BA_E); 2025 break; 2026 } 2027 case WIFIRECEIVED_RESPONSE_USER_7_0_E: 2028 { 2029 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_7_0_E); 2030 break; 2031 } 2032 case WIFIRECEIVED_RESPONSE_USER_15_8_E: 2033 { 2034 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_15_8_E); 2035 break; 2036 } 2037 case WIFIRECEIVED_RESPONSE_USER_23_16_E: 2038 { 2039 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_23_16_E); 2040 break; 2041 } 2042 case WIFIRECEIVED_RESPONSE_USER_31_24_E: 2043 { 2044 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_31_24_E); 2045 break; 2046 } 2047 case WIFIRECEIVED_RESPONSE_USER_36_32_E: 2048 { 2049 /* 2050 * RXPCU generates this TLV when it receives a response frame 2051 * that TXPCU pre-announced it was waiting for and in 2052 * RXPCU_SETUP TLV, TLV generated before the 2053 * RECEIVED_RESPONSE_INFO TLV. 2054 * 2055 * received info user fields are there which is not needed 2056 * for TX monitor 2057 */ 2058 SHOW_DEFINED(WIFIRECEIVED_RESPONSE_USER_36_32_E); 2059 break; 2060 } 2061 2062 case WIFITXPCU_BUFFER_STATUS_E: 2063 { 2064 SHOW_DEFINED(WIFITXPCU_BUFFER_STATUS_E); 2065 break; 2066 } 2067 case WIFITXPCU_USER_BUFFER_STATUS_E: 2068 { 2069 /* 2070 * WIFITXPCU_USER_BUFFER_STATUS_E - user tlv 2071 * for TX monitor we aren't interested in this tlv 2072 */ 2073 SHOW_DEFINED(WIFITXPCU_USER_BUFFER_STATUS_E); 2074 break; 2075 } 2076 case WIFITXDMA_STOP_REQUEST_E: 2077 { 2078 /* 2079 * no tlv content 2080 * 2081 * TLV is destined to TXDMA and informs TXDMA to stop 2082 * pushing data into the transmit path. 2083 */ 2084 SHOW_DEFINED(WIFITXDMA_STOP_REQUEST_E); 2085 break; 2086 } 2087 case WIFITX_CBF_INFO_E: 2088 { 2089 /* 2090 * After NDPA + NDP is received, RXPCU sends the TX_CBF_INFO to 2091 * TXPCU to respond the CBF frame 2092 * 2093 * compressed beamforming pkt doesn't has mac header 2094 * Tx monitor not interested in this pkt. 2095 */ 2096 SHOW_DEFINED(WIFITX_CBF_INFO_E); 2097 break; 2098 } 2099 case WIFITX_MPDU_COUNT_TRANSFER_END_E: 2100 { 2101 /* 2102 * no tlv content 2103 * 2104 * TLV indicates that TXPCU has finished generating the 2105 * TQM_UPDATE_TX_MPDU_COUNT TLV for all users 2106 */ 2107 SHOW_DEFINED(WIFITX_MPDU_COUNT_TRANSFER_END_E); 2108 break; 2109 } 2110 case WIFIPDG_RESPONSE_E: 2111 { 2112 /* 2113 * most of the feilds are already covered in 2114 * other TLV 2115 * This is generated by TX_PCU to PDG to calculate 2116 * all the PHY header info. 2117 * 2118 * some useful fields like min transmit power, 2119 * rate used for transmitting packet is present. 2120 */ 2121 SHOW_DEFINED(WIFIPDG_RESPONSE_E); 2122 break; 2123 } 2124 case WIFIPDG_TRIG_RESPONSE_E: 2125 { 2126 /* no tlv content */ 2127 SHOW_DEFINED(WIFIPDG_TRIG_RESPONSE_E); 2128 break; 2129 } 2130 case WIFIRECEIVED_TRIGGER_INFO_E: 2131 { 2132 /* 2133 * TLV generated by RXPCU to inform the scheduler that 2134 * a trigger frame has been received 2135 */ 2136 SHOW_DEFINED(WIFIRECEIVED_TRIGGER_INFO_E); 2137 break; 2138 } 2139 case WIFIOFDMA_TRIGGER_DETAILS_E: 2140 { 2141 SHOW_DEFINED(WIFIOFDMA_TRIGGER_DETAILS_E); 2142 break; 2143 } 2144 case WIFIRX_FRAME_BITMAP_ACK_E: 2145 { 2146 /* user tlv */ 2147 status = HAL_MON_RX_FRAME_BITMAP_ACK; 2148 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_ACK_E); 2149 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2150 TXMON_STATUS_INFO(tx_status_info, no_bitmap_avail) = 2151 HAL_TX_DESC_GET_64(tx_tlv, 2152 RX_FRAME_BITMAP_ACK, 2153 NO_BITMAP_AVAILABLE); 2154 2155 TXMON_STATUS_INFO(tx_status_info, explicit_ack) = 2156 HAL_TX_DESC_GET_64(tx_tlv, 2157 RX_FRAME_BITMAP_ACK, 2158 EXPLICIT_ACK); 2159 /* 2160 * get mac address, since address is received frame 2161 * change the order and store it 2162 */ 2163 *(uint32_t *)&tx_status_info->addr2[0] = 2164 HAL_TX_DESC_GET_64(tx_tlv, 2165 RX_FRAME_BITMAP_ACK, 2166 ADDR1_31_0); 2167 *(uint16_t *)&tx_status_info->addr2[4] = 2168 HAL_TX_DESC_GET_64(tx_tlv, 2169 RX_FRAME_BITMAP_ACK, 2170 ADDR1_47_32); 2171 *(uint32_t *)&tx_status_info->addr1[0] = 2172 HAL_TX_DESC_GET_64(tx_tlv, 2173 RX_FRAME_BITMAP_ACK, 2174 ADDR2_15_0); 2175 *(uint32_t *)&tx_status_info->addr1[2] = 2176 HAL_TX_DESC_GET_64(tx_tlv, 2177 RX_FRAME_BITMAP_ACK, 2178 ADDR2_47_16); 2179 2180 TXMON_STATUS_INFO(tx_status_info, explicit_ack_type) = 2181 HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_BITMAP_ACK, 2182 EXPLICT_ACK_TYPE); 2183 2184 TXMON_HAL_USER(ppdu_info, user_id, tid) = 2185 HAL_TX_DESC_GET_64(tx_tlv, 2186 RX_FRAME_BITMAP_ACK, 2187 BA_TID); 2188 TXMON_HAL_USER(ppdu_info, user_id, aid) = 2189 HAL_TX_DESC_GET_64(tx_tlv, 2190 RX_FRAME_BITMAP_ACK, 2191 STA_FULL_AID); 2192 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 2193 HAL_TX_DESC_GET_64(tx_tlv, 2194 RX_FRAME_BITMAP_ACK, 2195 BA_TS_SEQ); 2196 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 2197 HAL_TX_DESC_GET_64(tx_tlv, 2198 RX_FRAME_BITMAP_ACK, 2199 BA_TS_CTRL); 2200 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 2201 HAL_TX_DESC_GET_64(tx_tlv, 2202 RX_FRAME_BITMAP_ACK, 2203 BA_BITMAP_SIZE); 2204 2205 /* ba bitmap */ 2206 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 2207 &HAL_SET_FLD_OFFSET_64(tx_tlv, 2208 RX_FRAME_BITMAP_ACK, 2209 BA_TS_BITMAP_31_0, 0), 32); 2210 2211 break; 2212 } 2213 case WIFIRX_FRAME_1K_BITMAP_ACK_E: 2214 { 2215 /* user tlv */ 2216 status = HAL_MON_RX_FRAME_BITMAP_BLOCK_ACK_1K; 2217 SHOW_DEFINED(WIFIRX_FRAME_1K_BITMAP_ACK_E); 2218 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2219 TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap_sz) = 2220 (4 + HAL_TX_DESC_GET_64(tx_tlv, RX_FRAME_1K_BITMAP_ACK, 2221 BA_BITMAP_SIZE)); 2222 TXMON_HAL_USER(ppdu_info, user_id, tid) = 2223 HAL_TX_DESC_GET_64(tx_tlv, 2224 RX_FRAME_1K_BITMAP_ACK, 2225 BA_TID); 2226 TXMON_HAL_USER(ppdu_info, user_id, aid) = 2227 HAL_TX_DESC_GET_64(tx_tlv, 2228 RX_FRAME_1K_BITMAP_ACK, 2229 STA_FULL_AID); 2230 /* get mac address */ 2231 *(uint32_t *)&tx_status_info->addr1[0] = 2232 HAL_TX_DESC_GET_64(tx_tlv, 2233 RX_FRAME_1K_BITMAP_ACK, 2234 ADDR1_31_0); 2235 *(uint16_t *)&tx_status_info->addr1[4] = 2236 HAL_TX_DESC_GET_64(tx_tlv, 2237 RX_FRAME_1K_BITMAP_ACK, 2238 ADDR1_47_32); 2239 *(uint32_t *)&tx_status_info->addr2[0] = 2240 HAL_TX_DESC_GET_64(tx_tlv, 2241 RX_FRAME_1K_BITMAP_ACK, 2242 ADDR2_15_0); 2243 *(uint32_t *)&tx_status_info->addr2[2] = 2244 HAL_TX_DESC_GET_64(tx_tlv, 2245 RX_FRAME_1K_BITMAP_ACK, 2246 ADDR2_47_16); 2247 2248 TXMON_HAL_USER(ppdu_info, user_id, start_seq) = 2249 HAL_TX_DESC_GET_64(tx_tlv, 2250 RX_FRAME_1K_BITMAP_ACK, 2251 BA_TS_SEQ); 2252 TXMON_HAL_USER(ppdu_info, user_id, ba_control) = 2253 HAL_TX_DESC_GET_64(tx_tlv, 2254 RX_FRAME_1K_BITMAP_ACK, 2255 BA_TS_CTRL); 2256 /* memcpy ba bitmap */ 2257 qdf_mem_copy(TXMON_HAL_USER(ppdu_info, user_id, ba_bitmap), 2258 &HAL_SET_FLD_OFFSET_64(tx_tlv, 2259 RX_FRAME_1K_BITMAP_ACK, 2260 BA_TS_BITMAP_31_0, 0), 2261 4 << TXMON_HAL_USER(ppdu_info, 2262 user_id, ba_bitmap_sz)); 2263 2264 break; 2265 } 2266 case WIFIRESPONSE_START_STATUS_E: 2267 { 2268 /* 2269 * TLV indicates which HW response the TXPCU 2270 * started generating 2271 * 2272 * HW generated frames like 2273 * ACK frame - handled 2274 * CTS frame - handled 2275 * BA frame - handled 2276 * MBA frame - handled 2277 * CBF frame - no frame header 2278 * Trigger response - TODO 2279 * NDP LMR - no frame header 2280 */ 2281 SHOW_DEFINED(WIFIRESPONSE_START_STATUS_E); 2282 break; 2283 } 2284 case WIFIRX_START_PARAM_E: 2285 { 2286 /* 2287 * RXPCU send this TLV after PHY RX detected a frame 2288 * in the medium 2289 * 2290 * TX monitor not interested in this TLV 2291 */ 2292 SHOW_DEFINED(WIFIRX_START_PARAM_E); 2293 break; 2294 } 2295 case WIFIRXPCU_EARLY_RX_INDICATION_E: 2296 { 2297 /* 2298 * early indication of pkt type and mcs rate 2299 * already captured in other tlv 2300 */ 2301 SHOW_DEFINED(WIFIRXPCU_EARLY_RX_INDICATION_E); 2302 break; 2303 } 2304 case WIFIRX_PM_INFO_E: 2305 { 2306 SHOW_DEFINED(WIFIRX_PM_INFO_E); 2307 break; 2308 } 2309 2310 /* Active window */ 2311 case WIFITX_FLUSH_REQ_E: 2312 { 2313 SHOW_DEFINED(WIFITX_FLUSH_REQ_E); 2314 break; 2315 } 2316 case WIFICOEX_TX_STATUS_E: 2317 { 2318 /* duration are retrieved from coex tx status */ 2319 uint16_t duration; 2320 uint8_t status_reason; 2321 2322 status = HAL_MON_COEX_TX_STATUS; 2323 duration = HAL_TX_DESC_GET_64(tx_tlv, 2324 COEX_TX_STATUS, 2325 CURRENT_TX_DURATION); 2326 status_reason = HAL_TX_DESC_GET_64(tx_tlv, 2327 COEX_TX_STATUS, 2328 TX_STATUS_REASON); 2329 2330 /* update duration */ 2331 if (status_reason == COEX_FES_TX_START || 2332 status_reason == COEX_RESPONSE_TX_START) 2333 TXMON_HAL_USER(ppdu_info, user_id, duration) = duration; 2334 2335 SHOW_DEFINED(WIFICOEX_TX_STATUS_E); 2336 break; 2337 } 2338 case WIFIR2R_STATUS_END_E: 2339 { 2340 SHOW_DEFINED(WIFIR2R_STATUS_END_E); 2341 break; 2342 } 2343 case WIFIRX_PREAMBLE_E: 2344 { 2345 SHOW_DEFINED(WIFIRX_PREAMBLE_E); 2346 break; 2347 } 2348 case WIFIMACTX_SERVICE_E: 2349 { 2350 SHOW_DEFINED(WIFIMACTX_SERVICE_E); 2351 break; 2352 } 2353 2354 case WIFIMACTX_U_SIG_EHT_SU_MU_E: 2355 { 2356 struct hal_mon_usig_hdr *usig = NULL; 2357 struct hal_mon_usig_mu *usig_mu = NULL; 2358 2359 usig = (struct hal_mon_usig_hdr *)tx_tlv; 2360 usig_mu = &usig->usig_2.mu; 2361 2362 hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info); 2363 2364 TXMON_HAL_STATUS(ppdu_info, usig_mask) |= 2365 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 2366 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 2367 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 2368 QDF_MON_STATUS_USIG_MU_VALIDATE1_KNOWN | 2369 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_KNOWN | 2370 QDF_MON_STATUS_USIG_MU_VALIDATE2_KNOWN | 2371 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_KNOWN | 2372 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_KNOWN | 2373 QDF_MON_STATUS_USIG_CRC_KNOWN | 2374 QDF_MON_STATUS_USIG_TAIL_KNOWN; 2375 2376 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2377 (0x1F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 2378 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2379 (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE1_SHIFT); 2380 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2381 (usig_mu->ppdu_type_comp_mode << 2382 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 2383 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2384 (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 2385 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2386 (usig_mu->punc_ch_info << 2387 QDF_MON_STATUS_USIG_MU_PUNCTURE_CH_INFO_SHIFT); 2388 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2389 (0x1 << QDF_MON_STATUS_USIG_MU_VALIDATE2_SHIFT); 2390 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2391 (usig_mu->eht_sig_mcs << 2392 QDF_MON_STATUS_USIG_MU_EHT_SIG_MCS_SHIFT); 2393 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2394 (usig_mu->num_eht_sig_sym << 2395 QDF_MON_STATUS_USIG_MU_NUM_EHT_SIG_SYM_SHIFT); 2396 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2397 (usig_mu->crc << QDF_MON_STATUS_USIG_CRC_SHIFT); 2398 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2399 (usig_mu->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT); 2400 2401 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_SU_MU_E); 2402 break; 2403 } 2404 case WIFIMACTX_U_SIG_EHT_TB_E: 2405 { 2406 struct hal_mon_usig_hdr *usig = NULL; 2407 struct hal_mon_usig_tb *usig_tb = NULL; 2408 2409 usig = (struct hal_mon_usig_hdr *)tx_tlv; 2410 usig_tb = &usig->usig_2.tb; 2411 2412 hal_txmon_parse_u_sig_hdr(tx_tlv, ppdu_info); 2413 2414 TXMON_HAL_STATUS(ppdu_info, usig_mask) |= 2415 QDF_MON_STATUS_USIG_DISREGARD_KNOWN | 2416 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_KNOWN | 2417 QDF_MON_STATUS_USIG_VALIDATE_KNOWN | 2418 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_KNOWN | 2419 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_KNOWN | 2420 QDF_MON_STATUS_USIG_TB_DISREGARD1_KNOWN | 2421 QDF_MON_STATUS_USIG_CRC_KNOWN | 2422 QDF_MON_STATUS_USIG_TAIL_KNOWN; 2423 2424 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2425 (0x3F << QDF_MON_STATUS_USIG_DISREGARD_SHIFT); 2426 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2427 (usig_tb->ppdu_type_comp_mode << 2428 QDF_MON_STATUS_USIG_PPDU_TYPE_N_COMP_MODE_SHIFT); 2429 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2430 (0x1 << QDF_MON_STATUS_USIG_VALIDATE_SHIFT); 2431 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2432 (usig_tb->spatial_reuse_1 << 2433 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_1_SHIFT); 2434 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2435 (usig_tb->spatial_reuse_2 << 2436 QDF_MON_STATUS_USIG_TB_SPATIAL_REUSE_2_SHIFT); 2437 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2438 (0x1F << QDF_MON_STATUS_USIG_TB_DISREGARD1_SHIFT); 2439 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2440 (usig_tb->crc << QDF_MON_STATUS_USIG_CRC_SHIFT); 2441 TXMON_HAL_STATUS(ppdu_info, usig_value) |= 2442 (usig_tb->tail << QDF_MON_STATUS_USIG_TAIL_SHIFT); 2443 2444 SHOW_DEFINED(WIFIMACTX_U_SIG_EHT_TB_E); 2445 break; 2446 } 2447 case WIFIMACTX_EHT_SIG_USR_OFDMA_E: 2448 { 2449 hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id, 2450 ppdu_info); 2451 TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1; 2452 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_OFDMA_E); 2453 break; 2454 } 2455 case WIFIMACTX_EHT_SIG_USR_MU_MIMO_E: 2456 { 2457 hal_txmon_parse_eht_sig_mumimo_user_info(tx_tlv, user_id, 2458 ppdu_info); 2459 TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1; 2460 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_MU_MIMO_E); 2461 break; 2462 } 2463 case WIFIMACTX_EHT_SIG_USR_SU_E: 2464 { 2465 hal_txmon_parse_eht_sig_non_mumimo_user_info(tx_tlv, user_id, 2466 ppdu_info); 2467 TXMON_HAL_STATUS(ppdu_info, eht_flags) = 1; 2468 SHOW_DEFINED(WIFIMACTX_EHT_SIG_USR_SU_E); 2469 /* TODO: no radiotap info available */ 2470 break; 2471 } 2472 2473 case WIFIMACTX_HE_SIG_A_SU_E: 2474 { 2475 uint16_t he_mu_flag_1 = 0; 2476 uint16_t he_mu_flag_2 = 0; 2477 uint16_t num_users = 0; 2478 uint8_t mcs_of_sig_b = 0; 2479 uint8_t dcm_of_sig_b = 0; 2480 uint8_t sig_a_bw = 0; 2481 uint8_t i = 0; 2482 uint8_t bss_color_id; 2483 uint8_t coding; 2484 uint8_t stbc; 2485 uint8_t a_factor; 2486 uint8_t pe_disambiguity; 2487 uint8_t txbf; 2488 uint8_t txbw; 2489 uint8_t txop; 2490 2491 status = HAL_MON_MACTX_HE_SIG_A_SU; 2492 num_users = TXMON_HAL(ppdu_info, num_users); 2493 2494 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 2495 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2496 TRANSMIT_MCS); 2497 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 2498 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2499 DCM); 2500 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 2501 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2502 TRANSMIT_BW); 2503 2504 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 2505 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2506 BSS_COLOR_ID); 2507 coding = HAL_TX_DESC_GET_64(tx_tlv, 2508 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2509 CODING); 2510 stbc = HAL_TX_DESC_GET_64(tx_tlv, 2511 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2512 STBC); 2513 a_factor = HAL_TX_DESC_GET_64(tx_tlv, 2514 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2515 PACKET_EXTENSION_A_FACTOR); 2516 pe_disambiguity = HAL_TX_DESC_GET_64(tx_tlv, 2517 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2518 PACKET_EXTENSION_PE_DISAMBIGUITY); 2519 txbf = HAL_TX_DESC_GET_64(tx_tlv, 2520 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2521 TXBF); 2522 txbw = HAL_TX_DESC_GET_64(tx_tlv, 2523 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2524 TRANSMIT_BW); 2525 txop = HAL_TX_DESC_GET_64(tx_tlv, 2526 MACTX_HE_SIG_A_SU_MACTX_HE_SIG_A_SU_INFO_DETAILS, 2527 TXOP_DURATION); 2528 2529 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2530 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2531 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 2532 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 2533 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 2534 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN; 2535 2536 /* MCS */ 2537 he_mu_flag_1 |= mcs_of_sig_b << 2538 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 2539 /* DCM */ 2540 he_mu_flag_1 |= dcm_of_sig_b << 2541 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 2542 /* bandwidth */ 2543 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 2544 he_mu_flag_2 |= sig_a_bw << 2545 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 2546 2547 TXMON_HAL_STATUS(ppdu_info, 2548 he_mu_flags) = IS_MULTI_USERS(num_users); 2549 for (i = 0; i < num_users; i++) { 2550 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2551 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2552 } 2553 2554 /* HE data 1 */ 2555 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2556 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN | 2557 QDF_MON_STATUS_HE_CODING_KNOWN; 2558 2559 /* HE data 2 */ 2560 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2561 QDF_MON_STATUS_TXBF_KNOWN | 2562 QDF_MON_STATUS_PE_DISAMBIGUITY_KNOWN | 2563 QDF_MON_STATUS_TXOP_KNOWN | 2564 QDF_MON_STATUS_PRE_FEC_PADDING_KNOWN | 2565 QDF_MON_STATUS_MIDABLE_PERIODICITY_KNOWN; 2566 2567 /* HE data 3 */ 2568 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2569 bss_color_id | 2570 (!!txbf << QDF_MON_STATUS_BEAM_CHANGE_SHIFT) | 2571 (coding << QDF_MON_STATUS_CODING_SHIFT) | 2572 (stbc << QDF_MON_STATUS_STBC_SHIFT); 2573 2574 /* HE data 6 */ 2575 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 2576 (txop << QDF_MON_STATUS_TXOP_SHIFT); 2577 2578 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_SU_E); 2579 break; 2580 } 2581 case WIFIMACTX_HE_SIG_A_MU_DL_E: 2582 { 2583 uint16_t he_mu_flag_1 = 0; 2584 uint16_t he_mu_flag_2 = 0; 2585 uint16_t num_users = 0; 2586 uint8_t bss_color_id; 2587 uint8_t txop; 2588 uint8_t mcs_of_sig_b = 0; 2589 uint8_t dcm_of_sig_b = 0; 2590 uint8_t sig_a_bw = 0; 2591 uint8_t num_sig_b_symb = 0; 2592 uint8_t comp_mode_sig_b = 0; 2593 uint8_t punc_bw = 0; 2594 uint8_t i = 0; 2595 2596 status = HAL_MON_MACTX_HE_SIG_A_MU_DL; 2597 num_users = TXMON_HAL(ppdu_info, num_users); 2598 2599 mcs_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 2600 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2601 MCS_OF_SIG_B); 2602 dcm_of_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 2603 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2604 DCM_OF_SIG_B); 2605 sig_a_bw = HAL_TX_DESC_GET_64(tx_tlv, 2606 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2607 TRANSMIT_BW); 2608 num_sig_b_symb = HAL_TX_DESC_GET_64(tx_tlv, 2609 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2610 NUM_SIG_B_SYMBOLS); 2611 comp_mode_sig_b = HAL_TX_DESC_GET_64(tx_tlv, 2612 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2613 COMP_MODE_SIG_B); 2614 bss_color_id = HAL_TX_DESC_GET_64(tx_tlv, 2615 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2616 BSS_COLOR_ID); 2617 txop = HAL_TX_DESC_GET_64(tx_tlv, 2618 MACTX_HE_SIG_A_MU_DL_MACTX_HE_SIG_A_MU_DL_INFO_DETAILS, 2619 TXOP_DURATION); 2620 2621 he_mu_flag_1 |= QDF_MON_STATUS_SIG_B_MCS_KNOWN | 2622 QDF_MON_STATUS_SIG_B_DCM_KNOWN | 2623 QDF_MON_STATUS_SIG_B_SYM_NUM_KNOWN | 2624 QDF_MON_STATUS_CHANNEL_2_CENTER_26_RU_KNOWN | 2625 QDF_MON_STATUS_CHANNEL_1_RU_KNOWN | 2626 QDF_MON_STATUS_CHANNEL_2_RU_KNOWN | 2627 QDF_MON_STATUS_CHANNEL_1_CENTER_26_RU_KNOWN | 2628 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_1_KNOWN | 2629 QDF_MON_STATUS_SIG_B_SYMBOL_USER_KNOWN; 2630 2631 /* MCS */ 2632 he_mu_flag_1 |= mcs_of_sig_b << 2633 QDF_MON_STATUS_SIG_B_MCS_SHIFT; 2634 /* DCM */ 2635 he_mu_flag_1 |= dcm_of_sig_b << 2636 QDF_MON_STATUS_SIG_B_DCM_SHIFT; 2637 /* Compression */ 2638 he_mu_flag_2 |= comp_mode_sig_b << 2639 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2640 /* bandwidth */ 2641 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_BANDWIDTH_KNOWN; 2642 he_mu_flag_2 |= sig_a_bw << 2643 QDF_MON_STATUS_SIG_A_BANDWIDTH_SHIFT; 2644 he_mu_flag_2 |= comp_mode_sig_b << 2645 QDF_MON_STATUS_SIG_B_COMPRESSION_FLAG_2_SHIFT; 2646 /* number of symbol */ 2647 he_mu_flag_2 |= num_sig_b_symb << 2648 QDF_MON_STATUS_NUM_SIG_B_SYMBOLS_SHIFT; 2649 /* puncture bw */ 2650 he_mu_flag_2 |= QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_KNOWN; 2651 punc_bw = sig_a_bw; 2652 he_mu_flag_2 |= 2653 punc_bw << QDF_MON_STATUS_SIG_A_PUNC_BANDWIDTH_SHIFT; 2654 2655 /* copy per user info to all user */ 2656 TXMON_HAL_STATUS(ppdu_info, 2657 he_mu_flags) = IS_MULTI_USERS(num_users); 2658 for (i = 0; i < num_users; i++) { 2659 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 2660 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 2661 } 2662 2663 /* HE data 1 */ 2664 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2665 QDF_MON_STATUS_HE_BSS_COLOR_KNOWN; 2666 2667 /* HE data 2 */ 2668 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2669 QDF_MON_STATUS_TXOP_KNOWN; 2670 2671 /* HE data 3 */ 2672 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= bss_color_id; 2673 2674 /* HE data 6 */ 2675 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= 2676 (txop << QDF_MON_STATUS_TXOP_SHIFT); 2677 2678 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_DL_E); 2679 break; 2680 } 2681 case WIFIMACTX_HE_SIG_A_MU_UL_E: 2682 { 2683 SHOW_DEFINED(WIFIMACTX_HE_SIG_A_MU_UL_E); 2684 break; 2685 } 2686 case WIFIMACTX_HE_SIG_B1_MU_E: 2687 { 2688 status = HAL_MON_MACTX_HE_SIG_B1_MU; 2689 SHOW_DEFINED(WIFIMACTX_HE_SIG_B1_MU_E); 2690 break; 2691 } 2692 case WIFIMACTX_HE_SIG_B2_MU_E: 2693 { 2694 /* user tlv */ 2695 uint16_t sta_id = 0; 2696 uint16_t sta_spatial_config = 0; 2697 uint8_t sta_mcs = 0; 2698 uint8_t coding = 0; 2699 uint8_t nss = 0; 2700 uint8_t user_order = 0; 2701 2702 status = HAL_MON_MACTX_HE_SIG_B2_MU; 2703 2704 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2705 2706 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 2707 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2708 STA_ID); 2709 sta_spatial_config = HAL_TX_DESC_GET_64(tx_tlv, 2710 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2711 STA_SPATIAL_CONFIG); 2712 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 2713 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2714 STA_MCS); 2715 coding = HAL_TX_DESC_GET_64(tx_tlv, 2716 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2717 STA_CODING); 2718 nss = HAL_TX_DESC_GET_64(tx_tlv, 2719 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2720 NSTS) + 1; 2721 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2722 MACTX_HE_SIG_B2_MU_MACTX_HE_SIG_B2_MU_INFO_DETAILS, 2723 USER_ORDER); 2724 2725 /* HE data 1 */ 2726 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2727 QDF_MON_STATUS_HE_MCS_KNOWN | 2728 QDF_MON_STATUS_HE_CODING_KNOWN; 2729 /* HE data 2 */ 2730 2731 /* HE data 3 */ 2732 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2733 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2734 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2735 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2736 coding << QDF_MON_STATUS_CODING_SHIFT; 2737 2738 /* HE data 4 */ 2739 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2740 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2741 2742 /* HE data 5 */ 2743 2744 /* HE data 6 */ 2745 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2746 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2747 2748 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_MU_E); 2749 break; 2750 } 2751 case WIFIMACTX_HE_SIG_B2_OFDMA_E: 2752 { 2753 /* user tlv */ 2754 uint8_t *he_sig_b2_ofdma_info = NULL; 2755 uint16_t sta_id = 0; 2756 uint8_t nss = 0; 2757 uint8_t txbf = 0; 2758 uint8_t sta_mcs = 0; 2759 uint8_t sta_dcm = 0; 2760 uint8_t coding = 0; 2761 uint8_t user_order = 0; 2762 2763 status = HAL_MON_MACTX_HE_SIG_B2_OFDMA; 2764 2765 TXMON_HAL(ppdu_info, cur_usr_idx) = user_id; 2766 2767 he_sig_b2_ofdma_info = (uint8_t *)tx_tlv + 2768 HAL_OFFSET(MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2769 STA_ID); 2770 2771 sta_id = HAL_TX_DESC_GET_64(tx_tlv, 2772 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2773 STA_ID); 2774 nss = HAL_TX_DESC_GET_64(tx_tlv, 2775 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2776 NSTS); 2777 txbf = HAL_TX_DESC_GET_64(tx_tlv, 2778 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2779 TXBF); 2780 sta_mcs = HAL_TX_DESC_GET_64(tx_tlv, 2781 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2782 STA_MCS); 2783 sta_dcm = HAL_TX_DESC_GET_64(tx_tlv, 2784 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2785 STA_DCM); 2786 coding = HAL_TX_DESC_GET_64(tx_tlv, 2787 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2788 STA_CODING); 2789 user_order = HAL_TX_DESC_GET_64(tx_tlv, 2790 MACTX_HE_SIG_B2_OFDMA_MACTX_HE_SIG_B2_OFDMA_INFO_DETAILS, 2791 USER_ORDER); 2792 2793 /* HE data 1 */ 2794 TXMON_HAL_USER(ppdu_info, user_id, he_data1) |= 2795 QDF_MON_STATUS_HE_MCS_KNOWN | 2796 QDF_MON_STATUS_HE_CODING_KNOWN | 2797 QDF_MON_STATUS_HE_DCM_KNOWN; 2798 /* HE data 2 */ 2799 TXMON_HAL_USER(ppdu_info, user_id, he_data2) |= 2800 QDF_MON_STATUS_TXBF_KNOWN; 2801 2802 /* HE data 3 */ 2803 TXMON_HAL_USER(ppdu_info, user_id, mcs) = sta_mcs; 2804 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2805 sta_mcs << QDF_MON_STATUS_TRANSMIT_MCS_SHIFT; 2806 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2807 sta_dcm << QDF_MON_STATUS_DCM_SHIFT; 2808 TXMON_HAL_USER(ppdu_info, user_id, he_data3) |= 2809 coding << QDF_MON_STATUS_CODING_SHIFT; 2810 2811 /* HE data 4 */ 2812 TXMON_HAL_USER(ppdu_info, user_id, he_data4) |= 2813 sta_id << QDF_MON_STATUS_STA_ID_SHIFT; 2814 2815 /* HE data 5 */ 2816 TXMON_HAL_USER(ppdu_info, user_id, he_data5) |= 2817 txbf << QDF_MON_STATUS_TXBF_SHIFT; 2818 2819 /* HE data 6 */ 2820 TXMON_HAL_USER(ppdu_info, user_id, nss) = nss; 2821 TXMON_HAL_USER(ppdu_info, user_id, he_data6) |= nss; 2822 2823 SHOW_DEFINED(WIFIMACTX_HE_SIG_B2_OFDMA_E); 2824 break; 2825 } 2826 case WIFIMACTX_L_SIG_A_E: 2827 { 2828 uint8_t *l_sig_a_info = NULL; 2829 uint8_t rate = 0; 2830 2831 status = HAL_MON_MACTX_L_SIG_A; 2832 2833 l_sig_a_info = (uint8_t *)tx_tlv + 2834 HAL_OFFSET(MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2835 RATE); 2836 rate = HAL_TX_DESC_GET_64(tx_tlv, 2837 MACTX_L_SIG_A_MACTX_L_SIG_A_INFO_DETAILS, 2838 RATE); 2839 2840 switch (rate) { 2841 case 8: 2842 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_0MCS; 2843 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2844 break; 2845 case 9: 2846 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_1MCS; 2847 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2848 break; 2849 case 10: 2850 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_2MCS; 2851 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2852 break; 2853 case 11: 2854 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_3MCS; 2855 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2856 break; 2857 case 12: 2858 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_4MCS; 2859 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2860 break; 2861 case 13: 2862 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_5MCS; 2863 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2864 break; 2865 case 14: 2866 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_6MCS; 2867 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2868 break; 2869 case 15: 2870 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11A_RATE_7MCS; 2871 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS7; 2872 break; 2873 default: 2874 break; 2875 } 2876 2877 TXMON_HAL_STATUS(ppdu_info, ofdm_flag) = 1; 2878 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2879 TXMON_HAL_STATUS(ppdu_info, 2880 l_sig_a_info) = *((uint32_t *)l_sig_a_info); 2881 2882 SHOW_DEFINED(WIFIMACTX_L_SIG_A_E); 2883 break; 2884 } 2885 case WIFIMACTX_L_SIG_B_E: 2886 { 2887 uint8_t *l_sig_b_info = NULL; 2888 uint8_t rate = 0; 2889 2890 status = HAL_MON_MACTX_L_SIG_B; 2891 2892 l_sig_b_info = (uint8_t *)tx_tlv + 2893 HAL_OFFSET(MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2894 RATE); 2895 rate = HAL_TX_DESC_GET_64(tx_tlv, 2896 MACTX_L_SIG_B_MACTX_L_SIG_B_INFO_DETAILS, 2897 RATE); 2898 2899 switch (rate) { 2900 case 1: 2901 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_3MCS; 2902 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS3; 2903 break; 2904 case 2: 2905 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_2MCS; 2906 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS2; 2907 break; 2908 case 3: 2909 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_1MCS; 2910 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS1; 2911 break; 2912 case 4: 2913 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_0MCS; 2914 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS0; 2915 break; 2916 case 5: 2917 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_6MCS; 2918 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS6; 2919 break; 2920 case 6: 2921 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_5MCS; 2922 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS5; 2923 break; 2924 case 7: 2925 TXMON_HAL_STATUS(ppdu_info, rate) = HAL_11B_RATE_4MCS; 2926 TXMON_HAL_STATUS(ppdu_info, mcs) = HAL_LEGACY_MCS4; 2927 break; 2928 default: 2929 break; 2930 } 2931 2932 TXMON_HAL_STATUS(ppdu_info, cck_flag) = 1; 2933 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2934 TXMON_HAL_STATUS(ppdu_info, l_sig_b_info) = *l_sig_b_info; 2935 2936 SHOW_DEFINED(WIFIMACTX_L_SIG_B_E); 2937 break; 2938 } 2939 case WIFIMACTX_HT_SIG_E: 2940 { 2941 uint8_t mcs = 0; 2942 uint8_t bw = 0; 2943 uint8_t is_stbc = 0; 2944 uint8_t coding = 0; 2945 uint8_t gi = 0; 2946 2947 status = HAL_MON_MACTX_HT_SIG; 2948 mcs = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, MCS); 2949 bw = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, CBW); 2950 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, STBC); 2951 coding = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, FEC_CODING); 2952 gi = HAL_TX_DESC_GET_64(tx_tlv, HT_SIG_INFO, SHORT_GI); 2953 2954 TXMON_HAL_STATUS(ppdu_info, ldpc) = 2955 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 2956 TXMON_HAL_STATUS(ppdu_info, ht_mcs) = mcs; 2957 TXMON_HAL_STATUS(ppdu_info, bw) = bw; 2958 TXMON_HAL_STATUS(ppdu_info, sgi) = gi; 2959 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 2960 TXMON_HAL_STATUS(ppdu_info, reception_type) = HAL_RX_TYPE_SU; 2961 2962 SHOW_DEFINED(WIFIMACTX_HT_SIG_E); 2963 break; 2964 } 2965 case WIFIMACTX_VHT_SIG_A_E: 2966 { 2967 uint8_t bandwidth = 0; 2968 uint8_t is_stbc = 0; 2969 uint8_t group_id = 0; 2970 uint32_t nss_comb = 0; 2971 uint8_t nss_su = 0; 2972 uint8_t nss_mu[4] = {0}; 2973 uint8_t sgi = 0; 2974 uint8_t coding = 0; 2975 uint8_t mcs = 0; 2976 uint8_t beamformed = 0; 2977 uint8_t partial_aid = 0; 2978 2979 status = HAL_MON_MACTX_VHT_SIG_A; 2980 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, 2981 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2982 BANDWIDTH); 2983 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, 2984 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2985 STBC); 2986 group_id = HAL_TX_DESC_GET_64(tx_tlv, 2987 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2988 GROUP_ID); 2989 /* nss_comb is su nss, MU nss and partial AID */ 2990 nss_comb = HAL_TX_DESC_GET_64(tx_tlv, 2991 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 2992 N_STS); 2993 /* if it is SU */ 2994 nss_su = (nss_comb & 0x7) + 1; 2995 /* partial aid - applicable only for SU */ 2996 partial_aid = (nss_comb >> 3) & 0x1F; 2997 /* if it is MU */ 2998 nss_mu[0] = (nss_comb & 0x7) + 1; 2999 nss_mu[1] = ((nss_comb >> 3) & 0x7) + 1; 3000 nss_mu[2] = ((nss_comb >> 6) & 0x7) + 1; 3001 nss_mu[3] = ((nss_comb >> 9) & 0x7) + 1; 3002 3003 sgi = HAL_TX_DESC_GET_64(tx_tlv, 3004 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 3005 GI_SETTING); 3006 coding = HAL_TX_DESC_GET_64(tx_tlv, 3007 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 3008 SU_MU_CODING); 3009 mcs = HAL_TX_DESC_GET_64(tx_tlv, 3010 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 3011 MCS); 3012 beamformed = HAL_TX_DESC_GET_64(tx_tlv, 3013 MACTX_VHT_SIG_A_MACTX_VHT_SIG_A_INFO_DETAILS, 3014 BEAMFORMED); 3015 3016 TXMON_HAL_STATUS(ppdu_info, ldpc) = 3017 (coding == HAL_SU_MU_CODING_LDPC) ? 1 : 0; 3018 TXMON_STATUS_INFO(tx_status_info, sw_frame_group_id) = group_id; 3019 3020 TXMON_HAL_STATUS(ppdu_info, sgi) = sgi; 3021 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 3022 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 3023 TXMON_HAL_STATUS(ppdu_info, beamformed) = beamformed; 3024 3025 if (group_id == 0 || group_id == 63) { 3026 TXMON_HAL_STATUS(ppdu_info, reception_type) = 3027 HAL_RX_TYPE_SU; 3028 TXMON_HAL_STATUS(ppdu_info, mcs) = mcs; 3029 TXMON_HAL_STATUS(ppdu_info, nss) = 3030 nss_su & VHT_SIG_SU_NSS_MASK; 3031 3032 TXMON_HAL_USER(ppdu_info, user_id, 3033 vht_flag_values3[0]) = ((mcs << 4) | 3034 nss_su); 3035 } else { 3036 TXMON_HAL_STATUS(ppdu_info, reception_type) = 3037 HAL_RX_TYPE_MU_MIMO; 3038 TXMON_HAL_USER(ppdu_info, user_id, mcs) = mcs; 3039 TXMON_HAL_USER(ppdu_info, user_id, nss) = 3040 nss_su & VHT_SIG_SU_NSS_MASK; 3041 3042 TXMON_HAL_USER(ppdu_info, user_id, 3043 vht_flag_values3[0]) = ((mcs << 4) | 3044 nss_su); 3045 TXMON_HAL_USER(ppdu_info, user_id, 3046 vht_flag_values3[1]) = ((mcs << 4) | 3047 nss_mu[1]); 3048 TXMON_HAL_USER(ppdu_info, user_id, 3049 vht_flag_values3[2]) = ((mcs << 4) | 3050 nss_mu[2]); 3051 TXMON_HAL_USER(ppdu_info, user_id, 3052 vht_flag_values3[3]) = ((mcs << 4) | 3053 nss_mu[3]); 3054 } 3055 3056 /* TODO: loop over multiple user */ 3057 TXMON_HAL_USER(ppdu_info, user_id, 3058 vht_flag_values2) = bandwidth; 3059 TXMON_HAL_USER(ppdu_info, user_id, 3060 vht_flag_values4) = coding; 3061 TXMON_HAL_USER(ppdu_info, user_id, 3062 vht_flag_values5) = group_id; 3063 TXMON_HAL_USER(ppdu_info, user_id, 3064 vht_flag_values6) = partial_aid; 3065 SHOW_DEFINED(WIFIMACTX_VHT_SIG_A_E); 3066 break; 3067 } 3068 case WIFIMACTX_VHT_SIG_B_MU160_E: 3069 { 3070 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU160_E); 3071 break; 3072 } 3073 case WIFIMACTX_VHT_SIG_B_MU80_E: 3074 { 3075 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU80_E); 3076 break; 3077 } 3078 case WIFIMACTX_VHT_SIG_B_MU40_E: 3079 { 3080 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU40_E); 3081 break; 3082 } 3083 case WIFIMACTX_VHT_SIG_B_MU20_E: 3084 { 3085 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_MU20_E); 3086 break; 3087 } 3088 case WIFIMACTX_VHT_SIG_B_SU160_E: 3089 { 3090 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU160_E); 3091 break; 3092 } 3093 case WIFIMACTX_VHT_SIG_B_SU80_E: 3094 { 3095 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU80_E); 3096 break; 3097 } 3098 case WIFIMACTX_VHT_SIG_B_SU40_E: 3099 { 3100 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU40_E); 3101 break; 3102 } 3103 case WIFIMACTX_VHT_SIG_B_SU20_E: 3104 { 3105 SHOW_DEFINED(WIFIMACTX_VHT_SIG_B_SU20_E); 3106 break; 3107 } 3108 case WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E: 3109 { 3110 SHOW_DEFINED(WIFIPHYTX_PPDU_HEADER_INFO_REQUEST_E); 3111 break; 3112 } 3113 case WIFIMACTX_USER_DESC_PER_USER_E: 3114 { 3115 hal_txmon_parse_user_desc_per_user(tx_tlv, user_id, ppdu_info); 3116 3117 SHOW_DEFINED(WIFIMACTX_USER_DESC_PER_USER_E); 3118 break; 3119 } 3120 case WIFIMACTX_USER_DESC_COMMON_E: 3121 { 3122 hal_txmon_parse_user_desc_common(tx_tlv, user_id, ppdu_info); 3123 3124 /* copy per user info to all user */ 3125 SHOW_DEFINED(WIFIMACTX_USER_DESC_COMMON_E); 3126 break; 3127 } 3128 case WIFIMACTX_PHY_DESC_E: 3129 { 3130 /* pkt_type - preamble type */ 3131 uint32_t pkt_type = 0; 3132 uint8_t bandwidth = 0; 3133 uint8_t is_stbc = 0; 3134 uint8_t is_triggered = 0; 3135 uint8_t gi = 0; 3136 uint8_t he_ppdu_subtype = 0; 3137 uint32_t ltf_size = 0; 3138 uint32_t he_data1 = 0; 3139 uint32_t he_data2 = 0; 3140 uint32_t he_data3 = 0; 3141 uint32_t he_data5 = 0; 3142 uint16_t he_mu_flag_1 = 0; 3143 uint16_t he_mu_flag_2 = 0; 3144 uint16_t num_users = 0; 3145 uint8_t i = 0; 3146 3147 SHOW_DEFINED(WIFIMACTX_PHY_DESC_E); 3148 status = HAL_MON_MACTX_PHY_DESC; 3149 3150 num_users = TXMON_HAL(ppdu_info, num_users); 3151 pkt_type = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, PKT_TYPE); 3152 is_stbc = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, STBC); 3153 is_triggered = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 3154 TRIGGERED); 3155 if (!is_triggered) { 3156 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 3157 BANDWIDTH); 3158 } else { 3159 /* 3160 * is_triggered, bw is minimum of AP pkt bw 3161 * or STA bw 3162 */ 3163 bandwidth = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 3164 AP_PKT_BW); 3165 } 3166 3167 gi = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 3168 CP_SETTING); 3169 ltf_size = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, LTF_SIZE); 3170 he_ppdu_subtype = HAL_TX_DESC_GET_64(tx_tlv, MACTX_PHY_DESC, 3171 HE_PPDU_SUBTYPE); 3172 3173 TXMON_HAL_STATUS(ppdu_info, preamble_type) = pkt_type; 3174 TXMON_HAL_STATUS(ppdu_info, ltf_size) = ltf_size; 3175 TXMON_HAL_STATUS(ppdu_info, is_stbc) = is_stbc; 3176 TXMON_HAL_STATUS(ppdu_info, bw) = bandwidth; 3177 3178 switch (ppdu_info->rx_status.preamble_type) { 3179 case TXMON_PKT_TYPE_11N_MM: 3180 TXMON_HAL_STATUS(ppdu_info, ht_flags) = 1; 3181 TXMON_HAL_STATUS(ppdu_info, 3182 rtap_flags) |= HT_SGI_PRESENT; 3183 break; 3184 case TXMON_PKT_TYPE_11AC: 3185 TXMON_HAL_STATUS(ppdu_info, vht_flags) = 1; 3186 break; 3187 case TXMON_PKT_TYPE_11AX: 3188 TXMON_HAL_STATUS(ppdu_info, he_flags) = 1; 3189 break; 3190 default: 3191 break; 3192 } 3193 3194 if (!TXMON_HAL_STATUS(ppdu_info, he_flags)) 3195 break; 3196 3197 /* update he flags */ 3198 /* PPDU FORMAT */ 3199 switch (he_ppdu_subtype) { 3200 case TXMON_HE_SUBTYPE_SU: 3201 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 3202 QDF_MON_STATUS_HE_SU_FORMAT_TYPE; 3203 break; 3204 case TXMON_HE_SUBTYPE_TRIG: 3205 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 3206 QDF_MON_STATUS_HE_TRIG_FORMAT_TYPE; 3207 break; 3208 case TXMON_HE_SUBTYPE_MU: 3209 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 3210 QDF_MON_STATUS_HE_MU_FORMAT_TYPE; 3211 break; 3212 case TXMON_HE_SUBTYPE_EXT_SU: 3213 TXMON_HAL_STATUS(ppdu_info, he_data1) |= 3214 QDF_MON_STATUS_HE_EXT_SU_FORMAT_TYPE; 3215 break; 3216 }; 3217 3218 /* STBC */ 3219 he_data1 |= QDF_MON_STATUS_HE_STBC_KNOWN; 3220 he_data3 |= (is_stbc << QDF_MON_STATUS_STBC_SHIFT); 3221 3222 /* GI */ 3223 he_data2 |= QDF_MON_STATUS_HE_GI_KNOWN; 3224 he_data5 |= (gi << QDF_MON_STATUS_GI_SHIFT); 3225 3226 /* Data BW and RU allocation */ 3227 he_data1 |= QDF_MON_STATUS_HE_DATA_BW_RU_KNOWN; 3228 he_data5 = (he_data5 & 0xFFF0) | bandwidth; 3229 3230 he_data2 |= QDF_MON_STATUS_LTF_SYMBOLS_KNOWN; 3231 he_data5 |= ((1 + ltf_size) << 3232 QDF_MON_STATUS_HE_LTF_SIZE_SHIFT); 3233 3234 TXMON_HAL_STATUS(ppdu_info, 3235 he_mu_flags) = IS_MULTI_USERS(num_users); 3236 /* MAC TX PHY DESC is not a user tlv */ 3237 for (i = 0; i < num_users; i++) { 3238 TXMON_HAL_USER(ppdu_info, i, he_data1) = he_data1; 3239 TXMON_HAL_USER(ppdu_info, i, he_data2) = he_data2; 3240 TXMON_HAL_USER(ppdu_info, i, he_data3) = he_data3; 3241 TXMON_HAL_USER(ppdu_info, i, he_data5) = he_data5; 3242 3243 /* HE MU flags */ 3244 TXMON_HAL_USER(ppdu_info, i, he_flags1) |= he_mu_flag_1; 3245 TXMON_HAL_USER(ppdu_info, i, he_flags2) |= he_mu_flag_2; 3246 } 3247 break; 3248 } 3249 case WIFICOEX_RX_STATUS_E: 3250 { 3251 SHOW_DEFINED(WIFICOEX_RX_STATUS_E); 3252 break; 3253 } 3254 case WIFIRX_PPDU_ACK_REPORT_E: 3255 { 3256 SHOW_DEFINED(WIFIRX_PPDU_ACK_REPORT_E); 3257 break; 3258 } 3259 case WIFIRX_PPDU_NO_ACK_REPORT_E: 3260 { 3261 SHOW_DEFINED(WIFIRX_PPDU_NO_ACK_REPORT_E); 3262 break; 3263 } 3264 case WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E: 3265 { 3266 SHOW_DEFINED(WIFITXPCU_PHYTX_OTHER_TRANSMIT_INFO32_E); 3267 break; 3268 } 3269 case WIFITXPCU_PHYTX_DEBUG32_E: 3270 { 3271 SHOW_DEFINED(WIFITXPCU_PHYTX_DEBUG32_E); 3272 break; 3273 } 3274 case WIFITXPCU_PREAMBLE_DONE_E: 3275 { 3276 SHOW_DEFINED(WIFITXPCU_PREAMBLE_DONE_E); 3277 break; 3278 } 3279 case WIFIRX_PHY_SLEEP_E: 3280 { 3281 SHOW_DEFINED(WIFIRX_PHY_SLEEP_E); 3282 break; 3283 } 3284 case WIFIRX_FRAME_BITMAP_REQ_E: 3285 { 3286 SHOW_DEFINED(WIFIRX_FRAME_BITMAP_REQ_E); 3287 break; 3288 } 3289 case WIFIRXPCU_TX_SETUP_CLEAR_E: 3290 { 3291 SHOW_DEFINED(WIFIRXPCU_TX_SETUP_CLEAR_E); 3292 break; 3293 } 3294 case WIFIRX_TRIG_INFO_E: 3295 { 3296 SHOW_DEFINED(WIFIRX_TRIG_INFO_E); 3297 break; 3298 } 3299 case WIFIEXPECTED_RESPONSE_E: 3300 { 3301 SHOW_DEFINED(WIFIEXPECTED_RESPONSE_E); 3302 break; 3303 } 3304 case WIFITRIGGER_RESPONSE_TX_DONE_E: 3305 { 3306 SHOW_DEFINED(WIFITRIGGER_RESPONSE_TX_DONE_E); 3307 break; 3308 } 3309 case WIFIFW2SW_MON_E: 3310 { 3311 /* parse fw2sw tlv */ 3312 hal_txmon_parse_fw2sw(tx_tlv, tlv_user_id, data_status_info); 3313 status = HAL_MON_TX_FW2SW; 3314 SHOW_DEFINED(WIFIFW2SW_MON_E); 3315 break; 3316 } 3317 } 3318 3319 return status; 3320 } 3321 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */ 3322 3323 #ifdef REO_SHARED_QREF_TABLE_EN 3324 static void hal_reo_shared_qaddr_cache_clear_be(hal_soc_handle_t hal_soc_hdl) 3325 { 3326 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3327 uint32_t reg_val = 0; 3328 3329 /* Set Qdesc clear bit to erase REO internal storage for Qdesc pointers 3330 * of 37 peer/tids 3331 */ 3332 reg_val = HAL_REG_READ(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE)); 3333 reg_val |= HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1); 3334 HAL_REG_WRITE(hal, 3335 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 3336 reg_val); 3337 3338 /* Clear Qdesc clear bit to erase REO internal storage for Qdesc pointers 3339 * of 37 peer/tids 3340 */ 3341 reg_val &= ~(HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, CLEAR_QDESC_ARRAY, 1)); 3342 HAL_REG_WRITE(hal, 3343 HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 3344 reg_val); 3345 3346 hal_verbose_debug("hal_soc: %pK :Setting CLEAR_DESC_ARRAY field of" 3347 "WCSS_UMAC_REO_R0_QDESC_ADDR_READ and resetting back" 3348 "to erase stale entries in reo storage: regval:%x", hal, reg_val); 3349 } 3350 3351 /* hal_reo_shared_qaddr_write(): Write REO tid queue addr 3352 * LUT shared by SW and HW at the index given by peer id 3353 * and tid. 3354 * 3355 * @hal_soc: hal soc pointer 3356 * @reo_qref_addr: pointer to index pointed to be peer_id 3357 * and tid 3358 * @tid: tid queue number 3359 * @hw_qdesc_paddr: reo queue addr 3360 */ 3361 3362 static void hal_reo_shared_qaddr_write_be(hal_soc_handle_t hal_soc_hdl, 3363 uint16_t peer_id, 3364 int tid, 3365 qdf_dma_addr_t hw_qdesc_paddr) 3366 { 3367 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3368 struct rx_reo_queue_reference *reo_qref; 3369 uint32_t peer_tid_idx; 3370 3371 /* Plug hw_desc_addr in Host reo queue reference table */ 3372 if (HAL_PEER_ID_IS_MLO(peer_id)) { 3373 peer_tid_idx = ((peer_id - HAL_ML_PEER_ID_START) * 3374 DP_MAX_TIDS) + tid; 3375 reo_qref = (struct rx_reo_queue_reference *) 3376 &hal->reo_qref.mlo_reo_qref_table_vaddr[peer_tid_idx]; 3377 } else { 3378 peer_tid_idx = (peer_id * DP_MAX_TIDS) + tid; 3379 reo_qref = (struct rx_reo_queue_reference *) 3380 &hal->reo_qref.non_mlo_reo_qref_table_vaddr[peer_tid_idx]; 3381 } 3382 reo_qref->rx_reo_queue_desc_addr_31_0 = 3383 hw_qdesc_paddr & 0xffffffff; 3384 reo_qref->rx_reo_queue_desc_addr_39_32 = 3385 (hw_qdesc_paddr & 0xff00000000) >> 32; 3386 if (hw_qdesc_paddr != 0) 3387 reo_qref->receive_queue_number = tid; 3388 else 3389 reo_qref->receive_queue_number = 0; 3390 3391 hal_reo_shared_qaddr_cache_clear_be(hal_soc_hdl); 3392 hal_verbose_debug("hw_qdesc_paddr: %pK, tid: %d, reo_qref:%pK," 3393 "rx_reo_queue_desc_addr_31_0: %x," 3394 "rx_reo_queue_desc_addr_39_32: %x", 3395 (void *)hw_qdesc_paddr, tid, reo_qref, 3396 reo_qref->rx_reo_queue_desc_addr_31_0, 3397 reo_qref->rx_reo_queue_desc_addr_39_32); 3398 } 3399 3400 #ifdef BIG_ENDIAN_HOST 3401 static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal) 3402 { 3403 HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 3404 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, GXI_SWAP, 1) | 3405 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1)); 3406 } 3407 #else 3408 static inline void hal_reo_shared_qaddr_enable(struct hal_soc *hal) 3409 { 3410 HAL_REG_WRITE(hal, HWIO_REO_R0_QDESC_ADDR_READ_ADDR(REO_REG_REG_BASE), 3411 HAL_SM(HWIO_REO_R0_QDESC_ADDR_READ, LUT_FEATURE_ENABLE, 1)); 3412 } 3413 #endif 3414 3415 /** 3416 * hal_reo_shared_qaddr_setup_be() - Allocate MLO and Non MLO reo queue 3417 * reference table shared between SW and HW and initialize in Qdesc Base0 3418 * base1 registers provided by HW. 3419 * 3420 * @hal_soc_hdl: HAL Soc handle 3421 * @reo_qref: REO queue reference table 3422 * 3423 * Return: QDF_STATUS_SUCCESS on success else a QDF error. 3424 */ 3425 static QDF_STATUS 3426 hal_reo_shared_qaddr_setup_be(hal_soc_handle_t hal_soc_hdl, 3427 struct reo_queue_ref_table *reo_qref) 3428 { 3429 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3430 3431 reo_qref->reo_qref_table_en = 1; 3432 3433 reo_qref->mlo_reo_qref_table_vaddr = 3434 (uint64_t *)qdf_mem_alloc_consistent( 3435 hal->qdf_dev, hal->qdf_dev->dev, 3436 REO_QUEUE_REF_ML_TABLE_SIZE, 3437 &reo_qref->mlo_reo_qref_table_paddr); 3438 if (!reo_qref->mlo_reo_qref_table_vaddr) 3439 return QDF_STATUS_E_NOMEM; 3440 3441 reo_qref->non_mlo_reo_qref_table_vaddr = 3442 (uint64_t *)qdf_mem_alloc_consistent( 3443 hal->qdf_dev, hal->qdf_dev->dev, 3444 REO_QUEUE_REF_NON_ML_TABLE_SIZE, 3445 &reo_qref->non_mlo_reo_qref_table_paddr); 3446 if (!reo_qref->non_mlo_reo_qref_table_vaddr) { 3447 qdf_mem_free_consistent( 3448 hal->qdf_dev, hal->qdf_dev->dev, 3449 REO_QUEUE_REF_ML_TABLE_SIZE, 3450 reo_qref->mlo_reo_qref_table_vaddr, 3451 reo_qref->mlo_reo_qref_table_paddr, 3452 0); 3453 reo_qref->mlo_reo_qref_table_vaddr = NULL; 3454 return QDF_STATUS_E_NOMEM; 3455 } 3456 3457 hal_verbose_debug("MLO table start paddr:%pK," 3458 "Non-MLO table start paddr:%pK," 3459 "MLO table start vaddr: %pK," 3460 "Non MLO table start vaddr: %pK", 3461 (void *)reo_qref->mlo_reo_qref_table_paddr, 3462 (void *)reo_qref->non_mlo_reo_qref_table_paddr, 3463 reo_qref->mlo_reo_qref_table_vaddr, 3464 reo_qref->non_mlo_reo_qref_table_vaddr); 3465 3466 return QDF_STATUS_SUCCESS; 3467 } 3468 3469 /** 3470 * hal_reo_shared_qaddr_init_be() - Zero out REO qref LUT and 3471 * write start addr of MLO and Non MLO table in HW 3472 * 3473 * @hal_soc_hdl: HAL Soc handle 3474 * @qref_reset: reset qref LUT 3475 * 3476 * Return: None 3477 */ 3478 static void hal_reo_shared_qaddr_init_be(hal_soc_handle_t hal_soc_hdl, 3479 int qref_reset) 3480 { 3481 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3482 3483 if (qref_reset) { 3484 qdf_mem_zero(hal->reo_qref.mlo_reo_qref_table_vaddr, 3485 REO_QUEUE_REF_ML_TABLE_SIZE); 3486 qdf_mem_zero(hal->reo_qref.non_mlo_reo_qref_table_vaddr, 3487 REO_QUEUE_REF_NON_ML_TABLE_SIZE); 3488 } 3489 /* LUT_BASE0 and BASE1 registers expect upper 32bits of LUT base address 3490 * and lower 8 bits to be 0. Shift the physical address by 8 to plug 3491 * upper 32bits only 3492 */ 3493 HAL_REG_WRITE(hal, 3494 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 3495 hal->reo_qref.non_mlo_reo_qref_table_paddr >> 8); 3496 HAL_REG_WRITE(hal, 3497 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 3498 hal->reo_qref.mlo_reo_qref_table_paddr >> 8); 3499 hal_reo_shared_qaddr_enable(hal); 3500 HAL_REG_WRITE(hal, 3501 HWIO_REO_R0_QDESC_MAX_SW_PEER_ID_ADDR(REO_REG_REG_BASE), 3502 HAL_MS(HWIO_REO_R0_QDESC, MAX_SW_PEER_ID_MAX_SUPPORTED, 3503 0x1fff)); 3504 } 3505 3506 /** 3507 * hal_reo_shared_qaddr_detach_be() - Free MLO and Non MLO reo queue 3508 * reference table shared between SW and HW 3509 * 3510 * @hal_soc_hdl: HAL Soc handle 3511 * 3512 * Return: None 3513 */ 3514 static void hal_reo_shared_qaddr_detach_be(hal_soc_handle_t hal_soc_hdl) 3515 { 3516 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl; 3517 3518 HAL_REG_WRITE(hal, 3519 HWIO_REO_R0_QDESC_LUT_BASE0_ADDR_ADDR(REO_REG_REG_BASE), 3520 0); 3521 HAL_REG_WRITE(hal, 3522 HWIO_REO_R0_QDESC_LUT_BASE1_ADDR_ADDR(REO_REG_REG_BASE), 3523 0); 3524 } 3525 #endif 3526 3527 /** 3528 * hal_tx_vdev_mismatch_routing_set_generic_be() - set vdev mismatch exception routing 3529 * @hal_soc_hdl: HAL SoC context 3530 * @config: HAL_TX_VDEV_MISMATCH_TQM_NOTIFY - route via TQM 3531 * HAL_TX_VDEV_MISMATCH_FW_NOTIFY - route via FW 3532 * 3533 * Return: void 3534 */ 3535 #ifdef HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK 3536 static inline void 3537 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3538 enum hal_tx_vdev_mismatch_notify 3539 config) 3540 { 3541 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3542 uint32_t reg_addr, reg_val = 0; 3543 uint32_t val = 0; 3544 3545 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3546 3547 val = HAL_REG_READ(hal_soc, reg_addr); 3548 3549 /* reset the corresponding bits in register */ 3550 val &= (~(HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_BMSK)); 3551 3552 /* set config value */ 3553 reg_val = val | (config << 3554 HWIO_TCL_R0_CMN_CONFIG_VDEVID_MISMATCH_EXCEPTION_SHFT); 3555 3556 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3557 } 3558 #else 3559 static inline void 3560 hal_tx_vdev_mismatch_routing_set_generic_be(hal_soc_handle_t hal_soc_hdl, 3561 enum hal_tx_vdev_mismatch_notify 3562 config) 3563 { 3564 } 3565 #endif 3566 3567 /** 3568 * hal_tx_mcast_mlo_reinject_routing_set_generic_be() - set MLO multicast reinject routing 3569 * @hal_soc_hdl: HAL SoC context 3570 * @config: HAL_TX_MCAST_MLO_REINJECT_FW_NOTIFY - route via FW 3571 * HAL_TX_MCAST_MLO_REINJECT_TQM_NOTIFY - route via TQM 3572 * 3573 * Return: void 3574 */ 3575 #if defined(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK) && \ 3576 defined(WLAN_MCAST_MLO) 3577 static inline void 3578 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3579 hal_soc_handle_t hal_soc_hdl, 3580 enum hal_tx_mcast_mlo_reinject_notify config) 3581 { 3582 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3583 uint32_t reg_addr, reg_val = 0; 3584 uint32_t val = 0; 3585 3586 reg_addr = HWIO_TCL_R0_CMN_CONFIG_ADDR(MAC_TCL_REG_REG_BASE); 3587 val = HAL_REG_READ(hal_soc, reg_addr); 3588 3589 /* reset the corresponding bits in register */ 3590 val &= (~(HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_BMSK)); 3591 3592 /* set config value */ 3593 reg_val = val | (config << HWIO_TCL_R0_CMN_CONFIG_MCAST_CMN_PN_SN_MLO_REINJECT_ENABLE_SHFT); 3594 3595 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 3596 } 3597 #else 3598 static inline void 3599 hal_tx_mcast_mlo_reinject_routing_set_generic_be( 3600 hal_soc_handle_t hal_soc_hdl, 3601 enum hal_tx_mcast_mlo_reinject_notify config) 3602 { 3603 } 3604 #endif 3605 3606 /** 3607 * hal_get_ba_aging_timeout_be_generic() - Get BA Aging timeout 3608 * 3609 * @hal_soc_hdl: Opaque HAL SOC handle 3610 * @ac: Access category 3611 * @value: window size to get 3612 */ 3613 3614 static inline 3615 void hal_get_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3616 uint8_t ac, uint32_t *value) 3617 { 3618 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3619 3620 switch (ac) { 3621 case WME_AC_BE: 3622 *value = HAL_REG_READ(soc, 3623 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3624 REO_REG_REG_BASE)) / 1000; 3625 break; 3626 case WME_AC_BK: 3627 *value = HAL_REG_READ(soc, 3628 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3629 REO_REG_REG_BASE)) / 1000; 3630 break; 3631 case WME_AC_VI: 3632 *value = HAL_REG_READ(soc, 3633 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3634 REO_REG_REG_BASE)) / 1000; 3635 break; 3636 case WME_AC_VO: 3637 *value = HAL_REG_READ(soc, 3638 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3639 REO_REG_REG_BASE)) / 1000; 3640 break; 3641 default: 3642 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3643 "Invalid AC: %d\n", ac); 3644 } 3645 } 3646 3647 /** 3648 * hal_setup_link_idle_list_generic_be - Setup scattered idle list using the 3649 * buffer list provided 3650 * 3651 * @soc: Opaque HAL SOC handle 3652 * @scatter_bufs_base_paddr: Array of physical base addresses 3653 * @scatter_bufs_base_vaddr: Array of virtual base addresses 3654 * @num_scatter_bufs: Number of scatter buffers in the above lists 3655 * @scatter_buf_size: Size of each scatter buffer 3656 * @last_buf_end_offset: Offset to the last entry 3657 * @num_entries: Total entries of all scatter bufs 3658 * 3659 * Return: None 3660 */ 3661 static inline void 3662 hal_setup_link_idle_list_generic_be(struct hal_soc *soc, 3663 qdf_dma_addr_t scatter_bufs_base_paddr[], 3664 void *scatter_bufs_base_vaddr[], 3665 uint32_t num_scatter_bufs, 3666 uint32_t scatter_buf_size, 3667 uint32_t last_buf_end_offset, 3668 uint32_t num_entries) 3669 { 3670 int i; 3671 uint32_t *prev_buf_link_ptr = NULL; 3672 uint32_t reg_scatter_buf_size, reg_tot_scatter_buf_size; 3673 uint32_t val; 3674 3675 /* Link the scatter buffers */ 3676 for (i = 0; i < num_scatter_bufs; i++) { 3677 if (i > 0) { 3678 prev_buf_link_ptr[0] = 3679 scatter_bufs_base_paddr[i] & 0xffffffff; 3680 prev_buf_link_ptr[1] = HAL_SM( 3681 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3682 BASE_ADDRESS_39_32, 3683 ((uint64_t)(scatter_bufs_base_paddr[i]) 3684 >> 32)) | HAL_SM( 3685 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3686 ADDRESS_MATCH_TAG, 3687 ADDRESS_MATCH_TAG_VAL); 3688 } 3689 prev_buf_link_ptr = (uint32_t *)(scatter_bufs_base_vaddr[i] + 3690 scatter_buf_size - WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE); 3691 } 3692 3693 /* TBD: Register programming partly based on MLD & the rest based on 3694 * inputs from HW team. Not complete yet. 3695 */ 3696 3697 reg_scatter_buf_size = (scatter_buf_size - 3698 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) / 64; 3699 reg_tot_scatter_buf_size = ((scatter_buf_size - 3700 WBM_IDLE_SCATTER_BUF_NEXT_PTR_SIZE) * num_scatter_bufs) / 64; 3701 3702 HAL_REG_WRITE(soc, 3703 HWIO_WBM_R0_IDLE_LIST_CONTROL_ADDR( 3704 WBM_REG_REG_BASE), 3705 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, SCATTER_BUFFER_SIZE, 3706 reg_scatter_buf_size) | 3707 HAL_SM(HWIO_WBM_R0_IDLE_LIST_CONTROL, LINK_DESC_IDLE_LIST_MODE, 3708 0x1)); 3709 3710 HAL_REG_WRITE(soc, 3711 HWIO_WBM_R0_IDLE_LIST_SIZE_ADDR( 3712 WBM_REG_REG_BASE), 3713 HAL_SM(HWIO_WBM_R0_IDLE_LIST_SIZE, 3714 SCATTER_RING_SIZE_OF_IDLE_LINK_DESC_LIST, 3715 reg_tot_scatter_buf_size)); 3716 3717 HAL_REG_WRITE(soc, 3718 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_LSB_ADDR( 3719 WBM_REG_REG_BASE), 3720 scatter_bufs_base_paddr[0] & 0xffffffff); 3721 3722 HAL_REG_WRITE(soc, 3723 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3724 WBM_REG_REG_BASE), 3725 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 32) & 3726 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_BASE_ADDRESS_39_32_BMSK); 3727 3728 HAL_REG_WRITE(soc, 3729 HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB_ADDR( 3730 WBM_REG_REG_BASE), 3731 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3732 BASE_ADDRESS_39_32, ((uint64_t)(scatter_bufs_base_paddr[0]) 3733 >> 32)) | 3734 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_LIST_BASE_MSB, 3735 ADDRESS_MATCH_TAG, ADDRESS_MATCH_TAG_VAL)); 3736 3737 /* ADDRESS_MATCH_TAG field in the above register is expected to match 3738 * with the upper bits of link pointer. The above write sets this field 3739 * to zero and we are also setting the upper bits of link pointers to 3740 * zero while setting up the link list of scatter buffers above 3741 */ 3742 3743 /* Setup head and tail pointers for the idle list */ 3744 HAL_REG_WRITE(soc, 3745 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3746 WBM_REG_REG_BASE), 3747 scatter_bufs_base_paddr[num_scatter_bufs - 1] & 0xffffffff); 3748 HAL_REG_WRITE(soc, 3749 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1_ADDR( 3750 WBM_REG_REG_BASE), 3751 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3752 BUFFER_ADDRESS_39_32, 3753 ((uint64_t)(scatter_bufs_base_paddr[num_scatter_bufs - 1]) 3754 >> 32)) | 3755 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX1, 3756 HEAD_POINTER_OFFSET, last_buf_end_offset >> 2)); 3757 3758 HAL_REG_WRITE(soc, 3759 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HEAD_INFO_IX0_ADDR( 3760 WBM_REG_REG_BASE), 3761 scatter_bufs_base_paddr[0] & 0xffffffff); 3762 3763 HAL_REG_WRITE(soc, 3764 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX0_ADDR( 3765 WBM_REG_REG_BASE), 3766 scatter_bufs_base_paddr[0] & 0xffffffff); 3767 HAL_REG_WRITE(soc, 3768 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1_ADDR( 3769 WBM_REG_REG_BASE), 3770 HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3771 BUFFER_ADDRESS_39_32, 3772 ((uint64_t)(scatter_bufs_base_paddr[0]) >> 3773 32)) | HAL_SM(HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_TAIL_INFO_IX1, 3774 TAIL_POINTER_OFFSET, 0)); 3775 3776 HAL_REG_WRITE(soc, 3777 HWIO_WBM_R0_SCATTERED_LINK_DESC_PTR_HP_ADDR( 3778 WBM_REG_REG_BASE), 3779 2 * num_entries); 3780 3781 /* Set RING_ID_DISABLE */ 3782 val = HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, RING_ID_DISABLE, 1); 3783 3784 /* 3785 * SRNG_ENABLE bit is not available in HWK v1 (QCA8074v1). Hence 3786 * check the presence of the bit before toggling it. 3787 */ 3788 #ifdef HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_SRNG_ENABLE_BMSK 3789 val |= HAL_SM(HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC, SRNG_ENABLE, 1); 3790 #endif 3791 HAL_REG_WRITE(soc, 3792 HWIO_WBM_R0_WBM_IDLE_LINK_RING_MISC_ADDR(WBM_REG_REG_BASE), 3793 val); 3794 } 3795 3796 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3797 #define HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15 0x8000 3798 #endif 3799 3800 /** 3801 * hal_cookie_conversion_reg_cfg_generic_be() - set cookie conversion relevant register 3802 * for REO/WBM 3803 * @hal_soc_hdl: HAL soc handle 3804 * @cc_cfg: structure pointer for HW cookie conversion configuration 3805 * 3806 * Return: None 3807 */ 3808 static inline 3809 void hal_cookie_conversion_reg_cfg_generic_be(hal_soc_handle_t hal_soc_hdl, 3810 struct hal_hw_cc_config *cc_cfg) 3811 { 3812 uint32_t reg_addr, reg_val = 0; 3813 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3814 3815 /* REO CFG */ 3816 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG0_ADDR(REO_REG_REG_BASE); 3817 reg_val = cc_cfg->lut_base_addr_31_0; 3818 HAL_REG_WRITE(soc, reg_addr, reg_val); 3819 3820 reg_addr = HWIO_REO_R0_SW_COOKIE_CFG1_ADDR(REO_REG_REG_BASE); 3821 reg_val = 0; 3822 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3823 SW_COOKIE_CONVERT_GLOBAL_ENABLE, 3824 cc_cfg->cc_global_en); 3825 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3826 SW_COOKIE_CONVERT_ENABLE, 3827 cc_cfg->cc_global_en); 3828 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3829 PAGE_ALIGNMENT, 3830 cc_cfg->page_4k_align); 3831 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3832 COOKIE_OFFSET_MSB, 3833 cc_cfg->cookie_offset_msb); 3834 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3835 COOKIE_PAGE_MSB, 3836 cc_cfg->cookie_page_msb); 3837 reg_val |= HAL_SM(HWIO_REO_R0_SW_COOKIE_CFG1, 3838 CMEM_LUT_BASE_ADDR_39_32, 3839 cc_cfg->lut_base_addr_39_32); 3840 HAL_REG_WRITE(soc, reg_addr, reg_val); 3841 3842 /* WBM CFG */ 3843 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG0_ADDR(WBM_REG_REG_BASE); 3844 reg_val = cc_cfg->lut_base_addr_31_0; 3845 HAL_REG_WRITE(soc, reg_addr, reg_val); 3846 3847 reg_addr = HWIO_WBM_R0_SW_COOKIE_CFG1_ADDR(WBM_REG_REG_BASE); 3848 reg_val = 0; 3849 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3850 PAGE_ALIGNMENT, 3851 cc_cfg->page_4k_align); 3852 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3853 COOKIE_OFFSET_MSB, 3854 cc_cfg->cookie_offset_msb); 3855 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3856 COOKIE_PAGE_MSB, 3857 cc_cfg->cookie_page_msb); 3858 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CFG1, 3859 CMEM_LUT_BASE_ADDR_39_32, 3860 cc_cfg->lut_base_addr_39_32); 3861 HAL_REG_WRITE(soc, reg_addr, reg_val); 3862 3863 /* 3864 * WCSS_UMAC_WBM_R0_SW_COOKIE_CONVERT_CFG default value is 0x1FE, 3865 */ 3866 reg_addr = HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG_ADDR(WBM_REG_REG_BASE); 3867 reg_val = 0; 3868 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3869 WBM_COOKIE_CONV_GLOBAL_ENABLE, 3870 cc_cfg->cc_global_en); 3871 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3872 WBM2SW6_COOKIE_CONVERSION_EN, 3873 cc_cfg->wbm2sw6_cc_en); 3874 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3875 WBM2SW5_COOKIE_CONVERSION_EN, 3876 cc_cfg->wbm2sw5_cc_en); 3877 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3878 WBM2SW4_COOKIE_CONVERSION_EN, 3879 cc_cfg->wbm2sw4_cc_en); 3880 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3881 WBM2SW3_COOKIE_CONVERSION_EN, 3882 cc_cfg->wbm2sw3_cc_en); 3883 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3884 WBM2SW2_COOKIE_CONVERSION_EN, 3885 cc_cfg->wbm2sw2_cc_en); 3886 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3887 WBM2SW1_COOKIE_CONVERSION_EN, 3888 cc_cfg->wbm2sw1_cc_en); 3889 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3890 WBM2SW0_COOKIE_CONVERSION_EN, 3891 cc_cfg->wbm2sw0_cc_en); 3892 reg_val |= HAL_SM(HWIO_WBM_R0_SW_COOKIE_CONVERT_CFG, 3893 WBM2FW_COOKIE_CONVERSION_EN, 3894 cc_cfg->wbm2fw_cc_en); 3895 HAL_REG_WRITE(soc, reg_addr, reg_val); 3896 3897 #ifdef HWIO_WBM_R0_WBM_CFG_2_COOKIE_DEBUG_SEL_BMSK 3898 reg_addr = HWIO_WBM_R0_WBM_CFG_2_ADDR(WBM_REG_REG_BASE); 3899 reg_val = 0; 3900 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3901 COOKIE_DEBUG_SEL, 3902 cc_cfg->cc_global_en); 3903 3904 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3905 COOKIE_CONV_INDICATION_EN, 3906 cc_cfg->cc_global_en); 3907 3908 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3909 ERROR_PATH_COOKIE_CONV_EN, 3910 cc_cfg->error_path_cookie_conv_en); 3911 3912 reg_val |= HAL_SM(HWIO_WBM_R0_WBM_CFG_2, 3913 RELEASE_PATH_COOKIE_CONV_EN, 3914 cc_cfg->release_path_cookie_conv_en); 3915 3916 HAL_REG_WRITE(soc, reg_addr, reg_val); 3917 #endif 3918 #ifdef DP_HW_COOKIE_CONVERT_EXCEPTION 3919 /* 3920 * To enable indication for HW cookie conversion done or not for 3921 * WBM, WCSS_UMAC_WBM_R0_MISC_CONTROL spare_control field 15th 3922 * bit spare_control[15] should be set. 3923 */ 3924 reg_addr = HWIO_WBM_R0_MISC_CONTROL_ADDR(WBM_REG_REG_BASE); 3925 reg_val = HAL_REG_READ(soc, reg_addr); 3926 reg_val |= HAL_SM(HWIO_WCSS_UMAC_WBM_R0_MISC_CONTROL, 3927 SPARE_CONTROL, 3928 HAL_WBM_MISC_CONTROL_SPARE_CONTROL_FIELD_BIT15); 3929 HAL_REG_WRITE(soc, reg_addr, reg_val); 3930 #endif 3931 } 3932 3933 /** 3934 * hal_set_ba_aging_timeout_be_generic() - Set BA Aging timeout 3935 * @hal_soc_hdl: Opaque HAL SOC handle 3936 * @ac: Access category 3937 * ac: 0 - Background, 1 - Best Effort, 2 - Video, 3 - Voice 3938 * @value: Input value to set 3939 */ 3940 static inline 3941 void hal_set_ba_aging_timeout_be_generic(hal_soc_handle_t hal_soc_hdl, 3942 uint8_t ac, uint32_t value) 3943 { 3944 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl; 3945 3946 switch (ac) { 3947 case WME_AC_BE: 3948 HAL_REG_WRITE(soc, 3949 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR( 3950 REO_REG_REG_BASE), 3951 value * 1000); 3952 break; 3953 case WME_AC_BK: 3954 HAL_REG_WRITE(soc, 3955 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR( 3956 REO_REG_REG_BASE), 3957 value * 1000); 3958 break; 3959 case WME_AC_VI: 3960 HAL_REG_WRITE(soc, 3961 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR( 3962 REO_REG_REG_BASE), 3963 value * 1000); 3964 break; 3965 case WME_AC_VO: 3966 HAL_REG_WRITE(soc, 3967 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR( 3968 REO_REG_REG_BASE), 3969 value * 1000); 3970 break; 3971 default: 3972 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR, 3973 "Invalid AC: %d\n", ac); 3974 } 3975 } 3976 3977 /** 3978 * hal_tx_populate_bank_register_be() - populate the bank register with 3979 * the software configs. 3980 * @hal_soc_hdl: HAL soc handle 3981 * @config: bank config 3982 * @bank_id: bank id to be configured 3983 * 3984 * Returns: None 3985 */ 3986 #ifdef HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT 3987 static inline void 3988 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 3989 union hal_tx_bank_config *config, 3990 uint8_t bank_id) 3991 { 3992 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 3993 uint32_t reg_addr, reg_val = 0; 3994 3995 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 3996 bank_id); 3997 3998 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 3999 reg_val |= (config->encap_type << 4000 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 4001 reg_val |= (config->encrypt_type << 4002 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 4003 reg_val |= (config->src_buffer_swap << 4004 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 4005 reg_val |= (config->link_meta_swap << 4006 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 4007 reg_val |= (config->index_lookup_enable << 4008 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 4009 reg_val |= (config->addrx_en << 4010 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 4011 reg_val |= (config->addry_en << 4012 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 4013 reg_val |= (config->mesh_enable << 4014 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 4015 reg_val |= (config->vdev_id_check_en << 4016 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 4017 reg_val |= (config->pmac_id << 4018 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 4019 reg_val |= (config->mcast_pkt_ctrl << 4020 HWIO_TCL_R0_SW_CONFIG_BANK_n_MCAST_PACKET_CTRL_SHFT); 4021 4022 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 4023 } 4024 #else 4025 static inline void 4026 hal_tx_populate_bank_register_be(hal_soc_handle_t hal_soc_hdl, 4027 union hal_tx_bank_config *config, 4028 uint8_t bank_id) 4029 { 4030 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 4031 uint32_t reg_addr, reg_val = 0; 4032 4033 reg_addr = HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDR(MAC_TCL_REG_REG_BASE, 4034 bank_id); 4035 4036 reg_val |= (config->epd << HWIO_TCL_R0_SW_CONFIG_BANK_n_EPD_SHFT); 4037 reg_val |= (config->encap_type << 4038 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCAP_TYPE_SHFT); 4039 reg_val |= (config->encrypt_type << 4040 HWIO_TCL_R0_SW_CONFIG_BANK_n_ENCRYPT_TYPE_SHFT); 4041 reg_val |= (config->src_buffer_swap << 4042 HWIO_TCL_R0_SW_CONFIG_BANK_n_SRC_BUFFER_SWAP_SHFT); 4043 reg_val |= (config->link_meta_swap << 4044 HWIO_TCL_R0_SW_CONFIG_BANK_n_LINK_META_SWAP_SHFT); 4045 reg_val |= (config->index_lookup_enable << 4046 HWIO_TCL_R0_SW_CONFIG_BANK_n_INDEX_LOOKUP_ENABLE_SHFT); 4047 reg_val |= (config->addrx_en << 4048 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRX_EN_SHFT); 4049 reg_val |= (config->addry_en << 4050 HWIO_TCL_R0_SW_CONFIG_BANK_n_ADDRY_EN_SHFT); 4051 reg_val |= (config->mesh_enable << 4052 HWIO_TCL_R0_SW_CONFIG_BANK_n_MESH_ENABLE_SHFT); 4053 reg_val |= (config->vdev_id_check_en << 4054 HWIO_TCL_R0_SW_CONFIG_BANK_n_VDEV_ID_CHECK_EN_SHFT); 4055 reg_val |= (config->pmac_id << 4056 HWIO_TCL_R0_SW_CONFIG_BANK_n_PMAC_ID_SHFT); 4057 reg_val |= (config->dscp_tid_map_id << 4058 HWIO_TCL_R0_SW_CONFIG_BANK_n_DSCP_TID_TABLE_NUM_SHFT); 4059 4060 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 4061 } 4062 #endif 4063 4064 4065 #ifdef HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_VAL_SHFT 4066 4067 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id) (vdev_id >> 0x4) 4068 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id) (vdev_id & 0xF) 4069 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK 0x3 4070 #define HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT 0x2 4071 4072 /** 4073 * hal_tx_vdev_mcast_ctrl_set_be() - set mcast_ctrl value 4074 * @hal_soc_hdl: HAL SoC context 4075 * @vdev_id: vdev identifier 4076 * @mcast_ctrl_val: mcast ctrl value for this VAP 4077 * 4078 * Return: void 4079 */ 4080 static inline void 4081 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 4082 uint8_t vdev_id, uint8_t mcast_ctrl_val) 4083 { 4084 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 4085 uint32_t reg_addr, reg_val = 0; 4086 uint32_t val; 4087 uint8_t reg_idx = HAL_TCL_VDEV_MCAST_PACKET_CTRL_REG_ID(vdev_id); 4088 uint8_t index_in_reg = 4089 HAL_TCL_VDEV_MCAST_PACKET_CTRL_INDEX_IN_REG(vdev_id); 4090 4091 reg_addr = 4092 HWIO_TCL_R0_VDEV_MCAST_PACKET_CTRL_MAP_n_ADDR(MAC_TCL_REG_REG_BASE, 4093 reg_idx); 4094 4095 val = HAL_REG_READ(hal_soc, reg_addr); 4096 4097 /* mask out other stored value */ 4098 val &= (~(HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK << 4099 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg))); 4100 4101 reg_val = val | 4102 ((HAL_TCL_VDEV_MCAST_PACKET_CTRL_MASK & mcast_ctrl_val) << 4103 (HAL_TCL_VDEV_MCAST_PACKET_CTRL_SHIFT * index_in_reg)); 4104 4105 HAL_REG_WRITE(hal_soc, reg_addr, reg_val); 4106 } 4107 #else 4108 static inline void 4109 hal_tx_vdev_mcast_ctrl_set_be(hal_soc_handle_t hal_soc_hdl, 4110 uint8_t vdev_id, uint8_t mcast_ctrl_val) 4111 { 4112 } 4113 #endif 4114 4115 #endif /* _HAL_BE_GENERIC_API_H_ */ 4116