1 /*
2  * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3  * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4  *
5  * Permission to use, copy, modify, and/or distribute this software for any
6  * purpose with or without fee is hereby granted, provided that the above
7  * copyright notice and this permission notice appear in all copies.
8  *
9  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16  */
17 #include "hal_9224.h"
18 
19 struct hal_hw_srng_config hw_srng_table_9224v2[] = {
20 	/* TODO: max_rings can populated by querying HW capabilities */
21 	{ /* REO_DST */
22 		.start_ring_id = HAL_SRNG_REO2SW1,
23 		.max_rings = 8,
24 		.entry_size = sizeof(struct reo_destination_ring) >> 2,
25 		.lmac_ring = FALSE,
26 		.ring_dir = HAL_SRNG_DST_RING,
27 		.reg_start = {
28 			HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
29 				REO_REG_REG_BASE),
30 			HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
31 				REO_REG_REG_BASE)
32 		},
33 		.reg_size = {
34 			HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
35 				HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
36 			HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
37 				HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
38 		},
39 		.max_size =
40 			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
41 			HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
42 	},
43 	{ /* REO_EXCEPTION */
44 		/* Designating REO2SW0 ring as exception ring. This ring is
45 		 * similar to other REO2SW rings though it is named as REO2SW0.
46 		 * Any of theREO2SW rings can be used as exception ring.
47 		 */
48 		.start_ring_id = HAL_SRNG_REO2SW0,
49 		.max_rings = 1,
50 		.entry_size = sizeof(struct reo_destination_ring) >> 2,
51 		.lmac_ring = FALSE,
52 		.ring_dir = HAL_SRNG_DST_RING,
53 		.reg_start = {
54 			HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
55 				REO_REG_REG_BASE),
56 			HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
57 				REO_REG_REG_BASE)
58 		},
59 		/* Single ring - provide ring size if multiple rings of this
60 		 * type are supported
61 		 */
62 		.reg_size = {},
63 		.max_size =
64 			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
65 			HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
66 	},
67 	{ /* REO_REINJECT */
68 		.start_ring_id = HAL_SRNG_SW2REO,
69 		.max_rings = 4,
70 		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
71 		.lmac_ring = FALSE,
72 		.ring_dir = HAL_SRNG_SRC_RING,
73 		.reg_start = {
74 			HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
75 				REO_REG_REG_BASE),
76 			HWIO_REO_R2_SW2REO_RING_HP_ADDR(
77 				REO_REG_REG_BASE)
78 		},
79 		/* Single ring - provide ring size if multiple rings of this
80 		 * type are supported
81 		 */
82 		.reg_size = {
83 			HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
84 				HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
85 			HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
86 				HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
87 		},
88 		.max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
89 				HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
90 	},
91 	{ /* REO_CMD */
92 		.start_ring_id = HAL_SRNG_REO_CMD,
93 		.max_rings = 1,
94 		.entry_size = (sizeof(struct tlv_32_hdr) +
95 			sizeof(struct reo_get_queue_stats)) >> 2,
96 		.lmac_ring = FALSE,
97 		.ring_dir = HAL_SRNG_SRC_RING,
98 		.reg_start = {
99 			HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
100 				REO_REG_REG_BASE),
101 			HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
102 				REO_REG_REG_BASE),
103 		},
104 		/* Single ring - provide ring size if multiple rings of this
105 		 * type are supported
106 		 */
107 		.reg_size = {},
108 		.max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
109 			HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
110 	},
111 	{ /* REO_STATUS */
112 		.start_ring_id = HAL_SRNG_REO_STATUS,
113 		.max_rings = 1,
114 		.entry_size = (sizeof(struct tlv_32_hdr) +
115 			sizeof(struct reo_get_queue_stats_status)) >> 2,
116 		.lmac_ring = FALSE,
117 		.ring_dir = HAL_SRNG_DST_RING,
118 		.reg_start = {
119 			HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
120 				REO_REG_REG_BASE),
121 			HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
122 				REO_REG_REG_BASE),
123 		},
124 		/* Single ring - provide ring size if multiple rings of this
125 		 * type are supported
126 		 */
127 		.reg_size = {},
128 		.max_size =
129 		HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
130 			HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
131 	},
132 	{ /* TCL_DATA */
133 		.start_ring_id = HAL_SRNG_SW2TCL1,
134 		.max_rings = 6,
135 		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
136 		.lmac_ring = FALSE,
137 		.ring_dir = HAL_SRNG_SRC_RING,
138 		.reg_start = {
139 			HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
140 				MAC_TCL_REG_REG_BASE),
141 			HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
142 				MAC_TCL_REG_REG_BASE),
143 		},
144 		.reg_size = {
145 			HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
146 				HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
147 			HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
148 				HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
149 		},
150 		.max_size =
151 			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
152 			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
153 	},
154 	{ /* TCL_CMD/CREDIT */
155 	  /* qca8074v2 and qcn9224 uses this ring for data commands */
156 		.start_ring_id = HAL_SRNG_SW2TCL_CMD,
157 		.max_rings = 1,
158 		.entry_size = sizeof(struct tcl_data_cmd) >> 2,
159 		.lmac_ring =  FALSE,
160 		.ring_dir = HAL_SRNG_SRC_RING,
161 		.reg_start = {
162 			HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
163 				MAC_TCL_REG_REG_BASE),
164 			HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
165 				MAC_TCL_REG_REG_BASE),
166 		},
167 		/* Single ring - provide ring size if multiple rings of this
168 		 * type are supported
169 		 */
170 		.reg_size = {},
171 		.max_size =
172 		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
173 		HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
174 	},
175 	{ /* TCL_STATUS */
176 		.start_ring_id = HAL_SRNG_TCL_STATUS,
177 		.max_rings = 1,
178 		.entry_size = (sizeof(struct tlv_32_hdr) +
179 			sizeof(struct tcl_status_ring)) >> 2,
180 		.lmac_ring = FALSE,
181 		.ring_dir = HAL_SRNG_DST_RING,
182 		.reg_start = {
183 			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
184 				MAC_TCL_REG_REG_BASE),
185 			HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
186 				MAC_TCL_REG_REG_BASE),
187 		},
188 		/* Single ring - provide ring size if multiple rings of this
189 		 * type are supported
190 		 */
191 		.reg_size = {},
192 		.max_size =
193 			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
194 			HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
195 	},
196 	{ /* CE_SRC */
197 		.start_ring_id = HAL_SRNG_CE_0_SRC,
198 		.max_rings = 16,
199 		.entry_size = sizeof(struct ce_src_desc) >> 2,
200 		.lmac_ring = FALSE,
201 		.ring_dir = HAL_SRNG_SRC_RING,
202 		.reg_start = {
203 		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
204 				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
205 		HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
206 				WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
207 		},
208 		.reg_size = {
209 		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
210 		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
211 		WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
212 		WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
213 		},
214 		.max_size =
215 		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
216 		HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
217 	},
218 	{ /* CE_DST */
219 		.start_ring_id = HAL_SRNG_CE_0_DST,
220 		.max_rings = 16,
221 		.entry_size = 8 >> 2,
222 		/*TODO: entry_size above should actually be
223 		 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
224 		 * of struct ce_dst_desc in HW header files
225 		 */
226 		.lmac_ring = FALSE,
227 		.ring_dir = HAL_SRNG_SRC_RING,
228 		.reg_start = {
229 		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
230 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
231 		HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
232 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
233 		},
234 		.reg_size = {
235 		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
236 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
237 		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
238 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
239 		},
240 		.max_size =
241 		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
242 		HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
243 	},
244 	{ /* CE_DST_STATUS */
245 		.start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
246 		.max_rings = 16,
247 		.entry_size = sizeof(struct ce_stat_desc) >> 2,
248 		.lmac_ring = FALSE,
249 		.ring_dir = HAL_SRNG_DST_RING,
250 		.reg_start = {
251 		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
252 				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
253 		HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
254 				WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
255 		},
256 		/* TODO: check destination status ring registers */
257 		.reg_size = {
258 		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
259 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
260 		WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
261 		WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
262 		},
263 		.max_size =
264 	HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
265 		HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
266 	},
267 	{ /* WBM_IDLE_LINK */
268 		.start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
269 		.max_rings = 1,
270 		.entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
271 		.lmac_ring = FALSE,
272 		.ring_dir = HAL_SRNG_SRC_RING,
273 		.reg_start = {
274 		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
275 		HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
276 		},
277 		/* Single ring - provide ring size if multiple rings of this
278 		 * type are supported
279 		 */
280 		.reg_size = {},
281 		.max_size =
282 		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
283 		HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
284 	},
285 	{ /* SW2WBM_RELEASE */
286 		.start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
287 		.max_rings = 2,
288 		.entry_size = sizeof(struct wbm_release_ring) >> 2,
289 		.lmac_ring = FALSE,
290 		.ring_dir = HAL_SRNG_SRC_RING,
291 		.reg_start = {
292 		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
293 		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
294 		},
295 		.reg_size = {
296 		HWIO_WBM_R0_SW1_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE) -
297 		HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
298 		HWIO_WBM_R2_SW1_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE) -
299 		HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE)
300 		},
301 		.max_size =
302 		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
303 		HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
304 	},
305 	{ /* WBM2SW_RELEASE */
306 		.start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
307 		.max_rings = 8,
308 		.entry_size = sizeof(struct wbm_release_ring) >> 2,
309 		.lmac_ring = FALSE,
310 		.ring_dir = HAL_SRNG_DST_RING,
311 		.reg_start = {
312 		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
313 				WBM_REG_REG_BASE),
314 		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
315 				WBM_REG_REG_BASE),
316 		},
317 		.reg_size = {
318 		HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
319 				WBM_REG_REG_BASE) -
320 		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
321 				WBM_REG_REG_BASE),
322 		HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
323 				WBM_REG_REG_BASE) -
324 		HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
325 				WBM_REG_REG_BASE),
326 		},
327 		.max_size =
328 		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
329 		HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
330 	},
331 	{ /* RXDMA_BUF */
332 		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
333 #ifdef IPA_OFFLOAD
334 #ifdef IPA_WDI3_VLAN_SUPPORT
335 		.max_rings = 4,
336 #else
337 		.max_rings = 3,
338 #endif
339 #else
340 		.max_rings = 3,
341 #endif
342 		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
343 		.lmac_ring = TRUE,
344 		.ring_dir = HAL_SRNG_SRC_RING,
345 		/* reg_start is not set because LMAC rings are not accessed
346 		 * from host
347 		 */
348 		.reg_start = {},
349 		.reg_size = {},
350 		.max_size = HAL_RXDMA_MAX_RING_SIZE,
351 	},
352 	{ /* RXDMA_DST */
353 		.start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
354 		.max_rings = 0,
355 		.entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
356 		.lmac_ring =  TRUE,
357 		.ring_dir = HAL_SRNG_DST_RING,
358 		/* reg_start is not set because LMAC rings are not accessed
359 		 * from host
360 		 */
361 		.reg_start = {},
362 		.reg_size = {},
363 		.max_size = HAL_RXDMA_MAX_RING_SIZE,
364 	},
365 #ifdef WLAN_PKT_CAPTURE_RX_2_0
366 	{ /* RXDMA_MONITOR_BUF */
367 		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
368 		.max_rings = 1,
369 		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
370 		.lmac_ring = TRUE,
371 		.ring_dir = HAL_SRNG_SRC_RING,
372 		/* reg_start is not set because LMAC rings are not accessed
373 		 * from host
374 		 */
375 		.reg_start = {},
376 		.reg_size = {},
377 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
378 	},
379 #else
380 	{},
381 #endif
382 	{ /* RXDMA_MONITOR_STATUS */
383 		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
384 		.max_rings = 0,
385 		.entry_size = sizeof(struct wbm_buffer_ring) >> 2,
386 		.lmac_ring = TRUE,
387 		.ring_dir = HAL_SRNG_SRC_RING,
388 		/* reg_start is not set because LMAC rings are not accessed
389 		 * from host
390 		 */
391 		.reg_start = {},
392 		.reg_size = {},
393 		.max_size = HAL_RXDMA_MAX_RING_SIZE,
394 	},
395 #ifdef WLAN_PKT_CAPTURE_RX_2_0
396 	{ /* RXDMA_MONITOR_DST */
397 		.start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
398 		.max_rings = 2,
399 		.entry_size = sizeof(struct mon_destination_ring) >> 2,
400 		.lmac_ring = TRUE,
401 		.ring_dir = HAL_SRNG_DST_RING,
402 		/* reg_start is not set because LMAC rings are not accessed
403 		 * from host
404 		 */
405 		.reg_start = {},
406 		.reg_size = {},
407 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
408 	},
409 #else
410 	{},
411 #endif
412 	{ /* RXDMA_MONITOR_DESC */
413 		.start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
414 		.max_rings = 0,
415 		.entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
416 		.lmac_ring = TRUE,
417 		.ring_dir = HAL_SRNG_DST_RING,
418 		/* reg_start is not set because LMAC rings are not accessed
419 		 * from host
420 		 */
421 		.reg_start = {},
422 		.reg_size = {},
423 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
424 	},
425 
426 	{ /* DIR_BUF_RX_DMA_SRC */
427 		.start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
428 		/* one ring for spectral, one ring for cfr and
429 		 * another one ring for txbf cv upload
430 		 */
431 		.max_rings = 3,
432 		.entry_size = 2,
433 		.lmac_ring = TRUE,
434 		.ring_dir = HAL_SRNG_SRC_RING,
435 		/* reg_start is not set because LMAC rings are not accessed
436 		 * from host
437 		 */
438 		.reg_start = {},
439 		.reg_size = {},
440 		.max_size = HAL_RXDMA_MAX_RING_SIZE,
441 	},
442 #ifdef WLAN_FEATURE_CIF_CFR
443 	{ /* WIFI_POS_SRC */
444 		.start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
445 		.max_rings = 1,
446 		.entry_size = sizeof(wmi_oem_dma_buf_release_entry)  >> 2,
447 		.lmac_ring = TRUE,
448 		.ring_dir = HAL_SRNG_SRC_RING,
449 		/* reg_start is not set because LMAC rings are not accessed
450 		 * from host
451 		 */
452 		.reg_start = {},
453 		.reg_size = {},
454 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
455 	},
456 #endif
457 	{ /* REO2PPE */
458 		.start_ring_id = HAL_SRNG_REO2PPE,
459 		.max_rings = 1,
460 		.entry_size = sizeof(struct reo_destination_ring) >> 2,
461 		.lmac_ring = FALSE,
462 		.ring_dir = HAL_SRNG_DST_RING,
463 		.reg_start = {
464 			HWIO_REO_R0_REO2PPE_RING_BASE_LSB_ADDR(
465 				REO_REG_REG_BASE),
466 			HWIO_REO_R2_REO2PPE_RING_HP_ADDR(
467 				REO_REG_REG_BASE),
468 		},
469 		/* Single ring - provide ring size if multiple rings of this
470 		 * type are supported
471 		 */
472 		.reg_size = {},
473 		.max_size =
474 		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_BMSK >>
475 		HWIO_REO_R0_REO2PPE_RING_BASE_LSB_RING_BASE_ADDR_LSB_SHFT,
476 	},
477 	{ /* PPE2TCL */
478 		.start_ring_id = HAL_SRNG_PPE2TCL1,
479 		.max_rings = 1,
480 		.entry_size = sizeof(struct tcl_entrance_from_ppe_ring) >> 2,
481 		.lmac_ring = FALSE,
482 		.ring_dir = HAL_SRNG_SRC_RING,
483 		.reg_start = {
484 			HWIO_TCL_R0_PPE2TCL1_RING_BASE_LSB_ADDR(
485 				MAC_TCL_REG_REG_BASE),
486 			HWIO_TCL_R2_PPE2TCL1_RING_HP_ADDR(
487 				MAC_TCL_REG_REG_BASE),
488 		},
489 		.reg_size = {},
490 		.max_size =
491 			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
492 			HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
493 	},
494 	{ /* PPE_RELEASE */
495 		.start_ring_id = HAL_SRNG_WBM_PPE_RELEASE,
496 		.max_rings = 1,
497 		.entry_size = sizeof(struct wbm_release_ring) >> 2,
498 		.lmac_ring = FALSE,
499 		.ring_dir = HAL_SRNG_SRC_RING,
500 		.reg_start = {
501 		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
502 		HWIO_WBM_R2_PPE_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
503 		},
504 		.reg_size = {},
505 		.max_size =
506 		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
507 		HWIO_WBM_R0_PPE_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
508 	},
509 #ifdef WLAN_PKT_CAPTURE_TX_2_0
510 	{ /* TX_MONITOR_BUF */
511 		.start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
512 		.max_rings = 1,
513 		.entry_size = sizeof(struct mon_ingress_ring) >> 2,
514 		.lmac_ring = TRUE,
515 		.ring_dir = HAL_SRNG_SRC_RING,
516 		/* reg_start is not set because LMAC rings are not accessed
517 		 * from host
518 		 */
519 		.reg_start = {},
520 		.reg_size = {},
521 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
522 	},
523 	{ /* TX_MONITOR_DST */
524 		.start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
525 		.max_rings = 2,
526 		.entry_size = sizeof(struct mon_destination_ring) >> 2,
527 		.lmac_ring = TRUE,
528 		.ring_dir = HAL_SRNG_DST_RING,
529 		/* reg_start is not set because LMAC rings are not accessed
530 		 * from host
531 		 */
532 		.reg_start = {},
533 		.reg_size = {},
534 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
535 	},
536 #else
537 	{},
538 	{},
539 #endif
540 	{ /* SW2RXDMA */
541 		.start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
542 		.max_rings = 3,
543 		.entry_size = sizeof(struct reo_entrance_ring) >> 2,
544 		.lmac_ring =  TRUE,
545 		.ring_dir = HAL_SRNG_SRC_RING,
546 		/* reg_start is not set because LMAC rings are not accessed
547 		 * from host
548 		 */
549 		.reg_start = {},
550 		.reg_size = {},
551 		.max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
552 		.dmac_cmn_ring = TRUE,
553 	},
554 	{ /* SW2RXDMA_LINK_RELEASE */ 0},
555 };
556 
557 /**
558  * hal_reo_config_reo2ppe_dest_info_9224() - Configure reo2ppe dest info
559  * @hal_soc_hdl: HAL SoC Context
560  *
561  * Return: None.
562  */
563 static inline
hal_reo_config_reo2ppe_dest_info_9224(hal_soc_handle_t hal_soc_hdl)564 void hal_reo_config_reo2ppe_dest_info_9224(hal_soc_handle_t hal_soc_hdl)
565 {
566 	HAL_REG_WRITE((struct hal_soc *)hal_soc_hdl,
567 		      HWIO_REO_R0_REO2PPE_DEST_INFO_ADDR(REO_REG_REG_BASE),
568 		      REO2PPE_RULE_FAIL_FB);
569 }
570 
571 #define PMM_REG_BASE_QCN9224_V2 0xB500FC
572 
573 /**
574  * hal_get_tsf2_scratch_reg_qcn9224_v2() - API to read tsf2 scratch register
575  * @hal_soc_hdl: HAL soc context
576  * @mac_id: mac id
577  * @value: Pointer to update tsf2 value
578  *
579  * Return: void
580  */
hal_get_tsf2_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)581 static void hal_get_tsf2_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,
582 						uint8_t mac_id, uint64_t *value)
583 {
584 	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
585 	uint32_t offset_lo, offset_hi;
586 	enum hal_scratch_reg_enum enum_lo, enum_hi;
587 
588 	hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
589 
590 	offset_lo = hal_read_pmm_scratch_reg(soc,
591 					     PMM_REG_BASE_QCN9224_V2,
592 					     enum_lo);
593 
594 	offset_hi = hal_read_pmm_scratch_reg(soc,
595 					     PMM_REG_BASE_QCN9224_V2,
596 					     enum_hi);
597 
598 	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
599 }
600 
601 /**
602  * hal_get_tqm_scratch_reg_qcn9224_v2() - API to read tqm scratch register
603  * @hal_soc_hdl: HAL soc context
604  * @value: Pointer to update tqm value
605  *
606  * Return: void
607  */
hal_get_tqm_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,uint64_t * value)608 static void hal_get_tqm_scratch_reg_qcn9224_v2(hal_soc_handle_t hal_soc_hdl,
609 					       uint64_t *value)
610 {
611 	struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
612 	uint32_t offset_lo, offset_hi;
613 
614 	offset_lo = hal_read_pmm_scratch_reg(soc,
615 					     PMM_REG_BASE_QCN9224_V2,
616 					     PMM_TQM_CLOCK_OFFSET_LO_US);
617 
618 	offset_hi = hal_read_pmm_scratch_reg(soc,
619 					     PMM_REG_BASE_QCN9224_V2,
620 					     PMM_TQM_CLOCK_OFFSET_HI_US);
621 
622 	*value = ((uint64_t)(offset_hi) << 32 | offset_lo);
623 }
624 
hal_hw_txrx_ops_override_qcn9224_v2(struct hal_soc * hal_soc)625 static void hal_hw_txrx_ops_override_qcn9224_v2(struct hal_soc *hal_soc)
626 {
627 	hal_soc->ops->hal_reo_config_reo2ppe_dest_info =
628 					hal_reo_config_reo2ppe_dest_info_9224;
629 
630 	hal_soc->ops->hal_get_tsf2_scratch_reg =
631 					hal_get_tsf2_scratch_reg_qcn9224_v2;
632 	hal_soc->ops->hal_get_tqm_scratch_reg =
633 					hal_get_tqm_scratch_reg_qcn9224_v2;
634 }
635 /**
636  * hal_qcn9224v2_attach() - Attach 9224v2 target specific hal_soc ops,
637  *			    offset and srng table
638  * @hal_soc: HAL SoC context
639  *
640  * Return: void
641  */
hal_qcn9224v2_attach(struct hal_soc * hal_soc)642 void hal_qcn9224v2_attach(struct hal_soc *hal_soc)
643 {
644 	hal_soc->hw_srng_table = hw_srng_table_9224v2;
645 
646 	hal_srng_hw_reg_offset_init_generic(hal_soc);
647 	hal_srng_hw_reg_offset_init_qcn9224(hal_soc);
648 
649 	hal_hw_txrx_default_ops_attach_be(hal_soc);
650 	hal_hw_txrx_ops_attach_qcn9224(hal_soc);
651 	if (hal_soc->static_window_map)
652 		hal_write_window_register(hal_soc);
653 	hal_soc->dmac_cmn_src_rxbuf_ring = true;
654 
655 	hal_hw_txrx_ops_override_qcn9224_v2(hal_soc);
656 }
657