1 /*
2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for
6 * any purpose with or without fee is hereby granted, provided that the
7 * above copyright notice and this permission notice appear in all
8 * copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
17 * PERFORMANCE OF THIS SOFTWARE.
18 */
19 #include "hal_li_hw_headers.h"
20 #include "hal_internal.h"
21 #include "hal_api.h"
22 #include "target_type.h"
23 #include "wcss_version.h"
24 #include "qdf_module.h"
25 #include "hal_flow.h"
26 #include "rx_flow_search_entry.h"
27 #include "hal_rx_flow_info.h"
28
29 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_OFFSET \
30 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_OFFSET
31 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_MASK \
32 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_MASK
33 #define UNIFIED_RXPCU_PPDU_END_INFO_8_RX_PPDU_DURATION_LSB \
34 RXPCU_PPDU_END_INFO_9_RX_PPDU_DURATION_LSB
35 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET \
36 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_OFFSET
37 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK \
38 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_MASK
39 #define UNIFIED_RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB \
40 RXPCU_PPDU_END_INFO_11_PHYRX_ABORT_REQUEST_INFO_DETAILS_PHYRX_ABORT_REASON_LSB
41 #define UNIFIED_PHYRX_HT_SIG_0_HT_SIG_INFO_PHYRX_HT_SIG_INFO_DETAILS_OFFSET \
42 PHYRX_HT_SIG_0_PHYRX_HT_SIG_INFO_DETAILS_MCS_OFFSET
43 #define UNIFIED_PHYRX_L_SIG_B_0_L_SIG_B_INFO_PHYRX_L_SIG_B_INFO_DETAILS_OFFSET \
44 PHYRX_L_SIG_B_0_PHYRX_L_SIG_B_INFO_DETAILS_RATE_OFFSET
45 #define UNIFIED_PHYRX_L_SIG_A_0_L_SIG_A_INFO_PHYRX_L_SIG_A_INFO_DETAILS_OFFSET \
46 PHYRX_L_SIG_A_0_PHYRX_L_SIG_A_INFO_DETAILS_RATE_OFFSET
47 #define UNIFIED_PHYRX_VHT_SIG_A_0_VHT_SIG_A_INFO_PHYRX_VHT_SIG_A_INFO_DETAILS_OFFSET \
48 PHYRX_VHT_SIG_A_0_PHYRX_VHT_SIG_A_INFO_DETAILS_BANDWIDTH_OFFSET
49 #define UNIFIED_PHYRX_HE_SIG_A_SU_0_HE_SIG_A_SU_INFO_PHYRX_HE_SIG_A_SU_INFO_DETAILS_OFFSET \
50 PHYRX_HE_SIG_A_SU_0_PHYRX_HE_SIG_A_SU_INFO_DETAILS_FORMAT_INDICATION_OFFSET
51 #define UNIFIED_PHYRX_HE_SIG_A_MU_DL_0_HE_SIG_A_MU_DL_INFO_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_OFFSET \
52 PHYRX_HE_SIG_A_MU_DL_0_PHYRX_HE_SIG_A_MU_DL_INFO_DETAILS_DL_UL_FLAG_OFFSET
53 #define UNIFIED_PHYRX_HE_SIG_B1_MU_0_HE_SIG_B1_MU_INFO_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_OFFSET \
54 PHYRX_HE_SIG_B1_MU_0_PHYRX_HE_SIG_B1_MU_INFO_DETAILS_RU_ALLOCATION_OFFSET
55 #define UNIFIED_PHYRX_HE_SIG_B2_MU_0_HE_SIG_B2_MU_INFO_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_OFFSET \
56 PHYRX_HE_SIG_B2_MU_0_PHYRX_HE_SIG_B2_MU_INFO_DETAILS_STA_ID_OFFSET
57 #define UNIFIED_PHYRX_HE_SIG_B2_OFDMA_0_HE_SIG_B2_OFDMA_INFO_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_OFFSET \
58 PHYRX_HE_SIG_B2_OFDMA_0_PHYRX_HE_SIG_B2_OFDMA_INFO_DETAILS_STA_ID_OFFSET
59 #define UNIFIED_PHYRX_RSSI_LEGACY_3_RECEIVE_RSSI_INFO_PRE_RSSI_INFO_DETAILS_OFFSET \
60 PHYRX_RSSI_LEGACY_3_PRE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
61 #define UNIFIED_PHYRX_RSSI_LEGACY_19_RECEIVE_RSSI_INFO_PREAMBLE_RSSI_INFO_DETAILS_OFFSET \
62 PHYRX_RSSI_LEGACY_19_PREAMBLE_RSSI_INFO_DETAILS_RSSI_PRI20_CHAIN0_OFFSET
63 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
64 RX_MPDU_START_0_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
66 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
67 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
68 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
69 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
70 RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
71 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
72 REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
73 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
74 STATUS_HEADER_REO_STATUS_NUMBER
75 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
76 STATUS_HEADER_TIMESTAMP
77 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
78 RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
79 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
80 RX_MSDU_LINK_8_MSDU_0_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
81 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
82 TCL_DATA_CMD_0_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
83 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
84 TCL_DATA_CMD_1_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
85 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
86 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET
87 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
88 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB
89 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
90 BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK
91 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
92 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB
93 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
94 BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK
95 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
96 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB
97 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
98 BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK
99 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
100 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB
101 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
102 BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK
103 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
104 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB
105 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
106 TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK
107 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
108 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
109 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
110 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
111 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
112 WBM_RELEASE_RING_6_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
113
114 #include "hal_8074v2_tx.h"
115 #include "hal_8074v2_rx.h"
116 #include <hal_generic_api.h>
117 #include "hal_li_rx.h"
118 #include "hal_li_api.h"
119 #include "hal_li_generic_api.h"
120
121 /**
122 * hal_rx_get_rx_fragment_number_8074v2() - Function to retrieve
123 * rx fragment number
124 * @buf: Network buffer
125 *
126 * Return: rx fragment number
127 */
128 static
hal_rx_get_rx_fragment_number_8074v2(uint8_t * buf)129 uint8_t hal_rx_get_rx_fragment_number_8074v2(uint8_t *buf)
130 {
131 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
132 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
133
134 /* Return first 4 bits as fragment number */
135 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info) &
136 DOT11_SEQ_FRAG_MASK;
137 }
138
139 /**
140 * hal_rx_msdu_end_da_is_mcbc_get_8074v2() - API to check if pkt is MCBC
141 * from rx_msdu_end TLV
142 * @buf: pointer to the start of RX PKT TLV headers
143 *
144 * Return: da_is_mcbc
145 */
146 static uint8_t
hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t * buf)147 hal_rx_msdu_end_da_is_mcbc_get_8074v2(uint8_t *buf)
148 {
149 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
150 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
151
152 return HAL_RX_MSDU_END_DA_IS_MCBC_GET(msdu_end);
153 }
154
155 /**
156 * hal_rx_msdu_end_sa_is_valid_get_8074v2() - API to get_8074v2 the sa_is_valid
157 * bit from rx_msdu_end TLV
158 * @buf: pointer to the start of RX PKT TLV headers
159 *
160 * Return: sa_is_valid bit
161 */
162 static uint8_t
hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t * buf)163 hal_rx_msdu_end_sa_is_valid_get_8074v2(uint8_t *buf)
164 {
165 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
166 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
167 uint8_t sa_is_valid;
168
169 sa_is_valid = HAL_RX_MSDU_END_SA_IS_VALID_GET(msdu_end);
170
171 return sa_is_valid;
172 }
173
174 /**
175 * hal_rx_msdu_end_sa_idx_get_8074v2() - API to get_8074v2 the sa_idx from
176 * rx_msdu_end TLV
177 * @buf: pointer to the start of RX PKT TLV headers
178 *
179 * Return: sa_idx (SA AST index)
180 */
hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t * buf)181 static uint16_t hal_rx_msdu_end_sa_idx_get_8074v2(uint8_t *buf)
182 {
183 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
184 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
185 uint16_t sa_idx;
186
187 sa_idx = HAL_RX_MSDU_END_SA_IDX_GET(msdu_end);
188
189 return sa_idx;
190 }
191
192 /**
193 * hal_rx_desc_is_first_msdu_8074v2() - Check if first msdu
194 * @hw_desc_addr: hardware descriptor address
195 *
196 * Return: 0 - success/ non-zero failure
197 */
hal_rx_desc_is_first_msdu_8074v2(void * hw_desc_addr)198 static uint32_t hal_rx_desc_is_first_msdu_8074v2(void *hw_desc_addr)
199 {
200 struct rx_pkt_tlvs *rx_tlvs = (struct rx_pkt_tlvs *)hw_desc_addr;
201 struct rx_msdu_end *msdu_end = &rx_tlvs->msdu_end_tlv.rx_msdu_end;
202
203 return HAL_RX_GET(msdu_end, RX_MSDU_END_5, FIRST_MSDU);
204 }
205
206 /**
207 * hal_rx_msdu_end_l3_hdr_padding_get_8074v2() - API to get_8074v2 the
208 * l3_header padding from
209 * rx_msdu_end TLV
210 * @buf: pointer to the start of RX PKT TLV headers
211 *
212 * Return: number of l3 header padding bytes
213 */
hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t * buf)214 static uint32_t hal_rx_msdu_end_l3_hdr_padding_get_8074v2(uint8_t *buf)
215 {
216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
217 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
218 uint32_t l3_header_padding;
219
220 l3_header_padding = HAL_RX_MSDU_END_L3_HEADER_PADDING_GET(msdu_end);
221
222 return l3_header_padding;
223 }
224
225 /**
226 * hal_rx_encryption_info_valid_8074v2() - Returns encryption type.
227 * @buf: rx_tlv_hdr of the received packet
228 *
229 * Return: encryption type
230 */
hal_rx_encryption_info_valid_8074v2(uint8_t * buf)231 static uint32_t hal_rx_encryption_info_valid_8074v2(uint8_t *buf)
232 {
233 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
234 struct rx_mpdu_start *mpdu_start =
235 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
236 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
237 uint32_t encryption_info = HAL_RX_MPDU_ENCRYPTION_INFO_VALID(mpdu_info);
238
239 return encryption_info;
240 }
241
242 /**
243 * hal_rx_print_pn_8074v2() - Prints the PN of rx packet.
244 * @buf: rx_tlv_hdr of the received packet
245 *
246 * Return: void
247 */
hal_rx_print_pn_8074v2(uint8_t * buf)248 static void hal_rx_print_pn_8074v2(uint8_t *buf)
249 {
250 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
251 struct rx_mpdu_start *mpdu_start =
252 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
253 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
254
255 uint32_t pn_31_0 = HAL_RX_MPDU_PN_31_0_GET(mpdu_info);
256 uint32_t pn_63_32 = HAL_RX_MPDU_PN_63_32_GET(mpdu_info);
257 uint32_t pn_95_64 = HAL_RX_MPDU_PN_95_64_GET(mpdu_info);
258 uint32_t pn_127_96 = HAL_RX_MPDU_PN_127_96_GET(mpdu_info);
259
260 hal_debug("PN number pn_127_96 0x%x pn_95_64 0x%x pn_63_32 0x%x pn_31_0 0x%x",
261 pn_127_96, pn_95_64, pn_63_32, pn_31_0);
262 }
263
264 /**
265 * hal_rx_msdu_end_first_msdu_get_8074v2() - API to get first msdu status
266 * from rx_msdu_end TLV
267 * @buf: pointer to the start of RX PKT TLV headers
268 *
269 * Return: first_msdu
270 */
hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t * buf)271 static uint8_t hal_rx_msdu_end_first_msdu_get_8074v2(uint8_t *buf)
272 {
273 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
274 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
275 uint8_t first_msdu;
276
277 first_msdu = HAL_RX_MSDU_END_FIRST_MSDU_GET(msdu_end);
278
279 return first_msdu;
280 }
281
282 /**
283 * hal_rx_msdu_end_da_is_valid_get_8074v2() - API to check if da is valid
284 * from rx_msdu_end TLV
285 * @buf: pointer to the start of RX PKT TLV headers
286 *
287 * Return: da_is_valid
288 */
hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t * buf)289 static uint8_t hal_rx_msdu_end_da_is_valid_get_8074v2(uint8_t *buf)
290 {
291 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
292 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
293 uint8_t da_is_valid;
294
295 da_is_valid = HAL_RX_MSDU_END_DA_IS_VALID_GET(msdu_end);
296
297 return da_is_valid;
298 }
299
300 /**
301 * hal_rx_msdu_end_last_msdu_get_8074v2() - API to get last msdu status
302 * from rx_msdu_end TLV
303 * @buf: pointer to the start of RX PKT TLV headers
304 *
305 * Return: last_msdu
306 */
hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t * buf)307 static uint8_t hal_rx_msdu_end_last_msdu_get_8074v2(uint8_t *buf)
308 {
309 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
310 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
311 uint8_t last_msdu;
312
313 last_msdu = HAL_RX_MSDU_END_LAST_MSDU_GET(msdu_end);
314
315 return last_msdu;
316 }
317
318 /**
319 * hal_rx_get_mpdu_mac_ad4_valid_8074v2() - Retrieves if mpdu 4th addr is valid
320 * @buf: Network buffer
321 *
322 * Return: value of mpdu 4th address valid field
323 */
hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t * buf)324 static bool hal_rx_get_mpdu_mac_ad4_valid_8074v2(uint8_t *buf)
325 {
326 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
327 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
328 bool ad4_valid = 0;
329
330 ad4_valid = HAL_RX_MPDU_GET_MAC_AD4_VALID(rx_mpdu_info);
331
332 return ad4_valid;
333 }
334
335 /**
336 * hal_rx_mpdu_start_sw_peer_id_get_8074v2() - Retrieve sw peer_id
337 * @buf: network buffer
338 *
339 * Return: sw peer_id
340 */
hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t * buf)341 static uint32_t hal_rx_mpdu_start_sw_peer_id_get_8074v2(uint8_t *buf)
342 {
343 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
344 struct rx_mpdu_start *mpdu_start =
345 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
346
347 return HAL_RX_MPDU_INFO_SW_PEER_ID_GET(
348 &mpdu_start->rx_mpdu_info_details);
349 }
350
351 /**
352 * hal_rx_mpdu_get_to_ds_8074v2() - API to get the tods info from rx_mpdu_start
353 * @buf: pointer to the start of RX PKT TLV header
354 *
355 * Return: uint32_t(to_ds)
356 */
hal_rx_mpdu_get_to_ds_8074v2(uint8_t * buf)357 static uint32_t hal_rx_mpdu_get_to_ds_8074v2(uint8_t *buf)
358 {
359 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
360 struct rx_mpdu_start *mpdu_start =
361 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
362
363 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
364
365 return HAL_RX_MPDU_GET_TODS(mpdu_info);
366 }
367
368 /**
369 * hal_rx_mpdu_get_fr_ds_8074v2() - API to get the from ds info from
370 * rx_mpdu_start
371 * @buf: pointer to the start of RX PKT TLV header
372 *
373 * Return: uint32_t(fr_ds)
374 */
hal_rx_mpdu_get_fr_ds_8074v2(uint8_t * buf)375 static uint32_t hal_rx_mpdu_get_fr_ds_8074v2(uint8_t *buf)
376 {
377 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
378 struct rx_mpdu_start *mpdu_start =
379 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
380
381 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
382
383 return HAL_RX_MPDU_GET_FROMDS(mpdu_info);
384 }
385
386 /**
387 * hal_rx_get_mpdu_frame_control_valid_8074v2() - Retrieves mpdu
388 * frame control valid
389 * @buf: Network buffer
390 *
391 * Return: value of frame control valid field
392 */
hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t * buf)393 static uint8_t hal_rx_get_mpdu_frame_control_valid_8074v2(uint8_t *buf)
394 {
395 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
396 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
397
398 return HAL_RX_MPDU_GET_FRAME_CONTROL_VALID(rx_mpdu_info);
399 }
400
401 /**
402 * hal_rx_get_mpdu_frame_control_field_8074v2() - Function to retrieve frame
403 * control field
404 * @buf: Network buffer
405 *
406 * Return: value of frame control field
407 *
408 */
hal_rx_get_mpdu_frame_control_field_8074v2(uint8_t * buf)409 static uint16_t hal_rx_get_mpdu_frame_control_field_8074v2(uint8_t *buf)
410 {
411 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
412 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
413 uint16_t frame_ctrl = 0;
414
415 frame_ctrl = HAL_RX_MPDU_GET_FRAME_CONTROL_FIELD(rx_mpdu_info);
416
417 return frame_ctrl;
418 }
419
420 /**
421 * hal_rx_mpdu_get_addr1_8074v2() - API to check get address1 of the mpdu
422 * @buf: pointer to the start of RX PKT TLV headera
423 * @mac_addr: pointer to mac address
424 *
425 * Return: success/failure
426 */
hal_rx_mpdu_get_addr1_8074v2(uint8_t * buf,uint8_t * mac_addr)427 static QDF_STATUS hal_rx_mpdu_get_addr1_8074v2(uint8_t *buf, uint8_t *mac_addr)
428 {
429 struct __attribute__((__packed__)) hal_addr1 {
430 uint32_t ad1_31_0;
431 uint16_t ad1_47_32;
432 };
433
434 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
435 struct rx_mpdu_start *mpdu_start =
436 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
437
438 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
439 struct hal_addr1 *addr = (struct hal_addr1 *)mac_addr;
440 uint32_t mac_addr_ad1_valid;
441
442 mac_addr_ad1_valid = HAL_RX_MPDU_MAC_ADDR_AD1_VALID_GET(mpdu_info);
443
444 if (mac_addr_ad1_valid) {
445 addr->ad1_31_0 = HAL_RX_MPDU_AD1_31_0_GET(mpdu_info);
446 addr->ad1_47_32 = HAL_RX_MPDU_AD1_47_32_GET(mpdu_info);
447 return QDF_STATUS_SUCCESS;
448 }
449
450 return QDF_STATUS_E_FAILURE;
451 }
452
453 /**
454 * hal_rx_mpdu_get_addr2_8074v2() - API to check get address2 of the mpdu
455 * in the packet
456 * @buf: pointer to the start of RX PKT TLV header
457 * @mac_addr: pointer to mac address
458 *
459 * Return: success/failure
460 */
hal_rx_mpdu_get_addr2_8074v2(uint8_t * buf,uint8_t * mac_addr)461 static QDF_STATUS hal_rx_mpdu_get_addr2_8074v2(uint8_t *buf, uint8_t *mac_addr)
462 {
463 struct __attribute__((__packed__)) hal_addr2 {
464 uint16_t ad2_15_0;
465 uint32_t ad2_47_16;
466 };
467
468 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
469 struct rx_mpdu_start *mpdu_start =
470 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
471
472 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
473 struct hal_addr2 *addr = (struct hal_addr2 *)mac_addr;
474 uint32_t mac_addr_ad2_valid;
475
476 mac_addr_ad2_valid = HAL_RX_MPDU_MAC_ADDR_AD2_VALID_GET(mpdu_info);
477
478 if (mac_addr_ad2_valid) {
479 addr->ad2_15_0 = HAL_RX_MPDU_AD2_15_0_GET(mpdu_info);
480 addr->ad2_47_16 = HAL_RX_MPDU_AD2_47_16_GET(mpdu_info);
481 return QDF_STATUS_SUCCESS;
482 }
483
484 return QDF_STATUS_E_FAILURE;
485 }
486
487 /**
488 * hal_rx_mpdu_get_addr3_8074v2() - API to get address3 of the mpdu
489 * in the packet
490 * @buf: pointer to the start of RX PKT TLV header
491 * @mac_addr: pointer to mac address
492 *
493 * Return: success/failure
494 */
hal_rx_mpdu_get_addr3_8074v2(uint8_t * buf,uint8_t * mac_addr)495 static QDF_STATUS hal_rx_mpdu_get_addr3_8074v2(uint8_t *buf, uint8_t *mac_addr)
496 {
497 struct __attribute__((__packed__)) hal_addr3 {
498 uint32_t ad3_31_0;
499 uint16_t ad3_47_32;
500 };
501
502 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
503 struct rx_mpdu_start *mpdu_start =
504 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
505
506 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
507 struct hal_addr3 *addr = (struct hal_addr3 *)mac_addr;
508 uint32_t mac_addr_ad3_valid;
509
510 mac_addr_ad3_valid = HAL_RX_MPDU_MAC_ADDR_AD3_VALID_GET(mpdu_info);
511
512 if (mac_addr_ad3_valid) {
513 addr->ad3_31_0 = HAL_RX_MPDU_AD3_31_0_GET(mpdu_info);
514 addr->ad3_47_32 = HAL_RX_MPDU_AD3_47_32_GET(mpdu_info);
515 return QDF_STATUS_SUCCESS;
516 }
517
518 return QDF_STATUS_E_FAILURE;
519 }
520
521 /**
522 * hal_rx_mpdu_get_addr4_8074v2() - API to get address4 of the mpdu
523 * in the packet
524 * @buf: pointer to the start of RX PKT TLV header
525 * @mac_addr: pointer to mac address
526 *
527 * Return: success/failure
528 */
hal_rx_mpdu_get_addr4_8074v2(uint8_t * buf,uint8_t * mac_addr)529 static QDF_STATUS hal_rx_mpdu_get_addr4_8074v2(uint8_t *buf, uint8_t *mac_addr)
530 {
531 struct __attribute__((__packed__)) hal_addr4 {
532 uint32_t ad4_31_0;
533 uint16_t ad4_47_32;
534 };
535
536 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
537 struct rx_mpdu_start *mpdu_start =
538 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
539
540 struct rx_mpdu_info *mpdu_info = &mpdu_start->rx_mpdu_info_details;
541 struct hal_addr4 *addr = (struct hal_addr4 *)mac_addr;
542 uint32_t mac_addr_ad4_valid;
543
544 mac_addr_ad4_valid = HAL_RX_MPDU_MAC_ADDR_AD4_VALID_GET(mpdu_info);
545
546 if (mac_addr_ad4_valid) {
547 addr->ad4_31_0 = HAL_RX_MPDU_AD4_31_0_GET(mpdu_info);
548 addr->ad4_47_32 = HAL_RX_MPDU_AD4_47_32_GET(mpdu_info);
549 return QDF_STATUS_SUCCESS;
550 }
551
552 return QDF_STATUS_E_FAILURE;
553 }
554
555 /**
556 * hal_rx_get_mpdu_sequence_control_valid_8074v2() - Get mpdu sequence control
557 * valid
558 * @buf: Network buffer
559 *
560 * Return: value of sequence control valid field
561 */
hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t * buf)562 static uint8_t hal_rx_get_mpdu_sequence_control_valid_8074v2(uint8_t *buf)
563 {
564 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
565 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
566
567 return HAL_RX_MPDU_GET_SEQUENCE_CONTROL_VALID(rx_mpdu_info);
568 }
569
570 /**
571 * hal_rx_is_unicast_8074v2() - check packet is unicast frame or not.
572 * @buf: pointer to rx pkt TLV.
573 *
574 * Return: true on unicast.
575 */
hal_rx_is_unicast_8074v2(uint8_t * buf)576 static bool hal_rx_is_unicast_8074v2(uint8_t *buf)
577 {
578 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
579 struct rx_mpdu_start *mpdu_start =
580 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
581 uint32_t grp_id;
582 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
583
584 grp_id = (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
585 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_OFFSET)),
586 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_MASK,
587 RX_MPDU_INFO_0_SW_FRAME_GROUP_ID_LSB));
588
589 return (HAL_MPDU_SW_FRAME_GROUP_UNICAST_DATA == grp_id) ? true : false;
590 }
591
592 /**
593 * hal_rx_tid_get_8074v2() - get tid based on qos control valid.
594 * @hal_soc_hdl: hal soc handle
595 * @buf: pointer to rx pkt TLV.
596 *
597 * Return: tid
598 */
hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl,uint8_t * buf)599 static uint32_t hal_rx_tid_get_8074v2(hal_soc_handle_t hal_soc_hdl,
600 uint8_t *buf)
601 {
602 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
603 struct rx_mpdu_start *mpdu_start =
604 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
605 uint8_t *rx_mpdu_info = (uint8_t *)&mpdu_start->rx_mpdu_info_details;
606 uint8_t qos_control_valid =
607 (_HAL_MS((*_OFFSET_TO_WORD_PTR((rx_mpdu_info),
608 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_OFFSET)),
609 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_MASK,
610 RX_MPDU_INFO_2_MPDU_QOS_CONTROL_VALID_LSB));
611
612 if (qos_control_valid)
613 return hal_rx_mpdu_start_tid_get_8074v2(buf);
614
615 return HAL_RX_NON_QOS_TID;
616 }
617
618 /**
619 * hal_rx_hw_desc_get_ppduid_get_8074v2() - retrieve ppdu id
620 * @rx_tlv_hdr: packtet rx tlv header
621 * @rxdma_dst_ring_desc: rxdma HW descriptor
622 *
623 * Return: ppdu id
624 */
hal_rx_hw_desc_get_ppduid_get_8074v2(void * rx_tlv_hdr,void * rxdma_dst_ring_desc)625 static uint32_t hal_rx_hw_desc_get_ppduid_get_8074v2(void *rx_tlv_hdr,
626 void *rxdma_dst_ring_desc)
627 {
628 struct rx_mpdu_info *rx_mpdu_info;
629 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
630
631 rx_mpdu_info =
632 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
633
634 return HAL_RX_GET(rx_mpdu_info, RX_MPDU_INFO_0, PHY_PPDU_ID);
635 }
636
637 /**
638 * hal_reo_status_get_header_8074v2() - Process reo desc info
639 * @ring_desc: REO status ring descriptor
640 * @b: tlv type info
641 * @h1: Pointer to hal_reo_status_header where info to be stored
642 *
643 * Return: none.
644 */
hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc,int b,void * h1)645 static void hal_reo_status_get_header_8074v2(hal_ring_desc_t ring_desc, int b,
646 void *h1)
647 {
648 uint32_t *d = (uint32_t *)ring_desc;
649 uint32_t val1 = 0;
650 struct hal_reo_status_header *h =
651 (struct hal_reo_status_header *)h1;
652
653 /* Offsets of descriptor fields defined in HW headers start
654 * from the field after TLV header
655 */
656 d += HAL_GET_NUM_DWORDS(sizeof(struct tlv_32_hdr));
657
658 switch (b) {
659 case HAL_REO_QUEUE_STATS_STATUS_TLV:
660 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_0,
661 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
662 break;
663 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
664 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_0,
665 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
666 break;
667 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
668 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_0,
669 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
670 break;
671 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
672 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_0,
673 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
674 break;
675 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
676 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_0,
677 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
678 break;
679 case HAL_REO_DESC_THRES_STATUS_TLV:
680 val1 =
681 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_0,
682 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
683 break;
684 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
685 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_0,
686 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER)];
687 break;
688 default:
689 qdf_nofl_err("ERROR: Unknown tlv\n");
690 break;
691 }
692 h->cmd_num =
693 HAL_GET_FIELD(
694 UNIFORM_REO_STATUS_HEADER_0, REO_STATUS_NUMBER,
695 val1);
696 h->exec_time =
697 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
698 CMD_EXECUTION_TIME, val1);
699 h->status =
700 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_0,
701 REO_CMD_EXECUTION_STATUS, val1);
702 switch (b) {
703 case HAL_REO_QUEUE_STATS_STATUS_TLV:
704 val1 = d[HAL_OFFSET_DW(REO_GET_QUEUE_STATS_STATUS_1,
705 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
706 break;
707 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
708 val1 = d[HAL_OFFSET_DW(REO_FLUSH_QUEUE_STATUS_1,
709 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
710 break;
711 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
712 val1 = d[HAL_OFFSET_DW(REO_FLUSH_CACHE_STATUS_1,
713 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
714 break;
715 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
716 val1 = d[HAL_OFFSET_DW(REO_UNBLOCK_CACHE_STATUS_1,
717 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
718 break;
719 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
720 val1 = d[HAL_OFFSET_DW(REO_FLUSH_TIMEOUT_LIST_STATUS_1,
721 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
722 break;
723 case HAL_REO_DESC_THRES_STATUS_TLV:
724 val1 =
725 d[HAL_OFFSET_DW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS_1,
726 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
727 break;
728 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
729 val1 = d[HAL_OFFSET_DW(REO_UPDATE_RX_REO_QUEUE_STATUS_1,
730 UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC)];
731 break;
732 default:
733 qdf_nofl_err("ERROR: Unknown tlv\n");
734 break;
735 }
736 h->tstamp =
737 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER_1, TIMESTAMP, val1);
738 }
739
740 /**
741 * hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2() -
742 * Retrieve qos control valid bit from the tlv.
743 * @buf: pointer to rx pkt TLV.
744 *
745 * Return: qos control value.
746 */
747 static inline uint32_t
hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t * buf)748 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2(uint8_t *buf)
749 {
750 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
751 struct rx_mpdu_start *mpdu_start =
752 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
753
754 return HAL_RX_MPDU_INFO_QOS_CONTROL_VALID_GET(
755 &mpdu_start->rx_mpdu_info_details);
756 }
757
758 /**
759 * hal_rx_msdu_end_sa_sw_peer_id_get_8074v2() - API to get the sa_sw_peer_id
760 * from rx_msdu_end TLV
761 * @buf: pointer to the start of RX PKT TLV headers
762 *
763 * Return: sa_sw_peer_id index
764 */
765 static inline uint32_t
hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t * buf)766 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2(uint8_t *buf)
767 {
768 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
769 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
770
771 return HAL_RX_MSDU_END_SA_SW_PEER_ID_GET(msdu_end);
772 }
773
774 /**
775 * hal_tx_desc_set_mesh_en_8074v2() - Set mesh_enable flag in Tx descriptor
776 * @desc: Handle to Tx Descriptor
777 * @en: For raw WiFi frames, this indicates transmission to a mesh STA,
778 * enabling the interpretation of the 'Mesh Control Present' bit
779 * (bit 8) of QoS Control (otherwise this bit is ignored),
780 * For native WiFi frames, this indicates that a 'Mesh Control' field
781 * is present between the header and the LLC.
782 *
783 * Return: void
784 */
785 static inline
hal_tx_desc_set_mesh_en_8074v2(void * desc,uint8_t en)786 void hal_tx_desc_set_mesh_en_8074v2(void *desc, uint8_t en)
787 {
788 HAL_SET_FLD(desc, TCL_DATA_CMD_4, MESH_ENABLE) |=
789 HAL_TX_SM(TCL_DATA_CMD_4, MESH_ENABLE, en);
790 }
791
792 static
hal_rx_msdu0_buffer_addr_lsb_8074v2(void * link_desc_va)793 void *hal_rx_msdu0_buffer_addr_lsb_8074v2(void *link_desc_va)
794 {
795 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
796 }
797
798 static
hal_rx_msdu_desc_info_ptr_get_8074v2(void * msdu0)799 void *hal_rx_msdu_desc_info_ptr_get_8074v2(void *msdu0)
800 {
801 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
802 }
803
804 static
hal_ent_mpdu_desc_info_8074v2(void * ent_ring_desc)805 void *hal_ent_mpdu_desc_info_8074v2(void *ent_ring_desc)
806 {
807 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
808 }
809
810 static
hal_dst_mpdu_desc_info_8074v2(void * dst_ring_desc)811 void *hal_dst_mpdu_desc_info_8074v2(void *dst_ring_desc)
812 {
813 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
814 }
815
816 static
hal_rx_get_fc_valid_8074v2(uint8_t * buf)817 uint8_t hal_rx_get_fc_valid_8074v2(uint8_t *buf)
818 {
819 return HAL_RX_GET_FC_VALID(buf);
820 }
821
hal_rx_get_to_ds_flag_8074v2(uint8_t * buf)822 static uint8_t hal_rx_get_to_ds_flag_8074v2(uint8_t *buf)
823 {
824 return HAL_RX_GET_TO_DS_FLAG(buf);
825 }
826
hal_rx_get_mac_addr2_valid_8074v2(uint8_t * buf)827 static uint8_t hal_rx_get_mac_addr2_valid_8074v2(uint8_t *buf)
828 {
829 return HAL_RX_GET_MAC_ADDR2_VALID(buf);
830 }
831
hal_rx_get_filter_category_8074v2(uint8_t * buf)832 static uint8_t hal_rx_get_filter_category_8074v2(uint8_t *buf)
833 {
834 return HAL_RX_GET_FILTER_CATEGORY(buf);
835 }
836
837 static uint32_t
hal_rx_get_ppdu_id_8074v2(uint8_t * buf)838 hal_rx_get_ppdu_id_8074v2(uint8_t *buf)
839 {
840 struct rx_mpdu_info *rx_mpdu_info;
841 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)buf;
842
843 rx_mpdu_info =
844 &rx_desc->mpdu_start_tlv.rx_mpdu_start.rx_mpdu_info_details;
845
846 return HAL_RX_GET_PPDU_ID(rx_mpdu_info);
847 }
848
849 /**
850 * hal_reo_config_8074v2() - Set reo config parameters
851 * @soc: hal soc handle
852 * @reg_val: value to be set
853 * @reo_params: reo parameters
854 *
855 * Return: void
856 */
857 static void
hal_reo_config_8074v2(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)858 hal_reo_config_8074v2(struct hal_soc *soc,
859 uint32_t reg_val,
860 struct hal_reo_params *reo_params)
861 {
862 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
863 }
864
865 /**
866 * hal_rx_msdu_desc_info_get_ptr_8074v2() - Get msdu desc info ptr
867 * @msdu_details_ptr: Pointer to msdu_details_ptr
868 *
869 * Return: Pointer to rx_msdu_desc_info structure.
870 *
871 */
hal_rx_msdu_desc_info_get_ptr_8074v2(void * msdu_details_ptr)872 static void *hal_rx_msdu_desc_info_get_ptr_8074v2(void *msdu_details_ptr)
873 {
874 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
875 }
876
877 /**
878 * hal_rx_link_desc_msdu0_ptr_8074v2() - Get pointer to rx_msdu details
879 * @link_desc: Pointer to link desc
880 *
881 * Return: Pointer to rx_msdu_details structure
882 */
hal_rx_link_desc_msdu0_ptr_8074v2(void * link_desc)883 static void *hal_rx_link_desc_msdu0_ptr_8074v2(void *link_desc)
884 {
885 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
886 }
887
888 /**
889 * hal_rx_msdu_flow_idx_get_8074v2() - API to get flow index
890 * from rx_msdu_end TLV
891 * @buf: pointer to the start of RX PKT TLV headers
892 *
893 * Return: flow index value from MSDU END TLV
894 */
hal_rx_msdu_flow_idx_get_8074v2(uint8_t * buf)895 static inline uint32_t hal_rx_msdu_flow_idx_get_8074v2(uint8_t *buf)
896 {
897 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
898 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
899
900 return HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
901 }
902
903 /**
904 * hal_rx_msdu_flow_idx_invalid_8074v2() - API to get flow index invalid
905 * from rx_msdu_end TLV
906 * @buf: pointer to the start of RX PKT TLV headers
907 *
908 * Return: flow index invalid value from MSDU END TLV
909 */
hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t * buf)910 static bool hal_rx_msdu_flow_idx_invalid_8074v2(uint8_t *buf)
911 {
912 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
913 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
914
915 return HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
916 }
917
918 /**
919 * hal_rx_msdu_flow_idx_timeout_8074v2() - API to get flow index timeout
920 * from rx_msdu_end TLV
921 * @buf: pointer to the start of RX PKT TLV headers
922 *
923 * Return: flow index timeout value from MSDU END TLV
924 */
hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t * buf)925 static bool hal_rx_msdu_flow_idx_timeout_8074v2(uint8_t *buf)
926 {
927 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
928 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
929
930 return HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
931 }
932
933 /**
934 * hal_rx_msdu_fse_metadata_get_8074v2() - API to get FSE metadata
935 * from rx_msdu_end TLV
936 * @buf: pointer to the start of RX PKT TLV headers
937 *
938 * Return: fse metadata value from MSDU END TLV
939 */
hal_rx_msdu_fse_metadata_get_8074v2(uint8_t * buf)940 static uint32_t hal_rx_msdu_fse_metadata_get_8074v2(uint8_t *buf)
941 {
942 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
943 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
944
945 return HAL_RX_MSDU_END_FSE_METADATA_GET(msdu_end);
946 }
947
948 /**
949 * hal_rx_msdu_cce_metadata_get_8074v2() - API to get CCE metadata
950 * from rx_msdu_end TLV
951 * @buf: pointer to the start of RX PKT TLV headers
952 *
953 * Return: cce_metadata
954 */
955 static uint16_t
hal_rx_msdu_cce_metadata_get_8074v2(uint8_t * buf)956 hal_rx_msdu_cce_metadata_get_8074v2(uint8_t *buf)
957 {
958 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
959 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
960
961 return HAL_RX_MSDU_END_CCE_METADATA_GET(msdu_end);
962 }
963
964 /**
965 * hal_rx_msdu_get_flow_params_8074v2() - API to get flow index, flow index
966 * invalid and flow index timeout from
967 * rx_msdu_end TLV
968 * @buf: pointer to the start of RX PKT TLV headers
969 * @flow_invalid: pointer to return value of flow_idx_valid
970 * @flow_timeout: pointer to return value of flow_idx_timeout
971 * @flow_index: pointer to return value of flow_idx
972 *
973 * Return: none
974 */
975 static inline void
hal_rx_msdu_get_flow_params_8074v2(uint8_t * buf,bool * flow_invalid,bool * flow_timeout,uint32_t * flow_index)976 hal_rx_msdu_get_flow_params_8074v2(uint8_t *buf,
977 bool *flow_invalid,
978 bool *flow_timeout,
979 uint32_t *flow_index)
980 {
981 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
982 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
983
984 *flow_invalid = HAL_RX_MSDU_END_FLOW_IDX_INVALID_GET(msdu_end);
985 *flow_timeout = HAL_RX_MSDU_END_FLOW_IDX_TIMEOUT_GET(msdu_end);
986 *flow_index = HAL_RX_MSDU_END_FLOW_IDX_GET(msdu_end);
987 }
988
989 /**
990 * hal_rx_tlv_get_tcp_chksum_8074v2() - API to get tcp checksum
991 * @buf: rx_tlv_hdr
992 *
993 * Return: tcp checksum
994 */
995 static uint16_t
hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t * buf)996 hal_rx_tlv_get_tcp_chksum_8074v2(uint8_t *buf)
997 {
998 return HAL_RX_TLV_GET_TCP_CHKSUM(buf);
999 }
1000
1001 /**
1002 * hal_rx_get_rx_sequence_8074v2() - Function to retrieve rx sequence number
1003 * @buf: Network buffer
1004 *
1005 * Return: rx sequence number
1006 */
1007 static
hal_rx_get_rx_sequence_8074v2(uint8_t * buf)1008 uint16_t hal_rx_get_rx_sequence_8074v2(uint8_t *buf)
1009 {
1010 struct rx_pkt_tlvs *pkt_tlvs = hal_rx_get_pkt_tlvs(buf);
1011 struct rx_mpdu_info *rx_mpdu_info = hal_rx_get_mpdu_info(pkt_tlvs);
1012
1013 return HAL_RX_MPDU_GET_SEQUENCE_NUMBER(rx_mpdu_info);
1014 }
1015
1016 /**
1017 * hal_get_window_address_8074v2() - Function to get hp/tp address
1018 * @hal_soc: Pointer to hal_soc
1019 * @addr: address offset of register
1020 *
1021 * Return: modified address offset of register
1022 */
hal_get_window_address_8074v2(struct hal_soc * hal_soc,qdf_iomem_t addr)1023 static inline qdf_iomem_t hal_get_window_address_8074v2(struct hal_soc *hal_soc,
1024 qdf_iomem_t addr)
1025 {
1026 return addr;
1027 }
1028
1029 /**
1030 * hal_rx_mpdu_start_tlv_tag_valid_8074v2 () - API to check if RX_MPDU_START
1031 * tlv tag is valid
1032 *
1033 * @rx_tlv_hdr: start address of rx_pkt_tlvs
1034 *
1035 * Return: true if RX_MPDU_START is valid, else false.
1036 */
hal_rx_mpdu_start_tlv_tag_valid_8074v2(void * rx_tlv_hdr)1037 uint8_t hal_rx_mpdu_start_tlv_tag_valid_8074v2(void *rx_tlv_hdr)
1038 {
1039 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)rx_tlv_hdr;
1040 uint32_t tlv_tag;
1041
1042 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(&rx_desc->mpdu_start_tlv);
1043
1044 return tlv_tag == WIFIRX_MPDU_START_E ? true : false;
1045 }
1046
1047 /**
1048 * hal_rx_flow_setup_fse_8074v2() - Setup a flow search entry in HW FST
1049 * @rx_fst: Pointer to the Rx Flow Search Table
1050 * @table_offset: offset into the table where the flow is to be setup
1051 * @rx_flow: Flow Parameters
1052 *
1053 * Return: Success/Failure
1054 */
1055 static void *
hal_rx_flow_setup_fse_8074v2(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)1056 hal_rx_flow_setup_fse_8074v2(uint8_t *rx_fst, uint32_t table_offset,
1057 uint8_t *rx_flow)
1058 {
1059 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
1060 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
1061 uint8_t *fse;
1062 bool fse_valid;
1063
1064 if (table_offset >= fst->max_entries) {
1065 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1066 "HAL FSE table offset %u exceeds max entries %u",
1067 table_offset, fst->max_entries);
1068 return NULL;
1069 }
1070
1071 fse = (uint8_t *)fst->base_vaddr +
1072 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1073
1074 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1075
1076 if (fse_valid) {
1077 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1078 "HAL FSE %pK already valid", fse);
1079 return NULL;
1080 }
1081
1082 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96) =
1083 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_0, SRC_IP_127_96,
1084 qdf_htonl(flow->tuple_info.src_ip_127_96));
1085
1086 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64) =
1087 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_1, SRC_IP_95_64,
1088 qdf_htonl(flow->tuple_info.src_ip_95_64));
1089
1090 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32) =
1091 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_2, SRC_IP_63_32,
1092 qdf_htonl(flow->tuple_info.src_ip_63_32));
1093
1094 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0) =
1095 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_3, SRC_IP_31_0,
1096 qdf_htonl(flow->tuple_info.src_ip_31_0));
1097
1098 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96) =
1099 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_4, DEST_IP_127_96,
1100 qdf_htonl(flow->tuple_info.dest_ip_127_96));
1101
1102 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64) =
1103 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_5, DEST_IP_95_64,
1104 qdf_htonl(flow->tuple_info.dest_ip_95_64));
1105
1106 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32) =
1107 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_6, DEST_IP_63_32,
1108 qdf_htonl(flow->tuple_info.dest_ip_63_32));
1109
1110 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0) =
1111 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_7, DEST_IP_31_0,
1112 qdf_htonl(flow->tuple_info.dest_ip_31_0));
1113
1114 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT);
1115 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, DEST_PORT) |=
1116 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, DEST_PORT,
1117 (flow->tuple_info.dest_port));
1118
1119 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT);
1120 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_8, SRC_PORT) |=
1121 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_8, SRC_PORT,
1122 (flow->tuple_info.src_port));
1123
1124 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL);
1125 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL) |=
1126 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, L4_PROTOCOL,
1127 flow->tuple_info.l4_protocol);
1128
1129 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER);
1130 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER) |=
1131 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, REO_DESTINATION_HANDLER,
1132 flow->reo_destination_handler);
1133
1134 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID);
1135 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, VALID) |=
1136 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_9, VALID, 1);
1137
1138 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA);
1139 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_10, METADATA) =
1140 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_10, METADATA,
1141 flow->fse_metadata);
1142
1143 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION);
1144 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, REO_DESTINATION_INDICATION) |=
1145 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY_11,
1146 REO_DESTINATION_INDICATION,
1147 flow->reo_destination_indication);
1148
1149 /* Reset all the other fields in FSE */
1150 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_9, RESERVED_9);
1151 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_DROP);
1152 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, RESERVED_11);
1153 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_11, MSDU_COUNT);
1154 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_12, MSDU_BYTE_COUNT);
1155 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY_13, TIMESTAMP);
1156
1157 return fse;
1158 }
1159
1160 static
hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)1161 void hal_compute_reo_remap_ix2_ix3_8074v2(uint32_t *ring, uint32_t num_rings,
1162 uint32_t *remap1, uint32_t *remap2)
1163 {
1164 switch (num_rings) {
1165 case 1:
1166 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1167 HAL_REO_REMAP_IX2(ring[0], 17) |
1168 HAL_REO_REMAP_IX2(ring[0], 18) |
1169 HAL_REO_REMAP_IX2(ring[0], 19) |
1170 HAL_REO_REMAP_IX2(ring[0], 20) |
1171 HAL_REO_REMAP_IX2(ring[0], 21) |
1172 HAL_REO_REMAP_IX2(ring[0], 22) |
1173 HAL_REO_REMAP_IX2(ring[0], 23);
1174
1175 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1176 HAL_REO_REMAP_IX3(ring[0], 25) |
1177 HAL_REO_REMAP_IX3(ring[0], 26) |
1178 HAL_REO_REMAP_IX3(ring[0], 27) |
1179 HAL_REO_REMAP_IX3(ring[0], 28) |
1180 HAL_REO_REMAP_IX3(ring[0], 29) |
1181 HAL_REO_REMAP_IX3(ring[0], 30) |
1182 HAL_REO_REMAP_IX3(ring[0], 31);
1183 break;
1184 case 2:
1185 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1186 HAL_REO_REMAP_IX2(ring[0], 17) |
1187 HAL_REO_REMAP_IX2(ring[1], 18) |
1188 HAL_REO_REMAP_IX2(ring[1], 19) |
1189 HAL_REO_REMAP_IX2(ring[0], 20) |
1190 HAL_REO_REMAP_IX2(ring[0], 21) |
1191 HAL_REO_REMAP_IX2(ring[1], 22) |
1192 HAL_REO_REMAP_IX2(ring[1], 23);
1193
1194 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1195 HAL_REO_REMAP_IX3(ring[0], 25) |
1196 HAL_REO_REMAP_IX3(ring[1], 26) |
1197 HAL_REO_REMAP_IX3(ring[1], 27) |
1198 HAL_REO_REMAP_IX3(ring[0], 28) |
1199 HAL_REO_REMAP_IX3(ring[0], 29) |
1200 HAL_REO_REMAP_IX3(ring[1], 30) |
1201 HAL_REO_REMAP_IX3(ring[1], 31);
1202 break;
1203 case 3:
1204 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1205 HAL_REO_REMAP_IX2(ring[1], 17) |
1206 HAL_REO_REMAP_IX2(ring[2], 18) |
1207 HAL_REO_REMAP_IX2(ring[0], 19) |
1208 HAL_REO_REMAP_IX2(ring[1], 20) |
1209 HAL_REO_REMAP_IX2(ring[2], 21) |
1210 HAL_REO_REMAP_IX2(ring[0], 22) |
1211 HAL_REO_REMAP_IX2(ring[1], 23);
1212
1213 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
1214 HAL_REO_REMAP_IX3(ring[0], 25) |
1215 HAL_REO_REMAP_IX3(ring[1], 26) |
1216 HAL_REO_REMAP_IX3(ring[2], 27) |
1217 HAL_REO_REMAP_IX3(ring[0], 28) |
1218 HAL_REO_REMAP_IX3(ring[1], 29) |
1219 HAL_REO_REMAP_IX3(ring[2], 30) |
1220 HAL_REO_REMAP_IX3(ring[0], 31);
1221 break;
1222 case 4:
1223 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
1224 HAL_REO_REMAP_IX2(ring[1], 17) |
1225 HAL_REO_REMAP_IX2(ring[2], 18) |
1226 HAL_REO_REMAP_IX2(ring[3], 19) |
1227 HAL_REO_REMAP_IX2(ring[0], 20) |
1228 HAL_REO_REMAP_IX2(ring[1], 21) |
1229 HAL_REO_REMAP_IX2(ring[2], 22) |
1230 HAL_REO_REMAP_IX2(ring[3], 23);
1231
1232 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
1233 HAL_REO_REMAP_IX3(ring[1], 25) |
1234 HAL_REO_REMAP_IX3(ring[2], 26) |
1235 HAL_REO_REMAP_IX3(ring[3], 27) |
1236 HAL_REO_REMAP_IX3(ring[0], 28) |
1237 HAL_REO_REMAP_IX3(ring[1], 29) |
1238 HAL_REO_REMAP_IX3(ring[2], 30) |
1239 HAL_REO_REMAP_IX3(ring[3], 31);
1240 break;
1241 }
1242 }
1243
hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc * hal_soc)1244 static void hal_hw_txrx_ops_attach_qca8074v2(struct hal_soc *hal_soc)
1245 {
1246
1247 /* init and setup */
1248 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1249 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1250 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1251 hal_soc->ops->hal_reo_setup = hal_reo_setup_generic_li;
1252 hal_soc->ops->hal_get_window_address = hal_get_window_address_8074v2;
1253
1254 /* tx */
1255 hal_soc->ops->hal_tx_desc_set_dscp_tid_table_id =
1256 hal_tx_desc_set_dscp_tid_table_id_8074v2;
1257 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_8074v2;
1258 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_8074v2;
1259 hal_soc->ops->hal_tx_desc_set_lmac_id = hal_tx_desc_set_lmac_id_8074v2;
1260 hal_soc->ops->hal_tx_desc_set_buf_addr =
1261 hal_tx_desc_set_buf_addr_generic_li;
1262 hal_soc->ops->hal_tx_desc_set_search_type =
1263 hal_tx_desc_set_search_type_generic_li;
1264 hal_soc->ops->hal_tx_desc_set_search_index =
1265 hal_tx_desc_set_search_index_generic_li;
1266 hal_soc->ops->hal_tx_desc_set_cache_set_num =
1267 hal_tx_desc_set_cache_set_num_generic_li;
1268 hal_soc->ops->hal_tx_comp_get_status =
1269 hal_tx_comp_get_status_generic_li;
1270 hal_soc->ops->hal_tx_comp_get_release_reason =
1271 hal_tx_comp_get_release_reason_generic_li;
1272 hal_soc->ops->hal_get_wbm_internal_error =
1273 hal_get_wbm_internal_error_generic_li;
1274 hal_soc->ops->hal_tx_desc_set_mesh_en = hal_tx_desc_set_mesh_en_8074v2;
1275 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1276 hal_tx_init_cmd_credit_ring_8074v2;
1277
1278 /* rx */
1279 hal_soc->ops->hal_rx_msdu_start_nss_get =
1280 hal_rx_msdu_start_nss_get_8074v2;
1281 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1282 hal_rx_mon_hw_desc_get_mpdu_status_8074v2;
1283 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_8074v2;
1284 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1285 hal_rx_proc_phyrx_other_receive_info_tlv_8074v2;
1286
1287 hal_soc->ops->hal_rx_dump_msdu_end_tlv =
1288 hal_rx_dump_msdu_end_tlv_8074v2;
1289 hal_soc->ops->hal_rx_dump_rx_attention_tlv =
1290 hal_rx_dump_rx_attention_tlv_generic_li;
1291 hal_soc->ops->hal_rx_dump_msdu_start_tlv =
1292 hal_rx_dump_msdu_start_tlv_8074v2;
1293 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1294 hal_rx_dump_mpdu_start_tlv_generic_li;
1295 hal_soc->ops->hal_rx_dump_mpdu_end_tlv =
1296 hal_rx_dump_mpdu_end_tlv_generic_li;
1297 hal_soc->ops->hal_rx_dump_pkt_hdr_tlv =
1298 hal_rx_dump_pkt_hdr_tlv_generic_li;
1299
1300 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_8074v2;
1301 hal_soc->ops->hal_rx_mpdu_start_tid_get =
1302 hal_rx_mpdu_start_tid_get_8074v2;
1303 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1304 hal_rx_msdu_start_reception_type_get_8074v2;
1305 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1306 hal_rx_msdu_end_da_idx_get_8074v2;
1307 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1308 hal_rx_msdu_desc_info_get_ptr_8074v2;
1309 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1310 hal_rx_link_desc_msdu0_ptr_8074v2;
1311 hal_soc->ops->hal_reo_status_get_header =
1312 hal_reo_status_get_header_8074v2;
1313 hal_soc->ops->hal_rx_status_get_tlv_info =
1314 hal_rx_status_get_tlv_info_generic_li;
1315 hal_soc->ops->hal_rx_wbm_err_info_get =
1316 hal_rx_wbm_err_info_get_generic_li;
1317
1318 hal_soc->ops->hal_tx_set_pcp_tid_map =
1319 hal_tx_set_pcp_tid_map_generic_li;
1320 hal_soc->ops->hal_tx_update_pcp_tid_map =
1321 hal_tx_update_pcp_tid_generic_li;
1322 hal_soc->ops->hal_tx_set_tidmap_prty =
1323 hal_tx_update_tidmap_prty_generic_li;
1324 hal_soc->ops->hal_rx_get_rx_fragment_number =
1325 hal_rx_get_rx_fragment_number_8074v2;
1326 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1327 hal_rx_msdu_end_da_is_mcbc_get_8074v2;
1328 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1329 hal_rx_msdu_end_sa_is_valid_get_8074v2;
1330 hal_soc->ops->hal_rx_msdu_end_sa_idx_get =
1331 hal_rx_msdu_end_sa_idx_get_8074v2;
1332 hal_soc->ops->hal_rx_desc_is_first_msdu =
1333 hal_rx_desc_is_first_msdu_8074v2;
1334 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1335 hal_rx_msdu_end_l3_hdr_padding_get_8074v2;
1336 hal_soc->ops->hal_rx_encryption_info_valid =
1337 hal_rx_encryption_info_valid_8074v2;
1338 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_8074v2;
1339 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1340 hal_rx_msdu_end_first_msdu_get_8074v2;
1341 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1342 hal_rx_msdu_end_da_is_valid_get_8074v2;
1343 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1344 hal_rx_msdu_end_last_msdu_get_8074v2;
1345 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1346 hal_rx_get_mpdu_mac_ad4_valid_8074v2;
1347 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1348 hal_rx_mpdu_start_sw_peer_id_get_8074v2;
1349 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1350 hal_rx_mpdu_peer_meta_data_get_li;
1351 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_8074v2;
1352 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_8074v2;
1353 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1354 hal_rx_get_mpdu_frame_control_valid_8074v2;
1355 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1356 hal_rx_get_mpdu_frame_control_field_8074v2;
1357 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_8074v2;
1358 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_8074v2;
1359 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_8074v2;
1360 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_8074v2;
1361 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1362 hal_rx_get_mpdu_sequence_control_valid_8074v2;
1363 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_8074v2;
1364 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_8074v2;
1365 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1366 hal_rx_hw_desc_get_ppduid_get_8074v2;
1367 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1368 hal_rx_mpdu_start_mpdu_qos_control_valid_get_8074v2;
1369 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1370 hal_rx_msdu_end_sa_sw_peer_id_get_8074v2;
1371 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1372 hal_rx_msdu0_buffer_addr_lsb_8074v2;
1373 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1374 hal_rx_msdu_desc_info_ptr_get_8074v2;
1375 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_8074v2;
1376 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_8074v2;
1377 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_8074v2;
1378 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_8074v2;
1379 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1380 hal_rx_get_mac_addr2_valid_8074v2;
1381 hal_soc->ops->hal_rx_get_filter_category =
1382 hal_rx_get_filter_category_8074v2;
1383 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_8074v2;
1384 hal_soc->ops->hal_reo_config = hal_reo_config_8074v2;
1385 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_8074v2;
1386 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1387 hal_rx_msdu_flow_idx_invalid_8074v2;
1388 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1389 hal_rx_msdu_flow_idx_timeout_8074v2;
1390 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1391 hal_rx_msdu_fse_metadata_get_8074v2;
1392 hal_soc->ops->hal_rx_msdu_cce_match_get =
1393 hal_rx_msdu_cce_match_get_li;
1394 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1395 hal_rx_msdu_cce_metadata_get_8074v2;
1396 hal_soc->ops->hal_rx_msdu_get_flow_params =
1397 hal_rx_msdu_get_flow_params_8074v2;
1398 hal_soc->ops->hal_rx_tlv_get_tcp_chksum =
1399 hal_rx_tlv_get_tcp_chksum_8074v2;
1400 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_8074v2;
1401 #if defined(QCA_WIFI_QCA6018) && defined(WLAN_CFR_ENABLE) && \
1402 defined(WLAN_ENH_CFR_ENABLE)
1403 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_8074v2;
1404 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_8074v2;
1405 #endif
1406 /* rx - msdu fast path info fields */
1407 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1408 hal_rx_msdu_packet_metadata_get_generic_li;
1409 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1410 hal_rx_mpdu_start_tlv_tag_valid_8074v2;
1411
1412 /* rx - TLV struct offsets */
1413 hal_soc->ops->hal_rx_msdu_end_offset_get =
1414 hal_rx_msdu_end_offset_get_generic;
1415 hal_soc->ops->hal_rx_attn_offset_get = hal_rx_attn_offset_get_generic;
1416 hal_soc->ops->hal_rx_msdu_start_offset_get =
1417 hal_rx_msdu_start_offset_get_generic;
1418 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1419 hal_rx_mpdu_start_offset_get_generic;
1420 hal_soc->ops->hal_rx_mpdu_end_offset_get =
1421 hal_rx_mpdu_end_offset_get_generic;
1422 #ifndef NO_RX_PKT_HDR_TLV
1423 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1424 hal_rx_pkt_tlv_offset_get_generic;
1425 #endif
1426 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_8074v2;
1427 hal_soc->ops->hal_rx_flow_get_tuple_info =
1428 hal_rx_flow_get_tuple_info_li;
1429 hal_soc->ops->hal_rx_flow_delete_entry =
1430 hal_rx_flow_delete_entry_li;
1431 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_li;
1432 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1433 hal_compute_reo_remap_ix2_ix3_8074v2;
1434 hal_soc->ops->hal_setup_link_idle_list =
1435 hal_setup_link_idle_list_generic_li;
1436 hal_soc->ops->hal_rx_tlv_get_pn_num = hal_rx_tlv_get_pn_num_li;
1437 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_li;
1438 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1439 hal_rx_tlv_decrypt_err_get_li;
1440 hal_soc->ops->hal_rx_tlv_get_pkt_capture_flags =
1441 hal_rx_tlv_get_pkt_capture_flags_li;
1442 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1443 hal_rx_mpdu_info_ampdu_flag_get_li;
1444 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1445 };
1446
1447 struct hal_hw_srng_config hw_srng_table_8074v2[] = {
1448 /* TODO: max_rings can populated by querying HW capabilities */
1449 { /* REO_DST */
1450 .start_ring_id = HAL_SRNG_REO2SW1,
1451 .max_rings = 4,
1452 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1453 .lmac_ring = FALSE,
1454 .ring_dir = HAL_SRNG_DST_RING,
1455 .reg_start = {
1456 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1457 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1458 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1459 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1460 },
1461 .reg_size = {
1462 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1463 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1464 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1465 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1466 },
1467 .max_size =
1468 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1469 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1470 },
1471 { /* REO_EXCEPTION */
1472 /* Designating REO2TCL ring as exception ring. This ring is
1473 * similar to other REO2SW rings though it is named as REO2TCL.
1474 * Any of theREO2SW rings can be used as exception ring.
1475 */
1476 .start_ring_id = HAL_SRNG_REO2TCL,
1477 .max_rings = 1,
1478 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1479 .lmac_ring = FALSE,
1480 .ring_dir = HAL_SRNG_DST_RING,
1481 .reg_start = {
1482 HWIO_REO_R0_REO2TCL_RING_BASE_LSB_ADDR(
1483 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1484 HWIO_REO_R2_REO2TCL_RING_HP_ADDR(
1485 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1486 },
1487 /* Single ring - provide ring size if multiple rings of this
1488 * type are supported
1489 */
1490 .reg_size = {},
1491 .max_size =
1492 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_BMSK >>
1493 HWIO_REO_R0_REO2TCL_RING_BASE_MSB_RING_SIZE_SHFT,
1494 },
1495 { /* REO_REINJECT */
1496 .start_ring_id = HAL_SRNG_SW2REO,
1497 .max_rings = 1,
1498 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1499 .lmac_ring = FALSE,
1500 .ring_dir = HAL_SRNG_SRC_RING,
1501 .reg_start = {
1502 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1503 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1504 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1505 SEQ_WCSS_UMAC_REO_REG_OFFSET)
1506 },
1507 /* Single ring - provide ring size if multiple rings of this
1508 * type are supported
1509 */
1510 .reg_size = {},
1511 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1512 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1513 },
1514 { /* REO_CMD */
1515 .start_ring_id = HAL_SRNG_REO_CMD,
1516 .max_rings = 1,
1517 .entry_size = (sizeof(struct tlv_32_hdr) +
1518 sizeof(struct reo_get_queue_stats)) >> 2,
1519 .lmac_ring = FALSE,
1520 .ring_dir = HAL_SRNG_SRC_RING,
1521 .reg_start = {
1522 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1523 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1524 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1525 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1526 },
1527 /* Single ring - provide ring size if multiple rings of this
1528 * type are supported
1529 */
1530 .reg_size = {},
1531 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1532 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1533 },
1534 { /* REO_STATUS */
1535 .start_ring_id = HAL_SRNG_REO_STATUS,
1536 .max_rings = 1,
1537 .entry_size = (sizeof(struct tlv_32_hdr) +
1538 sizeof(struct reo_get_queue_stats_status)) >> 2,
1539 .lmac_ring = FALSE,
1540 .ring_dir = HAL_SRNG_DST_RING,
1541 .reg_start = {
1542 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1543 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1544 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1545 SEQ_WCSS_UMAC_REO_REG_OFFSET),
1546 },
1547 /* Single ring - provide ring size if multiple rings of this
1548 * type are supported
1549 */
1550 .reg_size = {},
1551 .max_size =
1552 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1553 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1554 },
1555 { /* TCL_DATA */
1556 .start_ring_id = HAL_SRNG_SW2TCL1,
1557 .max_rings = 3,
1558 .entry_size = (sizeof(struct tlv_32_hdr) +
1559 sizeof(struct tcl_data_cmd)) >> 2,
1560 .lmac_ring = FALSE,
1561 .ring_dir = HAL_SRNG_SRC_RING,
1562 .reg_start = {
1563 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1564 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1565 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1566 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1567 },
1568 .reg_size = {
1569 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1570 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1571 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1572 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1573 },
1574 .max_size =
1575 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1576 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1577 },
1578 { /* TCL_CMD */
1579 /* qca8074v2 and qcn9000 uses this ring for data commands */
1580 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1581 .max_rings = 1,
1582 .entry_size = (sizeof(struct tlv_32_hdr) +
1583 sizeof(struct tcl_data_cmd)) >> 2,
1584 .lmac_ring = FALSE,
1585 .ring_dir = HAL_SRNG_SRC_RING,
1586 .reg_start = {
1587 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_LSB_ADDR(
1588 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1589 HWIO_TCL_R2_SW2TCL_CMD_RING_HP_ADDR(
1590 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1591 },
1592 /* Single ring - provide ring size if multiple rings of this
1593 * type are supported
1594 */
1595 .reg_size = {},
1596 .max_size =
1597 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1598 HWIO_TCL_R0_SW2TCL_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1599 },
1600 { /* TCL_STATUS */
1601 .start_ring_id = HAL_SRNG_TCL_STATUS,
1602 .max_rings = 1,
1603 .entry_size = (sizeof(struct tlv_32_hdr) +
1604 sizeof(struct tcl_status_ring)) >> 2,
1605 .lmac_ring = FALSE,
1606 .ring_dir = HAL_SRNG_DST_RING,
1607 .reg_start = {
1608 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1609 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1610 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1611 SEQ_WCSS_UMAC_MAC_TCL_REG_OFFSET),
1612 },
1613 /* Single ring - provide ring size if multiple rings of this
1614 * type are supported
1615 */
1616 .reg_size = {},
1617 .max_size =
1618 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1619 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1620 },
1621 { /* CE_SRC */
1622 .start_ring_id = HAL_SRNG_CE_0_SRC,
1623 .max_rings = 12,
1624 .entry_size = sizeof(struct ce_src_desc) >> 2,
1625 .lmac_ring = FALSE,
1626 .ring_dir = HAL_SRNG_SRC_RING,
1627 .reg_start = {
1628 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1629 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1630 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1631 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET),
1632 },
1633 .reg_size = {
1634 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1635 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1636 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_SRC_REG_OFFSET -
1637 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_SRC_REG_OFFSET,
1638 },
1639 .max_size =
1640 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1641 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1642 },
1643 { /* CE_DST */
1644 .start_ring_id = HAL_SRNG_CE_0_DST,
1645 .max_rings = 12,
1646 .entry_size = 8 >> 2,
1647 /*TODO: entry_size above should actually be
1648 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1649 * of struct ce_dst_desc in HW header files
1650 */
1651 .lmac_ring = FALSE,
1652 .ring_dir = HAL_SRNG_SRC_RING,
1653 .reg_start = {
1654 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1655 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1656 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1657 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1658 },
1659 .reg_size = {
1660 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1661 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1662 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1663 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1664 },
1665 .max_size =
1666 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1667 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1668 },
1669 { /* CE_DST_STATUS */
1670 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1671 .max_rings = 12,
1672 .entry_size = sizeof(struct ce_stat_desc) >> 2,
1673 .lmac_ring = FALSE,
1674 .ring_dir = HAL_SRNG_DST_RING,
1675 .reg_start = {
1676 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
1677 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1678 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
1679 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET),
1680 },
1681 /* TODO: check destination status ring registers */
1682 .reg_size = {
1683 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1684 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1685 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_1_CHANNEL_DST_REG_OFFSET -
1686 SEQ_WCSS_UMAC_WFSS_CE_0_REG_WFSS_CE_0_CHANNEL_DST_REG_OFFSET,
1687 },
1688 .max_size =
1689 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1690 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1691 },
1692 { /* WBM_IDLE_LINK */
1693 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
1694 .max_rings = 1,
1695 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
1696 .lmac_ring = FALSE,
1697 .ring_dir = HAL_SRNG_SRC_RING,
1698 .reg_start = {
1699 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1700 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1701 },
1702 /* Single ring - provide ring size if multiple rings of this
1703 * type are supported
1704 */
1705 .reg_size = {},
1706 .max_size =
1707 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
1708 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
1709 },
1710 { /* SW2WBM_RELEASE */
1711 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
1712 .max_rings = 1,
1713 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1714 .lmac_ring = FALSE,
1715 .ring_dir = HAL_SRNG_SRC_RING,
1716 .reg_start = {
1717 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1718 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1719 },
1720 /* Single ring - provide ring size if multiple rings of this
1721 * type are supported
1722 */
1723 .reg_size = {},
1724 .max_size =
1725 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1726 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1727 },
1728 { /* WBM2SW_RELEASE */
1729 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
1730 .max_rings = 5,
1731 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1732 .lmac_ring = FALSE,
1733 .ring_dir = HAL_SRNG_DST_RING,
1734 .reg_start = {
1735 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1736 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1737 },
1738 .reg_size = {
1739 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1740 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1741 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET) -
1742 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(SEQ_WCSS_UMAC_WBM_REG_OFFSET),
1743 },
1744 .max_size =
1745 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1746 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1747 },
1748 { /* RXDMA_BUF */
1749 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
1750 #ifdef IPA_OFFLOAD
1751 .max_rings = 3,
1752 #else
1753 .max_rings = 2,
1754 #endif
1755 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1756 .lmac_ring = TRUE,
1757 .ring_dir = HAL_SRNG_SRC_RING,
1758 /* reg_start is not set because LMAC rings are not accessed
1759 * from host
1760 */
1761 .reg_start = {},
1762 .reg_size = {},
1763 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1764 },
1765 { /* RXDMA_DST */
1766 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
1767 .max_rings = 1,
1768 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1769 .lmac_ring = TRUE,
1770 .ring_dir = HAL_SRNG_DST_RING,
1771 /* reg_start is not set because LMAC rings are not accessed
1772 * from host
1773 */
1774 .reg_start = {},
1775 .reg_size = {},
1776 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1777 },
1778 { /* RXDMA_MONITOR_BUF */
1779 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
1780 .max_rings = 1,
1781 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1782 .lmac_ring = TRUE,
1783 .ring_dir = HAL_SRNG_SRC_RING,
1784 /* reg_start is not set because LMAC rings are not accessed
1785 * from host
1786 */
1787 .reg_start = {},
1788 .reg_size = {},
1789 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1790 },
1791 { /* RXDMA_MONITOR_STATUS */
1792 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
1793 .max_rings = 1,
1794 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1795 .lmac_ring = TRUE,
1796 .ring_dir = HAL_SRNG_SRC_RING,
1797 /* reg_start is not set because LMAC rings are not accessed
1798 * from host
1799 */
1800 .reg_start = {},
1801 .reg_size = {},
1802 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1803 },
1804 { /* RXDMA_MONITOR_DST */
1805 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW1,
1806 .max_rings = 1,
1807 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1808 .lmac_ring = TRUE,
1809 .ring_dir = HAL_SRNG_DST_RING,
1810 /* reg_start is not set because LMAC rings are not accessed
1811 * from host
1812 */
1813 .reg_start = {},
1814 .reg_size = {},
1815 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1816 },
1817 { /* RXDMA_MONITOR_DESC */
1818 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
1819 .max_rings = 1,
1820 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1821 .lmac_ring = TRUE,
1822 .ring_dir = HAL_SRNG_SRC_RING,
1823 /* reg_start is not set because LMAC rings are not accessed
1824 * from host
1825 */
1826 .reg_start = {},
1827 .reg_size = {},
1828 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1829 },
1830 { /* DIR_BUF_RX_DMA_SRC */
1831 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
1832 /* one ring for spectral and one ring for cfr */
1833 .max_rings = 2,
1834 .entry_size = 2,
1835 .lmac_ring = TRUE,
1836 .ring_dir = HAL_SRNG_SRC_RING,
1837 /* reg_start is not set because LMAC rings are not accessed
1838 * from host
1839 */
1840 .reg_start = {},
1841 .reg_size = {},
1842 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1843 },
1844 #ifdef WLAN_FEATURE_CIF_CFR
1845 { /* WIFI_POS_SRC */
1846 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
1847 .max_rings = 1,
1848 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
1849 .lmac_ring = TRUE,
1850 .ring_dir = HAL_SRNG_SRC_RING,
1851 /* reg_start is not set because LMAC rings are not accessed
1852 * from host
1853 */
1854 .reg_start = {},
1855 .reg_size = {},
1856 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1857 },
1858 #endif
1859 { /* REO2PPE */ 0},
1860 { /* PPE2TCL */ 0},
1861 { /* PPE_RELEASE */ 0},
1862 { /* TX_MONITOR_BUF */ 0},
1863 { /* TX_MONITOR_DST */ 0},
1864 { /* SW2RXDMA_NEW */ 0},
1865 { /* SW2RXDMA_LINK_RELEASE */ 0},
1866 };
1867
1868
1869 /**
1870 * hal_qca8074v2_attach() - Attach 8074v2 target specific hal_soc ops,
1871 * offset and srng table
1872 * @hal_soc: HAL SoC context
1873 */
hal_qca8074v2_attach(struct hal_soc * hal_soc)1874 void hal_qca8074v2_attach(struct hal_soc *hal_soc)
1875 {
1876 hal_soc->hw_srng_table = hw_srng_table_8074v2;
1877 hal_srng_hw_reg_offset_init_generic(hal_soc);
1878 hal_hw_txrx_default_ops_attach_li(hal_soc);
1879 hal_hw_txrx_ops_attach_qca8074v2(hal_soc);
1880 }
1881