1 /*
2 * Copyright (c) 2021 The Linux Foundation. All rights reserved.
3 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE
16 */
17 #include "qdf_types.h"
18 #include "qdf_util.h"
19 #include "qdf_mem.h"
20 #include "qdf_nbuf.h"
21 #include "qdf_module.h"
22
23 #include "target_type.h"
24 #include "wcss_version.h"
25
26 #include "hal_be_hw_headers.h"
27 #include "hal_internal.h"
28 #include "hal_api.h"
29 #include "hal_flow.h"
30 #include "rx_flow_search_entry.h"
31 #include "hal_rx_flow_info.h"
32 #include "hal_be_api.h"
33 #include "tcl_entrance_from_ppe_ring.h"
34 #include "sw_monitor_ring.h"
35 #include "wcss_seq_hwioreg_umac.h"
36 #include "wfss_ce_reg_seq_hwioreg.h"
37 #include <uniform_reo_status_header.h>
38 #include <wbm_release_ring_tx.h>
39 #include <phyrx_location.h>
40 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || \
41 defined(WLAN_PKT_CAPTURE_RX_2_0)
42 #include <mon_ingress_ring.h>
43 #include <mon_destination_ring.h>
44 #endif
45 #include "rx_reo_queue_1k.h"
46
47 #include <hal_be_rx.h>
48
49 #define UNIFIED_RX_MPDU_START_0_RX_MPDU_INFO_RX_MPDU_INFO_DETAILS_OFFSET \
50 RX_MPDU_START_RX_MPDU_INFO_DETAILS_RXPCU_MPDU_FILTER_IN_CATEGORY_OFFSET
51 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
52 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
53 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
54 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
55 #define UNIFIED_RX_MPDU_DETAILS_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
56 RX_MPDU_DETAILS_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
57 #define UNIFIED_REO_DESTINATION_RING_2_RX_MPDU_DESC_INFO_RX_MPDU_DESC_INFO_DETAILS_OFFSET \
58 REO_DESTINATION_RING_RX_MPDU_DESC_INFO_DETAILS_MSDU_COUNT_OFFSET
59 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER \
60 STATUS_HEADER_REO_STATUS_NUMBER
61 #define UNIFORM_REO_STATUS_HEADER_STATUS_HEADER_GENERIC \
62 STATUS_HEADER_TIMESTAMP
63 #define UNIFIED_RX_MSDU_DETAILS_2_RX_MSDU_DESC_INFO_RX_MSDU_DESC_INFO_DETAILS_OFFSET \
64 RX_MSDU_DETAILS_RX_MSDU_DESC_INFO_DETAILS_FIRST_MSDU_IN_MPDU_FLAG_OFFSET
65 #define UNIFIED_RX_MSDU_LINK_8_RX_MSDU_DETAILS_MSDU_0_OFFSET \
66 RX_MSDU_LINK_MSDU_BUFFER_ADDR_INFO_DETAILS_BUFFER_ADDR_31_0_OFFSET
67 #define UNIFIED_TCL_DATA_CMD_0_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
68 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_31_0_OFFSET
69 #define UNIFIED_TCL_DATA_CMD_1_BUFFER_ADDR_INFO_BUF_ADDR_INFO_OFFSET \
70 TCL_DATA_CMD_BUF_ADDR_INFO_BUFFER_ADDR_39_32_OFFSET
71 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_OFFSET \
72 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_OFFSET
73 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_LSB \
74 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_LSB
75 #define UNIFIED_BUFFER_ADDR_INFO_0_BUFFER_ADDR_31_0_MASK \
76 BUFFER_ADDR_INFO_BUFFER_ADDR_31_0_MASK
77 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_LSB \
78 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_LSB
79 #define UNIFIED_BUFFER_ADDR_INFO_1_BUFFER_ADDR_39_32_MASK \
80 BUFFER_ADDR_INFO_BUFFER_ADDR_39_32_MASK
81 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_LSB \
82 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_LSB
83 #define UNIFIED_BUFFER_ADDR_INFO_1_RETURN_BUFFER_MANAGER_MASK \
84 BUFFER_ADDR_INFO_RETURN_BUFFER_MANAGER_MASK
85 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_LSB \
86 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_LSB
87 #define UNIFIED_BUFFER_ADDR_INFO_1_SW_BUFFER_COOKIE_MASK \
88 BUFFER_ADDR_INFO_SW_BUFFER_COOKIE_MASK
89 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_LSB \
90 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_LSB
91 #define UNIFIED_TCL_DATA_CMD_2_BUF_OR_EXT_DESC_TYPE_MASK \
92 TCL_DATA_CMD_BUF_OR_EXT_DESC_TYPE_MASK
93 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_MASK \
94 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_MASK
95 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_OFFSET \
96 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_OFFSET
97 #define UNIFIED_WBM_RELEASE_RING_6_TX_RATE_STATS_INFO_TX_RATE_STATS_LSB \
98 WBM_RELEASE_RING_TX_TX_RATE_STATS_PPDU_TRANSMISSION_TSF_LSB
99
100 #if defined(WLAN_PKT_CAPTURE_TX_2_0) || defined(WLAN_PKT_CAPTURE_RX_2_0)
101 #include "hal_be_api_mon.h"
102 #endif
103
104 #define CMEM_REG_BASE 0x00100000
105
106 /* For Berryllium sw2rxdma ring size increased to 20 bits */
107 #define HAL_RXDMA_MAX_RING_SIZE_BE 0xFFFFF
108
109 #include "hal_5332_rx.h"
110 #include "hal_5332_tx.h"
111 #include "hal_be_rx_tlv.h"
112 #include <hal_be_generic_api.h>
113
114
115 /**
116 * hal_read_pmm_scratch_reg_5332() - API to read PMM Scratch register
117 *
118 * @soc: HAL soc
119 * @reg_enum: Enum of the scratch register
120 *
121 * Return: uint32_t
122 */
123 static inline
hal_read_pmm_scratch_reg_5332(struct hal_soc * soc,enum hal_scratch_reg_enum reg_enum)124 uint32_t hal_read_pmm_scratch_reg_5332(struct hal_soc *soc,
125 enum hal_scratch_reg_enum reg_enum)
126 {
127 uint32_t val = 0;
128
129 pld_reg_read(soc->qdf_dev->dev, (reg_enum * 4), &val,
130 soc->dev_base_addr_pmm);
131 return val;
132 }
133
134 /**
135 * hal_get_tsf2_scratch_reg_qca5332() - API to read tsf2 scratch register
136 *
137 * @hal_soc_hdl: HAL soc context
138 * @mac_id: mac id
139 * @value: Pointer to update tsf2 value
140 *
141 * Return: void
142 */
hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,uint8_t mac_id,uint64_t * value)143 static void hal_get_tsf2_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
144 uint8_t mac_id, uint64_t *value)
145 {
146 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
147 uint32_t offset_lo, offset_hi;
148 enum hal_scratch_reg_enum enum_lo, enum_hi;
149
150 hal_get_tsf_enum(DEFAULT_TSF_ID, mac_id, &enum_lo, &enum_hi);
151
152 offset_lo = hal_read_pmm_scratch_reg_5332(soc,
153 enum_lo);
154
155 offset_hi = hal_read_pmm_scratch_reg_5332(soc,
156 enum_hi);
157
158 *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
159 }
160
161 /**
162 * hal_get_tqm_scratch_reg_qca5332() - API to read tqm scratch register
163 *
164 * @hal_soc_hdl: HAL soc context
165 * @value: Pointer to update tqm value
166 *
167 * Return: void
168 */
hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,uint64_t * value)169 static void hal_get_tqm_scratch_reg_qca5332(hal_soc_handle_t hal_soc_hdl,
170 uint64_t *value)
171 {
172 struct hal_soc *soc = (struct hal_soc *)hal_soc_hdl;
173 uint32_t offset_lo, offset_hi;
174
175 offset_lo = hal_read_pmm_scratch_reg_5332(soc,
176 PMM_TQM_CLOCK_OFFSET_LO_US);
177
178 offset_hi = hal_read_pmm_scratch_reg_5332(soc,
179 PMM_TQM_CLOCK_OFFSET_HI_US);
180
181 *value = ((uint64_t)(offset_hi) << 32 | offset_lo);
182 }
183
184 #define LINK_DESC_SIZE (NUM_OF_DWORDS_RX_MSDU_LINK << 2)
185 #define HAL_PPE_VP_ENTRIES_MAX 32
186 /**
187 * hal_get_link_desc_size_5332() - API to get the link desc size
188 *
189 * Return: uint32_t
190 */
hal_get_link_desc_size_5332(void)191 static uint32_t hal_get_link_desc_size_5332(void)
192 {
193 return LINK_DESC_SIZE;
194 }
195
196 /**
197 * hal_rx_get_tlv_5332() - API to get the tlv
198 *
199 * @rx_tlv: TLV data extracted from the rx packet
200 * Return: uint8_t
201 */
hal_rx_get_tlv_5332(void * rx_tlv)202 static uint8_t hal_rx_get_tlv_5332(void *rx_tlv)
203 {
204 return HAL_RX_GET(rx_tlv, PHYRX_RSSI_LEGACY, RECEIVE_BANDWIDTH);
205 }
206
207 /**
208 * hal_rx_wbm_err_msdu_continuation_get_5332() - API to check if WBM
209 * msdu continuation bit is set
210 *
211 * @wbm_desc: wbm release ring descriptor
212 *
213 * Return: true if msdu continuation bit is set.
214 */
hal_rx_wbm_err_msdu_continuation_get_5332(void * wbm_desc)215 uint8_t hal_rx_wbm_err_msdu_continuation_get_5332(void *wbm_desc)
216 {
217 uint32_t comp_desc = *(uint32_t *)(((uint8_t *)wbm_desc) +
218 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_OFFSET);
219
220 return (comp_desc &
221 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_MASK) >>
222 WBM_RELEASE_RING_RX_RX_MSDU_DESC_INFO_DETAILS_MSDU_CONTINUATION_LSB;
223 }
224
225 /**
226 * hal_rx_proc_phyrx_other_receive_info_tlv_5332() - API to get tlv info
227 * @rx_tlv_hdr: start address of rx_pkt_tlvs
228 * @ppdu_info_hdl: PPDU info handle to fill
229 *
230 * Return: uint32_t
231 */
232 static inline
hal_rx_proc_phyrx_other_receive_info_tlv_5332(void * rx_tlv_hdr,void * ppdu_info_hdl)233 void hal_rx_proc_phyrx_other_receive_info_tlv_5332(void *rx_tlv_hdr,
234 void *ppdu_info_hdl)
235 {
236 uint32_t tlv_tag, tlv_len;
237 uint32_t temp_len, other_tlv_len, other_tlv_tag;
238 void *rx_tlv = (uint8_t *)rx_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
239 void *other_tlv_hdr = NULL;
240 void *other_tlv = NULL;
241
242 tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(rx_tlv_hdr);
243 tlv_len = HAL_RX_GET_USER_TLV32_LEN(rx_tlv_hdr);
244 temp_len = 0;
245
246 other_tlv_hdr = rx_tlv + HAL_RX_TLV32_HDR_SIZE;
247 other_tlv_tag = HAL_RX_GET_USER_TLV32_TYPE(other_tlv_hdr);
248 other_tlv_len = HAL_RX_GET_USER_TLV32_LEN(other_tlv_hdr);
249
250 temp_len += other_tlv_len;
251 other_tlv = other_tlv_hdr + HAL_RX_TLV32_HDR_SIZE;
252
253 switch (other_tlv_tag) {
254 default:
255 QDF_TRACE(QDF_MODULE_ID_DP, QDF_TRACE_LEVEL_ERROR,
256 "%s unhandled TLV type: %d, TLV len:%d",
257 __func__, other_tlv_tag, other_tlv_len);
258 break;
259 }
260 }
261
262 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
263 static inline
hal_rx_get_bb_info_5332(void * rx_tlv,void * ppdu_info_hdl)264 void hal_rx_get_bb_info_5332(void *rx_tlv, void *ppdu_info_hdl)
265 {
266 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
267
268 ppdu_info->cfr_info.bb_captured_channel =
269 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_CHANNEL);
270
271 ppdu_info->cfr_info.bb_captured_timeout =
272 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_TIMEOUT);
273
274 ppdu_info->cfr_info.bb_captured_reason =
275 HAL_RX_GET_64(rx_tlv, RXPCU_PPDU_END_INFO, BB_CAPTURED_REASON);
276 }
277
278 static inline
hal_rx_get_rtt_info_5332(void * rx_tlv,void * ppdu_info_hdl)279 void hal_rx_get_rtt_info_5332(void *rx_tlv, void *ppdu_info_hdl)
280 {
281 struct hal_rx_ppdu_info *ppdu_info = ppdu_info_hdl;
282
283 ppdu_info->cfr_info.rx_location_info_valid =
284 HAL_RX_GET_64(rx_tlv, PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
285 RX_LOCATION_INFO_VALID);
286
287 ppdu_info->cfr_info.rtt_che_buffer_pointer_low32 =
288 HAL_RX_GET_64(rx_tlv,
289 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
290 RTT_CHE_BUFFER_POINTER_LOW32);
291
292 ppdu_info->cfr_info.rtt_che_buffer_pointer_high8 =
293 HAL_RX_GET_64(rx_tlv,
294 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
295 RTT_CHE_BUFFER_POINTER_HIGH8);
296
297 ppdu_info->cfr_info.chan_capture_status =
298 HAL_GET_RX_LOCATION_INFO_CHAN_CAPTURE_STATUS(rx_tlv);
299
300 ppdu_info->cfr_info.rx_start_ts =
301 HAL_RX_GET_64(rx_tlv,
302 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
303 RX_START_TS);
304
305 ppdu_info->cfr_info.rtt_cfo_measurement = (int16_t)
306 HAL_RX_GET_64(rx_tlv,
307 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
308 RTT_CFO_MEASUREMENT);
309
310 ppdu_info->cfr_info.agc_gain_info0 =
311 HAL_RX_GET_64(rx_tlv,
312 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
313 GAIN_CHAIN0);
314
315 ppdu_info->cfr_info.agc_gain_info0 |=
316 (((uint32_t)HAL_RX_GET_64(rx_tlv,
317 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
318 GAIN_CHAIN1)) << 16);
319
320 ppdu_info->cfr_info.agc_gain_info1 =
321 HAL_RX_GET_64(rx_tlv,
322 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
323 GAIN_CHAIN2);
324
325 ppdu_info->cfr_info.agc_gain_info1 |=
326 (((uint32_t)HAL_RX_GET_64(rx_tlv,
327 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
328 GAIN_CHAIN3)) << 16);
329
330 ppdu_info->cfr_info.agc_gain_info2 = 0;
331
332 ppdu_info->cfr_info.agc_gain_info3 = 0;
333
334 ppdu_info->cfr_info.mcs_rate =
335 HAL_RX_GET_64(rx_tlv,
336 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
337 RTT_MCS_RATE);
338
339 ppdu_info->cfr_info.gi_type =
340 HAL_RX_GET_64(rx_tlv,
341 PHYRX_LOCATION_RX_LOCATION_INFO_DETAILS,
342 RTT_GI_TYPE);
343 }
344 #endif
345 #ifdef CONFIG_WORD_BASED_TLV
346 /**
347 * hal_rx_dump_mpdu_start_tlv_5332() - dump RX mpdu_start TLV in structured
348 * human readable format.
349 * @mpdustart: pointer the rx_attention TLV in pkt.
350 * @dbg_level: log level.
351 *
352 * Return: void
353 */
hal_rx_dump_mpdu_start_tlv_5332(void * mpdustart,uint8_t dbg_level)354 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
355 uint8_t dbg_level)
356 {
357 struct rx_mpdu_start_compact *mpdu_info =
358 (struct rx_mpdu_start_compact *)mpdustart;
359
360 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
361 "rx_mpdu_start tlv (1/5) - "
362 "rx_reo_queue_desc_addr_39_32 :%x"
363 "receive_queue_number:%x "
364 "pre_delim_err_warning:%x "
365 "first_delim_err:%x "
366 "pn_31_0:%x "
367 "pn_63_32:%x "
368 "pn_95_64:%x ",
369 mpdu_info->rx_reo_queue_desc_addr_39_32,
370 mpdu_info->receive_queue_number,
371 mpdu_info->pre_delim_err_warning,
372 mpdu_info->first_delim_err,
373 mpdu_info->pn_31_0,
374 mpdu_info->pn_63_32,
375 mpdu_info->pn_95_64);
376
377 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
378 "rx_mpdu_start tlv (2/5) - "
379 "ast_index:%x "
380 "sw_peer_id:%x "
381 "mpdu_frame_control_valid:%x "
382 "mpdu_duration_valid:%x "
383 "mac_addr_ad1_valid:%x "
384 "mac_addr_ad2_valid:%x "
385 "mac_addr_ad3_valid:%x "
386 "mac_addr_ad4_valid:%x "
387 "mpdu_sequence_control_valid :%x"
388 "mpdu_qos_control_valid:%x "
389 "mpdu_ht_control_valid:%x "
390 "frame_encryption_info_valid :%x",
391 mpdu_info->ast_index,
392 mpdu_info->sw_peer_id,
393 mpdu_info->mpdu_frame_control_valid,
394 mpdu_info->mpdu_duration_valid,
395 mpdu_info->mac_addr_ad1_valid,
396 mpdu_info->mac_addr_ad2_valid,
397 mpdu_info->mac_addr_ad3_valid,
398 mpdu_info->mac_addr_ad4_valid,
399 mpdu_info->mpdu_sequence_control_valid,
400 mpdu_info->mpdu_qos_control_valid,
401 mpdu_info->mpdu_ht_control_valid,
402 mpdu_info->frame_encryption_info_valid);
403
404 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
405 "rx_mpdu_start tlv (3/5) - "
406 "mpdu_fragment_number:%x "
407 "more_fragment_flag:%x "
408 "fr_ds:%x "
409 "to_ds:%x "
410 "encrypted:%x "
411 "mpdu_retry:%x "
412 "mpdu_sequence_number:%x ",
413 mpdu_info->mpdu_fragment_number,
414 mpdu_info->more_fragment_flag,
415 mpdu_info->fr_ds,
416 mpdu_info->to_ds,
417 mpdu_info->encrypted,
418 mpdu_info->mpdu_retry,
419 mpdu_info->mpdu_sequence_number);
420
421 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
422 "rx_mpdu_start tlv (4/5) - "
423 "mpdu_frame_control_field:%x "
424 "mpdu_duration_field:%x ",
425 mpdu_info->mpdu_frame_control_field,
426 mpdu_info->mpdu_duration_field);
427
428 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
429 "rx_mpdu_start tlv (5/5) - "
430 "mac_addr_ad1_31_0:%x "
431 "mac_addr_ad1_47_32:%x "
432 "mac_addr_ad2_15_0:%x "
433 "mac_addr_ad2_47_16:%x "
434 "mac_addr_ad3_31_0:%x "
435 "mac_addr_ad3_47_32:%x "
436 "mpdu_sequence_control_field :%x",
437 mpdu_info->mac_addr_ad1_31_0,
438 mpdu_info->mac_addr_ad1_47_32,
439 mpdu_info->mac_addr_ad2_15_0,
440 mpdu_info->mac_addr_ad2_47_16,
441 mpdu_info->mac_addr_ad3_31_0,
442 mpdu_info->mac_addr_ad3_47_32,
443 mpdu_info->mpdu_sequence_control_field);
444 }
445
446 /**
447 * hal_rx_dump_msdu_end_tlv_5332() - dump RX msdu_end TLV in structured
448 * human readable format.
449 * @msduend: pointer the msdu_end TLV in pkt.
450 * @dbg_level: log level.
451 *
452 * Return: void
453 */
hal_rx_dump_msdu_end_tlv_5332(void * msduend,uint8_t dbg_level)454 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
455 uint8_t dbg_level)
456 {
457 struct rx_msdu_end_compact *msdu_end =
458 (struct rx_msdu_end_compact *)msduend;
459
460 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
461 "rx_msdu_end tlv - "
462 "key_id_octet: %d "
463 "tcp_udp_chksum: %d "
464 "sa_idx_timeout: %d "
465 "da_idx_timeout: %d "
466 "msdu_limit_error: %d "
467 "flow_idx_timeout: %d "
468 "flow_idx_invalid: %d "
469 "wifi_parser_error: %d "
470 "sa_is_valid: %d "
471 "da_is_valid: %d "
472 "da_is_mcbc: %d "
473 "tkip_mic_err: %d "
474 "l3_header_padding: %d "
475 "first_msdu: %d "
476 "last_msdu: %d "
477 "sa_idx: %d "
478 "msdu_drop: %d "
479 "reo_destination_indication: %d "
480 "flow_idx: %d "
481 "fse_metadata: %d "
482 "cce_metadata: %d "
483 "sa_sw_peer_id: %d ",
484 msdu_end->key_id_octet,
485 msdu_end->tcp_udp_chksum,
486 msdu_end->sa_idx_timeout,
487 msdu_end->da_idx_timeout,
488 msdu_end->msdu_limit_error,
489 msdu_end->flow_idx_timeout,
490 msdu_end->flow_idx_invalid,
491 msdu_end->wifi_parser_error,
492 msdu_end->sa_is_valid,
493 msdu_end->da_is_valid,
494 msdu_end->da_is_mcbc,
495 msdu_end->tkip_mic_err,
496 msdu_end->l3_header_padding,
497 msdu_end->first_msdu,
498 msdu_end->last_msdu,
499 msdu_end->sa_idx,
500 msdu_end->msdu_drop,
501 msdu_end->reo_destination_indication,
502 msdu_end->flow_idx,
503 msdu_end->fse_metadata,
504 msdu_end->cce_metadata,
505 msdu_end->sa_sw_peer_id);
506 }
507 #else
hal_rx_dump_mpdu_start_tlv_5332(void * mpdustart,uint8_t dbg_level)508 static inline void hal_rx_dump_mpdu_start_tlv_5332(void *mpdustart,
509 uint8_t dbg_level)
510 {
511 struct rx_mpdu_start *mpdu_start = (struct rx_mpdu_start *)mpdustart;
512 struct rx_mpdu_info *mpdu_info =
513 (struct rx_mpdu_info *)&mpdu_start->rx_mpdu_info_details;
514
515 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
516 "rx_mpdu_start tlv (1/5) - "
517 "rx_reo_queue_desc_addr_31_0 :%x"
518 "rx_reo_queue_desc_addr_39_32 :%x"
519 "receive_queue_number:%x "
520 "pre_delim_err_warning:%x "
521 "first_delim_err:%x "
522 "reserved_2a:%x "
523 "pn_31_0:%x "
524 "pn_63_32:%x "
525 "pn_95_64:%x "
526 "pn_127_96:%x "
527 "epd_en:%x "
528 "all_frames_shall_be_encrypted :%x"
529 "encrypt_type:%x "
530 "wep_key_width_for_variable_key :%x"
531 "mesh_sta:%x "
532 "bssid_hit:%x "
533 "bssid_number:%x "
534 "tid:%x "
535 "reserved_7a:%x ",
536 mpdu_info->rx_reo_queue_desc_addr_31_0,
537 mpdu_info->rx_reo_queue_desc_addr_39_32,
538 mpdu_info->receive_queue_number,
539 mpdu_info->pre_delim_err_warning,
540 mpdu_info->first_delim_err,
541 mpdu_info->reserved_2a,
542 mpdu_info->pn_31_0,
543 mpdu_info->pn_63_32,
544 mpdu_info->pn_95_64,
545 mpdu_info->pn_127_96,
546 mpdu_info->epd_en,
547 mpdu_info->all_frames_shall_be_encrypted,
548 mpdu_info->encrypt_type,
549 mpdu_info->wep_key_width_for_variable_key,
550 mpdu_info->mesh_sta,
551 mpdu_info->bssid_hit,
552 mpdu_info->bssid_number,
553 mpdu_info->tid,
554 mpdu_info->reserved_7a);
555
556 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
557 "rx_mpdu_start tlv (2/5) - "
558 "ast_index:%x "
559 "sw_peer_id:%x "
560 "mpdu_frame_control_valid:%x "
561 "mpdu_duration_valid:%x "
562 "mac_addr_ad1_valid:%x "
563 "mac_addr_ad2_valid:%x "
564 "mac_addr_ad3_valid:%x "
565 "mac_addr_ad4_valid:%x "
566 "mpdu_sequence_control_valid :%x"
567 "mpdu_qos_control_valid:%x "
568 "mpdu_ht_control_valid:%x "
569 "frame_encryption_info_valid :%x",
570 mpdu_info->ast_index,
571 mpdu_info->sw_peer_id,
572 mpdu_info->mpdu_frame_control_valid,
573 mpdu_info->mpdu_duration_valid,
574 mpdu_info->mac_addr_ad1_valid,
575 mpdu_info->mac_addr_ad2_valid,
576 mpdu_info->mac_addr_ad3_valid,
577 mpdu_info->mac_addr_ad4_valid,
578 mpdu_info->mpdu_sequence_control_valid,
579 mpdu_info->mpdu_qos_control_valid,
580 mpdu_info->mpdu_ht_control_valid,
581 mpdu_info->frame_encryption_info_valid);
582
583 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
584 "rx_mpdu_start tlv (3/5) - "
585 "mpdu_fragment_number:%x "
586 "more_fragment_flag:%x "
587 "reserved_11a:%x "
588 "fr_ds:%x "
589 "to_ds:%x "
590 "encrypted:%x "
591 "mpdu_retry:%x "
592 "mpdu_sequence_number:%x ",
593 mpdu_info->mpdu_fragment_number,
594 mpdu_info->more_fragment_flag,
595 mpdu_info->reserved_11a,
596 mpdu_info->fr_ds,
597 mpdu_info->to_ds,
598 mpdu_info->encrypted,
599 mpdu_info->mpdu_retry,
600 mpdu_info->mpdu_sequence_number);
601
602 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
603 "rx_mpdu_start tlv (4/5) - "
604 "mpdu_frame_control_field:%x "
605 "mpdu_duration_field:%x ",
606 mpdu_info->mpdu_frame_control_field,
607 mpdu_info->mpdu_duration_field);
608
609 QDF_TRACE(QDF_MODULE_ID_HAL, dbg_level,
610 "rx_mpdu_start tlv (5/5) - "
611 "mac_addr_ad1_31_0:%x "
612 "mac_addr_ad1_47_32:%x "
613 "mac_addr_ad2_15_0:%x "
614 "mac_addr_ad2_47_16:%x "
615 "mac_addr_ad3_31_0:%x "
616 "mac_addr_ad3_47_32:%x "
617 "mpdu_sequence_control_field :%x"
618 "mac_addr_ad4_31_0:%x "
619 "mac_addr_ad4_47_32:%x "
620 "mpdu_qos_control_field:%x ",
621 mpdu_info->mac_addr_ad1_31_0,
622 mpdu_info->mac_addr_ad1_47_32,
623 mpdu_info->mac_addr_ad2_15_0,
624 mpdu_info->mac_addr_ad2_47_16,
625 mpdu_info->mac_addr_ad3_31_0,
626 mpdu_info->mac_addr_ad3_47_32,
627 mpdu_info->mpdu_sequence_control_field,
628 mpdu_info->mac_addr_ad4_31_0,
629 mpdu_info->mac_addr_ad4_47_32,
630 mpdu_info->mpdu_qos_control_field);
631 }
632
hal_rx_dump_msdu_end_tlv_5332(void * msduend,uint8_t dbg_level)633 static void hal_rx_dump_msdu_end_tlv_5332(void *msduend,
634 uint8_t dbg_level)
635 {
636 struct rx_msdu_end *msdu_end =
637 (struct rx_msdu_end *)msduend;
638
639 QDF_TRACE(QDF_MODULE_ID_DP, dbg_level,
640 "rx_msdu_end tlv - "
641 "key_id_octet: %d "
642 "cce_super_rule: %d "
643 "cce_classify_not_done_truncat: %d "
644 "cce_classify_not_done_cce_dis: %d "
645 "rule_indication_31_0: %d "
646 "tcp_udp_chksum: %d "
647 "sa_idx_timeout: %d "
648 "da_idx_timeout: %d "
649 "msdu_limit_error: %d "
650 "flow_idx_timeout: %d "
651 "flow_idx_invalid: %d "
652 "wifi_parser_error: %d "
653 "sa_is_valid: %d "
654 "da_is_valid: %d "
655 "da_is_mcbc: %d "
656 "tkip_mic_err: %d "
657 "l3_header_padding: %d "
658 "first_msdu: %d "
659 "last_msdu: %d "
660 "sa_idx: %d "
661 "msdu_drop: %d "
662 "reo_destination_indication: %d "
663 "flow_idx: %d "
664 "fse_metadata: %d "
665 "cce_metadata: %d "
666 "sa_sw_peer_id: %d ",
667 msdu_end->key_id_octet,
668 msdu_end->cce_super_rule,
669 msdu_end->cce_classify_not_done_truncate,
670 msdu_end->cce_classify_not_done_cce_dis,
671 msdu_end->rule_indication_31_0,
672 msdu_end->tcp_udp_chksum,
673 msdu_end->sa_idx_timeout,
674 msdu_end->da_idx_timeout,
675 msdu_end->msdu_limit_error,
676 msdu_end->flow_idx_timeout,
677 msdu_end->flow_idx_invalid,
678 msdu_end->wifi_parser_error,
679 msdu_end->sa_is_valid,
680 msdu_end->da_is_valid,
681 msdu_end->da_is_mcbc,
682 msdu_end->tkip_mic_err,
683 msdu_end->l3_header_padding,
684 msdu_end->first_msdu,
685 msdu_end->last_msdu,
686 msdu_end->sa_idx,
687 msdu_end->msdu_drop,
688 msdu_end->reo_destination_indication,
689 msdu_end->flow_idx,
690 msdu_end->fse_metadata,
691 msdu_end->cce_metadata,
692 msdu_end->sa_sw_peer_id);
693 }
694 #endif
695
696 /**
697 * hal_reo_status_get_header_5332() - Process reo desc info
698 * @ring_desc: Pointer to reo descriptor
699 * @b: tlv type info
700 * @h1: Pointer to hal_reo_status_header where info to be stored
701 *
702 * Return: none.
703 *
704 */
hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,int b,void * h1)705 static void hal_reo_status_get_header_5332(hal_ring_desc_t ring_desc,
706 int b, void *h1)
707 {
708 uint64_t *d = (uint64_t *)ring_desc;
709 uint64_t val1 = 0;
710 struct hal_reo_status_header *h =
711 (struct hal_reo_status_header *)h1;
712
713 /* Offsets of descriptor fields defined in HW headers start
714 * from the field after TLV header
715 */
716 d += HAL_GET_NUM_QWORDS(sizeof(struct tlv_32_hdr));
717
718 switch (b) {
719 case HAL_REO_QUEUE_STATS_STATUS_TLV:
720 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
721 STATUS_HEADER_REO_STATUS_NUMBER)];
722 break;
723 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
724 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
725 STATUS_HEADER_REO_STATUS_NUMBER)];
726 break;
727 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
728 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
729 STATUS_HEADER_REO_STATUS_NUMBER)];
730 break;
731 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
732 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
733 STATUS_HEADER_REO_STATUS_NUMBER)];
734 break;
735 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
736 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
737 STATUS_HEADER_REO_STATUS_NUMBER)];
738 break;
739 case HAL_REO_DESC_THRES_STATUS_TLV:
740 val1 =
741 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
742 STATUS_HEADER_REO_STATUS_NUMBER)];
743 break;
744 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
745 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
746 STATUS_HEADER_REO_STATUS_NUMBER)];
747 break;
748 default:
749 qdf_nofl_err("ERROR: Unknown tlv\n");
750 break;
751 }
752 h->cmd_num =
753 HAL_GET_FIELD(
754 UNIFORM_REO_STATUS_HEADER, REO_STATUS_NUMBER,
755 val1);
756 h->exec_time =
757 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
758 CMD_EXECUTION_TIME, val1);
759 h->status =
760 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER,
761 REO_CMD_EXECUTION_STATUS, val1);
762 switch (b) {
763 case HAL_REO_QUEUE_STATS_STATUS_TLV:
764 val1 = d[HAL_OFFSET_QW(REO_GET_QUEUE_STATS_STATUS,
765 STATUS_HEADER_TIMESTAMP)];
766 break;
767 case HAL_REO_FLUSH_QUEUE_STATUS_TLV:
768 val1 = d[HAL_OFFSET_QW(REO_FLUSH_QUEUE_STATUS,
769 STATUS_HEADER_TIMESTAMP)];
770 break;
771 case HAL_REO_FLUSH_CACHE_STATUS_TLV:
772 val1 = d[HAL_OFFSET_QW(REO_FLUSH_CACHE_STATUS,
773 STATUS_HEADER_TIMESTAMP)];
774 break;
775 case HAL_REO_UNBLK_CACHE_STATUS_TLV:
776 val1 = d[HAL_OFFSET_QW(REO_UNBLOCK_CACHE_STATUS,
777 STATUS_HEADER_TIMESTAMP)];
778 break;
779 case HAL_REO_TIMOUT_LIST_STATUS_TLV:
780 val1 = d[HAL_OFFSET_QW(REO_FLUSH_TIMEOUT_LIST_STATUS,
781 STATUS_HEADER_TIMESTAMP)];
782 break;
783 case HAL_REO_DESC_THRES_STATUS_TLV:
784 val1 =
785 d[HAL_OFFSET_QW(REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS,
786 STATUS_HEADER_TIMESTAMP)];
787 break;
788 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV:
789 val1 = d[HAL_OFFSET_QW(REO_UPDATE_RX_REO_QUEUE_STATUS,
790 STATUS_HEADER_TIMESTAMP)];
791 break;
792 default:
793 qdf_nofl_err("ERROR: Unknown tlv\n");
794 break;
795 }
796 h->tstamp =
797 HAL_GET_FIELD(UNIFORM_REO_STATUS_HEADER, TIMESTAMP, val1);
798 }
799
800 static
hal_rx_msdu0_buffer_addr_lsb_5332(void * link_desc_va)801 void *hal_rx_msdu0_buffer_addr_lsb_5332(void *link_desc_va)
802 {
803 return (void *)HAL_RX_MSDU0_BUFFER_ADDR_LSB(link_desc_va);
804 }
805
806 static
hal_rx_msdu_desc_info_ptr_get_5332(void * msdu0)807 void *hal_rx_msdu_desc_info_ptr_get_5332(void *msdu0)
808 {
809 return (void *)HAL_RX_MSDU_DESC_INFO_PTR_GET(msdu0);
810 }
811
812 static
hal_ent_mpdu_desc_info_5332(void * ent_ring_desc)813 void *hal_ent_mpdu_desc_info_5332(void *ent_ring_desc)
814 {
815 return (void *)HAL_ENT_MPDU_DESC_INFO(ent_ring_desc);
816 }
817
818 static
hal_dst_mpdu_desc_info_5332(void * dst_ring_desc)819 void *hal_dst_mpdu_desc_info_5332(void *dst_ring_desc)
820 {
821 return (void *)HAL_DST_MPDU_DESC_INFO(dst_ring_desc);
822 }
823
824 /**
825 * hal_reo_config_5332() - Set reo config parameters
826 * @soc: hal soc handle
827 * @reg_val: value to be set
828 * @reo_params: reo parameters
829 *
830 * Return: void
831 */
832 static void
hal_reo_config_5332(struct hal_soc * soc,uint32_t reg_val,struct hal_reo_params * reo_params)833 hal_reo_config_5332(struct hal_soc *soc,
834 uint32_t reg_val,
835 struct hal_reo_params *reo_params)
836 {
837 HAL_REO_R0_CONFIG(soc, reg_val, reo_params);
838 }
839
840 /**
841 * hal_rx_msdu_desc_info_get_ptr_5332() - Get msdu desc info ptr
842 * @msdu_details_ptr: Pointer to msdu_details_ptr
843 *
844 * Return: Pointer to rx_msdu_desc_info structure.
845 *
846 */
hal_rx_msdu_desc_info_get_ptr_5332(void * msdu_details_ptr)847 static void *hal_rx_msdu_desc_info_get_ptr_5332(void *msdu_details_ptr)
848 {
849 return HAL_RX_MSDU_DESC_INFO_GET(msdu_details_ptr);
850 }
851
852 /**
853 * hal_rx_link_desc_msdu0_ptr_5332() - Get pointer to rx_msdu details
854 * @link_desc: Pointer to link desc
855 *
856 * Return: Pointer to rx_msdu_details structure
857 *
858 */
hal_rx_link_desc_msdu0_ptr_5332(void * link_desc)859 static void *hal_rx_link_desc_msdu0_ptr_5332(void *link_desc)
860 {
861 return HAL_RX_LINK_DESC_MSDU0_PTR(link_desc);
862 }
863
864 /**
865 * hal_get_window_address_5332() - Function to get hp/tp address
866 * @hal_soc: Pointer to hal_soc
867 * @addr: address offset of register
868 *
869 * Return: modified address offset of register
870 */
hal_get_window_address_5332(struct hal_soc * hal_soc,qdf_iomem_t addr)871 static inline qdf_iomem_t hal_get_window_address_5332(struct hal_soc *hal_soc,
872 qdf_iomem_t addr)
873 {
874 uint32_t offset = addr - hal_soc->dev_base_addr;
875 qdf_iomem_t new_offset;
876
877 /*
878 * Check if offset lies within CE register range(0x740000)
879 * or UMAC/DP register range (0x00A00000).
880 * If offset lies within CE register range, map it
881 * into CE region.
882 */
883 if (offset < 0xA00000) {
884 offset = offset - CE_CFG_WFSS_CE_REG_BASE;
885 new_offset = (hal_soc->dev_base_addr_ce + offset);
886
887 return new_offset;
888 } else {
889 /*
890 * If offset lies within DP register range,
891 * return the address as such
892 */
893 return addr;
894 }
895 }
896
897 static
hal_compute_reo_remap_ix2_ix3_5332(uint32_t * ring,uint32_t num_rings,uint32_t * remap1,uint32_t * remap2)898 void hal_compute_reo_remap_ix2_ix3_5332(uint32_t *ring, uint32_t num_rings,
899 uint32_t *remap1, uint32_t *remap2)
900 {
901 switch (num_rings) {
902 case 1:
903 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
904 HAL_REO_REMAP_IX2(ring[0], 17) |
905 HAL_REO_REMAP_IX2(ring[0], 18) |
906 HAL_REO_REMAP_IX2(ring[0], 19) |
907 HAL_REO_REMAP_IX2(ring[0], 20) |
908 HAL_REO_REMAP_IX2(ring[0], 21) |
909 HAL_REO_REMAP_IX2(ring[0], 22) |
910 HAL_REO_REMAP_IX2(ring[0], 23);
911
912 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
913 HAL_REO_REMAP_IX3(ring[0], 25) |
914 HAL_REO_REMAP_IX3(ring[0], 26) |
915 HAL_REO_REMAP_IX3(ring[0], 27) |
916 HAL_REO_REMAP_IX3(ring[0], 28) |
917 HAL_REO_REMAP_IX3(ring[0], 29) |
918 HAL_REO_REMAP_IX3(ring[0], 30) |
919 HAL_REO_REMAP_IX3(ring[0], 31);
920 break;
921 case 2:
922 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
923 HAL_REO_REMAP_IX2(ring[0], 17) |
924 HAL_REO_REMAP_IX2(ring[1], 18) |
925 HAL_REO_REMAP_IX2(ring[1], 19) |
926 HAL_REO_REMAP_IX2(ring[0], 20) |
927 HAL_REO_REMAP_IX2(ring[0], 21) |
928 HAL_REO_REMAP_IX2(ring[1], 22) |
929 HAL_REO_REMAP_IX2(ring[1], 23);
930
931 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
932 HAL_REO_REMAP_IX3(ring[0], 25) |
933 HAL_REO_REMAP_IX3(ring[1], 26) |
934 HAL_REO_REMAP_IX3(ring[1], 27) |
935 HAL_REO_REMAP_IX3(ring[0], 28) |
936 HAL_REO_REMAP_IX3(ring[0], 29) |
937 HAL_REO_REMAP_IX3(ring[1], 30) |
938 HAL_REO_REMAP_IX3(ring[1], 31);
939 break;
940 case 3:
941 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
942 HAL_REO_REMAP_IX2(ring[1], 17) |
943 HAL_REO_REMAP_IX2(ring[2], 18) |
944 HAL_REO_REMAP_IX2(ring[0], 19) |
945 HAL_REO_REMAP_IX2(ring[1], 20) |
946 HAL_REO_REMAP_IX2(ring[2], 21) |
947 HAL_REO_REMAP_IX2(ring[0], 22) |
948 HAL_REO_REMAP_IX2(ring[1], 23);
949
950 *remap2 = HAL_REO_REMAP_IX3(ring[2], 24) |
951 HAL_REO_REMAP_IX3(ring[0], 25) |
952 HAL_REO_REMAP_IX3(ring[1], 26) |
953 HAL_REO_REMAP_IX3(ring[2], 27) |
954 HAL_REO_REMAP_IX3(ring[0], 28) |
955 HAL_REO_REMAP_IX3(ring[1], 29) |
956 HAL_REO_REMAP_IX3(ring[2], 30) |
957 HAL_REO_REMAP_IX3(ring[0], 31);
958 break;
959 case 4:
960 *remap1 = HAL_REO_REMAP_IX2(ring[0], 16) |
961 HAL_REO_REMAP_IX2(ring[1], 17) |
962 HAL_REO_REMAP_IX2(ring[2], 18) |
963 HAL_REO_REMAP_IX2(ring[3], 19) |
964 HAL_REO_REMAP_IX2(ring[0], 20) |
965 HAL_REO_REMAP_IX2(ring[1], 21) |
966 HAL_REO_REMAP_IX2(ring[2], 22) |
967 HAL_REO_REMAP_IX2(ring[3], 23);
968
969 *remap2 = HAL_REO_REMAP_IX3(ring[0], 24) |
970 HAL_REO_REMAP_IX3(ring[1], 25) |
971 HAL_REO_REMAP_IX3(ring[2], 26) |
972 HAL_REO_REMAP_IX3(ring[3], 27) |
973 HAL_REO_REMAP_IX3(ring[0], 28) |
974 HAL_REO_REMAP_IX3(ring[1], 29) |
975 HAL_REO_REMAP_IX3(ring[2], 30) |
976 HAL_REO_REMAP_IX3(ring[3], 31);
977 break;
978 }
979 }
980
981 /**
982 * hal_rx_flow_setup_fse_5332() - Setup a flow search entry in HW FST
983 * @rx_fst: Pointer to the Rx Flow Search Table
984 * @table_offset: offset into the table where the flow is to be setup
985 * @rx_flow: Flow Parameters
986 *
987 * Return: Success/Failure
988 */
989 static void *
hal_rx_flow_setup_fse_5332(uint8_t * rx_fst,uint32_t table_offset,uint8_t * rx_flow)990 hal_rx_flow_setup_fse_5332(uint8_t *rx_fst, uint32_t table_offset,
991 uint8_t *rx_flow)
992 {
993 struct hal_rx_fst *fst = (struct hal_rx_fst *)rx_fst;
994 struct hal_rx_flow *flow = (struct hal_rx_flow *)rx_flow;
995 uint8_t *fse;
996 bool fse_valid;
997
998 if (table_offset >= fst->max_entries) {
999 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_ERROR,
1000 "HAL FSE table offset %u exceeds max entries %u",
1001 table_offset, fst->max_entries);
1002 return NULL;
1003 }
1004
1005 fse = (uint8_t *)fst->base_vaddr +
1006 (table_offset * HAL_RX_FST_ENTRY_SIZE);
1007
1008 fse_valid = HAL_GET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1009
1010 if (fse_valid) {
1011 QDF_TRACE(QDF_MODULE_ID_TXRX, QDF_TRACE_LEVEL_DEBUG,
1012 "HAL FSE %pK already valid", fse);
1013 return NULL;
1014 }
1015
1016 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96) =
1017 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_127_96,
1018 qdf_htonl(flow->tuple_info.src_ip_127_96));
1019
1020 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64) =
1021 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_95_64,
1022 qdf_htonl(flow->tuple_info.src_ip_95_64));
1023
1024 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32) =
1025 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_63_32,
1026 qdf_htonl(flow->tuple_info.src_ip_63_32));
1027
1028 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0) =
1029 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_IP_31_0,
1030 qdf_htonl(flow->tuple_info.src_ip_31_0));
1031
1032 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96) =
1033 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_127_96,
1034 qdf_htonl(flow->tuple_info.dest_ip_127_96));
1035
1036 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64) =
1037 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_95_64,
1038 qdf_htonl(flow->tuple_info.dest_ip_95_64));
1039
1040 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32) =
1041 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_63_32,
1042 qdf_htonl(flow->tuple_info.dest_ip_63_32));
1043
1044 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0) =
1045 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_IP_31_0,
1046 qdf_htonl(flow->tuple_info.dest_ip_31_0));
1047
1048 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT);
1049 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, DEST_PORT) |=
1050 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, DEST_PORT,
1051 (flow->tuple_info.dest_port));
1052
1053 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT);
1054 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, SRC_PORT) |=
1055 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, SRC_PORT,
1056 (flow->tuple_info.src_port));
1057
1058 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL);
1059 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL) |=
1060 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, L4_PROTOCOL,
1061 flow->tuple_info.l4_protocol);
1062
1063 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER);
1064 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER) |=
1065 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_HANDLER,
1066 flow->reo_destination_handler);
1067
1068 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID);
1069 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, VALID) |=
1070 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, VALID, 1);
1071
1072 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA);
1073 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, METADATA) =
1074 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY, METADATA,
1075 flow->fse_metadata);
1076
1077 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION);
1078 HAL_SET_FLD(fse, RX_FLOW_SEARCH_ENTRY, REO_DESTINATION_INDICATION) |=
1079 HAL_SET_FLD_SM(RX_FLOW_SEARCH_ENTRY,
1080 REO_DESTINATION_INDICATION,
1081 flow->reo_destination_indication);
1082
1083 /* Reset all the other fields in FSE */
1084 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, RESERVED_9);
1085 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_DROP);
1086 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_COUNT);
1087 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, MSDU_BYTE_COUNT);
1088 HAL_CLR_FLD(fse, RX_FLOW_SEARCH_ENTRY, TIMESTAMP);
1089
1090 return fse;
1091 }
1092
1093 /**
1094 * hal_rx_dump_pkt_hdr_tlv_5332() - dump RX pkt header TLV in hex format
1095 * @pkt_tlvs: pointer the pkt_hdr_tlv in pkt.
1096 * @dbg_level: log level.
1097 *
1098 * Return: void
1099 */
1100 #ifndef NO_RX_PKT_HDR_TLV
hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1101 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
1102 uint8_t dbg_level)
1103 {
1104 struct rx_pkt_hdr_tlv *pkt_hdr_tlv = &pkt_tlvs->pkt_hdr_tlv;
1105
1106 hal_verbose_debug("\n---------------\n"
1107 "rx_pkt_hdr_tlv\n"
1108 "---------------\n"
1109 "phy_ppdu_id 0x%x ",
1110 pkt_hdr_tlv->phy_ppdu_id);
1111
1112 hal_verbose_hex_dump(pkt_hdr_tlv->rx_pkt_hdr,
1113 sizeof(pkt_hdr_tlv->rx_pkt_hdr));
1114 }
1115 #else
hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs * pkt_tlvs,uint8_t dbg_level)1116 static inline void hal_rx_dump_pkt_hdr_tlv_5332(struct rx_pkt_tlvs *pkt_tlvs,
1117 uint8_t dbg_level)
1118 {
1119 }
1120 #endif
1121
1122 /**
1123 * hal_rx_dump_pkt_tlvs_5332() - API to print RX Pkt TLVS qca5332
1124 * @hal_soc_hdl: hal_soc handle
1125 * @buf: pointer the pkt buffer
1126 * @dbg_level: log level
1127 *
1128 * Return: void
1129 */
1130 #ifdef CONFIG_WORD_BASED_TLV
hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1131 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
1132 uint8_t *buf, uint8_t dbg_level)
1133 {
1134 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1135 struct rx_msdu_end_compact *msdu_end =
1136 &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1137 struct rx_mpdu_start_compact *mpdu_start =
1138 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1139
1140 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
1141 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
1142 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
1143 }
1144 #else
hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,uint8_t * buf,uint8_t dbg_level)1145 static void hal_rx_dump_pkt_tlvs_5332(hal_soc_handle_t hal_soc_hdl,
1146 uint8_t *buf, uint8_t dbg_level)
1147 {
1148 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf;
1149 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end;
1150 struct rx_mpdu_start *mpdu_start =
1151 &pkt_tlvs->mpdu_start_tlv.rx_mpdu_start;
1152
1153 hal_rx_dump_msdu_end_tlv_5332(msdu_end, dbg_level);
1154 hal_rx_dump_mpdu_start_tlv_5332(mpdu_start, dbg_level);
1155 hal_rx_dump_pkt_hdr_tlv_5332(pkt_tlvs, dbg_level);
1156 }
1157 #endif
1158
1159 #define HAL_NUM_TCL_BANKS_5332 24
1160
1161 /**
1162 * hal_cmem_write_5332() - function for CMEM buffer writing
1163 * @hal_soc_hdl: HAL SOC handle
1164 * @offset: CMEM address
1165 * @value: value to write
1166 *
1167 * Return: None.
1168 */
hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,uint32_t offset,uint32_t value)1169 static void hal_cmem_write_5332(hal_soc_handle_t hal_soc_hdl,
1170 uint32_t offset,
1171 uint32_t value)
1172 {
1173 struct hal_soc *hal = (struct hal_soc *)hal_soc_hdl;
1174
1175 /* cmem region is ioremapped from CMEM_REG_BASE, hence subtracting
1176 * that from offset.
1177 */
1178 offset = offset - CMEM_REG_BASE;
1179 pld_reg_write(hal->qdf_dev->dev, offset, value,
1180 hal->dev_base_addr_cmem);
1181 }
1182
1183 /**
1184 * hal_tx_get_num_tcl_banks_5332() - Get number of banks in target
1185 *
1186 * Return: number of bank
1187 */
hal_tx_get_num_tcl_banks_5332(void)1188 static uint8_t hal_tx_get_num_tcl_banks_5332(void)
1189 {
1190 return HAL_NUM_TCL_BANKS_5332;
1191 }
1192
hal_reo_setup_5332(struct hal_soc * soc,void * reoparams,int qref_reset)1193 static void hal_reo_setup_5332(struct hal_soc *soc, void *reoparams,
1194 int qref_reset)
1195 {
1196 uint32_t reg_val;
1197 struct hal_reo_params *reo_params = (struct hal_reo_params *)reoparams;
1198
1199 reg_val = HAL_REG_READ(soc, HWIO_REO_R0_GENERAL_ENABLE_ADDR(
1200 REO_REG_REG_BASE));
1201
1202 hal_reo_config_5332(soc, reg_val, reo_params);
1203 /* Other ring enable bits and REO_ENABLE will be set by FW */
1204
1205 /* TODO: Setup destination ring mapping if enabled */
1206
1207 /* TODO: Error destination ring setting is left to default.
1208 * Default setting is to send all errors to release ring.
1209 */
1210
1211 /* Set the reo descriptor swap bits in case of BIG endian platform */
1212 hal_setup_reo_swap(soc);
1213
1214 HAL_REG_WRITE(soc,
1215 HWIO_REO_R0_AGING_THRESHOLD_IX_0_ADDR(REO_REG_REG_BASE),
1216 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000);
1217
1218 HAL_REG_WRITE(soc,
1219 HWIO_REO_R0_AGING_THRESHOLD_IX_1_ADDR(REO_REG_REG_BASE),
1220 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1221
1222 HAL_REG_WRITE(soc,
1223 HWIO_REO_R0_AGING_THRESHOLD_IX_2_ADDR(REO_REG_REG_BASE),
1224 (HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_MS * 1000));
1225
1226 HAL_REG_WRITE(soc,
1227 HWIO_REO_R0_AGING_THRESHOLD_IX_3_ADDR(REO_REG_REG_BASE),
1228 (HAL_DEFAULT_VO_REO_TIMEOUT_MS * 1000));
1229
1230 /*
1231 * When hash based routing is enabled, routing of the rx packet
1232 * is done based on the following value: 1 _ _ _ _ The last 4
1233 * bits are based on hash[3:0]. This means the possible values
1234 * are 0x10 to 0x1f. This value is used to look-up the
1235 * ring ID configured in Destination_Ring_Ctrl_IX_* register.
1236 * The Destination_Ring_Ctrl_IX_2 and Destination_Ring_Ctrl_IX_3
1237 * registers need to be configured to set-up the 16 entries to
1238 * map the hash values to a ring number. There are 3 bits per
1239 * hash entry – which are mapped as follows:
1240 * 0: TCL, 1:SW1, 2:SW2, * 3:SW3, 4:SW4, 5:Release, 6:FW(WIFI),
1241 * 7: NOT_USED.
1242 */
1243 if (reo_params->rx_hash_enabled) {
1244 HAL_REG_WRITE(soc,
1245 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR
1246 (REO_REG_REG_BASE), reo_params->remap0);
1247
1248 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1249 HAL_REG_READ(soc,
1250 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_1_ADDR(
1251 REO_REG_REG_BASE)));
1252
1253 HAL_REG_WRITE(soc,
1254 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR
1255 (REO_REG_REG_BASE), reo_params->remap1);
1256
1257 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR 0x%x",
1258 HAL_REG_READ(soc,
1259 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_2_ADDR(
1260 REO_REG_REG_BASE)));
1261
1262 HAL_REG_WRITE(soc,
1263 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR
1264 (REO_REG_REG_BASE), reo_params->remap2);
1265
1266 hal_debug("HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR 0x%x",
1267 HAL_REG_READ(soc,
1268 HWIO_REO_R0_DESTINATION_RING_CTRL_IX_3_ADDR(
1269 REO_REG_REG_BASE)));
1270 }
1271
1272 /* TODO: Check if the following registers shoould be setup by host:
1273 * AGING_CONTROL
1274 * HIGH_MEMORY_THRESHOLD
1275 * GLOBAL_LINK_DESC_COUNT_THRESH_IX_0[1,2]
1276 * GLOBAL_LINK_DESC_COUNT_CTRL
1277 */
1278
1279 soc->reo_qref = *reo_params->reo_qref;
1280 hal_reo_shared_qaddr_init((hal_soc_handle_t)soc, qref_reset);
1281 }
1282
hal_get_rx_max_ba_window_qca5332(int tid)1283 static uint16_t hal_get_rx_max_ba_window_qca5332(int tid)
1284 {
1285 return HAL_RX_BA_WINDOW_1024;
1286 }
1287
1288 /**
1289 * hal_qca5332_get_reo_qdesc_size() - Get the reo queue descriptor size
1290 * from the give Block-Ack window size
1291 * @ba_window_size: Block-Ack window size
1292 * @tid: TID
1293 *
1294 * Return: reo queue descriptor size
1295 */
hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size,int tid)1296 static uint32_t hal_qca5332_get_reo_qdesc_size(uint32_t ba_window_size, int tid)
1297 {
1298 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for
1299 * NON_QOS_TID until HW issues are resolved.
1300 */
1301 if (tid != HAL_NON_QOS_TID)
1302 ba_window_size = hal_get_rx_max_ba_window_qca5332(tid);
1303
1304 /* Return descriptor size corresponding to window size of 2 since
1305 * we set ba_window_size to 2 while setting up REO descriptors as
1306 * a WAR to get 2k jump exception aggregates are received without
1307 * a BA session.
1308 */
1309 if (ba_window_size <= 1) {
1310 if (tid != HAL_NON_QOS_TID)
1311 return sizeof(struct rx_reo_queue) +
1312 sizeof(struct rx_reo_queue_ext);
1313 else
1314 return sizeof(struct rx_reo_queue);
1315 }
1316
1317 if (ba_window_size <= 105)
1318 return sizeof(struct rx_reo_queue) +
1319 sizeof(struct rx_reo_queue_ext);
1320
1321 if (ba_window_size <= 210)
1322 return sizeof(struct rx_reo_queue) +
1323 (2 * sizeof(struct rx_reo_queue_ext));
1324
1325 if (ba_window_size <= 256)
1326 return sizeof(struct rx_reo_queue) +
1327 (3 * sizeof(struct rx_reo_queue_ext));
1328
1329 return sizeof(struct rx_reo_queue) +
1330 (10 * sizeof(struct rx_reo_queue_ext)) +
1331 sizeof(struct rx_reo_queue_1k);
1332 }
1333
1334 /**
1335 * hal_rx_tlv_msdu_done_copy_get_5332() - Get msdu done copy bit from rx_tlv
1336 * @buf: pointer the tx_tlv
1337 *
1338 * Return: msdu done copy bit
1339 */
hal_rx_tlv_msdu_done_copy_get_5332(uint8_t * buf)1340 static inline uint32_t hal_rx_tlv_msdu_done_copy_get_5332(uint8_t *buf)
1341 {
1342 return HAL_RX_TLV_MSDU_DONE_COPY_GET(buf);
1343 }
1344
hal_hw_txrx_ops_attach_qca5332(struct hal_soc * hal_soc)1345 static void hal_hw_txrx_ops_attach_qca5332(struct hal_soc *hal_soc)
1346 {
1347 /* init and setup */
1348 hal_soc->ops->hal_srng_dst_hw_init = hal_srng_dst_hw_init_generic;
1349 hal_soc->ops->hal_srng_src_hw_init = hal_srng_src_hw_init_generic;
1350 hal_soc->ops->hal_srng_hw_disable = hal_srng_hw_disable_generic;
1351 hal_soc->ops->hal_get_hw_hptp = hal_get_hw_hptp_generic;
1352 hal_soc->ops->hal_get_window_address = hal_get_window_address_5332;
1353 hal_soc->ops->hal_cmem_write = hal_cmem_write_5332;
1354
1355 /* tx */
1356 hal_soc->ops->hal_tx_set_dscp_tid_map = hal_tx_set_dscp_tid_map_5332;
1357 hal_soc->ops->hal_tx_update_dscp_tid = hal_tx_update_dscp_tid_5332;
1358 hal_soc->ops->hal_tx_comp_get_status =
1359 hal_tx_comp_get_status_generic_be;
1360 hal_soc->ops->hal_tx_init_cmd_credit_ring =
1361 hal_tx_init_cmd_credit_ring_5332;
1362 hal_soc->ops->hal_tx_set_ppe_cmn_cfg = NULL;
1363 hal_soc->ops->hal_tx_set_ppe_vp_entry = NULL;
1364 hal_soc->ops->hal_tx_set_ppe_pri2tid = NULL;
1365 hal_soc->ops->hal_tx_update_ppe_pri2tid = NULL;
1366 hal_soc->ops->hal_tx_dump_ppe_vp_entry = NULL;
1367 hal_soc->ops->hal_tx_get_num_ppe_vp_tbl_entries = NULL;
1368 hal_soc->ops->hal_tx_enable_pri2tid_map = NULL;
1369 hal_soc->ops->hal_ppeds_cfg_ast_override_map_reg = NULL;
1370 hal_soc->ops->hal_tx_config_rbm_mapping_be =
1371 hal_tx_config_rbm_mapping_be_5332;
1372
1373 /* rx */
1374 hal_soc->ops->hal_rx_msdu_start_nss_get = hal_rx_tlv_nss_get_be;
1375 hal_soc->ops->hal_rx_mon_hw_desc_get_mpdu_status =
1376 hal_rx_mon_hw_desc_get_mpdu_status_be;
1377 hal_soc->ops->hal_rx_get_tlv = hal_rx_get_tlv_5332;
1378 hal_soc->ops->hal_rx_proc_phyrx_other_receive_info_tlv =
1379 hal_rx_proc_phyrx_other_receive_info_tlv_5332;
1380
1381 hal_soc->ops->hal_rx_dump_msdu_end_tlv = hal_rx_dump_msdu_end_tlv_5332;
1382 hal_soc->ops->hal_rx_dump_mpdu_start_tlv =
1383 hal_rx_dump_mpdu_start_tlv_5332;
1384 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_5332;
1385
1386 hal_soc->ops->hal_get_link_desc_size = hal_get_link_desc_size_5332;
1387 hal_soc->ops->hal_rx_mpdu_start_tid_get = hal_rx_tlv_tid_get_be;
1388 hal_soc->ops->hal_rx_msdu_start_reception_type_get =
1389 hal_rx_tlv_reception_type_get_be;
1390 hal_soc->ops->hal_rx_msdu_end_da_idx_get =
1391 hal_rx_msdu_end_da_idx_get_be;
1392 hal_soc->ops->hal_rx_msdu_desc_info_get_ptr =
1393 hal_rx_msdu_desc_info_get_ptr_5332;
1394 hal_soc->ops->hal_rx_link_desc_msdu0_ptr =
1395 hal_rx_link_desc_msdu0_ptr_5332;
1396 hal_soc->ops->hal_reo_status_get_header =
1397 hal_reo_status_get_header_5332;
1398 #ifdef WLAN_PKT_CAPTURE_RX_2_0
1399 hal_soc->ops->hal_rx_status_get_tlv_info =
1400 hal_rx_status_get_tlv_info_wrapper_be;
1401 #endif
1402 hal_soc->ops->hal_rx_wbm_err_info_get =
1403 hal_rx_wbm_err_info_get_generic_be;
1404 hal_soc->ops->hal_tx_set_pcp_tid_map =
1405 hal_tx_set_pcp_tid_map_generic_be;
1406 hal_soc->ops->hal_tx_update_pcp_tid_map =
1407 hal_tx_update_pcp_tid_generic_be;
1408 hal_soc->ops->hal_tx_set_tidmap_prty =
1409 hal_tx_update_tidmap_prty_generic_be;
1410 hal_soc->ops->hal_rx_get_rx_fragment_number =
1411 hal_rx_get_rx_fragment_number_be,
1412 hal_soc->ops->hal_rx_msdu_end_da_is_mcbc_get =
1413 hal_rx_tlv_da_is_mcbc_get_be;
1414 hal_soc->ops->hal_rx_msdu_end_is_tkip_mic_err =
1415 hal_rx_tlv_is_tkip_mic_err_get_be;
1416 hal_soc->ops->hal_rx_msdu_end_sa_is_valid_get =
1417 hal_rx_tlv_sa_is_valid_get_be;
1418 hal_soc->ops->hal_rx_msdu_end_sa_idx_get = hal_rx_tlv_sa_idx_get_be;
1419 hal_soc->ops->hal_rx_desc_is_first_msdu = hal_rx_desc_is_first_msdu_be;
1420 hal_soc->ops->hal_rx_msdu_end_l3_hdr_padding_get =
1421 hal_rx_tlv_l3_hdr_padding_get_be;
1422 hal_soc->ops->hal_rx_encryption_info_valid =
1423 hal_rx_encryption_info_valid_be;
1424 hal_soc->ops->hal_rx_print_pn = hal_rx_print_pn_be;
1425 hal_soc->ops->hal_rx_msdu_end_first_msdu_get =
1426 hal_rx_tlv_first_msdu_get_be;
1427 hal_soc->ops->hal_rx_msdu_end_da_is_valid_get =
1428 hal_rx_tlv_da_is_valid_get_be;
1429 hal_soc->ops->hal_rx_msdu_end_last_msdu_get =
1430 hal_rx_tlv_last_msdu_get_be;
1431 hal_soc->ops->hal_rx_get_mpdu_mac_ad4_valid =
1432 hal_rx_get_mpdu_mac_ad4_valid_be;
1433 hal_soc->ops->hal_rx_mpdu_start_sw_peer_id_get =
1434 hal_rx_mpdu_start_sw_peer_id_get_be;
1435 hal_soc->ops->hal_rx_tlv_peer_meta_data_get =
1436 hal_rx_msdu_peer_meta_data_get_be;
1437 #ifndef CONFIG_WORD_BASED_TLV
1438 hal_soc->ops->hal_rx_mpdu_get_addr4 = hal_rx_mpdu_get_addr4_be;
1439 hal_soc->ops->hal_rx_mpdu_info_ampdu_flag_get =
1440 hal_rx_mpdu_info_ampdu_flag_get_be;
1441 hal_soc->ops->hal_rx_hw_desc_get_ppduid_get =
1442 hal_rx_hw_desc_get_ppduid_get_be;
1443 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get =
1444 hal_rx_attn_phy_ppdu_id_get_be;
1445 hal_soc->ops->hal_rx_get_filter_category =
1446 hal_rx_get_filter_category_be;
1447 #endif
1448 hal_soc->ops->hal_rx_get_ppdu_id = hal_rx_get_ppdu_id_be;
1449 hal_soc->ops->hal_rx_mpdu_get_to_ds = hal_rx_mpdu_get_to_ds_be;
1450 hal_soc->ops->hal_rx_mpdu_get_fr_ds = hal_rx_mpdu_get_fr_ds_be;
1451 hal_soc->ops->hal_rx_get_mpdu_frame_control_valid =
1452 hal_rx_get_mpdu_frame_control_valid_be;
1453 hal_soc->ops->hal_rx_mpdu_get_addr1 = hal_rx_mpdu_get_addr1_be;
1454 hal_soc->ops->hal_rx_mpdu_get_addr2 = hal_rx_mpdu_get_addr2_be;
1455 hal_soc->ops->hal_rx_mpdu_get_addr3 = hal_rx_mpdu_get_addr3_be;
1456 hal_soc->ops->hal_rx_get_mpdu_sequence_control_valid =
1457 hal_rx_get_mpdu_sequence_control_valid_be;
1458 hal_soc->ops->hal_rx_is_unicast = hal_rx_is_unicast_be;
1459 hal_soc->ops->hal_rx_tid_get = hal_rx_tid_get_be;
1460 hal_soc->ops->hal_rx_mpdu_start_mpdu_qos_control_valid_get =
1461 hal_rx_mpdu_start_mpdu_qos_control_valid_get_be;
1462 hal_soc->ops->hal_rx_msdu_end_sa_sw_peer_id_get =
1463 hal_rx_msdu_end_sa_sw_peer_id_get_be;
1464 hal_soc->ops->hal_rx_msdu0_buffer_addr_lsb =
1465 hal_rx_msdu0_buffer_addr_lsb_5332;
1466 hal_soc->ops->hal_rx_msdu_desc_info_ptr_get =
1467 hal_rx_msdu_desc_info_ptr_get_5332;
1468 hal_soc->ops->hal_ent_mpdu_desc_info = hal_ent_mpdu_desc_info_5332;
1469 hal_soc->ops->hal_dst_mpdu_desc_info = hal_dst_mpdu_desc_info_5332;
1470 hal_soc->ops->hal_rx_get_fc_valid = hal_rx_get_fc_valid_be;
1471 hal_soc->ops->hal_rx_get_to_ds_flag = hal_rx_get_to_ds_flag_be;
1472 hal_soc->ops->hal_rx_get_mac_addr2_valid =
1473 hal_rx_get_mac_addr2_valid_be;
1474 hal_soc->ops->hal_reo_config = hal_reo_config_5332;
1475 hal_soc->ops->hal_rx_msdu_flow_idx_get = hal_rx_msdu_flow_idx_get_be;
1476 hal_soc->ops->hal_rx_msdu_flow_idx_invalid =
1477 hal_rx_msdu_flow_idx_invalid_be;
1478 hal_soc->ops->hal_rx_msdu_flow_idx_timeout =
1479 hal_rx_msdu_flow_idx_timeout_be;
1480 hal_soc->ops->hal_rx_msdu_fse_metadata_get =
1481 hal_rx_msdu_fse_metadata_get_be;
1482 hal_soc->ops->hal_rx_msdu_cce_match_get =
1483 hal_rx_msdu_cce_match_get_be;
1484 hal_soc->ops->hal_rx_msdu_cce_metadata_get =
1485 hal_rx_msdu_cce_metadata_get_be;
1486 hal_soc->ops->hal_rx_msdu_get_flow_params =
1487 hal_rx_msdu_get_flow_params_be;
1488 hal_soc->ops->hal_rx_tlv_get_tcp_chksum = hal_rx_tlv_get_tcp_chksum_be;
1489 hal_soc->ops->hal_rx_get_rx_sequence = hal_rx_get_rx_sequence_be;
1490 #if defined(WLAN_CFR_ENABLE) && defined(WLAN_ENH_CFR_ENABLE)
1491 hal_soc->ops->hal_rx_get_bb_info = hal_rx_get_bb_info_5332;
1492 hal_soc->ops->hal_rx_get_rtt_info = hal_rx_get_rtt_info_5332;
1493 #else
1494 hal_soc->ops->hal_rx_get_bb_info = NULL;
1495 hal_soc->ops->hal_rx_get_rtt_info = NULL;
1496 #endif
1497 /* rx - msdu fast path info fields */
1498 hal_soc->ops->hal_rx_msdu_packet_metadata_get =
1499 hal_rx_msdu_packet_metadata_get_generic_be;
1500 hal_soc->ops->hal_rx_mpdu_start_tlv_tag_valid =
1501 hal_rx_mpdu_start_tlv_tag_valid_be;
1502 hal_soc->ops->hal_rx_wbm_err_msdu_continuation_get =
1503 hal_rx_wbm_err_msdu_continuation_get_5332;
1504
1505 /* rx - TLV struct offsets */
1506 hal_soc->ops->hal_rx_msdu_end_offset_get =
1507 hal_rx_msdu_end_offset_get_generic;
1508 hal_soc->ops->hal_rx_mpdu_start_offset_get =
1509 hal_rx_mpdu_start_offset_get_generic;
1510 #ifndef NO_RX_PKT_HDR_TLV
1511 hal_soc->ops->hal_rx_pkt_tlv_offset_get =
1512 hal_rx_pkt_tlv_offset_get_generic;
1513 #endif
1514 hal_soc->ops->hal_rx_flow_setup_fse = hal_rx_flow_setup_fse_5332;
1515
1516 hal_soc->ops->hal_rx_flow_get_tuple_info =
1517 hal_rx_flow_get_tuple_info_be;
1518 hal_soc->ops->hal_rx_flow_delete_entry =
1519 hal_rx_flow_delete_entry_be;
1520 hal_soc->ops->hal_rx_fst_get_fse_size = hal_rx_fst_get_fse_size_be;
1521 hal_soc->ops->hal_compute_reo_remap_ix2_ix3 =
1522 hal_compute_reo_remap_ix2_ix3_5332;
1523
1524 hal_soc->ops->hal_rx_msdu_get_reo_destination_indication =
1525 hal_rx_msdu_get_reo_destination_indication_be;
1526 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_be;
1527 hal_soc->ops->hal_rx_msdu_is_wlan_mcast =
1528 hal_rx_msdu_is_wlan_mcast_generic_be;
1529 hal_soc->ops->hal_tx_get_num_tcl_banks = hal_tx_get_num_tcl_banks_5332;
1530 hal_soc->ops->hal_rx_tlv_decap_format_get =
1531 hal_rx_tlv_decap_format_get_be;
1532 #ifdef RECEIVE_OFFLOAD
1533 hal_soc->ops->hal_rx_tlv_get_offload_info =
1534 hal_rx_tlv_get_offload_info_be;
1535 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_be;
1536 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_be;
1537 #endif
1538 hal_soc->ops->hal_rx_tlv_msdu_done_get =
1539 hal_rx_tlv_msdu_done_copy_get_5332;
1540 hal_soc->ops->hal_rx_tlv_msdu_len_get =
1541 hal_rx_msdu_start_msdu_len_get_be;
1542 hal_soc->ops->hal_rx_get_frame_ctrl_field =
1543 hal_rx_get_frame_ctrl_field_be;
1544 hal_soc->ops->hal_rx_tlv_csum_err_get = hal_rx_tlv_csum_err_get_be;
1545 hal_soc->ops->hal_rx_tlv_msdu_len_set =
1546 hal_rx_msdu_start_msdu_len_set_be;
1547 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_be;
1548 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_be;
1549 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_be;
1550 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_be;
1551 hal_soc->ops->hal_rx_tlv_mic_err_get = hal_rx_tlv_mic_err_get_be;
1552 hal_soc->ops->hal_rx_tlv_decrypt_err_get =
1553 hal_rx_tlv_decrypt_err_get_be;
1554 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_be;
1555 hal_soc->ops->hal_rx_tlv_get_is_decrypted =
1556 hal_rx_tlv_get_is_decrypted_be;
1557 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_be;
1558 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_be;
1559 hal_soc->ops->hal_rx_priv_info_set_in_tlv =
1560 hal_rx_priv_info_set_in_tlv_be;
1561 hal_soc->ops->hal_rx_priv_info_get_from_tlv =
1562 hal_rx_priv_info_get_from_tlv_be;
1563 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_be;
1564 hal_soc->ops->hal_reo_setup = hal_reo_setup_5332;
1565 #ifdef REO_SHARED_QREF_TABLE_EN
1566 hal_soc->ops->hal_reo_shared_qaddr_setup = hal_reo_shared_qaddr_setup_be;
1567 hal_soc->ops->hal_reo_shared_qaddr_init = hal_reo_shared_qaddr_init_be;
1568 hal_soc->ops->hal_reo_shared_qaddr_detach = hal_reo_shared_qaddr_detach_be;
1569 hal_soc->ops->hal_reo_shared_qaddr_write = hal_reo_shared_qaddr_write_be;
1570 hal_soc->ops->hal_reo_shared_qaddr_cache_clear = hal_reo_shared_qaddr_cache_clear_be;
1571 #endif
1572 /* Overwrite the default BE ops */
1573 hal_soc->ops->hal_get_rx_max_ba_window =
1574 hal_get_rx_max_ba_window_qca5332;
1575 hal_soc->ops->hal_get_reo_qdesc_size = hal_qca5332_get_reo_qdesc_size;
1576 /* TX MONITOR */
1577 #ifdef WLAN_PKT_CAPTURE_TX_2_0
1578 hal_soc->ops->hal_txmon_is_mon_buf_addr_tlv =
1579 hal_txmon_is_mon_buf_addr_tlv_generic_be;
1580 hal_soc->ops->hal_txmon_populate_packet_info =
1581 hal_txmon_populate_packet_info_generic_be;
1582 hal_soc->ops->hal_txmon_status_parse_tlv =
1583 hal_txmon_status_parse_tlv_generic_be;
1584 hal_soc->ops->hal_txmon_status_get_num_users =
1585 hal_txmon_status_get_num_users_generic_be;
1586 #if defined(TX_MONITOR_WORD_MASK)
1587 hal_soc->ops->hal_txmon_get_word_mask =
1588 hal_txmon_get_word_mask_qca5332;
1589 #else
1590 hal_soc->ops->hal_txmon_get_word_mask =
1591 hal_txmon_get_word_mask_generic_be;
1592 #endif /* TX_MONITOR_WORD_MASK */
1593 #endif /* WLAN_PKT_CAPTURE_TX_2_0 */
1594 hal_soc->ops->hal_compute_reo_remap_ix0 = NULL;
1595 hal_soc->ops->hal_tx_vdev_mismatch_routing_set =
1596 hal_tx_vdev_mismatch_routing_set_generic_be;
1597 hal_soc->ops->hal_tx_mcast_mlo_reinject_routing_set =
1598 hal_tx_mcast_mlo_reinject_routing_set_generic_be;
1599 hal_soc->ops->hal_get_ba_aging_timeout =
1600 hal_get_ba_aging_timeout_be_generic;
1601 hal_soc->ops->hal_setup_link_idle_list =
1602 hal_setup_link_idle_list_generic_be;
1603 hal_soc->ops->hal_cookie_conversion_reg_cfg_be =
1604 hal_cookie_conversion_reg_cfg_generic_be;
1605 hal_soc->ops->hal_set_ba_aging_timeout =
1606 hal_set_ba_aging_timeout_be_generic;
1607 hal_soc->ops->hal_tx_populate_bank_register =
1608 hal_tx_populate_bank_register_be;
1609 hal_soc->ops->hal_tx_vdev_mcast_ctrl_set =
1610 hal_tx_vdev_mcast_ctrl_set_be;
1611 hal_soc->ops->hal_get_tsf2_scratch_reg =
1612 hal_get_tsf2_scratch_reg_qca5332;
1613 hal_soc->ops->hal_get_tqm_scratch_reg =
1614 hal_get_tqm_scratch_reg_qca5332;
1615 #ifdef CONFIG_WORD_BASED_TLV
1616 hal_soc->ops->hal_rx_mpdu_start_wmask_get =
1617 hal_rx_mpdu_start_wmask_get_be;
1618 hal_soc->ops->hal_rx_msdu_end_wmask_get =
1619 hal_rx_msdu_end_wmask_get_be;
1620 #endif
1621 };
1622
1623 struct hal_hw_srng_config hw_srng_table_5332[] = {
1624 /* TODO: max_rings can populated by querying HW capabilities */
1625 { /* REO_DST */
1626 .start_ring_id = HAL_SRNG_REO2SW1,
1627 .max_rings = 8,
1628 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1629 .lmac_ring = FALSE,
1630 .ring_dir = HAL_SRNG_DST_RING,
1631 .reg_start = {
1632 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(
1633 REO_REG_REG_BASE),
1634 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(
1635 REO_REG_REG_BASE)
1636 },
1637 .reg_size = {
1638 HWIO_REO_R0_REO2SW2_RING_BASE_LSB_ADDR(0) -
1639 HWIO_REO_R0_REO2SW1_RING_BASE_LSB_ADDR(0),
1640 HWIO_REO_R2_REO2SW2_RING_HP_ADDR(0) -
1641 HWIO_REO_R2_REO2SW1_RING_HP_ADDR(0),
1642 },
1643 .max_size =
1644 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_BMSK >>
1645 HWIO_REO_R0_REO2SW1_RING_BASE_MSB_RING_SIZE_SHFT,
1646 },
1647 { /* REO_EXCEPTION */
1648 /* Designating REO2SW0 ring as exception ring. This ring is
1649 * similar to other REO2SW rings though it is named as REO2SW0.
1650 * Any of theREO2SW rings can be used as exception ring.
1651 */
1652 .start_ring_id = HAL_SRNG_REO2SW0,
1653 .max_rings = 1,
1654 .entry_size = sizeof(struct reo_destination_ring) >> 2,
1655 .lmac_ring = FALSE,
1656 .ring_dir = HAL_SRNG_DST_RING,
1657 .reg_start = {
1658 HWIO_REO_R0_REO2SW0_RING_BASE_LSB_ADDR(
1659 REO_REG_REG_BASE),
1660 HWIO_REO_R2_REO2SW0_RING_HP_ADDR(
1661 REO_REG_REG_BASE)
1662 },
1663 /* Single ring - provide ring size if multiple rings of this
1664 * type are supported
1665 */
1666 .reg_size = {},
1667 .max_size =
1668 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_BMSK >>
1669 HWIO_REO_R0_REO2SW0_RING_BASE_MSB_RING_SIZE_SHFT,
1670 },
1671 { /* REO_REINJECT */
1672 .start_ring_id = HAL_SRNG_SW2REO,
1673 .max_rings = 4,
1674 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
1675 .lmac_ring = FALSE,
1676 .ring_dir = HAL_SRNG_SRC_RING,
1677 .reg_start = {
1678 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(
1679 REO_REG_REG_BASE),
1680 HWIO_REO_R2_SW2REO_RING_HP_ADDR(
1681 REO_REG_REG_BASE)
1682 },
1683 /* Single ring - provide ring size if multiple rings of this
1684 * type are supported
1685 */
1686 .reg_size = {
1687 HWIO_REO_R0_SW2REO1_RING_BASE_LSB_ADDR(0) -
1688 HWIO_REO_R0_SW2REO_RING_BASE_LSB_ADDR(0),
1689 HWIO_REO_R2_SW2REO1_RING_HP_ADDR(0) -
1690 HWIO_REO_R2_SW2REO_RING_HP_ADDR(0)
1691 },
1692 .max_size = HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_BMSK >>
1693 HWIO_REO_R0_SW2REO_RING_BASE_MSB_RING_SIZE_SHFT,
1694 },
1695 { /* REO_CMD */
1696 .start_ring_id = HAL_SRNG_REO_CMD,
1697 .max_rings = 1,
1698 .entry_size = (sizeof(struct tlv_32_hdr) +
1699 sizeof(struct reo_get_queue_stats)) >> 2,
1700 .lmac_ring = FALSE,
1701 .ring_dir = HAL_SRNG_SRC_RING,
1702 .reg_start = {
1703 HWIO_REO_R0_REO_CMD_RING_BASE_LSB_ADDR(
1704 REO_REG_REG_BASE),
1705 HWIO_REO_R2_REO_CMD_RING_HP_ADDR(
1706 REO_REG_REG_BASE),
1707 },
1708 /* Single ring - provide ring size if multiple rings of this
1709 * type are supported
1710 */
1711 .reg_size = {},
1712 .max_size = HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_BMSK >>
1713 HWIO_REO_R0_REO_CMD_RING_BASE_MSB_RING_SIZE_SHFT,
1714 },
1715 { /* REO_STATUS */
1716 .start_ring_id = HAL_SRNG_REO_STATUS,
1717 .max_rings = 1,
1718 .entry_size = (sizeof(struct tlv_32_hdr) +
1719 sizeof(struct reo_get_queue_stats_status)) >> 2,
1720 .lmac_ring = FALSE,
1721 .ring_dir = HAL_SRNG_DST_RING,
1722 .reg_start = {
1723 HWIO_REO_R0_REO_STATUS_RING_BASE_LSB_ADDR(
1724 REO_REG_REG_BASE),
1725 HWIO_REO_R2_REO_STATUS_RING_HP_ADDR(
1726 REO_REG_REG_BASE),
1727 },
1728 /* Single ring - provide ring size if multiple rings of this
1729 * type are supported
1730 */
1731 .reg_size = {},
1732 .max_size =
1733 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1734 HWIO_REO_R0_REO_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1735 },
1736 { /* TCL_DATA */
1737 .start_ring_id = HAL_SRNG_SW2TCL1,
1738 .max_rings = 6,
1739 .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1740 .lmac_ring = FALSE,
1741 .ring_dir = HAL_SRNG_SRC_RING,
1742 .reg_start = {
1743 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(
1744 MAC_TCL_REG_REG_BASE),
1745 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(
1746 MAC_TCL_REG_REG_BASE),
1747 },
1748 .reg_size = {
1749 HWIO_TCL_R0_SW2TCL2_RING_BASE_LSB_ADDR(0) -
1750 HWIO_TCL_R0_SW2TCL1_RING_BASE_LSB_ADDR(0),
1751 HWIO_TCL_R2_SW2TCL2_RING_HP_ADDR(0) -
1752 HWIO_TCL_R2_SW2TCL1_RING_HP_ADDR(0),
1753 },
1754 .max_size =
1755 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_BMSK >>
1756 HWIO_TCL_R0_SW2TCL1_RING_BASE_MSB_RING_SIZE_SHFT,
1757 },
1758 { /* TCL_CMD/CREDIT */
1759 /* qca8074v2 and qca5332 uses this ring for data commands */
1760 .start_ring_id = HAL_SRNG_SW2TCL_CMD,
1761 .max_rings = 1,
1762 .entry_size = sizeof(struct tcl_data_cmd) >> 2,
1763 .lmac_ring = FALSE,
1764 .ring_dir = HAL_SRNG_SRC_RING,
1765 .reg_start = {
1766 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_LSB_ADDR(
1767 MAC_TCL_REG_REG_BASE),
1768 HWIO_TCL_R2_SW2TCL_CREDIT_RING_HP_ADDR(
1769 MAC_TCL_REG_REG_BASE),
1770 },
1771 /* Single ring - provide ring size if multiple rings of this
1772 * type are supported
1773 */
1774 .reg_size = {},
1775 .max_size =
1776 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_BMSK >>
1777 HWIO_TCL_R0_SW2TCL_CREDIT_RING_BASE_MSB_RING_SIZE_SHFT,
1778 },
1779 { /* TCL_STATUS */
1780 .start_ring_id = HAL_SRNG_TCL_STATUS,
1781 .max_rings = 1,
1782 .entry_size = (sizeof(struct tlv_32_hdr) +
1783 sizeof(struct tcl_status_ring)) >> 2,
1784 .lmac_ring = FALSE,
1785 .ring_dir = HAL_SRNG_DST_RING,
1786 .reg_start = {
1787 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_LSB_ADDR(
1788 MAC_TCL_REG_REG_BASE),
1789 HWIO_TCL_R2_TCL_STATUS1_RING_HP_ADDR(
1790 MAC_TCL_REG_REG_BASE),
1791 },
1792 /* Single ring - provide ring size if multiple rings of this
1793 * type are supported
1794 */
1795 .reg_size = {},
1796 .max_size =
1797 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_BMSK >>
1798 HWIO_TCL_R0_TCL_STATUS1_RING_BASE_MSB_RING_SIZE_SHFT,
1799 },
1800 { /* CE_SRC */
1801 .start_ring_id = HAL_SRNG_CE_0_SRC,
1802 .max_rings = 16,
1803 .entry_size = sizeof(struct ce_src_desc) >> 2,
1804 .lmac_ring = FALSE,
1805 .ring_dir = HAL_SRNG_SRC_RING,
1806 .reg_start = {
1807 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_LSB_ADDR(
1808 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1809 HWIO_WFSS_CE_CHANNEL_SRC_R2_SRC_RING_HP_ADDR(
1810 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE),
1811 },
1812 .reg_size = {
1813 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1814 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1815 WFSS_CE_1_CHANNEL_SRC_REG_REG_BASE -
1816 WFSS_CE_0_CHANNEL_SRC_REG_REG_BASE,
1817 },
1818 .max_size =
1819 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_BMSK >>
1820 HWIO_WFSS_CE_CHANNEL_SRC_R0_SRC_RING_BASE_MSB_RING_SIZE_SHFT,
1821 },
1822 { /* CE_DST */
1823 .start_ring_id = HAL_SRNG_CE_0_DST,
1824 .max_rings = 16,
1825 .entry_size = 8 >> 2,
1826 /*TODO: entry_size above should actually be
1827 * sizeof(struct ce_dst_desc) >> 2, but couldn't find definition
1828 * of struct ce_dst_desc in HW header files
1829 */
1830 .lmac_ring = FALSE,
1831 .ring_dir = HAL_SRNG_SRC_RING,
1832 .reg_start = {
1833 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_LSB_ADDR(
1834 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1835 HWIO_WFSS_CE_CHANNEL_DST_R2_DEST_RING_HP_ADDR(
1836 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1837 },
1838 .reg_size = {
1839 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1840 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1841 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1842 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1843 },
1844 .max_size =
1845 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_BMSK >>
1846 HWIO_WFSS_CE_CHANNEL_DST_R0_DEST_RING_BASE_MSB_RING_SIZE_SHFT,
1847 },
1848 { /* CE_DST_STATUS */
1849 .start_ring_id = HAL_SRNG_CE_0_DST_STATUS,
1850 .max_rings = 16,
1851 .entry_size = sizeof(struct ce_stat_desc) >> 2,
1852 .lmac_ring = FALSE,
1853 .ring_dir = HAL_SRNG_DST_RING,
1854 .reg_start = {
1855 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_LSB_ADDR(
1856 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1857 HWIO_WFSS_CE_CHANNEL_DST_R2_STATUS_RING_HP_ADDR(
1858 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE),
1859 },
1860 /* TODO: check destination status ring registers */
1861 .reg_size = {
1862 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1863 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1864 WFSS_CE_1_CHANNEL_DST_REG_REG_BASE -
1865 WFSS_CE_0_CHANNEL_DST_REG_REG_BASE,
1866 },
1867 .max_size =
1868 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_BMSK >>
1869 HWIO_WFSS_CE_CHANNEL_DST_R0_STATUS_RING_BASE_MSB_RING_SIZE_SHFT,
1870 },
1871 { /* WBM_IDLE_LINK */
1872 .start_ring_id = HAL_SRNG_WBM_IDLE_LINK,
1873 .max_rings = 1,
1874 .entry_size = sizeof(struct wbm_link_descriptor_ring) >> 2,
1875 .lmac_ring = FALSE,
1876 .ring_dir = HAL_SRNG_SRC_RING,
1877 .reg_start = {
1878 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
1879 HWIO_WBM_R2_WBM_IDLE_LINK_RING_HP_ADDR(WBM_REG_REG_BASE),
1880 },
1881 /* Single ring - provide ring size if multiple rings of this
1882 * type are supported
1883 */
1884 .reg_size = {},
1885 .max_size =
1886 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_BMSK >>
1887 HWIO_WBM_R0_WBM_IDLE_LINK_RING_BASE_MSB_RING_SIZE_SHFT,
1888 },
1889 { /* SW2WBM_RELEASE */
1890 .start_ring_id = HAL_SRNG_WBM_SW_RELEASE,
1891 .max_rings = 1,
1892 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1893 .lmac_ring = FALSE,
1894 .ring_dir = HAL_SRNG_SRC_RING,
1895 .reg_start = {
1896 HWIO_WBM_R0_SW_RELEASE_RING_BASE_LSB_ADDR(WBM_REG_REG_BASE),
1897 HWIO_WBM_R2_SW_RELEASE_RING_HP_ADDR(WBM_REG_REG_BASE),
1898 },
1899 /* Single ring - provide ring size if multiple rings of this
1900 * type are supported
1901 */
1902 .reg_size = {},
1903 .max_size =
1904 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1905 HWIO_WBM_R0_SW_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1906 },
1907 { /* WBM2SW_RELEASE */
1908 .start_ring_id = HAL_SRNG_WBM2SW0_RELEASE,
1909 .max_rings = 8,
1910 .entry_size = sizeof(struct wbm_release_ring) >> 2,
1911 .lmac_ring = FALSE,
1912 .ring_dir = HAL_SRNG_DST_RING,
1913 .reg_start = {
1914 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
1915 WBM_REG_REG_BASE),
1916 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
1917 WBM_REG_REG_BASE),
1918 },
1919 .reg_size = {
1920 HWIO_WBM_R0_WBM2SW1_RELEASE_RING_BASE_LSB_ADDR(
1921 WBM_REG_REG_BASE) -
1922 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_LSB_ADDR(
1923 WBM_REG_REG_BASE),
1924 HWIO_WBM_R2_WBM2SW1_RELEASE_RING_HP_ADDR(
1925 WBM_REG_REG_BASE) -
1926 HWIO_WBM_R2_WBM2SW0_RELEASE_RING_HP_ADDR(
1927 WBM_REG_REG_BASE),
1928 },
1929 .max_size =
1930 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_BMSK >>
1931 HWIO_WBM_R0_WBM2SW0_RELEASE_RING_BASE_MSB_RING_SIZE_SHFT,
1932 },
1933 { /* RXDMA_BUF */
1934 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA0_BUF0,
1935 #ifdef IPA_OFFLOAD
1936 .max_rings = 3,
1937 #else
1938 .max_rings = 3,
1939 #endif
1940 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1941 .lmac_ring = TRUE,
1942 .ring_dir = HAL_SRNG_SRC_RING,
1943 /* reg_start is not set because LMAC rings are not accessed
1944 * from host
1945 */
1946 .reg_start = {},
1947 .reg_size = {},
1948 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1949 },
1950 { /* RXDMA_DST */
1951 .start_ring_id = HAL_SRNG_WMAC1_RXDMA2SW0,
1952 .max_rings = 0,
1953 .entry_size = 0/*sizeof(struct reo_entrance_ring) >> 2*/,
1954 .lmac_ring = TRUE,
1955 .ring_dir = HAL_SRNG_DST_RING,
1956 /* reg_start is not set because LMAC rings are not accessed
1957 * from host
1958 */
1959 .reg_start = {},
1960 .reg_size = {},
1961 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1962 },
1963 #ifdef WLAN_PKT_CAPTURE_RX_2_0
1964 { /* RXDMA_MONITOR_BUF */
1965 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA2_BUF,
1966 .max_rings = 1,
1967 .entry_size = sizeof(struct mon_ingress_ring) >> 2,
1968 .lmac_ring = TRUE,
1969 .ring_dir = HAL_SRNG_SRC_RING,
1970 /* reg_start is not set because LMAC rings are not accessed
1971 * from host
1972 */
1973 .reg_start = {},
1974 .reg_size = {},
1975 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
1976 },
1977 #else
1978 {},
1979 #endif
1980 { /* RXDMA_MONITOR_STATUS */
1981 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_STATBUF,
1982 .max_rings = 0,
1983 .entry_size = sizeof(struct wbm_buffer_ring) >> 2,
1984 .lmac_ring = TRUE,
1985 .ring_dir = HAL_SRNG_SRC_RING,
1986 /* reg_start is not set because LMAC rings are not accessed
1987 * from host
1988 */
1989 .reg_start = {},
1990 .reg_size = {},
1991 .max_size = HAL_RXDMA_MAX_RING_SIZE,
1992 },
1993 #ifdef WLAN_PKT_CAPTURE_RX_2_0
1994 { /* RXDMA_MONITOR_DST */
1995 .start_ring_id = HAL_SRNG_WMAC1_RXMON2SW0,
1996 .max_rings = 2,
1997 .entry_size = sizeof(struct mon_destination_ring) >> 2,
1998 .lmac_ring = TRUE,
1999 .ring_dir = HAL_SRNG_DST_RING,
2000 /* reg_start is not set because LMAC rings are not accessed
2001 * from host
2002 */
2003 .reg_start = {},
2004 .reg_size = {},
2005 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2006 },
2007 #else
2008 {},
2009 #endif
2010 { /* RXDMA_MONITOR_DESC */
2011 .start_ring_id = HAL_SRNG_WMAC1_SW2RXDMA1_DESC,
2012 .max_rings = 0,
2013 .entry_size = 0/*sizeof(struct sw_monitor_ring) >> 2*/,
2014 .lmac_ring = TRUE,
2015 .ring_dir = HAL_SRNG_DST_RING,
2016 /* reg_start is not set because LMAC rings are not accessed
2017 * from host
2018 */
2019 .reg_start = {},
2020 .reg_size = {},
2021 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2022 },
2023
2024 { /* DIR_BUF_RX_DMA_SRC */
2025 .start_ring_id = HAL_SRNG_DIR_BUF_RX_SRC_DMA_RING,
2026 /* one ring for spectral, one ring for cfr and
2027 * another one ring for txbf cv upload.
2028 */
2029 .max_rings = 3,
2030 .entry_size = 2,
2031 .lmac_ring = TRUE,
2032 .ring_dir = HAL_SRNG_SRC_RING,
2033 /* reg_start is not set because LMAC rings are not accessed
2034 * from host
2035 */
2036 .reg_start = {},
2037 .reg_size = {},
2038 .max_size = HAL_RXDMA_MAX_RING_SIZE,
2039 },
2040 #ifdef WLAN_FEATURE_CIF_CFR
2041 { /* WIFI_POS_SRC */
2042 .start_ring_id = HAL_SRNG_WIFI_POS_SRC_DMA_RING,
2043 .max_rings = 1,
2044 .entry_size = sizeof(wmi_oem_dma_buf_release_entry) >> 2,
2045 .lmac_ring = TRUE,
2046 .ring_dir = HAL_SRNG_SRC_RING,
2047 /* reg_start is not set because LMAC rings are not accessed
2048 * from host
2049 */
2050 .reg_start = {},
2051 .reg_size = {},
2052 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2053 },
2054 #endif
2055 /* PPE rings are not present in Miami. Added dummy entries to preserve
2056 * Array Index
2057 */
2058 /* REO2PPE */
2059 {},
2060 /* PPE2TCL */
2061 {},
2062 /* PPE_RELEASE */
2063 {},
2064 #ifdef WLAN_PKT_CAPTURE_TX_2_0
2065 { /* TX_MONITOR_BUF */
2066 .start_ring_id = HAL_SRNG_SW2TXMON_BUF0,
2067 .max_rings = 1,
2068 .entry_size = sizeof(struct mon_ingress_ring) >> 2,
2069 .lmac_ring = TRUE,
2070 .ring_dir = HAL_SRNG_SRC_RING,
2071 /* reg_start is not set because LMAC rings are not accessed
2072 * from host
2073 */
2074 .reg_start = {},
2075 .reg_size = {},
2076 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2077 },
2078 { /* TX_MONITOR_DST */
2079 .start_ring_id = HAL_SRNG_WMAC1_TXMON2SW0,
2080 .max_rings = 2,
2081 .entry_size = sizeof(struct mon_destination_ring) >> 2,
2082 .lmac_ring = TRUE,
2083 .ring_dir = HAL_SRNG_DST_RING,
2084 /* reg_start is not set because LMAC rings are not accessed
2085 * from host
2086 */
2087 .reg_start = {},
2088 .reg_size = {},
2089 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2090 },
2091 #else
2092 {},
2093 {},
2094 #endif
2095 { /* SW2RXDMA */
2096 .start_ring_id = HAL_SRNG_SW2RXDMA_BUF0,
2097 .max_rings = 3,
2098 .entry_size = sizeof(struct reo_entrance_ring) >> 2,
2099 .lmac_ring = TRUE,
2100 .ring_dir = HAL_SRNG_SRC_RING,
2101 /* reg_start is not set because LMAC rings are not accessed
2102 * from host
2103 */
2104 .reg_start = {},
2105 .reg_size = {},
2106 .max_size = HAL_RXDMA_MAX_RING_SIZE_BE,
2107 .dmac_cmn_ring = TRUE,
2108 },
2109 { /* SW2RXDMA_LINK_RELEASE */ 0},
2110 };
2111
2112 /**
2113 * hal_srng_hw_reg_offset_init_qca5332() - Initialize the HW srng reg offset
2114 * applicable only for qca5332
2115 * @hal_soc: HAL Soc handle
2116 *
2117 * Return: None
2118 */
hal_srng_hw_reg_offset_init_qca5332(struct hal_soc * hal_soc)2119 static inline void hal_srng_hw_reg_offset_init_qca5332(struct hal_soc *hal_soc)
2120 {
2121 int32_t *hw_reg_offset = hal_soc->hal_hw_reg_offset;
2122
2123 hw_reg_offset[DST_MSI2_BASE_LSB] = REG_OFFSET(DST, MSI2_BASE_LSB),
2124 hw_reg_offset[DST_MSI2_BASE_MSB] = REG_OFFSET(DST, MSI2_BASE_MSB),
2125 hw_reg_offset[DST_MSI2_DATA] = REG_OFFSET(DST, MSI2_DATA),
2126 hw_reg_offset[DST_PRODUCER_INT2_SETUP] =
2127 REG_OFFSET(DST, PRODUCER_INT2_SETUP);
2128 }
2129
2130 /**
2131 * hal_qca5332_attach() - Attach 5332 target specific hal_soc ops,
2132 * offset and srng table
2133 * @hal_soc: hal_soc handle
2134 *
2135 * Return: void
2136 */
hal_qca5332_attach(struct hal_soc * hal_soc)2137 void hal_qca5332_attach(struct hal_soc *hal_soc)
2138 {
2139 hal_soc->hw_srng_table = hw_srng_table_5332;
2140
2141 hal_srng_hw_reg_offset_init_generic(hal_soc);
2142 hal_srng_hw_reg_offset_init_qca5332(hal_soc);
2143
2144 hal_hw_txrx_default_ops_attach_be(hal_soc);
2145 hal_hw_txrx_ops_attach_qca5332(hal_soc);
2146 hal_soc->dmac_cmn_src_rxbuf_ring = true;
2147 }
2148