1 /* 2 * Copyright (c) 2016-2021 The Linux Foundation. All rights reserved. 3 * Copyright (c) 2021-2024 Qualcomm Innovation Center, Inc. All rights reserved. 4 * 5 * Permission to use, copy, modify, and/or distribute this software for 6 * any purpose with or without fee is hereby granted, provided that the 7 * above copyright notice and this permission notice appear in all 8 * copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL 11 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED 12 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE 13 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL 14 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR 15 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 16 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR 17 * PERFORMANCE OF THIS SOFTWARE. 18 */ 19 20 #include "hal_li_api.h" 21 #include "hal_li_hw_headers.h" 22 #include "hal_li_reo.h" 23 24 #include "hal_rx.h" 25 #include "hal_li_rx.h" 26 #include "hal_tx.h" 27 #include <hal_api_mon.h> 28 29 static uint16_t hal_get_rx_max_ba_window_li(int tid) 30 { 31 return HAL_RX_BA_WINDOW_256; 32 } 33 34 static uint32_t hal_get_reo_qdesc_size_li(uint32_t ba_window_size, int tid) 35 { 36 /* Hardcode the ba_window_size to HAL_RX_MAX_BA_WINDOW for 37 * NON_QOS_TID until HW issues are resolved. 38 */ 39 if (tid != HAL_NON_QOS_TID) 40 ba_window_size = hal_get_rx_max_ba_window_li(tid); 41 42 /* Return descriptor size corresponding to window size of 2 since 43 * we set ba_window_size to 2 while setting up REO descriptors as 44 * a WAR to get 2k jump exception aggregates are received without 45 * a BA session. 46 */ 47 if (ba_window_size <= 1) { 48 if (tid != HAL_NON_QOS_TID) 49 return sizeof(struct rx_reo_queue) + 50 sizeof(struct rx_reo_queue_ext); 51 else 52 return sizeof(struct rx_reo_queue); 53 } 54 55 if (ba_window_size <= 105) 56 return sizeof(struct rx_reo_queue) + 57 sizeof(struct rx_reo_queue_ext); 58 59 if (ba_window_size <= 210) 60 return sizeof(struct rx_reo_queue) + 61 (2 * sizeof(struct rx_reo_queue_ext)); 62 63 return sizeof(struct rx_reo_queue) + 64 (3 * sizeof(struct rx_reo_queue_ext)); 65 } 66 67 void hal_set_link_desc_addr_li(void *desc, uint32_t cookie, 68 qdf_dma_addr_t link_desc_paddr, 69 uint8_t bm_id) 70 { 71 uint32_t *buf_addr = (uint32_t *)desc; 72 73 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_0, BUFFER_ADDR_31_0, 74 link_desc_paddr & 0xffffffff); 75 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, BUFFER_ADDR_39_32, 76 (uint64_t)link_desc_paddr >> 32); 77 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, RETURN_BUFFER_MANAGER, 78 bm_id); 79 HAL_DESC_SET_FIELD(buf_addr, BUFFER_ADDR_INFO_1, SW_BUFFER_COOKIE, 80 cookie); 81 } 82 83 void hal_tx_init_data_ring_li(hal_soc_handle_t hal_soc_hdl, 84 hal_ring_handle_t hal_ring_hdl) 85 { 86 uint8_t *desc_addr; 87 struct hal_srng_params srng_params; 88 uint32_t desc_size; 89 uint32_t num_desc; 90 91 hal_get_srng_params(hal_soc_hdl, hal_ring_hdl, &srng_params); 92 93 desc_addr = (uint8_t *)srng_params.ring_base_vaddr; 94 desc_size = sizeof(struct tcl_data_cmd); 95 num_desc = srng_params.num_entries; 96 97 while (num_desc) { 98 HAL_TX_DESC_SET_TLV_HDR(desc_addr, HAL_TX_TCL_DATA_TAG, 99 desc_size); 100 desc_addr += (desc_size + sizeof(struct tlv_32_hdr)); 101 num_desc--; 102 } 103 } 104 105 /** 106 * hal_rx_msdu_is_wlan_mcast_generic_li(): Check if the buffer is for multicast 107 * address 108 * @nbuf: Network buffer 109 * 110 * Returns: flag to indicate whether the nbuf has MC/BC address 111 */ 112 static uint32_t hal_rx_msdu_is_wlan_mcast_generic_li(qdf_nbuf_t nbuf) 113 { 114 uint8_t *buf = qdf_nbuf_data(nbuf); 115 116 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 117 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 118 119 return rx_attn->mcast_bcast; 120 } 121 122 /** 123 * hal_rx_tlv_decap_format_get_li() - Get packet decap format from the TLV 124 * @hw_desc_addr: rx tlv desc 125 * 126 * Return: pkt decap format 127 */ 128 static uint32_t hal_rx_tlv_decap_format_get_li(void *hw_desc_addr) 129 { 130 struct rx_msdu_start *rx_msdu_start; 131 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 132 133 rx_msdu_start = &rx_desc->msdu_start_tlv.rx_msdu_start; 134 135 return HAL_RX_GET(rx_msdu_start, RX_MSDU_START_2, DECAP_FORMAT); 136 } 137 138 /** 139 * hal_rx_dump_pkt_tlvs_li(): API to print all member elements of 140 * RX TLVs 141 * @hal_soc_hdl: hal_soc handle 142 * @buf: pointer the pkt buffer. 143 * @dbg_level: log level. 144 * 145 * Return: void 146 */ 147 static void hal_rx_dump_pkt_tlvs_li(hal_soc_handle_t hal_soc_hdl, 148 uint8_t *buf, uint8_t dbg_level) 149 { 150 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 151 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 152 153 hal_rx_dump_msdu_end_tlv(hal_soc, pkt_tlvs, dbg_level); 154 hal_rx_dump_rx_attention_tlv(hal_soc, pkt_tlvs, dbg_level); 155 hal_rx_dump_msdu_start_tlv(hal_soc, pkt_tlvs, dbg_level); 156 hal_rx_dump_mpdu_start_tlv(hal_soc, pkt_tlvs, dbg_level); 157 hal_rx_dump_mpdu_end_tlv(hal_soc, pkt_tlvs, dbg_level); 158 hal_rx_dump_pkt_hdr_tlv(hal_soc, pkt_tlvs, dbg_level); 159 } 160 161 /** 162 * hal_rx_tlv_get_offload_info_li() - Get the offload info from TLV 163 * @rx_tlv: RX tlv start address in buffer 164 * @offload_info: Buffer to store the offload info 165 * 166 * Return: 0 on success, -EINVAL on failure. 167 */ 168 static int 169 hal_rx_tlv_get_offload_info_li(uint8_t *rx_tlv, 170 struct hal_offload_info *offload_info) 171 { 172 offload_info->flow_id = HAL_RX_TLV_GET_FLOW_ID_TOEPLITZ(rx_tlv); 173 offload_info->ipv6_proto = HAL_RX_TLV_GET_IPV6(rx_tlv); 174 offload_info->lro_eligible = HAL_RX_TLV_GET_LRO_ELIGIBLE(rx_tlv); 175 offload_info->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(rx_tlv); 176 177 if (offload_info->tcp_proto) { 178 offload_info->tcp_pure_ack = 179 HAL_RX_TLV_GET_TCP_PURE_ACK(rx_tlv); 180 offload_info->tcp_offset = HAL_RX_TLV_GET_TCP_OFFSET(rx_tlv); 181 offload_info->tcp_win = HAL_RX_TLV_GET_TCP_WIN(rx_tlv); 182 offload_info->tcp_seq_num = HAL_RX_TLV_GET_TCP_SEQ(rx_tlv); 183 offload_info->tcp_ack_num = HAL_RX_TLV_GET_TCP_ACK(rx_tlv); 184 } 185 return 0; 186 } 187 188 /** 189 * hal_rx_attn_phy_ppdu_id_get_li(): get phy_ppdu_id value 190 * from rx attention 191 * @buf: pointer to rx_pkt_tlvs 192 * 193 * Return: phy_ppdu_id 194 */ 195 static uint16_t hal_rx_attn_phy_ppdu_id_get_li(uint8_t *buf) 196 { 197 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 198 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 199 uint16_t phy_ppdu_id; 200 201 phy_ppdu_id = HAL_RX_ATTN_PHY_PPDU_ID_GET(rx_attn); 202 203 return phy_ppdu_id; 204 } 205 206 /** 207 * hal_rx_msdu_start_msdu_len_get_li(): API to get the MSDU length 208 * from rx_msdu_start TLV 209 * 210 * @buf: pointer to the start of RX PKT TLV headers 211 * 212 * Return: msdu length 213 */ 214 static uint32_t hal_rx_msdu_start_msdu_len_get_li(uint8_t *buf) 215 { 216 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 217 struct rx_msdu_start *msdu_start = 218 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 219 uint32_t msdu_len; 220 221 msdu_len = HAL_RX_MSDU_START_MSDU_LEN_GET(msdu_start); 222 223 return msdu_len; 224 } 225 226 /** 227 * hal_rx_get_proto_params_li() - Get l4 proto values from TLV 228 * @buf: rx tlv address 229 * @proto_params: Buffer to store proto parameters 230 * 231 * Return: 0 on success. 232 */ 233 static int hal_rx_get_proto_params_li(uint8_t *buf, void *proto_params) 234 { 235 struct hal_proto_params *param = 236 (struct hal_proto_params *)proto_params; 237 238 param->tcp_proto = HAL_RX_TLV_GET_TCP_PROTO(buf); 239 param->udp_proto = HAL_RX_TLV_GET_UDP_PROTO(buf); 240 param->ipv6_proto = HAL_RX_TLV_GET_IPV6(buf); 241 242 return 0; 243 } 244 245 /** 246 * hal_rx_get_l3_l4_offsets_li() - Get l3/l4 header offset from TLV 247 * @buf: rx tlv start address 248 * @l3_hdr_offset: buffer to store l3 offset 249 * @l4_hdr_offset: buffer to store l4 offset 250 * 251 * Return: 0 on success. 252 */ 253 static int hal_rx_get_l3_l4_offsets_li(uint8_t *buf, uint32_t *l3_hdr_offset, 254 uint32_t *l4_hdr_offset) 255 { 256 *l3_hdr_offset = HAL_RX_TLV_GET_IP_OFFSET(buf); 257 *l4_hdr_offset = HAL_RX_TLV_GET_TCP_OFFSET(buf); 258 259 return 0; 260 } 261 262 #ifdef NO_RX_PKT_HDR_TLV 263 /** 264 * hal_rx_pkt_hdr_get_li() - Get rx packet header start address. 265 * @buf: packet start address 266 * 267 * Return: packet data start address. 268 */ 269 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 270 { 271 return buf + RX_PKT_TLVS_LEN; 272 } 273 #else 274 static inline uint8_t *hal_rx_pkt_hdr_get_li(uint8_t *buf) 275 { 276 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 277 278 return pkt_tlvs->pkt_hdr_tlv.rx_pkt_hdr; 279 } 280 #endif 281 282 /** 283 * hal_rx_priv_info_set_in_tlv_li(): Save the private info to 284 * the reserved bytes of rx_tlv_hdr 285 * @buf: start of rx_tlv_hdr 286 * @priv_data: hal_wbm_err_desc_info structure 287 * @len: length of the private data 288 * Return: void 289 */ 290 static inline void 291 hal_rx_priv_info_set_in_tlv_li(uint8_t *buf, uint8_t *priv_data, 292 uint32_t len) 293 { 294 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 295 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 296 RX_PADDING0_BYTES : len; 297 298 qdf_mem_copy(pkt_tlvs->rx_padding0, priv_data, copy_len); 299 } 300 301 /** 302 * hal_rx_priv_info_get_from_tlv_li(): retrieve the private data from 303 * the reserved bytes of rx_tlv_hdr. 304 * @buf: start of rx_tlv_hdr 305 * @priv_data: hal_wbm_err_desc_info structure 306 * @len: length of the private data 307 * Return: void 308 */ 309 static inline void 310 hal_rx_priv_info_get_from_tlv_li(uint8_t *buf, uint8_t *priv_data, 311 uint32_t len) 312 { 313 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 314 uint32_t copy_len = (len > RX_PADDING0_BYTES) ? 315 RX_PADDING0_BYTES : len; 316 317 qdf_mem_copy(priv_data, pkt_tlvs->rx_padding0, copy_len); 318 } 319 320 /** 321 * hal_rx_get_tlv_size_generic_li() - Get rx packet tlv size 322 * @rx_pkt_tlv_size: TLV size for regular RX packets 323 * @rx_mon_pkt_tlv_size: TLV size for monitor mode packets 324 * 325 * Return: size of rx pkt tlv before the actual data 326 */ 327 static void hal_rx_get_tlv_size_generic_li(uint16_t *rx_pkt_tlv_size, 328 uint16_t *rx_mon_pkt_tlv_size) 329 { 330 *rx_pkt_tlv_size = RX_PKT_TLVS_LEN; 331 *rx_mon_pkt_tlv_size = SIZE_OF_MONITOR_TLV; 332 } 333 334 /** 335 * hal_rx_wbm_err_src_get_li() - Get WBM error source from descriptor 336 * @ring_desc: ring descriptor 337 * 338 * Return: wbm error source 339 */ 340 uint32_t hal_rx_wbm_err_src_get_li(hal_ring_desc_t ring_desc) 341 { 342 return HAL_WBM2SW_RELEASE_SRC_GET(ring_desc); 343 } 344 345 /** 346 * hal_rx_ret_buf_manager_get_li() - Get return buffer manager from ring desc 347 * @ring_desc: ring descriptor 348 * 349 * Return: rbm 350 */ 351 uint8_t hal_rx_ret_buf_manager_get_li(hal_ring_desc_t ring_desc) 352 { 353 /* 354 * The following macro takes buf_addr_info as argument, 355 * but since buf_addr_info is the first field in ring_desc 356 * Hence the following call is OK 357 */ 358 return HAL_RX_BUF_RBM_GET(ring_desc); 359 } 360 361 /** 362 * hal_rx_reo_buf_paddr_get_li() - Gets the physical address and 363 * cookie from the REO destination ring element 364 * 365 * @rx_desc: Opaque cookie pointer used by HAL to get to 366 * the current descriptor 367 * @buf_info: structure to return the buffer information 368 * 369 * Return: void 370 */ 371 static void hal_rx_reo_buf_paddr_get_li(hal_ring_desc_t rx_desc, 372 struct hal_buf_info *buf_info) 373 { 374 struct reo_destination_ring *reo_ring = 375 (struct reo_destination_ring *)rx_desc; 376 377 buf_info->paddr = 378 (HAL_RX_REO_BUFFER_ADDR_31_0_GET(reo_ring) | 379 ((uint64_t)(HAL_RX_REO_BUFFER_ADDR_39_32_GET(reo_ring)) << 32)); 380 buf_info->sw_cookie = HAL_RX_REO_BUF_COOKIE_GET(reo_ring); 381 } 382 383 /** 384 * hal_rx_msdu_link_desc_set_li() - Retrieves MSDU Link Descriptor to WBM 385 * 386 * @hal_soc_hdl: HAL version of the SOC pointer 387 * @src_srng_desc: void pointer to the WBM Release Ring descriptor 388 * @buf_addr_info: void pointer to the buffer_addr_info 389 * @bm_action: put in IDLE list or release to MSDU_LIST 390 * 391 * Return: void 392 */ 393 /* look at implementation at dp_hw_link_desc_pool_setup()*/ 394 static void hal_rx_msdu_link_desc_set_li(hal_soc_handle_t hal_soc_hdl, 395 void *src_srng_desc, 396 hal_buff_addrinfo_t buf_addr_info, 397 uint8_t bm_action) 398 { 399 /* 400 * The offsets for fields used in this function are same in 401 * wbm_release_ring for Lithium and wbm_release_ring_tx 402 * for Beryllium. hence we can use wbm_release_ring directly. 403 */ 404 struct wbm_release_ring *wbm_rel_srng = 405 (struct wbm_release_ring *)src_srng_desc; 406 uint32_t addr_31_0; 407 uint8_t addr_39_32; 408 409 /* Structure copy !!! */ 410 wbm_rel_srng->released_buff_or_desc_addr_info = 411 *(struct buffer_addr_info *)buf_addr_info; 412 413 addr_31_0 = 414 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_31_0; 415 addr_39_32 = 416 wbm_rel_srng->released_buff_or_desc_addr_info.buffer_addr_39_32; 417 418 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 419 RELEASE_SOURCE_MODULE, HAL_RX_WBM_ERR_SRC_SW); 420 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, BM_ACTION, 421 bm_action); 422 HAL_DESC_SET_FIELD(src_srng_desc, HAL_SW2WBM_RELEASE_RING, 423 BUFFER_OR_DESC_TYPE, 424 HAL_RX_WBM_BUF_TYPE_MSDU_LINK_DESC); 425 426 /* WBM error is indicated when any of the link descriptors given to 427 * WBM has a NULL address, and one those paths is the link descriptors 428 * released from host after processing RXDMA errors, 429 * or from Rx defrag path, and we want to add an assert here to ensure 430 * host is not releasing descriptors with NULL address. 431 */ 432 433 if (qdf_unlikely(!addr_31_0 && !addr_39_32)) { 434 hal_dump_wbm_rel_desc(src_srng_desc); 435 qdf_assert_always(0); 436 } 437 } 438 439 static 440 void hal_rx_buf_cookie_rbm_get_li(uint32_t *buf_addr_info_hdl, 441 hal_buf_info_t buf_info_hdl) 442 { 443 struct hal_buf_info *buf_info = 444 (struct hal_buf_info *)buf_info_hdl; 445 struct buffer_addr_info *buf_addr_info = 446 (struct buffer_addr_info *)buf_addr_info_hdl; 447 448 buf_info->sw_cookie = HAL_RX_BUF_COOKIE_GET(buf_addr_info); 449 /* 450 * buffer addr info is the first member of ring desc, so the typecast 451 * can be done. 452 */ 453 buf_info->rbm = hal_rx_ret_buf_manager_get_li 454 ((hal_ring_desc_t)buf_addr_info); 455 } 456 457 /** 458 * hal_rx_msdu_list_get_li(): API to get the MSDU information 459 * from the MSDU link descriptor 460 * 461 * @hal_soc_hdl: HAL version of the SOC pointer 462 * @msdu_link_desc: Opaque pointer used by HAL to get to the 463 * MSDU link descriptor (struct rx_msdu_link) 464 * 465 * @hal_msdu_list: Return the list of MSDUs contained in this link descriptor 466 * 467 * @num_msdus: Number of MSDUs in the MPDU 468 * 469 * Return: void 470 */ 471 static inline void hal_rx_msdu_list_get_li(hal_soc_handle_t hal_soc_hdl, 472 void *msdu_link_desc, 473 void *hal_msdu_list, 474 uint16_t *num_msdus) 475 { 476 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 477 struct rx_msdu_details *msdu_details; 478 struct rx_msdu_desc_info *msdu_desc_info; 479 struct hal_rx_msdu_list *msdu_list = hal_msdu_list; 480 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 481 int i; 482 struct hal_buf_info buf_info; 483 484 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 485 486 hal_debug("msdu_link=%pK msdu_details=%pK", msdu_link, msdu_details); 487 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 488 /* num_msdus received in mpdu descriptor may be incorrect 489 * sometimes due to HW issue. Check msdu buffer address also 490 */ 491 if (!i && (HAL_RX_BUFFER_ADDR_31_0_GET( 492 &msdu_details[i].buffer_addr_info_details) == 0)) 493 break; 494 if (HAL_RX_BUFFER_ADDR_31_0_GET( 495 &msdu_details[i].buffer_addr_info_details) == 0) { 496 /* set the last msdu bit in the prev msdu_desc_info */ 497 msdu_desc_info = 498 hal_rx_msdu_desc_info_get_ptr 499 (&msdu_details[i - 1], hal_soc); 500 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 501 break; 502 } 503 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[i], 504 hal_soc); 505 506 /* set first MSDU bit or the last MSDU bit */ 507 if (!i) 508 HAL_RX_FIRST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 509 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 510 HAL_RX_LAST_MSDU_IN_MPDU_FLAG_SET(msdu_desc_info, 1); 511 512 msdu_list->msdu_info[i].msdu_flags = 513 hal_rx_msdu_flags_get(hal_soc_hdl, msdu_desc_info); 514 msdu_list->msdu_info[i].msdu_len = 515 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info); 516 517 /* addr field in buf_info will not be valid */ 518 hal_rx_buf_cookie_rbm_get_li( 519 (uint32_t *) 520 &msdu_details[i].buffer_addr_info_details, 521 &buf_info); 522 msdu_list->sw_cookie[i] = buf_info.sw_cookie; 523 msdu_list->rbm[i] = buf_info.rbm; 524 msdu_list->paddr[i] = HAL_RX_BUFFER_ADDR_31_0_GET( 525 &msdu_details[i].buffer_addr_info_details) | 526 (uint64_t)HAL_RX_BUFFER_ADDR_39_32_GET( 527 &msdu_details[i].buffer_addr_info_details) << 32; 528 hal_debug("i=%d sw_cookie=%d", i, msdu_list->sw_cookie[i]); 529 } 530 *num_msdus = i; 531 } 532 533 /* 534 * hal_rxdma_buff_addr_info_set() - set the buffer_addr_info of the 535 * rxdma ring entry. 536 * @rxdma_entry: descriptor entry 537 * @paddr: physical address of nbuf data pointer. 538 * @cookie: SW cookie used as a index to SW rx desc. 539 * @manager: who owns the nbuf (host, NSS, etc...). 540 * 541 */ 542 static void hal_rxdma_buff_addr_info_set_li(void *rxdma_entry, 543 qdf_dma_addr_t paddr, uint32_t cookie, uint8_t manager) 544 { 545 uint32_t paddr_lo = ((u64)paddr & 0x00000000ffffffff); 546 uint32_t paddr_hi = ((u64)paddr & 0xffffffff00000000) >> 32; 547 548 HAL_RXDMA_PADDR_LO_SET(rxdma_entry, paddr_lo); 549 HAL_RXDMA_PADDR_HI_SET(rxdma_entry, paddr_hi); 550 HAL_RXDMA_COOKIE_SET(rxdma_entry, cookie); 551 HAL_RXDMA_MANAGER_SET(rxdma_entry, manager); 552 } 553 554 /** 555 * hal_rx_get_reo_error_code_li() - Get REO error code from ring desc 556 * @rx_desc: rx descriptor 557 * 558 * Return: REO error code 559 */ 560 static uint32_t hal_rx_get_reo_error_code_li(hal_ring_desc_t rx_desc) 561 { 562 struct reo_destination_ring *reo_desc = 563 (struct reo_destination_ring *)rx_desc; 564 565 return HAL_RX_REO_ERROR_GET(reo_desc); 566 } 567 568 /** 569 * hal_gen_reo_remap_val_generic_li() - Generate the reo map value 570 * @remap_reg: remap register 571 * @ix0_map: mapping values for reo 572 * 573 * Return: IX0 reo remap register value to be written 574 */ 575 static uint32_t 576 hal_gen_reo_remap_val_generic_li(enum hal_reo_remap_reg remap_reg, 577 uint8_t *ix0_map) 578 { 579 uint32_t ix_val = 0; 580 581 switch (remap_reg) { 582 case HAL_REO_REMAP_REG_IX0: 583 ix_val = HAL_REO_REMAP_IX0(ix0_map[0], 0) | 584 HAL_REO_REMAP_IX0(ix0_map[1], 1) | 585 HAL_REO_REMAP_IX0(ix0_map[2], 2) | 586 HAL_REO_REMAP_IX0(ix0_map[3], 3) | 587 HAL_REO_REMAP_IX0(ix0_map[4], 4) | 588 HAL_REO_REMAP_IX0(ix0_map[5], 5) | 589 HAL_REO_REMAP_IX0(ix0_map[6], 6) | 590 HAL_REO_REMAP_IX0(ix0_map[7], 7); 591 break; 592 case HAL_REO_REMAP_REG_IX2: 593 ix_val = HAL_REO_REMAP_IX2(ix0_map[0], 16) | 594 HAL_REO_REMAP_IX2(ix0_map[1], 17) | 595 HAL_REO_REMAP_IX2(ix0_map[2], 18) | 596 HAL_REO_REMAP_IX2(ix0_map[3], 19) | 597 HAL_REO_REMAP_IX2(ix0_map[4], 20) | 598 HAL_REO_REMAP_IX2(ix0_map[5], 21) | 599 HAL_REO_REMAP_IX2(ix0_map[6], 22) | 600 HAL_REO_REMAP_IX2(ix0_map[7], 23); 601 break; 602 default: 603 break; 604 } 605 606 return ix_val; 607 } 608 609 /** 610 * hal_rx_tlv_csum_err_get_li() - Get IP and tcp-udp checksum fail flag 611 * @rx_tlv_hdr: start address of rx_tlv_hdr 612 * @ip_csum_err: buffer to return ip_csum_fail flag 613 * @tcp_udp_csum_err: placeholder to return tcp-udp checksum fail flag 614 * 615 * Return: None 616 */ 617 static inline void 618 hal_rx_tlv_csum_err_get_li(uint8_t *rx_tlv_hdr, uint32_t *ip_csum_err, 619 uint32_t *tcp_udp_csum_err) 620 { 621 *ip_csum_err = hal_rx_attn_ip_cksum_fail_get(rx_tlv_hdr); 622 *tcp_udp_csum_err = hal_rx_attn_tcp_udp_cksum_fail_get(rx_tlv_hdr); 623 } 624 625 static uint8_t hal_rx_err_status_get_li(hal_ring_desc_t rx_desc) 626 { 627 return HAL_RX_ERROR_STATUS_GET(rx_desc); 628 } 629 630 static uint8_t hal_rx_reo_buf_type_get_li(hal_ring_desc_t rx_desc) 631 { 632 return HAL_RX_REO_BUF_TYPE_GET(rx_desc); 633 } 634 635 static 636 uint32_t hal_rx_tlv_mpdu_len_err_get_li(void *hw_desc_addr) 637 { 638 struct rx_attention *rx_attn; 639 struct rx_mon_pkt_tlvs *rx_desc = 640 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 641 642 rx_attn = &rx_desc->attn_tlv.rx_attn; 643 644 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, MPDU_LENGTH_ERR); 645 } 646 647 static 648 uint32_t hal_rx_tlv_mpdu_fcs_err_get_li(void *hw_desc_addr) 649 { 650 struct rx_attention *rx_attn; 651 struct rx_mon_pkt_tlvs *rx_desc = 652 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 653 654 rx_attn = &rx_desc->attn_tlv.rx_attn; 655 656 return HAL_RX_GET(rx_attn, RX_ATTENTION_1, FCS_ERR); 657 } 658 659 #ifdef NO_RX_PKT_HDR_TLV 660 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 661 { 662 uint8_t *rx_pkt_hdr; 663 struct rx_mon_pkt_tlvs *rx_desc = 664 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 665 666 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 667 668 return rx_pkt_hdr; 669 } 670 #else 671 static uint8_t *hal_rx_desc_get_80211_hdr_li(void *hw_desc_addr) 672 { 673 uint8_t *rx_pkt_hdr; 674 675 struct rx_pkt_tlvs *rx_desc = (struct rx_pkt_tlvs *)hw_desc_addr; 676 677 rx_pkt_hdr = &rx_desc->pkt_hdr_tlv.rx_pkt_hdr[0]; 678 679 return rx_pkt_hdr; 680 } 681 #endif 682 683 static uint32_t hal_rx_hw_desc_mpdu_user_id_li(void *hw_desc_addr) 684 { 685 struct rx_mon_pkt_tlvs *rx_desc = 686 (struct rx_mon_pkt_tlvs *)hw_desc_addr; 687 uint32_t user_id; 688 689 user_id = HAL_RX_GET_USER_TLV32_USERID( 690 &rx_desc->mpdu_start_tlv); 691 692 return user_id; 693 } 694 695 /** 696 * hal_rx_msdu_start_msdu_len_set_li(): API to set the MSDU length 697 * from rx_msdu_start TLV 698 * 699 * @buf: pointer to the start of RX PKT TLV headers 700 * @len: msdu length 701 * 702 * Return: none 703 */ 704 static inline void 705 hal_rx_msdu_start_msdu_len_set_li(uint8_t *buf, uint32_t len) 706 { 707 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 708 struct rx_msdu_start *msdu_start = 709 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 710 void *wrd1; 711 712 wrd1 = (uint8_t *)msdu_start + RX_MSDU_START_1_MSDU_LENGTH_OFFSET; 713 *(uint32_t *)wrd1 &= (~RX_MSDU_START_1_MSDU_LENGTH_MASK); 714 *(uint32_t *)wrd1 |= len; 715 } 716 717 /* 718 * hal_rx_tlv_bw_get_li(): API to get the Bandwidth 719 * Interval from rx_msdu_start 720 * 721 * @buf: pointer to the start of RX PKT TLV header 722 * Return: uint32_t(bw) 723 */ 724 static inline uint32_t hal_rx_tlv_bw_get_li(uint8_t *buf) 725 { 726 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 727 struct rx_msdu_start *msdu_start = 728 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 729 uint32_t bw; 730 731 bw = HAL_RX_MSDU_START_BW_GET(msdu_start); 732 733 return bw; 734 } 735 736 /* 737 * hal_rx_tlv_get_freq_li(): API to get the frequency of operating channel 738 * from rx_msdu_start 739 * 740 * @buf: pointer to the start of RX PKT TLV header 741 * Return: uint32_t(frequency) 742 */ 743 static inline uint32_t 744 hal_rx_tlv_get_freq_li(uint8_t *buf) 745 { 746 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 747 struct rx_msdu_start *msdu_start = 748 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 749 uint32_t freq; 750 751 freq = HAL_RX_MSDU_START_FREQ_GET(msdu_start); 752 753 return freq; 754 } 755 756 /** 757 * hal_rx_tlv_sgi_get_li(): API to get the Short Guard 758 * Interval from rx_msdu_start TLV 759 * 760 * @buf: pointer to the start of RX PKT TLV headers 761 * Return: uint32_t(sgi) 762 */ 763 static inline uint32_t 764 hal_rx_tlv_sgi_get_li(uint8_t *buf) 765 { 766 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 767 struct rx_msdu_start *msdu_start = 768 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 769 uint32_t sgi; 770 771 sgi = HAL_RX_MSDU_START_SGI_GET(msdu_start); 772 773 return sgi; 774 } 775 776 /** 777 * hal_rx_tlv_rate_mcs_get_li(): API to get the MCS rate 778 * from rx_msdu_start TLV 779 * 780 * @buf: pointer to the start of RX PKT TLV headers 781 * Return: uint32_t(rate_mcs) 782 */ 783 static inline uint32_t 784 hal_rx_tlv_rate_mcs_get_li(uint8_t *buf) 785 { 786 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 787 struct rx_msdu_start *msdu_start = 788 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 789 uint32_t rate_mcs; 790 791 rate_mcs = HAL_RX_MSDU_START_RATE_MCS_GET(msdu_start); 792 793 return rate_mcs; 794 } 795 796 /* 797 * hal_rx_tlv_get_pkt_type_li(): API to get the pkt type 798 * from rx_msdu_start 799 * 800 * @buf: pointer to the start of RX PKT TLV header 801 * Return: uint32_t(pkt type) 802 */ 803 804 static inline uint32_t hal_rx_tlv_get_pkt_type_li(uint8_t *buf) 805 { 806 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 807 struct rx_msdu_start *msdu_start = 808 &pkt_tlvs->msdu_start_tlv.rx_msdu_start; 809 uint32_t pkt_type; 810 811 pkt_type = HAL_RX_MSDU_START_PKT_TYPE_GET(msdu_start); 812 813 return pkt_type; 814 } 815 816 /* 817 * hal_rx_tlv_first_mpdu_get_li(): get fist_mpdu bit from rx attention 818 * @buf: pointer to rx_pkt_tlvs 819 * 820 * reutm: uint32_t(first_msdu) 821 */ 822 static inline uint32_t 823 hal_rx_tlv_first_mpdu_get_li(uint8_t *buf) 824 { 825 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 826 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 827 uint32_t first_mpdu; 828 829 first_mpdu = HAL_RX_ATTN_FIRST_MPDU_GET(rx_attn); 830 831 return first_mpdu; 832 } 833 834 /** 835 * hal_rx_phy_legacy_get_rssi_li() - API to get RSSI from TLV 836 * WIFIPHYRX_RSSI_LEGACY_E 837 * @buf: pointer to the start of WIFIPHYRX_RSSI_LEGACY_E TLV 838 * 839 * Return: value of RSSI 840 */ 841 static inline int8_t hal_rx_phy_legacy_get_rssi_li(uint8_t *buf) 842 { 843 return HAL_RX_GET(buf, PHYRX_RSSI_LEGACY_35, RSSI_COMB); 844 } 845 846 /* 847 * hal_rx_msdu_get_keyid_li(): API to get the key id if the decrypted packet 848 * from rx_msdu_end 849 * 850 * @buf: pointer to the start of RX PKT TLV header 851 * Return: uint32_t(key id) 852 */ 853 static inline uint8_t 854 hal_rx_msdu_get_keyid_li(uint8_t *buf) 855 { 856 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 857 struct rx_msdu_end *msdu_end = &pkt_tlvs->msdu_end_tlv.rx_msdu_end; 858 uint32_t keyid_octet; 859 860 keyid_octet = HAL_RX_MSDU_END_KEYID_OCTET_GET(msdu_end); 861 862 return keyid_octet & 0x3; 863 } 864 865 /* 866 * hal_rx_tlv_get_is_decrypted_li(): API to get the decrypt status of the 867 * packet from rx_attention 868 * 869 * @buf: pointer to the start of RX PKT TLV header 870 * Return: uint32_t(decryt status) 871 */ 872 static inline uint32_t 873 hal_rx_tlv_get_is_decrypted_li(uint8_t *buf) 874 { 875 struct rx_pkt_tlvs *pkt_tlvs = (struct rx_pkt_tlvs *)buf; 876 struct rx_attention *rx_attn = &pkt_tlvs->attn_tlv.rx_attn; 877 uint32_t is_decrypt = 0; 878 uint32_t decrypt_status; 879 880 decrypt_status = HAL_RX_ATTN_DECRYPT_STATUS_GET(rx_attn); 881 882 if (!decrypt_status) 883 is_decrypt = 1; 884 885 return is_decrypt; 886 } 887 888 /** 889 * hal_rx_msdu_reo_dst_ind_get_li() - Gets the REO 890 * destination ring ID from the msdu desc info 891 * 892 * @hal_soc_hdl: HAL version of the SOC pointer 893 * @msdu_link_desc: Opaque cookie pointer used by HAL to get to 894 * the current descriptor 895 * 896 * Return: dst_ind (REO destination ring ID) 897 */ 898 static inline uint32_t 899 hal_rx_msdu_reo_dst_ind_get_li(hal_soc_handle_t hal_soc_hdl, 900 void *msdu_link_desc) 901 { 902 struct hal_soc *hal_soc = (struct hal_soc *)hal_soc_hdl; 903 struct rx_msdu_details *msdu_details; 904 struct rx_msdu_desc_info *msdu_desc_info; 905 struct rx_msdu_link *msdu_link = (struct rx_msdu_link *)msdu_link_desc; 906 uint32_t dst_ind; 907 908 msdu_details = hal_rx_link_desc_msdu0_ptr(msdu_link, hal_soc); 909 910 /* The first msdu in the link should exist */ 911 msdu_desc_info = hal_rx_msdu_desc_info_get_ptr(&msdu_details[0], 912 hal_soc); 913 dst_ind = HAL_RX_MSDU_REO_DST_IND_GET(msdu_desc_info); 914 return dst_ind; 915 } 916 917 static inline void 918 hal_mpdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 919 void *ent_desc, 920 void *mpdu_desc, 921 uint32_t seq_no) 922 { 923 struct rx_mpdu_desc_info *mpdu_desc_info = 924 (struct rx_mpdu_desc_info *)mpdu_desc; 925 926 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 927 MSDU_COUNT, 0x1); 928 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 929 MPDU_SEQUENCE_NUMBER, seq_no); 930 /* unset frag bit */ 931 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 932 FRAGMENT_FLAG, 0x0); 933 /* set sa/da valid bits */ 934 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 935 SA_IS_VALID, 0x1); 936 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 937 DA_IS_VALID, 0x1); 938 HAL_RX_MPDU_DESC_INFO_SET(mpdu_desc_info, 939 RAW_MPDU, 0x0); 940 } 941 942 static inline void 943 hal_msdu_desc_info_set_li(hal_soc_handle_t hal_soc_hdl, 944 void *msdu_desc, uint32_t dst_ind, 945 uint32_t nbuf_len) 946 { 947 struct rx_msdu_desc_info *msdu_desc_info = 948 (struct rx_msdu_desc_info *)msdu_desc; 949 950 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 951 FIRST_MSDU_IN_MPDU_FLAG, 1); 952 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 953 LAST_MSDU_IN_MPDU_FLAG, 1); 954 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 955 MSDU_CONTINUATION, 0x0); 956 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 957 REO_DESTINATION_INDICATION, 958 dst_ind); 959 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 960 MSDU_LENGTH, nbuf_len); 961 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 962 SA_IS_VALID, 1); 963 HAL_RX_MSDU_DESC_INFO_SET(msdu_desc_info, 964 DA_IS_VALID, 1); 965 } 966 967 static inline 968 uint8_t *hal_get_reo_ent_desc_qdesc_addr_li(uint8_t *desc) 969 { 970 return desc + REO_ENTRANCE_RING_4_RX_REO_QUEUE_DESC_ADDR_31_0_OFFSET; 971 } 972 973 static inline 974 void hal_set_reo_ent_desc_reo_dest_ind_li(uint8_t *desc, uint32_t dst_ind) 975 { 976 HAL_RX_FLD_SET(desc, REO_ENTRANCE_RING_5, 977 REO_DESTINATION_INDICATION, dst_ind); 978 } 979 980 static inline void 981 hal_rx_wbm_rel_buf_paddr_get_li(hal_ring_desc_t rx_desc, 982 struct hal_buf_info *buf_info) 983 { 984 struct wbm_release_ring *wbm_rel_ring = 985 (struct wbm_release_ring *)rx_desc; 986 987 buf_info->paddr = 988 (HAL_RX_WBM_BUF_ADDR_31_0_GET(wbm_rel_ring) | 989 ((uint64_t)(HAL_RX_WBM_BUF_ADDR_39_32_GET(wbm_rel_ring)) << 32)); 990 991 buf_info->sw_cookie = HAL_RX_WBM_BUF_COOKIE_GET(wbm_rel_ring); 992 } 993 994 static QDF_STATUS hal_reo_status_update_li(hal_soc_handle_t hal_soc_hdl, 995 hal_ring_desc_t reo_desc, 996 void *st_handle, 997 uint32_t tlv, int *num_ref) 998 { 999 union hal_reo_status *reo_status_ref; 1000 1001 reo_status_ref = (union hal_reo_status *)st_handle; 1002 1003 switch (tlv) { 1004 case HAL_REO_QUEUE_STATS_STATUS_TLV: 1005 hal_reo_queue_stats_status_li(reo_desc, 1006 &reo_status_ref->queue_status, 1007 hal_soc_hdl); 1008 *num_ref = reo_status_ref->queue_status.header.cmd_num; 1009 break; 1010 case HAL_REO_FLUSH_QUEUE_STATUS_TLV: 1011 hal_reo_flush_queue_status_li(reo_desc, 1012 &reo_status_ref->fl_queue_status, 1013 hal_soc_hdl); 1014 *num_ref = reo_status_ref->fl_queue_status.header.cmd_num; 1015 break; 1016 case HAL_REO_FLUSH_CACHE_STATUS_TLV: 1017 hal_reo_flush_cache_status_li(reo_desc, 1018 &reo_status_ref->fl_cache_status, 1019 hal_soc_hdl); 1020 *num_ref = reo_status_ref->fl_cache_status.header.cmd_num; 1021 break; 1022 case HAL_REO_UNBLK_CACHE_STATUS_TLV: 1023 hal_reo_unblock_cache_status_li( 1024 reo_desc, hal_soc_hdl, 1025 &reo_status_ref->unblk_cache_status); 1026 *num_ref = reo_status_ref->unblk_cache_status.header.cmd_num; 1027 break; 1028 case HAL_REO_TIMOUT_LIST_STATUS_TLV: 1029 hal_reo_flush_timeout_list_status_li( 1030 reo_desc, 1031 &reo_status_ref->fl_timeout_status, 1032 hal_soc_hdl); 1033 *num_ref = reo_status_ref->fl_timeout_status.header.cmd_num; 1034 break; 1035 case HAL_REO_DESC_THRES_STATUS_TLV: 1036 hal_reo_desc_thres_reached_status_li( 1037 reo_desc, 1038 &reo_status_ref->thres_status, 1039 hal_soc_hdl); 1040 *num_ref = reo_status_ref->thres_status.header.cmd_num; 1041 break; 1042 case HAL_REO_UPDATE_RX_QUEUE_STATUS_TLV: 1043 hal_reo_rx_update_queue_status_li( 1044 reo_desc, 1045 &reo_status_ref->rx_queue_status, 1046 hal_soc_hdl); 1047 *num_ref = reo_status_ref->rx_queue_status.header.cmd_num; 1048 break; 1049 default: 1050 QDF_TRACE(QDF_MODULE_ID_DP_REO, QDF_TRACE_LEVEL_WARN, 1051 "hal_soc %pK: no handler for TLV:%d", 1052 hal_soc_hdl, tlv); 1053 return QDF_STATUS_E_FAILURE; 1054 } /* switch */ 1055 1056 return QDF_STATUS_SUCCESS; 1057 } 1058 1059 /** 1060 * hal_get_idle_link_bm_id_li() - Get idle link BM id from chid_id 1061 * @chip_id: mlo chip_id 1062 * 1063 * Returns: RBM ID 1064 */ 1065 static uint8_t hal_get_idle_link_bm_id_li(uint8_t chip_id) 1066 { 1067 return WBM_IDLE_DESC_LIST; 1068 } 1069 1070 static inline uint8_t hal_rx_get_phy_ppdu_id_size_li(void) 1071 { 1072 return sizeof(uint32_t); 1073 } 1074 1075 /** 1076 * hal_rx_parse_eht_sig_hdr_li() 1077 * - process eht sig header 1078 * @hal_soc: HAL soc handle 1079 * @tlv: pointer to EHT SIG TLV buffer 1080 * @ppdu_info_handle: pointer to ppdu_info 1081 * 1082 * Return: None 1083 */ 1084 static inline 1085 void hal_rx_parse_eht_sig_hdr_li(struct hal_soc *hal_soc, uint8_t *tlv, 1086 void *ppdu_info_handle) 1087 { 1088 } 1089 1090 void hal_hw_txrx_default_ops_attach_li(struct hal_soc *hal_soc) 1091 { 1092 hal_soc->ops->hal_get_reo_qdesc_size = hal_get_reo_qdesc_size_li; 1093 hal_soc->ops->hal_get_rx_max_ba_window = 1094 hal_get_rx_max_ba_window_li; 1095 hal_soc->ops->hal_set_link_desc_addr = hal_set_link_desc_addr_li; 1096 hal_soc->ops->hal_tx_init_data_ring = hal_tx_init_data_ring_li; 1097 hal_soc->ops->hal_get_ba_aging_timeout = hal_get_ba_aging_timeout_li; 1098 hal_soc->ops->hal_set_ba_aging_timeout = hal_set_ba_aging_timeout_li; 1099 hal_soc->ops->hal_get_reo_reg_base_offset = 1100 hal_get_reo_reg_base_offset_li; 1101 hal_soc->ops->hal_rx_get_tlv_size = hal_rx_get_tlv_size_generic_li; 1102 hal_soc->ops->hal_rx_msdu_is_wlan_mcast = 1103 hal_rx_msdu_is_wlan_mcast_generic_li; 1104 hal_soc->ops->hal_rx_tlv_decap_format_get = 1105 hal_rx_tlv_decap_format_get_li; 1106 hal_soc->ops->hal_rx_dump_pkt_tlvs = hal_rx_dump_pkt_tlvs_li; 1107 hal_soc->ops->hal_rx_tlv_get_offload_info = 1108 hal_rx_tlv_get_offload_info_li; 1109 hal_soc->ops->hal_rx_tlv_phy_ppdu_id_get = 1110 hal_rx_attn_phy_ppdu_id_get_li; 1111 hal_soc->ops->hal_rx_tlv_msdu_done_get = hal_rx_attn_msdu_done_get_li; 1112 hal_soc->ops->hal_rx_tlv_msdu_len_get = 1113 hal_rx_msdu_start_msdu_len_get_li; 1114 hal_soc->ops->hal_rx_get_proto_params = hal_rx_get_proto_params_li; 1115 hal_soc->ops->hal_rx_get_l3_l4_offsets = hal_rx_get_l3_l4_offsets_li; 1116 1117 hal_soc->ops->hal_rx_reo_buf_paddr_get = hal_rx_reo_buf_paddr_get_li; 1118 hal_soc->ops->hal_rx_msdu_link_desc_set = hal_rx_msdu_link_desc_set_li; 1119 hal_soc->ops->hal_rx_buf_cookie_rbm_get = hal_rx_buf_cookie_rbm_get_li; 1120 hal_soc->ops->hal_rx_ret_buf_manager_get = 1121 hal_rx_ret_buf_manager_get_li; 1122 hal_soc->ops->hal_rxdma_buff_addr_info_set = 1123 hal_rxdma_buff_addr_info_set_li; 1124 hal_soc->ops->hal_rx_msdu_flags_get = hal_rx_msdu_flags_get_li; 1125 hal_soc->ops->hal_rx_get_reo_error_code = hal_rx_get_reo_error_code_li; 1126 hal_soc->ops->hal_gen_reo_remap_val = 1127 hal_gen_reo_remap_val_generic_li; 1128 hal_soc->ops->hal_rx_tlv_csum_err_get = 1129 hal_rx_tlv_csum_err_get_li; 1130 hal_soc->ops->hal_rx_mpdu_desc_info_get = 1131 hal_rx_mpdu_desc_info_get_li; 1132 hal_soc->ops->hal_rx_err_status_get = hal_rx_err_status_get_li; 1133 hal_soc->ops->hal_rx_reo_buf_type_get = hal_rx_reo_buf_type_get_li; 1134 hal_soc->ops->hal_rx_pkt_hdr_get = hal_rx_pkt_hdr_get_li; 1135 hal_soc->ops->hal_rx_wbm_err_src_get = hal_rx_wbm_err_src_get_li; 1136 hal_soc->ops->hal_rx_wbm_rel_buf_paddr_get = 1137 hal_rx_wbm_rel_buf_paddr_get_li; 1138 hal_soc->ops->hal_rx_priv_info_set_in_tlv = 1139 hal_rx_priv_info_set_in_tlv_li; 1140 hal_soc->ops->hal_rx_priv_info_get_from_tlv = 1141 hal_rx_priv_info_get_from_tlv_li; 1142 hal_soc->ops->hal_rx_tlv_mpdu_len_err_get = 1143 hal_rx_tlv_mpdu_len_err_get_li; 1144 hal_soc->ops->hal_rx_tlv_mpdu_fcs_err_get = 1145 hal_rx_tlv_mpdu_fcs_err_get_li; 1146 hal_soc->ops->hal_reo_send_cmd = hal_reo_send_cmd_li; 1147 hal_soc->ops->hal_rx_desc_get_80211_hdr = hal_rx_desc_get_80211_hdr_li; 1148 hal_soc->ops->hal_rx_hw_desc_mpdu_user_id = 1149 hal_rx_hw_desc_mpdu_user_id_li; 1150 hal_soc->ops->hal_reo_qdesc_setup = hal_reo_qdesc_setup_li; 1151 hal_soc->ops->hal_rx_tlv_msdu_len_set = 1152 hal_rx_msdu_start_msdu_len_set_li; 1153 hal_soc->ops->hal_rx_tlv_bw_get = hal_rx_tlv_bw_get_li; 1154 hal_soc->ops->hal_rx_tlv_get_freq = hal_rx_tlv_get_freq_li; 1155 hal_soc->ops->hal_rx_tlv_sgi_get = hal_rx_tlv_sgi_get_li; 1156 hal_soc->ops->hal_rx_tlv_rate_mcs_get = hal_rx_tlv_rate_mcs_get_li; 1157 hal_soc->ops->hal_rx_tlv_get_pkt_type = hal_rx_tlv_get_pkt_type_li; 1158 hal_soc->ops->hal_rx_tlv_first_mpdu_get = hal_rx_tlv_first_mpdu_get_li; 1159 hal_soc->ops->hal_rx_tlv_get_is_decrypted = 1160 hal_rx_tlv_get_is_decrypted_li; 1161 hal_soc->ops->hal_rx_msdu_get_keyid = hal_rx_msdu_get_keyid_li; 1162 hal_soc->ops->hal_rx_msdu_reo_dst_ind_get = 1163 hal_rx_msdu_reo_dst_ind_get_li; 1164 hal_soc->ops->hal_msdu_desc_info_set = hal_msdu_desc_info_set_li; 1165 hal_soc->ops->hal_mpdu_desc_info_set = hal_mpdu_desc_info_set_li; 1166 hal_soc->ops->hal_reo_status_update = hal_reo_status_update_li; 1167 hal_soc->ops->hal_get_tlv_hdr_size = hal_get_tlv_hdr_size_li; 1168 hal_soc->ops->hal_get_reo_ent_desc_qdesc_addr = 1169 hal_get_reo_ent_desc_qdesc_addr_li; 1170 hal_soc->ops->hal_rx_get_qdesc_addr = hal_rx_get_qdesc_addr_li; 1171 hal_soc->ops->hal_set_reo_ent_desc_reo_dest_ind = 1172 hal_set_reo_ent_desc_reo_dest_ind_li; 1173 hal_soc->ops->hal_get_idle_link_bm_id = hal_get_idle_link_bm_id_li; 1174 hal_soc->ops->hal_rx_get_phy_ppdu_id_size = 1175 hal_rx_get_phy_ppdu_id_size_li; 1176 hal_soc->ops->hal_rx_phy_legacy_get_rssi = 1177 hal_rx_phy_legacy_get_rssi_li; 1178 hal_soc->ops->hal_rx_parse_eht_sig_hdr = hal_rx_parse_eht_sig_hdr_li; 1179 } 1180