1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2014-2019 Intel Corporation 4 */ 5 6 #ifndef _INTEL_GUC_FWIF_H 7 #define _INTEL_GUC_FWIF_H 8 9 #include <linux/bits.h> 10 #include <linux/compiler.h> 11 #include <linux/types.h> 12 #include "gt/intel_engine_types.h" 13 14 #include "abi/guc_actions_abi.h" 15 #include "abi/guc_actions_slpc_abi.h" 16 #include "abi/guc_errors_abi.h" 17 #include "abi/guc_communication_mmio_abi.h" 18 #include "abi/guc_communication_ctb_abi.h" 19 #include "abi/guc_klvs_abi.h" 20 #include "abi/guc_messages_abi.h" 21 22 /* Payload length only i.e. don't include G2H header length */ 23 #define G2H_LEN_DW_SCHED_CONTEXT_MODE_SET 2 24 #define G2H_LEN_DW_DEREGISTER_CONTEXT 1 25 #define G2H_LEN_DW_INVALIDATE_TLB 1 26 27 #define GUC_CONTEXT_DISABLE 0 28 #define GUC_CONTEXT_ENABLE 1 29 30 #define GUC_CLIENT_PRIORITY_KMD_HIGH 0 31 #define GUC_CLIENT_PRIORITY_HIGH 1 32 #define GUC_CLIENT_PRIORITY_KMD_NORMAL 2 33 #define GUC_CLIENT_PRIORITY_NORMAL 3 34 #define GUC_CLIENT_PRIORITY_NUM 4 35 36 #define GUC_MAX_CONTEXT_ID 65535 37 #define GUC_INVALID_CONTEXT_ID GUC_MAX_CONTEXT_ID 38 39 #define GUC_RENDER_CLASS 0 40 #define GUC_VIDEO_CLASS 1 41 #define GUC_VIDEOENHANCE_CLASS 2 42 #define GUC_BLITTER_CLASS 3 43 #define GUC_COMPUTE_CLASS 4 44 #define GUC_GSC_OTHER_CLASS 5 45 #define GUC_LAST_ENGINE_CLASS GUC_GSC_OTHER_CLASS 46 #define GUC_MAX_ENGINE_CLASSES 16 47 #define GUC_MAX_INSTANCES_PER_CLASS 32 48 49 #define GUC_DOORBELL_INVALID 256 50 51 /* 52 * Work queue item header definitions 53 * 54 * Work queue is circular buffer used to submit complex (multi-lrc) submissions 55 * to the GuC. A work queue item is an entry in the circular buffer. 56 */ 57 #define WQ_STATUS_ACTIVE 1 58 #define WQ_STATUS_SUSPENDED 2 59 #define WQ_STATUS_CMD_ERROR 3 60 #define WQ_STATUS_ENGINE_ID_NOT_USED 4 61 #define WQ_STATUS_SUSPENDED_FROM_RESET 5 62 #define WQ_TYPE_BATCH_BUF 0x1 63 #define WQ_TYPE_PSEUDO 0x2 64 #define WQ_TYPE_INORDER 0x3 65 #define WQ_TYPE_NOOP 0x4 66 #define WQ_TYPE_MULTI_LRC 0x5 67 #define WQ_TYPE_MASK GENMASK(7, 0) 68 #define WQ_LEN_MASK GENMASK(26, 16) 69 70 #define WQ_GUC_ID_MASK GENMASK(15, 0) 71 #define WQ_RING_TAIL_MASK GENMASK(28, 18) 72 73 #define GUC_STAGE_DESC_ATTR_ACTIVE BIT(0) 74 #define GUC_STAGE_DESC_ATTR_PENDING_DB BIT(1) 75 #define GUC_STAGE_DESC_ATTR_KERNEL BIT(2) 76 #define GUC_STAGE_DESC_ATTR_PREEMPT BIT(3) 77 #define GUC_STAGE_DESC_ATTR_RESET BIT(4) 78 #define GUC_STAGE_DESC_ATTR_WQLOCKED BIT(5) 79 #define GUC_STAGE_DESC_ATTR_PCH BIT(6) 80 #define GUC_STAGE_DESC_ATTR_TERMINATED BIT(7) 81 82 #define GUC_CTL_LOG_PARAMS 0 83 #define GUC_LOG_VALID BIT(0) 84 #define GUC_LOG_NOTIFY_ON_HALF_FULL BIT(1) 85 #define GUC_LOG_CAPTURE_ALLOC_UNITS BIT(2) 86 #define GUC_LOG_LOG_ALLOC_UNITS BIT(3) 87 #define GUC_LOG_CRASH_SHIFT 4 88 #define GUC_LOG_CRASH_MASK (0x3 << GUC_LOG_CRASH_SHIFT) 89 #define GUC_LOG_DEBUG_SHIFT 6 90 #define GUC_LOG_DEBUG_MASK (0xF << GUC_LOG_DEBUG_SHIFT) 91 #define GUC_LOG_CAPTURE_SHIFT 10 92 #define GUC_LOG_CAPTURE_MASK (0x3 << GUC_LOG_CAPTURE_SHIFT) 93 #define GUC_LOG_BUF_ADDR_SHIFT 12 94 95 #define GUC_CTL_WA 1 96 #define GUC_WA_GAM_CREDITS BIT(10) 97 #define GUC_WA_DUAL_QUEUE BIT(11) 98 #define GUC_WA_RCS_RESET_BEFORE_RC6 BIT(13) 99 #define GUC_WA_PRE_PARSER BIT(14) 100 #define GUC_WA_CONTEXT_ISOLATION BIT(15) 101 #define GUC_WA_RCS_CCS_SWITCHOUT BIT(16) 102 #define GUC_WA_HOLD_CCS_SWITCHOUT BIT(17) 103 #define GUC_WA_POLLCS BIT(18) 104 #define GUC_WA_RCS_REGS_IN_CCS_REGS_LIST BIT(21) 105 #define GUC_WA_ENABLE_TSC_CHECK_ON_RC6 BIT(22) 106 107 #define GUC_CTL_FEATURE 2 108 #define GUC_CTL_ENABLE_SLPC BIT(2) 109 #define GUC_CTL_DISABLE_SCHEDULER BIT(14) 110 111 #define GUC_CTL_DEBUG 3 112 #define GUC_LOG_VERBOSITY_SHIFT 0 113 #define GUC_LOG_VERBOSITY_LOW (0 << GUC_LOG_VERBOSITY_SHIFT) 114 #define GUC_LOG_VERBOSITY_MED (1 << GUC_LOG_VERBOSITY_SHIFT) 115 #define GUC_LOG_VERBOSITY_HIGH (2 << GUC_LOG_VERBOSITY_SHIFT) 116 #define GUC_LOG_VERBOSITY_ULTRA (3 << GUC_LOG_VERBOSITY_SHIFT) 117 /* Verbosity range-check limits, without the shift */ 118 #define GUC_LOG_VERBOSITY_MIN 0 119 #define GUC_LOG_VERBOSITY_MAX 3 120 #define GUC_LOG_VERBOSITY_MASK 0x0000000f 121 #define GUC_LOG_DESTINATION_MASK (3 << 4) 122 #define GUC_LOG_DISABLED (1 << 6) 123 #define GUC_PROFILE_ENABLED (1 << 7) 124 125 #define GUC_CTL_ADS 4 126 #define GUC_ADS_ADDR_SHIFT 1 127 #define GUC_ADS_ADDR_MASK (0xFFFFF << GUC_ADS_ADDR_SHIFT) 128 129 #define GUC_CTL_DEVID 5 130 131 #define GUC_CTL_MAX_DWORDS (SOFT_SCRATCH_COUNT - 2) /* [1..14] */ 132 133 /* Generic GT SysInfo data types */ 134 #define GUC_GENERIC_GT_SYSINFO_SLICE_ENABLED 0 135 #define GUC_GENERIC_GT_SYSINFO_VDBOX_SFC_SUPPORT_MASK 1 136 #define GUC_GENERIC_GT_SYSINFO_DOORBELL_COUNT_PER_SQIDI 2 137 #define GUC_GENERIC_GT_SYSINFO_MAX 16 138 139 /* 140 * The class goes in bits [0..2] of the GuC ID, the instance in bits [3..6]. 141 * Bit 7 can be used for operations that apply to all engine classes&instances. 142 */ 143 #define GUC_ENGINE_CLASS_SHIFT 0 144 #define GUC_ENGINE_CLASS_MASK (0x7 << GUC_ENGINE_CLASS_SHIFT) 145 #define GUC_ENGINE_INSTANCE_SHIFT 3 146 #define GUC_ENGINE_INSTANCE_MASK (0xf << GUC_ENGINE_INSTANCE_SHIFT) 147 #define GUC_ENGINE_ALL_INSTANCES BIT(7) 148 149 #define MAKE_GUC_ID(class, instance) \ 150 (((class) << GUC_ENGINE_CLASS_SHIFT) | \ 151 ((instance) << GUC_ENGINE_INSTANCE_SHIFT)) 152 153 #define GUC_ID_TO_ENGINE_CLASS(guc_id) \ 154 (((guc_id) & GUC_ENGINE_CLASS_MASK) >> GUC_ENGINE_CLASS_SHIFT) 155 #define GUC_ID_TO_ENGINE_INSTANCE(guc_id) \ 156 (((guc_id) & GUC_ENGINE_INSTANCE_MASK) >> GUC_ENGINE_INSTANCE_SHIFT) 157 158 #define SLPC_EVENT(id, c) (\ 159 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ID, id) | \ 160 FIELD_PREP(HOST2GUC_PC_SLPC_REQUEST_MSG_1_EVENT_ARGC, c) \ 161 ) 162 163 /* the GuC arrays don't include OTHER_CLASS */ 164 static u8 engine_class_guc_class_map[] = { 165 [RENDER_CLASS] = GUC_RENDER_CLASS, 166 [COPY_ENGINE_CLASS] = GUC_BLITTER_CLASS, 167 [VIDEO_DECODE_CLASS] = GUC_VIDEO_CLASS, 168 [VIDEO_ENHANCEMENT_CLASS] = GUC_VIDEOENHANCE_CLASS, 169 [OTHER_CLASS] = GUC_GSC_OTHER_CLASS, 170 [COMPUTE_CLASS] = GUC_COMPUTE_CLASS, 171 }; 172 173 static u8 guc_class_engine_class_map[] = { 174 [GUC_RENDER_CLASS] = RENDER_CLASS, 175 [GUC_BLITTER_CLASS] = COPY_ENGINE_CLASS, 176 [GUC_VIDEO_CLASS] = VIDEO_DECODE_CLASS, 177 [GUC_VIDEOENHANCE_CLASS] = VIDEO_ENHANCEMENT_CLASS, 178 [GUC_COMPUTE_CLASS] = COMPUTE_CLASS, 179 [GUC_GSC_OTHER_CLASS] = OTHER_CLASS, 180 }; 181 engine_class_to_guc_class(u8 class)182 static inline u8 engine_class_to_guc_class(u8 class) 183 { 184 BUILD_BUG_ON(ARRAY_SIZE(engine_class_guc_class_map) != MAX_ENGINE_CLASS + 1); 185 GEM_BUG_ON(class > MAX_ENGINE_CLASS); 186 187 return engine_class_guc_class_map[class]; 188 } 189 guc_class_to_engine_class(u8 guc_class)190 static inline u8 guc_class_to_engine_class(u8 guc_class) 191 { 192 BUILD_BUG_ON(ARRAY_SIZE(guc_class_engine_class_map) != GUC_LAST_ENGINE_CLASS + 1); 193 GEM_BUG_ON(guc_class > GUC_LAST_ENGINE_CLASS); 194 195 return guc_class_engine_class_map[guc_class]; 196 } 197 198 /* Work item for submitting workloads into work queue of GuC. */ 199 struct guc_wq_item { 200 u32 header; 201 u32 context_desc; 202 u32 submit_element_info; 203 u32 fence_id; 204 } __packed; 205 206 struct guc_process_desc_v69 { 207 u32 stage_id; 208 u64 db_base_addr; 209 u32 head; 210 u32 tail; 211 u32 error_offset; 212 u64 wq_base_addr; 213 u32 wq_size_bytes; 214 u32 wq_status; 215 u32 engine_presence; 216 u32 priority; 217 u32 reserved[36]; 218 } __packed; 219 220 struct guc_sched_wq_desc { 221 u32 head; 222 u32 tail; 223 u32 error_offset; 224 u32 wq_status; 225 u32 reserved[28]; 226 } __packed; 227 228 /* Helper for context registration H2G */ 229 struct guc_ctxt_registration_info { 230 u32 flags; 231 u32 context_idx; 232 u32 engine_class; 233 u32 engine_submit_mask; 234 u32 wq_desc_lo; 235 u32 wq_desc_hi; 236 u32 wq_base_lo; 237 u32 wq_base_hi; 238 u32 wq_size; 239 u32 hwlrca_lo; 240 u32 hwlrca_hi; 241 }; 242 #define CONTEXT_REGISTRATION_FLAG_KMD BIT(0) 243 244 /* Preempt to idle on quantum expiry */ 245 #define CONTEXT_POLICY_FLAG_PREEMPT_TO_IDLE_V69 BIT(0) 246 247 /* 248 * GuC Context registration descriptor. 249 * FIXME: This is only required to exist during context registration. 250 * The current 1:1 between guc_lrc_desc and LRCs for the lifetime of the LRC 251 * is not required. 252 */ 253 struct guc_lrc_desc_v69 { 254 u32 hw_context_desc; 255 u32 slpm_perf_mode_hint; /* SPLC v1 only */ 256 u32 slpm_freq_hint; 257 u32 engine_submit_mask; /* In logical space */ 258 u8 engine_class; 259 u8 reserved0[3]; 260 u32 priority; 261 u32 process_desc; 262 u32 wq_addr; 263 u32 wq_size; 264 u32 context_flags; /* CONTEXT_REGISTRATION_* */ 265 /* Time for one workload to execute. (in micro seconds) */ 266 u32 execution_quantum; 267 /* Time to wait for a preemption request to complete before issuing a 268 * reset. (in micro seconds). 269 */ 270 u32 preemption_timeout; 271 u32 policy_flags; /* CONTEXT_POLICY_* */ 272 u32 reserved1[19]; 273 } __packed; 274 275 /* 32-bit KLV structure as used by policy updates and others */ 276 struct guc_klv_generic_dw_t { 277 u32 kl; 278 u32 value; 279 } __packed; 280 281 /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */ 282 struct guc_update_context_policy_header { 283 u32 action; 284 u32 ctx_id; 285 } __packed; 286 287 struct guc_update_context_policy { 288 struct guc_update_context_policy_header header; 289 struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS]; 290 } __packed; 291 292 /* Format of the UPDATE_SCHEDULING_POLICIES H2G data packet */ 293 struct guc_update_scheduling_policy_header { 294 u32 action; 295 } __packed; 296 297 /* 298 * Can't dynamically allocate memory for the scheduling policy KLV because 299 * it will be sent from within the reset path. Need a fixed size lump on 300 * the stack instead :(. 301 * 302 * Currently, there is only one KLV defined, which has 1 word of KL + 2 words of V. 303 */ 304 #define MAX_SCHEDULING_POLICY_SIZE 3 305 306 struct guc_update_scheduling_policy { 307 struct guc_update_scheduling_policy_header header; 308 u32 data[MAX_SCHEDULING_POLICY_SIZE]; 309 } __packed; 310 311 #define GUC_POWER_UNSPECIFIED 0 312 #define GUC_POWER_D0 1 313 #define GUC_POWER_D1 2 314 #define GUC_POWER_D2 3 315 #define GUC_POWER_D3 4 316 317 /* Scheduling policy settings */ 318 319 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_DURATION 100 /* in ms */ 320 #define GLOBAL_SCHEDULE_POLICY_RC_YIELD_RATIO 50 /* in percent */ 321 322 #define GLOBAL_POLICY_MAX_NUM_WI 15 323 324 /* Don't reset an engine upon preemption failure */ 325 #define GLOBAL_POLICY_DISABLE_ENGINE_RESET BIT(0) 326 327 #define GLOBAL_POLICY_DEFAULT_DPC_PROMOTE_TIME_US 500000 328 329 /* 330 * GuC converts the timeout to clock ticks internally. Different platforms have 331 * different GuC clocks. Thus, the maximum value before overflow is platform 332 * dependent. Current worst case scenario is about 110s. So, the spec says to 333 * limit to 100s to be safe. 334 */ 335 #define GUC_POLICY_MAX_EXEC_QUANTUM_US (100 * 1000 * 1000UL) 336 #define GUC_POLICY_MAX_PREEMPT_TIMEOUT_US (100 * 1000 * 1000UL) 337 guc_policy_max_exec_quantum_ms(void)338 static inline u32 guc_policy_max_exec_quantum_ms(void) 339 { 340 BUILD_BUG_ON(GUC_POLICY_MAX_EXEC_QUANTUM_US >= UINT_MAX); 341 return GUC_POLICY_MAX_EXEC_QUANTUM_US / 1000; 342 } 343 guc_policy_max_preempt_timeout_ms(void)344 static inline u32 guc_policy_max_preempt_timeout_ms(void) 345 { 346 BUILD_BUG_ON(GUC_POLICY_MAX_PREEMPT_TIMEOUT_US >= UINT_MAX); 347 return GUC_POLICY_MAX_PREEMPT_TIMEOUT_US / 1000; 348 } 349 350 struct guc_policies { 351 u32 submission_queue_depth[GUC_MAX_ENGINE_CLASSES]; 352 /* In micro seconds. How much time to allow before DPC processing is 353 * called back via interrupt (to prevent DPC queue drain starving). 354 * Typically 1000s of micro seconds (example only, not granularity). */ 355 u32 dpc_promote_time; 356 357 /* Must be set to take these new values. */ 358 u32 is_valid; 359 360 /* Max number of WIs to process per call. A large value may keep CS 361 * idle. */ 362 u32 max_num_work_items; 363 364 u32 global_flags; 365 u32 reserved[4]; 366 } __packed; 367 368 /* GuC MMIO reg state struct */ 369 struct guc_mmio_reg { 370 u32 offset; 371 u32 value; 372 u32 flags; 373 #define GUC_REGSET_MASKED BIT(0) 374 #define GUC_REGSET_NEEDS_STEERING BIT(1) 375 #define GUC_REGSET_MASKED_WITH_VALUE BIT(2) 376 #define GUC_REGSET_RESTORE_ONLY BIT(3) 377 #define GUC_REGSET_STEERING_GROUP GENMASK(15, 12) 378 #define GUC_REGSET_STEERING_INSTANCE GENMASK(23, 20) 379 u32 mask; 380 } __packed; 381 382 /* GuC register sets */ 383 struct guc_mmio_reg_set { 384 u32 address; 385 u16 count; 386 u16 reserved; 387 } __packed; 388 389 /* HW info */ 390 struct guc_gt_system_info { 391 u8 mapping_table[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 392 u32 engine_enabled_masks[GUC_MAX_ENGINE_CLASSES]; 393 u32 generic_gt_sysinfo[GUC_GENERIC_GT_SYSINFO_MAX]; 394 } __packed; 395 396 enum { 397 GUC_CAPTURE_LIST_INDEX_PF = 0, 398 GUC_CAPTURE_LIST_INDEX_VF = 1, 399 GUC_CAPTURE_LIST_INDEX_MAX = 2, 400 }; 401 402 /*Register-types of GuC capture register lists */ 403 enum guc_capture_type { 404 GUC_CAPTURE_LIST_TYPE_GLOBAL = 0, 405 GUC_CAPTURE_LIST_TYPE_ENGINE_CLASS, 406 GUC_CAPTURE_LIST_TYPE_ENGINE_INSTANCE, 407 GUC_CAPTURE_LIST_TYPE_MAX, 408 }; 409 410 /* Class indecies for capture_class and capture_instance arrays */ 411 enum { 412 GUC_CAPTURE_LIST_CLASS_RENDER_COMPUTE = 0, 413 GUC_CAPTURE_LIST_CLASS_VIDEO = 1, 414 GUC_CAPTURE_LIST_CLASS_VIDEOENHANCE = 2, 415 GUC_CAPTURE_LIST_CLASS_BLITTER = 3, 416 GUC_CAPTURE_LIST_CLASS_GSC_OTHER = 4, 417 }; 418 419 /* GuC Additional Data Struct */ 420 struct guc_ads { 421 struct guc_mmio_reg_set reg_state_list[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 422 u32 reserved0; 423 u32 scheduler_policies; 424 u32 gt_system_info; 425 u32 reserved1; 426 u32 control_data; 427 u32 golden_context_lrca[GUC_MAX_ENGINE_CLASSES]; 428 u32 eng_state_size[GUC_MAX_ENGINE_CLASSES]; 429 u32 private_data; 430 u32 reserved2; 431 u32 capture_instance[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 432 u32 capture_class[GUC_CAPTURE_LIST_INDEX_MAX][GUC_MAX_ENGINE_CLASSES]; 433 u32 capture_global[GUC_CAPTURE_LIST_INDEX_MAX]; 434 u32 wa_klv_addr_lo; 435 u32 wa_klv_addr_hi; 436 u32 wa_klv_size; 437 u32 reserved[11]; 438 } __packed; 439 440 /* Engine usage stats */ 441 struct guc_engine_usage_record { 442 u32 current_context_index; 443 u32 last_switch_in_stamp; 444 u32 reserved0; 445 u32 total_runtime; 446 u32 reserved1[4]; 447 } __packed; 448 449 struct guc_engine_usage { 450 struct guc_engine_usage_record engines[GUC_MAX_ENGINE_CLASSES][GUC_MAX_INSTANCES_PER_CLASS]; 451 } __packed; 452 453 /* GuC logging structures */ 454 455 enum guc_log_buffer_type { 456 GUC_DEBUG_LOG_BUFFER, 457 GUC_CRASH_DUMP_LOG_BUFFER, 458 GUC_CAPTURE_LOG_BUFFER, 459 GUC_MAX_LOG_BUFFER 460 }; 461 462 /* 463 * struct guc_log_buffer_state - GuC log buffer state 464 * 465 * Below state structure is used for coordination of retrieval of GuC firmware 466 * logs. Separate state is maintained for each log buffer type. 467 * read_ptr points to the location where i915 read last in log buffer and 468 * is read only for GuC firmware. write_ptr is incremented by GuC with number 469 * of bytes written for each log entry and is read only for i915. 470 * When any type of log buffer becomes half full, GuC sends a flush interrupt. 471 * GuC firmware expects that while it is writing to 2nd half of the buffer, 472 * first half would get consumed by Host and then get a flush completed 473 * acknowledgment from Host, so that it does not end up doing any overwrite 474 * causing loss of logs. So when buffer gets half filled & i915 has requested 475 * for interrupt, GuC will set flush_to_file field, set the sampled_write_ptr 476 * to the value of write_ptr and raise the interrupt. 477 * On receiving the interrupt i915 should read the buffer, clear flush_to_file 478 * field and also update read_ptr with the value of sample_write_ptr, before 479 * sending an acknowledgment to GuC. marker & version fields are for internal 480 * usage of GuC and opaque to i915. buffer_full_cnt field is incremented every 481 * time GuC detects the log buffer overflow. 482 */ 483 struct guc_log_buffer_state { 484 u32 marker[2]; 485 u32 read_ptr; 486 u32 write_ptr; 487 u32 size; 488 u32 sampled_write_ptr; 489 u32 wrap_offset; 490 union { 491 struct { 492 u32 flush_to_file:1; 493 u32 buffer_full_cnt:4; 494 u32 reserved:27; 495 }; 496 u32 flags; 497 }; 498 u32 version; 499 } __packed; 500 501 /* This action will be programmed in C1BC - SOFT_SCRATCH_15_REG */ 502 enum intel_guc_recv_message { 503 INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED = BIT(1), 504 INTEL_GUC_RECV_MSG_EXCEPTION = BIT(30), 505 }; 506 507 #endif 508