1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */ 2 /* 3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved. 4 * Copyright (c) 2020, Intel Corporation. All rights reserved. 5 */ 6 7 #ifndef MLX5_IB_H 8 #define MLX5_IB_H 9 10 #include <linux/kernel.h> 11 #include <linux/sched.h> 12 #include <rdma/ib_verbs.h> 13 #include <rdma/ib_umem.h> 14 #include <rdma/ib_smi.h> 15 #include <linux/mlx5/driver.h> 16 #include <linux/mlx5/cq.h> 17 #include <linux/mlx5/fs.h> 18 #include <linux/mlx5/qp.h> 19 #include <linux/types.h> 20 #include <linux/mlx5/transobj.h> 21 #include <rdma/ib_user_verbs.h> 22 #include <rdma/mlx5-abi.h> 23 #include <rdma/uverbs_ioctl.h> 24 #include <rdma/mlx5_user_ioctl_cmds.h> 25 #include <rdma/mlx5_user_ioctl_verbs.h> 26 27 #include "srq.h" 28 #include "qp.h" 29 #include "macsec.h" 30 31 #define mlx5_ib_dbg(_dev, format, arg...) \ 32 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 33 __LINE__, current->pid, ##arg) 34 35 #define mlx5_ib_err(_dev, format, arg...) \ 36 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 37 __LINE__, current->pid, ##arg) 38 39 #define mlx5_ib_warn(_dev, format, arg...) \ 40 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \ 41 __LINE__, current->pid, ##arg) 42 43 #define mlx5_ib_log(lvl, _dev, format, arg...) \ 44 dev_printk(lvl, &(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, \ 45 __func__, __LINE__, current->pid, ##arg) 46 47 #define MLX5_IB_DEFAULT_UIDX 0xffffff 48 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index) 49 50 static __always_inline unsigned long __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,unsigned int pgsz_shift)51 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits, 52 unsigned int pgsz_shift) 53 { 54 unsigned int largest_pg_shift = 55 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift, 56 BITS_PER_LONG - 1); 57 58 /* 59 * Despite a command allowing it, the device does not support lower than 60 * 4k page size. 61 */ 62 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift); 63 return GENMASK(largest_pg_shift, pgsz_shift); 64 } 65 66 static __always_inline unsigned long __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,unsigned int offset_shift)67 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits, 68 unsigned int offset_shift) 69 { 70 unsigned int largest_offset_shift = 71 min_t(unsigned long, page_offset_bits - 1 + offset_shift, 72 BITS_PER_LONG - 1); 73 74 return GENMASK(largest_offset_shift, offset_shift); 75 } 76 77 /* 78 * QP/CQ/WQ/etc type commands take a page offset that satisifies: 79 * page_offset_quantized * (page_size/scale) = page_offset 80 * Which restricts allowed page sizes to ones that satisify the above. 81 */ 82 unsigned long __mlx5_umem_find_best_quantized_pgoff( 83 struct ib_umem *umem, unsigned long pgsz_bitmap, 84 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale, 85 unsigned int *page_offset_quantized); 86 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \ 87 pgsz_shift, page_offset_fld, \ 88 scale, page_offset_quantized) \ 89 __mlx5_umem_find_best_quantized_pgoff( \ 90 umem, \ 91 __mlx5_log_page_size_to_bitmap( \ 92 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 93 __mlx5_bit_sz(typ, page_offset_fld), \ 94 GENMASK(31, order_base_2(scale)), scale, \ 95 page_offset_quantized) 96 97 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \ 98 pgsz_shift, page_offset_fld, \ 99 scale, page_offset_quantized) \ 100 __mlx5_umem_find_best_quantized_pgoff( \ 101 umem, \ 102 __mlx5_log_page_size_to_bitmap( \ 103 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \ 104 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \ 105 page_offset_quantized) 106 107 static inline unsigned long mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf * umem_dmabuf)108 mlx5_umem_dmabuf_find_best_pgsz(struct ib_umem_dmabuf *umem_dmabuf) 109 { 110 /* 111 * mkeys used for dmabuf are fixed at PAGE_SIZE because we must be able 112 * to hold any sgl after a move operation. Ideally the mkc page size 113 * could be changed at runtime to be optimal, but right now the driver 114 * cannot do that. 115 */ 116 return ib_umem_find_best_pgsz(&umem_dmabuf->umem, PAGE_SIZE, 117 umem_dmabuf->umem.iova); 118 } 119 120 enum { 121 MLX5_IB_MMAP_OFFSET_START = 9, 122 MLX5_IB_MMAP_OFFSET_END = 255, 123 }; 124 125 enum { 126 MLX5_IB_MMAP_CMD_SHIFT = 8, 127 MLX5_IB_MMAP_CMD_MASK = 0xff, 128 }; 129 130 enum { 131 MLX5_RES_SCAT_DATA32_CQE = 0x1, 132 MLX5_RES_SCAT_DATA64_CQE = 0x2, 133 MLX5_REQ_SCAT_DATA32_CQE = 0x11, 134 MLX5_REQ_SCAT_DATA64_CQE = 0x22, 135 }; 136 137 enum mlx5_ib_mad_ifc_flags { 138 MLX5_MAD_IFC_IGNORE_MKEY = 1, 139 MLX5_MAD_IFC_IGNORE_BKEY = 2, 140 MLX5_MAD_IFC_NET_VIEW = 4, 141 }; 142 143 enum { 144 MLX5_CROSS_CHANNEL_BFREG = 0, 145 }; 146 147 enum { 148 MLX5_CQE_VERSION_V0, 149 MLX5_CQE_VERSION_V1, 150 }; 151 152 enum { 153 MLX5_TM_MAX_RNDV_MSG_SIZE = 64, 154 MLX5_TM_MAX_SGE = 1, 155 }; 156 157 enum { 158 MLX5_IB_INVALID_UAR_INDEX = BIT(31), 159 MLX5_IB_INVALID_BFREG = BIT(31), 160 }; 161 162 enum { 163 MLX5_MAX_MEMIC_PAGES = 0x100, 164 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f, 165 }; 166 167 enum { 168 MLX5_MEMIC_BASE_ALIGN = 6, 169 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN, 170 }; 171 172 enum mlx5_ib_mmap_type { 173 MLX5_IB_MMAP_TYPE_MEMIC = 1, 174 MLX5_IB_MMAP_TYPE_VAR = 2, 175 MLX5_IB_MMAP_TYPE_UAR_WC = 3, 176 MLX5_IB_MMAP_TYPE_UAR_NC = 4, 177 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5, 178 }; 179 180 struct mlx5_bfreg_info { 181 u32 *sys_pages; 182 int num_low_latency_bfregs; 183 unsigned int *count; 184 185 /* 186 * protect bfreg allocation data structs 187 */ 188 struct mutex lock; 189 u32 ver; 190 u8 lib_uar_4k : 1; 191 u8 lib_uar_dyn : 1; 192 u32 num_sys_pages; 193 u32 num_static_sys_pages; 194 u32 total_num_bfregs; 195 u32 num_dyn_bfregs; 196 }; 197 198 struct mlx5_ib_ucontext { 199 struct ib_ucontext ibucontext; 200 struct list_head db_page_list; 201 202 /* protect doorbell record alloc/free 203 */ 204 struct mutex db_page_mutex; 205 struct mlx5_bfreg_info bfregi; 206 u8 cqe_version; 207 /* Transport Domain number */ 208 u32 tdn; 209 210 u64 lib_caps; 211 u16 devx_uid; 212 /* For RoCE LAG TX affinity */ 213 atomic_t tx_port_affinity; 214 }; 215 to_mucontext(struct ib_ucontext * ibucontext)216 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext) 217 { 218 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext); 219 } 220 221 struct mlx5_ib_pd { 222 struct ib_pd ibpd; 223 u32 pdn; 224 u16 uid; 225 }; 226 227 enum { 228 MLX5_IB_FLOW_ACTION_MODIFY_HEADER, 229 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT, 230 MLX5_IB_FLOW_ACTION_DECAP, 231 }; 232 233 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1) 234 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1) 235 #if (MLX5_IB_FLOW_LAST_PRIO <= 0) 236 #error "Invalid number of bypass priorities" 237 #endif 238 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1) 239 240 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1) 241 #define MLX5_IB_NUM_SNIFFER_FTS 2 242 #define MLX5_IB_NUM_EGRESS_FTS 1 243 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS 244 245 struct mlx5_ib_anchor { 246 struct mlx5_flow_table *ft; 247 struct mlx5_flow_group *fg_goto_table; 248 struct mlx5_flow_group *fg_drop; 249 struct mlx5_flow_handle *rule_goto_table; 250 struct mlx5_flow_handle *rule_drop; 251 unsigned int rule_goto_table_ref; 252 }; 253 254 struct mlx5_ib_flow_prio { 255 struct mlx5_flow_table *flow_table; 256 struct mlx5_ib_anchor anchor; 257 unsigned int refcount; 258 }; 259 260 struct mlx5_ib_flow_handler { 261 struct list_head list; 262 struct ib_flow ibflow; 263 struct mlx5_ib_flow_prio *prio; 264 struct mlx5_flow_handle *rule; 265 struct ib_counters *ibcounters; 266 struct mlx5_ib_dev *dev; 267 struct mlx5_ib_flow_matcher *flow_matcher; 268 }; 269 270 struct mlx5_ib_flow_matcher { 271 struct mlx5_ib_match_params matcher_mask; 272 int mask_len; 273 enum mlx5_ib_flow_type flow_type; 274 enum mlx5_flow_namespace_type ns_type; 275 u16 priority; 276 struct mlx5_core_dev *mdev; 277 atomic_t usecnt; 278 u8 match_criteria_enable; 279 }; 280 281 struct mlx5_ib_steering_anchor { 282 struct mlx5_ib_flow_prio *ft_prio; 283 struct mlx5_ib_dev *dev; 284 atomic_t usecnt; 285 }; 286 287 struct mlx5_ib_pp { 288 u16 index; 289 struct mlx5_core_dev *mdev; 290 }; 291 292 enum mlx5_ib_optional_counter_type { 293 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS, 294 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS, 295 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS, 296 297 MLX5_IB_OPCOUNTER_MAX, 298 }; 299 300 struct mlx5_ib_flow_db { 301 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT]; 302 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT]; 303 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS]; 304 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS]; 305 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS]; 306 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT]; 307 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT]; 308 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX]; 309 struct mlx5_flow_table *lag_demux_ft; 310 /* Protect flow steering bypass flow tables 311 * when add/del flow rules. 312 * only single add/removal of flow steering rule could be done 313 * simultaneously. 314 */ 315 struct mutex lock; 316 }; 317 318 /* Use macros here so that don't have to duplicate 319 * enum ib_qp_type for low-level driver 320 */ 321 322 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1 323 /* 324 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI 325 * creates the actual hardware QP. 326 */ 327 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2 328 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3 329 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4 330 #define MLX5_IB_WR_UMR IB_WR_RESERVED1 331 332 #define MLX5_IB_UPD_XLT_ZAP BIT(0) 333 #define MLX5_IB_UPD_XLT_ENABLE BIT(1) 334 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2) 335 #define MLX5_IB_UPD_XLT_ADDR BIT(3) 336 #define MLX5_IB_UPD_XLT_PD BIT(4) 337 #define MLX5_IB_UPD_XLT_ACCESS BIT(5) 338 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6) 339 340 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags. 341 * 342 * These flags are intended for internal use by the mlx5_ib driver, and they 343 * rely on the range reserved for that use in the ib_qp_create_flags enum. 344 */ 345 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START 346 347 struct wr_list { 348 u16 opcode; 349 u16 next; 350 }; 351 352 enum mlx5_ib_rq_flags { 353 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0, 354 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1, 355 }; 356 357 struct mlx5_ib_wq { 358 struct mlx5_frag_buf_ctrl fbc; 359 u64 *wrid; 360 u32 *wr_data; 361 struct wr_list *w_list; 362 unsigned *wqe_head; 363 u16 unsig_count; 364 365 /* serialize post to the work queue 366 */ 367 spinlock_t lock; 368 int wqe_cnt; 369 int max_post; 370 int max_gs; 371 int offset; 372 int wqe_shift; 373 unsigned head; 374 unsigned tail; 375 u16 cur_post; 376 u16 last_poll; 377 void *cur_edge; 378 }; 379 380 enum mlx5_ib_wq_flags { 381 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1, 382 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2, 383 }; 384 385 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9 386 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16 387 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6 388 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13 389 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3 390 391 struct mlx5_ib_rwq { 392 struct ib_wq ibwq; 393 struct mlx5_core_qp core_qp; 394 u32 rq_num_pas; 395 u32 log_rq_stride; 396 u32 log_rq_size; 397 u32 rq_page_offset; 398 u32 log_page_size; 399 u32 log_num_strides; 400 u32 two_byte_shift_en; 401 u32 single_stride_log_num_of_bytes; 402 struct ib_umem *umem; 403 size_t buf_size; 404 unsigned int page_shift; 405 struct mlx5_db db; 406 u32 user_index; 407 u32 wqe_count; 408 u32 wqe_shift; 409 int wq_sig; 410 u32 create_flags; /* Use enum mlx5_ib_wq_flags */ 411 }; 412 413 struct mlx5_ib_rwq_ind_table { 414 struct ib_rwq_ind_table ib_rwq_ind_tbl; 415 u32 rqtn; 416 u16 uid; 417 }; 418 419 struct mlx5_ib_ubuffer { 420 struct ib_umem *umem; 421 int buf_size; 422 u64 buf_addr; 423 }; 424 425 struct mlx5_ib_qp_base { 426 struct mlx5_ib_qp *container_mibqp; 427 struct mlx5_core_qp mqp; 428 struct mlx5_ib_ubuffer ubuffer; 429 }; 430 431 struct mlx5_ib_qp_trans { 432 struct mlx5_ib_qp_base base; 433 u16 xrcdn; 434 u32 alt_port; 435 u8 atomic_rd_en; 436 u8 resp_depth; 437 }; 438 439 struct mlx5_ib_rss_qp { 440 u32 tirn; 441 }; 442 443 struct mlx5_ib_rq { 444 struct mlx5_ib_qp_base base; 445 struct mlx5_ib_wq *rq; 446 struct mlx5_ib_ubuffer ubuffer; 447 struct mlx5_db *doorbell; 448 u32 tirn; 449 u8 state; 450 u32 flags; 451 }; 452 453 struct mlx5_ib_sq { 454 struct mlx5_ib_qp_base base; 455 struct mlx5_ib_wq *sq; 456 struct mlx5_ib_ubuffer ubuffer; 457 struct mlx5_db *doorbell; 458 struct mlx5_flow_handle *flow_rule; 459 u32 tisn; 460 u8 state; 461 }; 462 463 struct mlx5_ib_raw_packet_qp { 464 struct mlx5_ib_sq sq; 465 struct mlx5_ib_rq rq; 466 }; 467 468 struct mlx5_bf { 469 int buf_size; 470 unsigned long offset; 471 struct mlx5_sq_bfreg *bfreg; 472 }; 473 474 struct mlx5_ib_dct { 475 struct mlx5_core_dct mdct; 476 u32 *in; 477 }; 478 479 struct mlx5_ib_gsi_qp { 480 struct ib_qp *rx_qp; 481 u32 port_num; 482 struct ib_qp_cap cap; 483 struct ib_cq *cq; 484 struct mlx5_ib_gsi_wr *outstanding_wrs; 485 u32 outstanding_pi, outstanding_ci; 486 int num_qps; 487 /* Protects access to the tx_qps. Post send operations synchronize 488 * with tx_qp creation in setup_qp(). Also protects the 489 * outstanding_wrs array and indices. 490 */ 491 spinlock_t lock; 492 struct ib_qp **tx_qps; 493 }; 494 495 struct mlx5_ib_qp { 496 struct ib_qp ibqp; 497 union { 498 struct mlx5_ib_qp_trans trans_qp; 499 struct mlx5_ib_raw_packet_qp raw_packet_qp; 500 struct mlx5_ib_rss_qp rss_qp; 501 struct mlx5_ib_dct dct; 502 struct mlx5_ib_gsi_qp gsi; 503 }; 504 struct mlx5_frag_buf buf; 505 506 struct mlx5_db db; 507 struct mlx5_ib_wq rq; 508 509 u8 sq_signal_bits; 510 u8 next_fence; 511 struct mlx5_ib_wq sq; 512 513 /* serialize qp state modifications 514 */ 515 struct mutex mutex; 516 /* cached variant of create_flags from struct ib_qp_init_attr */ 517 u32 flags; 518 u32 port; 519 u8 state; 520 int max_inline_data; 521 struct mlx5_bf bf; 522 u8 has_rq:1; 523 u8 is_rss:1; 524 525 /* only for user space QPs. For kernel 526 * we have it from the bf object 527 */ 528 int bfregn; 529 530 struct list_head qps_list; 531 struct list_head cq_recv_list; 532 struct list_head cq_send_list; 533 struct mlx5_rate_limit rl; 534 u32 underlay_qpn; 535 u32 flags_en; 536 /* 537 * IB/core doesn't store low-level QP types, so 538 * store both MLX and IBTA types in the field below. 539 */ 540 enum ib_qp_type type; 541 /* A flag to indicate if there's a new counter is configured 542 * but not take effective 543 */ 544 u32 counter_pending; 545 u16 gsi_lag_port; 546 }; 547 548 struct mlx5_ib_cq_buf { 549 struct mlx5_frag_buf_ctrl fbc; 550 struct mlx5_frag_buf frag_buf; 551 struct ib_umem *umem; 552 int cqe_size; 553 int nent; 554 }; 555 556 enum mlx5_ib_cq_pr_flags { 557 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0, 558 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1, 559 }; 560 561 struct mlx5_ib_cq { 562 struct ib_cq ibcq; 563 struct mlx5_core_cq mcq; 564 struct mlx5_ib_cq_buf buf; 565 struct mlx5_db db; 566 567 /* serialize access to the CQ 568 */ 569 spinlock_t lock; 570 571 /* protect resize cq 572 */ 573 struct mutex resize_mutex; 574 struct mlx5_ib_cq_buf *resize_buf; 575 struct ib_umem *resize_umem; 576 int cqe_size; 577 struct list_head list_send_qp; 578 struct list_head list_recv_qp; 579 u32 create_flags; 580 struct list_head wc_list; 581 enum ib_cq_notify_flags notify_flags; 582 struct work_struct notify_work; 583 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */ 584 }; 585 586 struct mlx5_ib_wc { 587 struct ib_wc wc; 588 struct list_head list; 589 }; 590 591 struct mlx5_ib_srq { 592 struct ib_srq ibsrq; 593 struct mlx5_core_srq msrq; 594 struct mlx5_frag_buf buf; 595 struct mlx5_db db; 596 struct mlx5_frag_buf_ctrl fbc; 597 u64 *wrid; 598 /* protect SRQ hanlding 599 */ 600 spinlock_t lock; 601 int head; 602 int tail; 603 u16 wqe_ctr; 604 struct ib_umem *umem; 605 /* serialize arming a SRQ 606 */ 607 struct mutex mutex; 608 int wq_sig; 609 }; 610 611 struct mlx5_ib_xrcd { 612 struct ib_xrcd ibxrcd; 613 u32 xrcdn; 614 }; 615 616 enum mlx5_ib_mtt_access_flags { 617 MLX5_IB_MTT_READ = (1 << 0), 618 MLX5_IB_MTT_WRITE = (1 << 1), 619 }; 620 621 struct mlx5_user_mmap_entry { 622 struct rdma_user_mmap_entry rdma_entry; 623 u8 mmap_flag; 624 u64 address; 625 u32 page_idx; 626 }; 627 628 enum mlx5_mkey_type { 629 MLX5_MKEY_MR = 1, 630 MLX5_MKEY_MW, 631 MLX5_MKEY_INDIRECT_DEVX, 632 MLX5_MKEY_NULL, 633 MLX5_MKEY_IMPLICIT_CHILD, 634 }; 635 636 struct mlx5r_cache_rb_key { 637 u8 ats:1; 638 unsigned int access_mode; 639 unsigned int access_flags; 640 unsigned int ndescs; 641 }; 642 643 struct mlx5_ib_mkey { 644 u32 key; 645 enum mlx5_mkey_type type; 646 unsigned int ndescs; 647 struct wait_queue_head wait; 648 refcount_t usecount; 649 /* Cacheable user Mkey must hold either a rb_key or a cache_ent. */ 650 struct mlx5r_cache_rb_key rb_key; 651 struct mlx5_cache_ent *cache_ent; 652 u8 cacheable : 1; 653 }; 654 655 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE) 656 657 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 658 IB_ACCESS_REMOTE_WRITE |\ 659 IB_ACCESS_REMOTE_READ |\ 660 IB_ACCESS_REMOTE_ATOMIC |\ 661 IB_ZERO_BASED) 662 663 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\ 664 IB_ACCESS_REMOTE_WRITE |\ 665 IB_ACCESS_REMOTE_READ |\ 666 IB_ZERO_BASED) 667 668 #define mlx5_update_odp_stats(mr, counter_name, value) \ 669 atomic64_add(value, &((mr)->odp_stats.counter_name)) 670 671 struct mlx5_ib_mr { 672 struct ib_mr ibmr; 673 struct mlx5_ib_mkey mmkey; 674 675 struct ib_umem *umem; 676 /* The mr is data direct related */ 677 u8 data_direct :1; 678 679 union { 680 /* Used only by kernel MRs (umem == NULL) */ 681 struct { 682 void *descs; 683 void *descs_alloc; 684 dma_addr_t desc_map; 685 int max_descs; 686 int desc_size; 687 int access_mode; 688 689 /* For Kernel IB_MR_TYPE_INTEGRITY */ 690 struct mlx5_core_sig_ctx *sig; 691 struct mlx5_ib_mr *pi_mr; 692 struct mlx5_ib_mr *klm_mr; 693 struct mlx5_ib_mr *mtt_mr; 694 u64 data_iova; 695 u64 pi_iova; 696 int meta_ndescs; 697 int meta_length; 698 int data_length; 699 }; 700 701 /* Used only by User MRs (umem != NULL) */ 702 struct { 703 unsigned int page_shift; 704 /* Current access_flags */ 705 int access_flags; 706 707 /* For User ODP */ 708 struct mlx5_ib_mr *parent; 709 struct xarray implicit_children; 710 union { 711 struct work_struct work; 712 } odp_destroy; 713 struct ib_odp_counters odp_stats; 714 bool is_odp_implicit; 715 /* The affilated data direct crossed mr */ 716 struct mlx5_ib_mr *dd_crossed_mr; 717 struct list_head dd_node; 718 u8 revoked :1; 719 struct mlx5_ib_mkey null_mmkey; 720 }; 721 }; 722 }; 723 is_odp_mr(struct mlx5_ib_mr * mr)724 static inline bool is_odp_mr(struct mlx5_ib_mr *mr) 725 { 726 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 727 mr->umem->is_odp; 728 } 729 is_dmabuf_mr(struct mlx5_ib_mr * mr)730 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr) 731 { 732 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem && 733 mr->umem->is_dmabuf; 734 } 735 736 struct mlx5_ib_mw { 737 struct ib_mw ibmw; 738 struct mlx5_ib_mkey mmkey; 739 }; 740 741 struct mlx5_ib_umr_context { 742 struct ib_cqe cqe; 743 enum ib_wc_status status; 744 struct completion done; 745 }; 746 747 enum { 748 MLX5_UMR_STATE_UNINIT, 749 MLX5_UMR_STATE_ACTIVE, 750 MLX5_UMR_STATE_RECOVER, 751 MLX5_UMR_STATE_ERR, 752 }; 753 754 struct umr_common { 755 struct ib_pd *pd; 756 struct ib_cq *cq; 757 struct ib_qp *qp; 758 /* Protects from UMR QP overflow 759 */ 760 struct semaphore sem; 761 /* Protects from using UMR while the UMR is not active 762 */ 763 struct mutex lock; 764 unsigned int state; 765 /* Protects from repeat UMR QP creation */ 766 struct mutex init_lock; 767 }; 768 769 #define NUM_MKEYS_PER_PAGE \ 770 ((PAGE_SIZE - sizeof(struct list_head)) / sizeof(u32)) 771 772 struct mlx5_mkeys_page { 773 u32 mkeys[NUM_MKEYS_PER_PAGE]; 774 struct list_head list; 775 }; 776 static_assert(sizeof(struct mlx5_mkeys_page) == PAGE_SIZE); 777 778 struct mlx5_mkeys_queue { 779 struct list_head pages_list; 780 u32 num_pages; 781 unsigned long ci; 782 spinlock_t lock; /* sync list ops */ 783 }; 784 785 struct mlx5_cache_ent { 786 struct mlx5_mkeys_queue mkeys_queue; 787 u32 pending; 788 789 char name[4]; 790 791 struct rb_node node; 792 struct mlx5r_cache_rb_key rb_key; 793 794 u8 is_tmp:1; 795 u8 disabled:1; 796 u8 fill_to_high_water:1; 797 u8 tmp_cleanup_scheduled:1; 798 799 /* 800 * - limit is the low water mark for stored mkeys, 2* limit is the 801 * upper water mark. 802 */ 803 u32 in_use; 804 u32 limit; 805 806 /* Statistics */ 807 u32 miss; 808 809 struct mlx5_ib_dev *dev; 810 struct delayed_work dwork; 811 }; 812 813 struct mlx5r_async_create_mkey { 814 union { 815 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)]; 816 u32 out[MLX5_ST_SZ_DW(create_mkey_out)]; 817 }; 818 struct mlx5_async_work cb_work; 819 struct mlx5_cache_ent *ent; 820 u32 mkey; 821 }; 822 823 struct mlx5_mkey_cache { 824 struct workqueue_struct *wq; 825 struct rb_root rb_root; 826 struct mutex rb_lock; 827 struct dentry *fs_root; 828 unsigned long last_add; 829 }; 830 831 struct mlx5_ib_port_resources { 832 struct mlx5_ib_gsi_qp *gsi; 833 struct work_struct pkey_change_work; 834 }; 835 836 struct mlx5_data_direct_resources { 837 u32 pdn; 838 u32 mkey; 839 }; 840 841 struct mlx5_ib_resources { 842 struct ib_cq *c0; 843 struct mutex cq_lock; 844 u32 xrcdn0; 845 u32 xrcdn1; 846 struct ib_pd *p0; 847 struct ib_srq *s0; 848 struct ib_srq *s1; 849 struct mutex srq_lock; 850 struct mlx5_ib_port_resources ports[2]; 851 }; 852 853 #define MAX_OPFC_RULES 2 854 855 struct mlx5_ib_op_fc { 856 struct mlx5_fc *fc; 857 struct mlx5_flow_handle *rule[MAX_OPFC_RULES]; 858 }; 859 860 struct mlx5_ib_counters { 861 struct rdma_stat_desc *descs; 862 size_t *offsets; 863 u32 num_q_counters; 864 u32 num_cong_counters; 865 u32 num_ext_ppcnt_counters; 866 u32 num_op_counters; 867 u16 set_id; 868 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX]; 869 }; 870 871 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num, 872 struct mlx5_ib_op_fc *opfc, 873 enum mlx5_ib_optional_counter_type type); 874 875 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev, 876 struct mlx5_ib_op_fc *opfc, 877 enum mlx5_ib_optional_counter_type type); 878 879 struct mlx5_ib_multiport_info; 880 881 struct mlx5_ib_multiport { 882 struct mlx5_ib_multiport_info *mpi; 883 /* To be held when accessing the multiport info */ 884 spinlock_t mpi_lock; 885 }; 886 887 struct mlx5_roce { 888 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL 889 * netdev pointer 890 */ 891 struct notifier_block nb; 892 struct netdev_net_notifier nn; 893 struct notifier_block mdev_nb; 894 struct net_device *tracking_netdev; 895 atomic_t tx_port_affinity; 896 enum ib_port_state last_port_state; 897 struct mlx5_ib_dev *dev; 898 u32 native_port_num; 899 }; 900 901 struct mlx5_ib_port { 902 struct mlx5_ib_counters cnts; 903 struct mlx5_ib_multiport mp; 904 struct mlx5_ib_dbg_cc_params *dbg_cc_params; 905 struct mlx5_roce roce; 906 struct mlx5_eswitch_rep *rep; 907 #ifdef CONFIG_MLX5_MACSEC 908 struct mlx5_reserved_gids *reserved_gids; 909 #endif 910 }; 911 912 struct mlx5_ib_dbg_param { 913 int offset; 914 struct mlx5_ib_dev *dev; 915 struct dentry *dentry; 916 u32 port_num; 917 }; 918 919 enum mlx5_ib_dbg_cc_types { 920 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE, 921 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI, 922 MLX5_IB_DBG_CC_RP_TIME_RESET, 923 MLX5_IB_DBG_CC_RP_BYTE_RESET, 924 MLX5_IB_DBG_CC_RP_THRESHOLD, 925 MLX5_IB_DBG_CC_RP_AI_RATE, 926 MLX5_IB_DBG_CC_RP_MAX_RATE, 927 MLX5_IB_DBG_CC_RP_HAI_RATE, 928 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC, 929 MLX5_IB_DBG_CC_RP_MIN_RATE, 930 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP, 931 MLX5_IB_DBG_CC_RP_DCE_TCP_G, 932 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT, 933 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD, 934 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE, 935 MLX5_IB_DBG_CC_RP_GD, 936 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS, 937 MLX5_IB_DBG_CC_NP_CNP_DSCP, 938 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE, 939 MLX5_IB_DBG_CC_NP_CNP_PRIO, 940 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP_VALID, 941 MLX5_IB_DBG_CC_GENERAL_RTT_RESP_DSCP, 942 MLX5_IB_DBG_CC_MAX, 943 }; 944 945 struct mlx5_ib_dbg_cc_params { 946 struct dentry *root; 947 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX]; 948 }; 949 950 enum { 951 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100, 952 }; 953 954 struct mlx5_ib_delay_drop { 955 struct mlx5_ib_dev *dev; 956 struct work_struct delay_drop_work; 957 /* serialize setting of delay drop */ 958 struct mutex lock; 959 u32 timeout; 960 bool activate; 961 atomic_t events_cnt; 962 atomic_t rqs_cnt; 963 struct dentry *dir_debugfs; 964 }; 965 966 enum mlx5_ib_stages { 967 MLX5_IB_STAGE_INIT, 968 MLX5_IB_STAGE_FS, 969 MLX5_IB_STAGE_CAPS, 970 MLX5_IB_STAGE_NON_DEFAULT_CB, 971 MLX5_IB_STAGE_ROCE, 972 MLX5_IB_STAGE_QP, 973 MLX5_IB_STAGE_SRQ, 974 MLX5_IB_STAGE_DEVICE_RESOURCES, 975 MLX5_IB_STAGE_DEVICE_NOTIFIER, 976 MLX5_IB_STAGE_ODP, 977 MLX5_IB_STAGE_COUNTERS, 978 MLX5_IB_STAGE_CONG_DEBUGFS, 979 MLX5_IB_STAGE_UAR, 980 MLX5_IB_STAGE_BFREG, 981 MLX5_IB_STAGE_PRE_IB_REG_UMR, 982 MLX5_IB_STAGE_WHITELIST_UID, 983 MLX5_IB_STAGE_IB_REG, 984 MLX5_IB_STAGE_POST_IB_REG_UMR, 985 MLX5_IB_STAGE_DELAY_DROP, 986 MLX5_IB_STAGE_RESTRACK, 987 MLX5_IB_STAGE_MAX, 988 }; 989 990 struct mlx5_ib_stage { 991 int (*init)(struct mlx5_ib_dev *dev); 992 void (*cleanup)(struct mlx5_ib_dev *dev); 993 }; 994 995 #define STAGE_CREATE(_stage, _init, _cleanup) \ 996 .stage[_stage] = {.init = _init, .cleanup = _cleanup} 997 998 struct mlx5_ib_profile { 999 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX]; 1000 }; 1001 1002 struct mlx5_ib_multiport_info { 1003 struct list_head list; 1004 struct mlx5_ib_dev *ibdev; 1005 struct mlx5_core_dev *mdev; 1006 struct notifier_block mdev_events; 1007 struct completion unref_comp; 1008 u64 sys_image_guid; 1009 u32 mdev_refcnt; 1010 bool is_master; 1011 bool unaffiliate; 1012 }; 1013 1014 struct mlx5_ib_flow_action { 1015 struct ib_flow_action ib_action; 1016 union { 1017 struct { 1018 u64 ib_flags; 1019 struct mlx5_accel_esp_xfrm *ctx; 1020 } esp_aes_gcm; 1021 struct { 1022 struct mlx5_ib_dev *dev; 1023 u32 sub_type; 1024 union { 1025 struct mlx5_modify_hdr *modify_hdr; 1026 struct mlx5_pkt_reformat *pkt_reformat; 1027 }; 1028 } flow_action_raw; 1029 }; 1030 }; 1031 1032 struct mlx5_dm { 1033 struct mlx5_core_dev *dev; 1034 /* This lock is used to protect the access to the shared 1035 * allocation map when concurrent requests by different 1036 * processes are handled. 1037 */ 1038 spinlock_t lock; 1039 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES); 1040 }; 1041 1042 struct mlx5_read_counters_attr { 1043 struct mlx5_fc *hw_cntrs_hndl; 1044 u64 *out; 1045 u32 flags; 1046 }; 1047 1048 enum mlx5_ib_counters_type { 1049 MLX5_IB_COUNTERS_FLOW, 1050 }; 1051 1052 struct mlx5_ib_mcounters { 1053 struct ib_counters ibcntrs; 1054 enum mlx5_ib_counters_type type; 1055 /* number of counters supported for this counters type */ 1056 u32 counters_num; 1057 struct mlx5_fc *hw_cntrs_hndl; 1058 /* read function for this counters type */ 1059 int (*read_counters)(struct ib_device *ibdev, 1060 struct mlx5_read_counters_attr *read_attr); 1061 /* max index set as part of create_flow */ 1062 u32 cntrs_max_index; 1063 /* number of counters data entries (<description,index> pair) */ 1064 u32 ncounters; 1065 /* counters data array for descriptions and indexes */ 1066 struct mlx5_ib_flow_counters_desc *counters_data; 1067 /* protects access to mcounters internal data */ 1068 struct mutex mcntrs_mutex; 1069 }; 1070 1071 static inline struct mlx5_ib_mcounters * to_mcounters(struct ib_counters * ibcntrs)1072 to_mcounters(struct ib_counters *ibcntrs) 1073 { 1074 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs); 1075 } 1076 1077 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction, 1078 bool is_egress, 1079 struct mlx5_flow_act *action); 1080 struct mlx5_ib_lb_state { 1081 /* protect the user_td */ 1082 struct mutex mutex; 1083 u32 user_td; 1084 int qps; 1085 bool enabled; 1086 }; 1087 1088 struct mlx5_ib_pf_eq { 1089 struct notifier_block irq_nb; 1090 struct mlx5_ib_dev *dev; 1091 struct mlx5_eq *core; 1092 struct work_struct work; 1093 spinlock_t lock; /* Pagefaults spinlock */ 1094 struct workqueue_struct *wq; 1095 mempool_t *pool; 1096 }; 1097 1098 struct mlx5_devx_event_table { 1099 struct mlx5_nb devx_nb; 1100 /* serialize updating the event_xa */ 1101 struct mutex event_xa_lock; 1102 struct xarray event_xa; 1103 }; 1104 1105 struct mlx5_var_table { 1106 /* serialize updating the bitmap */ 1107 struct mutex bitmap_lock; 1108 unsigned long *bitmap; 1109 u64 hw_start_addr; 1110 u32 stride_size; 1111 u64 num_var_hw_entries; 1112 }; 1113 1114 struct mlx5_port_caps { 1115 bool has_smi; 1116 u8 ext_port_cap; 1117 }; 1118 1119 1120 struct mlx5_special_mkeys { 1121 u32 dump_fill_mkey; 1122 __be32 null_mkey; 1123 __be32 terminate_scatter_list_mkey; 1124 }; 1125 1126 struct mlx5_macsec { 1127 struct mutex lock; /* Protects mlx5_macsec internal contexts */ 1128 struct list_head macsec_devices_list; 1129 struct notifier_block blocking_events_nb; 1130 }; 1131 1132 struct mlx5_ib_dev { 1133 struct ib_device ib_dev; 1134 struct mlx5_core_dev *mdev; 1135 struct mlx5_data_direct_dev *data_direct_dev; 1136 /* protect accessing data_direct_dev */ 1137 struct mutex data_direct_lock; 1138 struct notifier_block mdev_events; 1139 struct notifier_block lag_events; 1140 int num_ports; 1141 /* serialize update of capability mask 1142 */ 1143 struct mutex cap_mask_mutex; 1144 u8 ib_active:1; 1145 u8 is_rep:1; 1146 u8 lag_active:1; 1147 u8 fill_delay; 1148 struct umr_common umrc; 1149 /* sync used page count stats 1150 */ 1151 struct mlx5_ib_resources devr; 1152 1153 atomic_t mkey_var; 1154 struct mlx5_mkey_cache cache; 1155 struct timer_list delay_timer; 1156 /* Prevents soft lock on massive reg MRs */ 1157 struct mutex slow_path_mutex; 1158 struct ib_odp_caps odp_caps; 1159 u64 odp_max_size; 1160 struct mutex odp_eq_mutex; 1161 struct mlx5_ib_pf_eq odp_pf_eq; 1162 1163 struct xarray odp_mkeys; 1164 1165 struct mlx5_ib_flow_db *flow_db; 1166 /* protect resources needed as part of reset flow */ 1167 spinlock_t reset_flow_resource_lock; 1168 struct list_head qp_list; 1169 struct list_head data_direct_mr_list; 1170 /* Array with num_ports elements */ 1171 struct mlx5_ib_port *port; 1172 struct mlx5_sq_bfreg bfreg; 1173 struct mlx5_sq_bfreg fp_bfreg; 1174 struct mlx5_ib_delay_drop delay_drop; 1175 const struct mlx5_ib_profile *profile; 1176 1177 struct mlx5_ib_lb_state lb; 1178 u8 umr_fence; 1179 struct list_head ib_dev_list; 1180 u64 sys_image_guid; 1181 struct mlx5_dm dm; 1182 u16 devx_whitelist_uid; 1183 struct mlx5_srq_table srq_table; 1184 struct mlx5_qp_table qp_table; 1185 struct mlx5_async_ctx async_ctx; 1186 struct mlx5_devx_event_table devx_event_table; 1187 struct mlx5_var_table var_table; 1188 1189 struct xarray sig_mrs; 1190 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS]; 1191 u16 pkey_table_len; 1192 u8 lag_ports; 1193 struct mlx5_special_mkeys mkeys; 1194 struct mlx5_data_direct_resources ddr; 1195 1196 #ifdef CONFIG_MLX5_MACSEC 1197 struct mlx5_macsec macsec; 1198 #endif 1199 1200 u8 num_plane; 1201 struct mlx5_ib_dev *smi_dev; 1202 const char *sub_dev_name; 1203 }; 1204 to_mibcq(struct mlx5_core_cq * mcq)1205 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq) 1206 { 1207 return container_of(mcq, struct mlx5_ib_cq, mcq); 1208 } 1209 to_mxrcd(struct ib_xrcd * ibxrcd)1210 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd) 1211 { 1212 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd); 1213 } 1214 to_mdev(struct ib_device * ibdev)1215 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev) 1216 { 1217 return container_of(ibdev, struct mlx5_ib_dev, ib_dev); 1218 } 1219 mr_to_mdev(struct mlx5_ib_mr * mr)1220 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr) 1221 { 1222 return to_mdev(mr->ibmr.device); 1223 } 1224 mlx5_udata_to_mdev(struct ib_udata * udata)1225 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata) 1226 { 1227 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context( 1228 udata, struct mlx5_ib_ucontext, ibucontext); 1229 1230 return to_mdev(context->ibucontext.device); 1231 } 1232 to_mcq(struct ib_cq * ibcq)1233 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq) 1234 { 1235 return container_of(ibcq, struct mlx5_ib_cq, ibcq); 1236 } 1237 to_mibqp(struct mlx5_core_qp * mqp)1238 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp) 1239 { 1240 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp; 1241 } 1242 to_mibrwq(struct mlx5_core_qp * core_qp)1243 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp) 1244 { 1245 return container_of(core_qp, struct mlx5_ib_rwq, core_qp); 1246 } 1247 to_mpd(struct ib_pd * ibpd)1248 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd) 1249 { 1250 return container_of(ibpd, struct mlx5_ib_pd, ibpd); 1251 } 1252 to_msrq(struct ib_srq * ibsrq)1253 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq) 1254 { 1255 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq); 1256 } 1257 to_mqp(struct ib_qp * ibqp)1258 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp) 1259 { 1260 return container_of(ibqp, struct mlx5_ib_qp, ibqp); 1261 } 1262 to_mrwq(struct ib_wq * ibwq)1263 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq) 1264 { 1265 return container_of(ibwq, struct mlx5_ib_rwq, ibwq); 1266 } 1267 to_mrwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)1268 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl) 1269 { 1270 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl); 1271 } 1272 to_mibsrq(struct mlx5_core_srq * msrq)1273 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq) 1274 { 1275 return container_of(msrq, struct mlx5_ib_srq, msrq); 1276 } 1277 to_mmr(struct ib_mr * ibmr)1278 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr) 1279 { 1280 return container_of(ibmr, struct mlx5_ib_mr, ibmr); 1281 } 1282 to_mmw(struct ib_mw * ibmw)1283 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw) 1284 { 1285 return container_of(ibmw, struct mlx5_ib_mw, ibmw); 1286 } 1287 1288 static inline struct mlx5_ib_flow_action * to_mflow_act(struct ib_flow_action * ibact)1289 to_mflow_act(struct ib_flow_action *ibact) 1290 { 1291 return container_of(ibact, struct mlx5_ib_flow_action, ib_action); 1292 } 1293 1294 static inline struct mlx5_user_mmap_entry * to_mmmap(struct rdma_user_mmap_entry * rdma_entry)1295 to_mmmap(struct rdma_user_mmap_entry *rdma_entry) 1296 { 1297 return container_of(rdma_entry, 1298 struct mlx5_user_mmap_entry, rdma_entry); 1299 } 1300 1301 int mlx5_ib_dev_res_cq_init(struct mlx5_ib_dev *dev); 1302 int mlx5_ib_dev_res_srq_init(struct mlx5_ib_dev *dev); 1303 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt, 1304 struct mlx5_db *db); 1305 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db); 1306 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1307 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq); 1308 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index); 1309 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr, 1310 struct ib_udata *udata); 1311 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr); mlx5_ib_destroy_ah(struct ib_ah * ah,u32 flags)1312 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags) 1313 { 1314 return 0; 1315 } 1316 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr, 1317 struct ib_udata *udata); 1318 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, 1319 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata); 1320 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr); 1321 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata); 1322 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr, 1323 const struct ib_recv_wr **bad_wr); 1324 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1325 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp); 1326 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr, 1327 struct ib_udata *udata); 1328 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, 1329 int attr_mask, struct ib_udata *udata); 1330 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask, 1331 struct ib_qp_init_attr *qp_init_attr); 1332 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata); 1333 void mlx5_ib_drain_sq(struct ib_qp *qp); 1334 void mlx5_ib_drain_rq(struct ib_qp *qp); 1335 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1336 size_t buflen, size_t *bc); 1337 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer, 1338 size_t buflen, size_t *bc); 1339 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer, 1340 size_t buflen, size_t *bc); 1341 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr, 1342 struct uverbs_attr_bundle *attrs); 1343 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata); 1344 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); 1345 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); 1346 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period); 1347 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata); 1348 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc); 1349 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, 1350 u64 virt_addr, int access_flags, 1351 struct ib_udata *udata); 1352 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, 1353 u64 length, u64 virt_addr, 1354 int fd, int access_flags, 1355 struct uverbs_attr_bundle *attrs); 1356 int mlx5_ib_advise_mr(struct ib_pd *pd, 1357 enum ib_uverbs_advise_mr_advice advice, 1358 u32 flags, 1359 struct ib_sge *sg_list, 1360 u32 num_sge, 1361 struct uverbs_attr_bundle *attrs); 1362 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata); 1363 int mlx5_ib_dealloc_mw(struct ib_mw *mw); 1364 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd, 1365 int access_flags); 1366 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr); 1367 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, 1368 u64 length, u64 virt_addr, int access_flags, 1369 struct ib_pd *pd, struct ib_udata *udata); 1370 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata); 1371 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, 1372 u32 max_num_sg); 1373 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd, 1374 u32 max_num_sg, 1375 u32 max_num_meta_sg); 1376 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents, 1377 unsigned int *sg_offset); 1378 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg, 1379 int data_sg_nents, unsigned int *data_sg_offset, 1380 struct scatterlist *meta_sg, int meta_sg_nents, 1381 unsigned int *meta_sg_offset); 1382 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num, 1383 const struct ib_wc *in_wc, const struct ib_grh *in_grh, 1384 const struct ib_mad *in, struct ib_mad *out, 1385 size_t *out_mad_size, u16 *out_mad_pkey_index); 1386 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1387 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata); 1388 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port); 1389 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev, 1390 __be64 *sys_image_guid); 1391 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev, 1392 u16 *max_pkeys); 1393 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev, 1394 u32 *vendor_id); 1395 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc); 1396 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid); 1397 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index, 1398 u16 *pkey); 1399 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index, 1400 union ib_gid *gid); 1401 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port, 1402 struct ib_port_attr *props); 1403 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port, 1404 struct ib_port_attr *props); 1405 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas, 1406 u64 access_flags); 1407 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq); 1408 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev); 1409 void mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev); 1410 struct mlx5_cache_ent * 1411 mlx5r_cache_create_ent_locked(struct mlx5_ib_dev *dev, 1412 struct mlx5r_cache_rb_key rb_key, 1413 bool persistent_entry); 1414 1415 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, 1416 int access_flags, int access_mode, 1417 int ndescs); 1418 1419 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask, 1420 struct ib_mr_status *mr_status); 1421 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd, 1422 struct ib_wq_init_attr *init_attr, 1423 struct ib_udata *udata); 1424 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata); 1425 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr, 1426 u32 wq_attr_mask, struct ib_udata *udata); 1427 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table, 1428 struct ib_rwq_ind_table_init_attr *init_attr, 1429 struct ib_udata *udata); 1430 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table); 1431 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm, 1432 struct ib_dm_mr_attr *attr, 1433 struct uverbs_attr_bundle *attrs); 1434 void mlx5_ib_data_direct_bind(struct mlx5_ib_dev *ibdev, 1435 struct mlx5_data_direct_dev *dev); 1436 void mlx5_ib_data_direct_unbind(struct mlx5_ib_dev *ibdev); 1437 void mlx5_ib_revoke_data_direct_mrs(struct mlx5_ib_dev *dev); 1438 1439 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING 1440 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev); 1441 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq); 1442 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev); 1443 int __init mlx5_ib_odp_init(void); 1444 void mlx5_ib_odp_cleanup(void); 1445 int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev); 1446 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1447 struct mlx5_ib_mr *mr, int flags); 1448 1449 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1450 enum ib_uverbs_advise_mr_advice advice, 1451 u32 flags, struct ib_sge *sg_list, u32 num_sge); 1452 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr); 1453 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr); 1454 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ mlx5_ib_odp_init_one(struct mlx5_ib_dev * ibdev)1455 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; } mlx5r_odp_create_eq(struct mlx5_ib_dev * dev,struct mlx5_ib_pf_eq * eq)1456 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, 1457 struct mlx5_ib_pf_eq *eq) 1458 { 1459 return 0; 1460 } mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev * ibdev)1461 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {} mlx5_ib_odp_init(void)1462 static inline int mlx5_ib_odp_init(void) { return 0; } mlx5_ib_odp_cleanup(void)1463 static inline void mlx5_ib_odp_cleanup(void) {} mlx5_odp_init_mkey_cache(struct mlx5_ib_dev * dev)1464 static inline int mlx5_odp_init_mkey_cache(struct mlx5_ib_dev *dev) 1465 { 1466 return 0; 1467 } mlx5_odp_populate_xlt(void * xlt,size_t idx,size_t nentries,struct mlx5_ib_mr * mr,int flags)1468 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries, 1469 struct mlx5_ib_mr *mr, int flags) {} 1470 1471 static inline int mlx5_ib_advise_mr_prefetch(struct ib_pd * pd,enum ib_uverbs_advise_mr_advice advice,u32 flags,struct ib_sge * sg_list,u32 num_sge)1472 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd, 1473 enum ib_uverbs_advise_mr_advice advice, u32 flags, 1474 struct ib_sge *sg_list, u32 num_sge) 1475 { 1476 return -EOPNOTSUPP; 1477 } mlx5_ib_init_odp_mr(struct mlx5_ib_mr * mr)1478 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr) 1479 { 1480 return -EOPNOTSUPP; 1481 } mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr * mr)1482 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr) 1483 { 1484 return -EOPNOTSUPP; 1485 } 1486 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */ 1487 1488 extern const struct mmu_interval_notifier_ops mlx5_mn_ops; 1489 1490 /* Needed for rep profile */ 1491 void __mlx5_ib_remove(struct mlx5_ib_dev *dev, 1492 const struct mlx5_ib_profile *profile, 1493 int stage); 1494 int __mlx5_ib_add(struct mlx5_ib_dev *dev, 1495 const struct mlx5_ib_profile *profile); 1496 1497 int mlx5_ib_get_vf_config(struct ib_device *device, int vf, 1498 u32 port, struct ifla_vf_info *info); 1499 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf, 1500 u32 port, int state); 1501 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf, 1502 u32 port, struct ifla_vf_stats *stats); 1503 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port, 1504 struct ifla_vf_guid *node_guid, 1505 struct ifla_vf_guid *port_guid); 1506 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port, 1507 u64 guid, int type); 1508 1509 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev, 1510 const struct ib_gid_attr *attr); 1511 1512 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1513 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num); 1514 1515 /* GSI QP helper functions */ 1516 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp, 1517 struct ib_qp_init_attr *attr); 1518 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp); 1519 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr, 1520 int attr_mask); 1521 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr, 1522 int qp_attr_mask, 1523 struct ib_qp_init_attr *qp_init_attr); 1524 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr, 1525 const struct ib_send_wr **bad_wr); 1526 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr, 1527 const struct ib_recv_wr **bad_wr); 1528 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi); 1529 1530 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc); 1531 1532 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, 1533 int bfregn); 1534 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi); 1535 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev, 1536 u32 ib_port_num, 1537 u32 *native_port_num); 1538 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev, 1539 u32 port_num); 1540 1541 extern const struct uapi_definition mlx5_ib_devx_defs[]; 1542 extern const struct uapi_definition mlx5_ib_flow_defs[]; 1543 extern const struct uapi_definition mlx5_ib_qos_defs[]; 1544 extern const struct uapi_definition mlx5_ib_std_types_defs[]; 1545 extern const struct uapi_definition mlx5_ib_create_cq_defs[]; 1546 is_qp1(enum ib_qp_type qp_type)1547 static inline int is_qp1(enum ib_qp_type qp_type) 1548 { 1549 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI; 1550 } 1551 check_cq_create_flags(u32 flags)1552 static inline u32 check_cq_create_flags(u32 flags) 1553 { 1554 /* 1555 * It returns non-zero value for unsupported CQ 1556 * create flags, otherwise it returns zero. 1557 */ 1558 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN | 1559 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION)); 1560 } 1561 verify_assign_uidx(u8 cqe_version,u32 cmd_uidx,u32 * user_index)1562 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx, 1563 u32 *user_index) 1564 { 1565 if (cqe_version) { 1566 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) || 1567 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK)) 1568 return -EINVAL; 1569 *user_index = cmd_uidx; 1570 } else { 1571 *user_index = MLX5_IB_DEFAULT_UIDX; 1572 } 1573 1574 return 0; 1575 } 1576 get_qp_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_qp * ucmd,int inlen,u32 * user_index)1577 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext, 1578 struct mlx5_ib_create_qp *ucmd, 1579 int inlen, 1580 u32 *user_index) 1581 { 1582 u8 cqe_version = ucontext->cqe_version; 1583 1584 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1585 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1586 return 0; 1587 1588 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1589 return -EINVAL; 1590 1591 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1592 } 1593 get_srq_user_index(struct mlx5_ib_ucontext * ucontext,struct mlx5_ib_create_srq * ucmd,int inlen,u32 * user_index)1594 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext, 1595 struct mlx5_ib_create_srq *ucmd, 1596 int inlen, 1597 u32 *user_index) 1598 { 1599 u8 cqe_version = ucontext->cqe_version; 1600 1601 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version && 1602 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX)) 1603 return 0; 1604 1605 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version) 1606 return -EINVAL; 1607 1608 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index); 1609 } 1610 get_uars_per_sys_page(struct mlx5_ib_dev * dev,bool lib_support)1611 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support) 1612 { 1613 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ? 1614 MLX5_UARS_IN_PAGE : 1; 1615 } 1616 1617 extern void *xlt_emergency_page; 1618 1619 int bfregn_to_uar_index(struct mlx5_ib_dev *dev, 1620 struct mlx5_bfreg_info *bfregi, u32 bfregn, 1621 bool dyn_bfreg); 1622 mlx5r_store_odp_mkey(struct mlx5_ib_dev * dev,struct mlx5_ib_mkey * mmkey)1623 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev, 1624 struct mlx5_ib_mkey *mmkey) 1625 { 1626 refcount_set(&mmkey->usecount, 1); 1627 1628 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key), 1629 mmkey, GFP_KERNEL)); 1630 } 1631 1632 /* deref an mkey that can participate in ODP flow */ mlx5r_deref_odp_mkey(struct mlx5_ib_mkey * mmkey)1633 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey) 1634 { 1635 if (refcount_dec_and_test(&mmkey->usecount)) 1636 wake_up(&mmkey->wait); 1637 } 1638 1639 /* deref an mkey that can participate in ODP flow and wait for relese */ mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey * mmkey)1640 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey) 1641 { 1642 mlx5r_deref_odp_mkey(mmkey); 1643 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0); 1644 } 1645 mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev * dev)1646 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev) 1647 { 1648 /* 1649 * If the driver is in hash mode and the port_select_flow_table_bypass cap 1650 * is supported, it means that the driver no longer needs to assign the port 1651 * affinity by default. If a user wants to set the port affinity explicitly, 1652 * the user has a dedicated API to do that, so there is no need to assign 1653 * the port affinity by default. 1654 */ 1655 if (dev->lag_active && 1656 mlx5_lag_mode_is_hash(dev->mdev) && 1657 MLX5_CAP_PORT_SELECTION(dev->mdev, port_select_flow_table_bypass)) 1658 return 0; 1659 1660 if (mlx5_lag_is_lacp_owner(dev->mdev) && !dev->lag_active) 1661 return 0; 1662 1663 return dev->lag_active || 1664 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 && 1665 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity)); 1666 } 1667 rt_supported(int ts_cap)1668 static inline bool rt_supported(int ts_cap) 1669 { 1670 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME || 1671 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME; 1672 } 1673 1674 /* 1675 * PCI Peer to Peer is a trainwreck. If no switch is present then things 1676 * sometimes work, depending on the pci_distance_p2p logic for excluding broken 1677 * root complexes. However if a switch is present in the path, then things get 1678 * really ugly depending on how the switch is setup. This table assumes that the 1679 * root complex is strict and is validating that all req/reps are matches 1680 * perfectly - so any scenario where it sees only half the transaction is a 1681 * failure. 1682 * 1683 * CR/RR/DT ATS RO P2P 1684 * 00X X X OK 1685 * 010 X X fails (request is routed to root but root never sees comp) 1686 * 011 0 X fails (request is routed to root but root never sees comp) 1687 * 011 1 X OK 1688 * 10X X 1 OK 1689 * 101 X 0 fails (completion is routed to root but root didn't see req) 1690 * 110 X 0 SLOW 1691 * 111 0 0 SLOW 1692 * 111 1 0 fails (completion is routed to root but root didn't see req) 1693 * 111 1 1 OK 1694 * 1695 * Unfortunately we cannot reliably know if a switch is present or what the 1696 * CR/RR/DT ACS settings are, as in a VM that is all hidden. Assume that 1697 * CR/RR/DT is 111 if the ATS cap is enabled and follow the last three rows. 1698 * 1699 * For now assume if the umem is a dma_buf then it is P2P. 1700 */ mlx5_umem_needs_ats(struct mlx5_ib_dev * dev,struct ib_umem * umem,int access_flags)1701 static inline bool mlx5_umem_needs_ats(struct mlx5_ib_dev *dev, 1702 struct ib_umem *umem, int access_flags) 1703 { 1704 if (!MLX5_CAP_GEN(dev->mdev, ats) || !umem->is_dmabuf) 1705 return false; 1706 return access_flags & IB_ACCESS_RELAXED_ORDERING; 1707 } 1708 1709 int set_roce_addr(struct mlx5_ib_dev *dev, u32 port_num, 1710 unsigned int index, const union ib_gid *gid, 1711 const struct ib_gid_attr *attr); 1712 smi_to_native_portnum(struct mlx5_ib_dev * dev,u32 port)1713 static inline u32 smi_to_native_portnum(struct mlx5_ib_dev *dev, u32 port) 1714 { 1715 return (port - 1) / dev->num_ports + 1; 1716 } 1717 1718 /* 1719 * For mkc users, instead of a page_offset the command has a start_iova which 1720 * specifies both the page_offset and the on-the-wire IOVA 1721 */ 1722 static __always_inline unsigned long mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev * dev,struct ib_umem * umem,u64 iova)1723 mlx5_umem_mkc_find_best_pgsz(struct mlx5_ib_dev *dev, struct ib_umem *umem, 1724 u64 iova) 1725 { 1726 int page_size_bits = 1727 MLX5_CAP_GEN_2(dev->mdev, umr_log_entity_size_5) ? 6 : 5; 1728 unsigned long bitmap = 1729 __mlx5_log_page_size_to_bitmap(page_size_bits, 0); 1730 1731 return ib_umem_find_best_pgsz(umem, bitmap, iova); 1732 } 1733 1734 #endif /* MLX5_IB_H */ 1735