1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* 3 * Copyright (C) 2003-2015, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7 #ifndef __iwl_trans_int_pcie_h__ 8 #define __iwl_trans_int_pcie_h__ 9 10 #include <linux/spinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/skbuff.h> 13 #include <linux/wait.h> 14 #include <linux/pci.h> 15 #include <linux/timer.h> 16 #include <linux/cpu.h> 17 18 #include "iwl-fh.h" 19 #include "iwl-csr.h" 20 #include "iwl-trans.h" 21 #include "iwl-debug.h" 22 #include "iwl-io.h" 23 #include "iwl-op-mode.h" 24 #include "iwl-drv.h" 25 #include "iwl-context-info.h" 26 27 /* 28 * RX related structures and functions 29 */ 30 #define RX_NUM_QUEUES 1 31 #define RX_POST_REQ_ALLOC 2 32 #define RX_CLAIM_REQ_ALLOC 8 33 #define RX_PENDING_WATERMARK 16 34 #define FIRST_RX_QUEUE 512 35 36 struct iwl_host_cmd; 37 38 /*This file includes the declaration that are internal to the 39 * trans_pcie layer */ 40 41 /** 42 * struct iwl_rx_mem_buffer 43 * @page_dma: bus address of rxb page 44 * @page: driver's pointer to the rxb page 45 * @list: list entry for the membuffer 46 * @invalid: rxb is in driver ownership - not owned by HW 47 * @vid: index of this rxb in the global table 48 * @offset: indicates which offset of the page (in bytes) 49 * this buffer uses (if multiple RBs fit into one page) 50 */ 51 struct iwl_rx_mem_buffer { 52 dma_addr_t page_dma; 53 struct page *page; 54 struct list_head list; 55 u32 offset; 56 u16 vid; 57 bool invalid; 58 }; 59 60 /* interrupt statistics */ 61 struct isr_statistics { 62 u32 hw; 63 u32 sw; 64 u32 err_code; 65 u32 sch; 66 u32 alive; 67 u32 rfkill; 68 u32 ctkill; 69 u32 wakeup; 70 u32 rx; 71 u32 tx; 72 u32 unhandled; 73 }; 74 75 /** 76 * struct iwl_rx_transfer_desc - transfer descriptor 77 * @addr: ptr to free buffer start address 78 * @rbid: unique tag of the buffer 79 * @reserved: reserved 80 */ 81 struct iwl_rx_transfer_desc { 82 __le16 rbid; 83 __le16 reserved[3]; 84 __le64 addr; 85 } __packed; 86 87 #define IWL_RX_CD_FLAGS_FRAGMENTED BIT(0) 88 89 /** 90 * struct iwl_rx_completion_desc - completion descriptor 91 * @reserved1: reserved 92 * @rbid: unique tag of the received buffer 93 * @flags: flags (0: fragmented, all others: reserved) 94 * @reserved2: reserved 95 */ 96 struct iwl_rx_completion_desc { 97 __le32 reserved1; 98 __le16 rbid; 99 u8 flags; 100 u8 reserved2[25]; 101 } __packed; 102 103 /** 104 * struct iwl_rx_completion_desc_bz - Bz completion descriptor 105 * @rbid: unique tag of the received buffer 106 * @flags: flags (0: fragmented, all others: reserved) 107 * @reserved: reserved 108 */ 109 struct iwl_rx_completion_desc_bz { 110 __le16 rbid; 111 u8 flags; 112 u8 reserved[1]; 113 } __packed; 114 115 /** 116 * struct iwl_rxq - Rx queue 117 * @id: queue index 118 * @bd: driver's pointer to buffer of receive buffer descriptors (rbd). 119 * Address size is 32 bit in pre-9000 devices and 64 bit in 9000 devices. 120 * In AX210 devices it is a pointer to a list of iwl_rx_transfer_desc's 121 * @bd_dma: bus address of buffer of receive buffer descriptors (rbd) 122 * @used_bd: driver's pointer to buffer of used receive buffer descriptors (rbd) 123 * @used_bd_dma: physical address of buffer of used receive buffer descriptors (rbd) 124 * @read: Shared index to newest available Rx buffer 125 * @write: Shared index to oldest written Rx packet 126 * @write_actual: actual write pointer written to device, since we update in 127 * blocks of 8 only 128 * @free_count: Number of pre-allocated buffers in rx_free 129 * @used_count: Number of RBDs handled to allocator to use for allocation 130 * @write_actual: 131 * @rx_free: list of RBDs with allocated RB ready for use 132 * @rx_used: list of RBDs with no RB attached 133 * @need_update: flag to indicate we need to update read/write index 134 * @rb_stts: driver's pointer to receive buffer status 135 * @rb_stts_dma: bus address of receive buffer status 136 * @lock: per-queue lock 137 * @queue: actual rx queue. Not used for multi-rx queue. 138 * @next_rb_is_fragment: indicates that the previous RB that we handled set 139 * the fragmented flag, so the next one is still another fragment 140 * @napi: NAPI struct for this queue 141 * @queue_size: size of this queue 142 * 143 * NOTE: rx_free and rx_used are used as a FIFO for iwl_rx_mem_buffers 144 */ 145 struct iwl_rxq { 146 int id; 147 void *bd; 148 dma_addr_t bd_dma; 149 void *used_bd; 150 dma_addr_t used_bd_dma; 151 u32 read; 152 u32 write; 153 u32 free_count; 154 u32 used_count; 155 u32 write_actual; 156 u32 queue_size; 157 struct list_head rx_free; 158 struct list_head rx_used; 159 bool need_update, next_rb_is_fragment; 160 void *rb_stts; 161 dma_addr_t rb_stts_dma; 162 spinlock_t lock; 163 struct napi_struct napi; 164 struct iwl_rx_mem_buffer *queue[RX_QUEUE_SIZE]; 165 }; 166 167 /** 168 * struct iwl_rb_allocator - Rx allocator 169 * @req_pending: number of requests the allcator had not processed yet 170 * @req_ready: number of requests honored and ready for claiming 171 * @rbd_allocated: RBDs with pages allocated and ready to be handled to 172 * the queue. This is a list of &struct iwl_rx_mem_buffer 173 * @rbd_empty: RBDs with no page attached for allocator use. This is a list 174 * of &struct iwl_rx_mem_buffer 175 * @lock: protects the rbd_allocated and rbd_empty lists 176 * @alloc_wq: work queue for background calls 177 * @rx_alloc: work struct for background calls 178 */ 179 struct iwl_rb_allocator { 180 atomic_t req_pending; 181 atomic_t req_ready; 182 struct list_head rbd_allocated; 183 struct list_head rbd_empty; 184 spinlock_t lock; 185 struct workqueue_struct *alloc_wq; 186 struct work_struct rx_alloc; 187 }; 188 189 /** 190 * iwl_get_closed_rb_stts - get closed rb stts from different structs 191 * @trans: transport pointer (for configuration) 192 * @rxq: the rxq to get the rb stts from 193 */ iwl_get_closed_rb_stts(struct iwl_trans * trans,struct iwl_rxq * rxq)194 static inline u16 iwl_get_closed_rb_stts(struct iwl_trans *trans, 195 struct iwl_rxq *rxq) 196 { 197 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 198 __le16 *rb_stts = rxq->rb_stts; 199 200 return le16_to_cpu(READ_ONCE(*rb_stts)); 201 } else { 202 struct iwl_rb_status *rb_stts = rxq->rb_stts; 203 204 return le16_to_cpu(READ_ONCE(rb_stts->closed_rb_num)) & 0xFFF; 205 } 206 } 207 208 #ifdef CONFIG_IWLWIFI_DEBUGFS 209 /** 210 * enum iwl_fw_mon_dbgfs_state - the different states of the monitor_data 211 * debugfs file 212 * 213 * @IWL_FW_MON_DBGFS_STATE_CLOSED: the file is closed. 214 * @IWL_FW_MON_DBGFS_STATE_OPEN: the file is open. 215 * @IWL_FW_MON_DBGFS_STATE_DISABLED: the file is disabled, once this state is 216 * set the file can no longer be used. 217 */ 218 enum iwl_fw_mon_dbgfs_state { 219 IWL_FW_MON_DBGFS_STATE_CLOSED, 220 IWL_FW_MON_DBGFS_STATE_OPEN, 221 IWL_FW_MON_DBGFS_STATE_DISABLED, 222 }; 223 #endif 224 225 /** 226 * enum iwl_shared_irq_flags - level of sharing for irq 227 * @IWL_SHARED_IRQ_NON_RX: interrupt vector serves non rx causes. 228 * @IWL_SHARED_IRQ_FIRST_RSS: interrupt vector serves first RSS queue. 229 */ 230 enum iwl_shared_irq_flags { 231 IWL_SHARED_IRQ_NON_RX = BIT(0), 232 IWL_SHARED_IRQ_FIRST_RSS = BIT(1), 233 }; 234 235 /** 236 * enum iwl_image_response_code - image response values 237 * @IWL_IMAGE_RESP_DEF: the default value of the register 238 * @IWL_IMAGE_RESP_SUCCESS: iml was read successfully 239 * @IWL_IMAGE_RESP_FAIL: iml reading failed 240 */ 241 enum iwl_image_response_code { 242 IWL_IMAGE_RESP_DEF = 0, 243 IWL_IMAGE_RESP_SUCCESS = 1, 244 IWL_IMAGE_RESP_FAIL = 2, 245 }; 246 247 #ifdef CONFIG_IWLWIFI_DEBUGFS 248 /** 249 * struct cont_rec: continuous recording data structure 250 * @prev_wr_ptr: the last address that was read in monitor_data 251 * debugfs file 252 * @prev_wrap_cnt: the wrap count that was used during the last read in 253 * monitor_data debugfs file 254 * @state: the state of monitor_data debugfs file as described 255 * in &iwl_fw_mon_dbgfs_state enum 256 * @mutex: locked while reading from monitor_data debugfs file 257 */ 258 struct cont_rec { 259 u32 prev_wr_ptr; 260 u32 prev_wrap_cnt; 261 u8 state; 262 /* Used to sync monitor_data debugfs file with driver unload flow */ 263 struct mutex mutex; 264 }; 265 #endif 266 267 enum iwl_pcie_fw_reset_state { 268 FW_RESET_IDLE, 269 FW_RESET_REQUESTED, 270 FW_RESET_OK, 271 FW_RESET_ERROR, 272 }; 273 274 /** 275 * enum iwl_pcie_imr_status - imr dma transfer state 276 * @IMR_D2S_IDLE: default value of the dma transfer 277 * @IMR_D2S_REQUESTED: dma transfer requested 278 * @IMR_D2S_COMPLETED: dma transfer completed 279 * @IMR_D2S_ERROR: dma transfer error 280 */ 281 enum iwl_pcie_imr_status { 282 IMR_D2S_IDLE, 283 IMR_D2S_REQUESTED, 284 IMR_D2S_COMPLETED, 285 IMR_D2S_ERROR, 286 }; 287 288 /** 289 * struct iwl_pcie_txqs - TX queues data 290 * 291 * @bc_table_dword: true if the BC table expects DWORD (as opposed to bytes) 292 * @page_offs: offset from skb->cb to mac header page pointer 293 * @dev_cmd_offs: offset from skb->cb to iwl_device_tx_cmd pointer 294 * @queue_used: bit mask of used queues 295 * @queue_stopped: bit mask of stopped queues 296 * @txq: array of TXQ data structures representing the TXQs 297 * @scd_bc_tbls: gen1 pointer to the byte count table of the scheduler 298 * @queue_alloc_cmd_ver: queue allocation command version 299 * @bc_pool: bytecount DMA allocations pool 300 * @bc_tbl_size: bytecount table size 301 * @tso_hdr_page: page allocated (per CPU) for A-MSDU headers when doing TSO 302 * (and similar usage) 303 * @cmd: command queue data 304 * @cmd.fifo: FIFO number 305 * @cmd.q_id: queue ID 306 * @cmd.wdg_timeout: watchdog timeout 307 * @tfd: TFD data 308 * @tfd.max_tbs: max number of buffers per TFD 309 * @tfd.size: TFD size 310 * @tfd.addr_size: TFD/TB address size 311 */ 312 struct iwl_pcie_txqs { 313 unsigned long queue_used[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 314 unsigned long queue_stopped[BITS_TO_LONGS(IWL_MAX_TVQM_QUEUES)]; 315 struct iwl_txq *txq[IWL_MAX_TVQM_QUEUES]; 316 struct dma_pool *bc_pool; 317 size_t bc_tbl_size; 318 bool bc_table_dword; 319 u8 page_offs; 320 u8 dev_cmd_offs; 321 struct iwl_tso_hdr_page __percpu *tso_hdr_page; 322 323 struct { 324 u8 fifo; 325 u8 q_id; 326 unsigned int wdg_timeout; 327 } cmd; 328 329 struct { 330 u8 max_tbs; 331 u16 size; 332 u8 addr_size; 333 } tfd; 334 335 struct iwl_dma_ptr scd_bc_tbls; 336 337 u8 queue_alloc_cmd_ver; 338 }; 339 340 /** 341 * struct iwl_trans_pcie - PCIe transport specific data 342 * @rxq: all the RX queue data 343 * @rx_pool: initial pool of iwl_rx_mem_buffer for all the queues 344 * @global_table: table mapping received VID from hw to rxb 345 * @rba: allocator for RX replenishing 346 * @ctxt_info: context information for FW self init 347 * @ctxt_info_gen3: context information for gen3 devices 348 * @prph_info: prph info for self init 349 * @prph_scratch: prph scratch for self init 350 * @ctxt_info_dma_addr: dma addr of context information 351 * @prph_info_dma_addr: dma addr of prph info 352 * @prph_scratch_dma_addr: dma addr of prph scratch 353 * @ctxt_info_dma_addr: dma addr of context information 354 * @iml: image loader image virtual address 355 * @iml_dma_addr: image loader image DMA address 356 * @trans: pointer to the generic transport area 357 * @scd_base_addr: scheduler sram base address in SRAM 358 * @kw: keep warm address 359 * @pnvm_data: holds info about pnvm payloads allocated in DRAM 360 * @reduced_tables_data: holds info about power reduced tablse 361 * payloads allocated in DRAM 362 * @pci_dev: basic pci-network driver stuff 363 * @hw_base: pci hardware address support 364 * @ucode_write_complete: indicates that the ucode has been copied. 365 * @ucode_write_waitq: wait queue for uCode load 366 * @cmd_queue - command queue number 367 * @rx_buf_size: Rx buffer size 368 * @scd_set_active: should the transport configure the SCD for HCMD queue 369 * @rx_page_order: page order for receive buffer size 370 * @rx_buf_bytes: RX buffer (RB) size in bytes 371 * @reg_lock: protect hw register access 372 * @mutex: to protect stop_device / start_fw / start_hw 373 * @fw_mon_data: fw continuous recording data 374 * @cmd_hold_nic_awake: indicates NIC is held awake for APMG workaround 375 * during commands in flight 376 * @msix_entries: array of MSI-X entries 377 * @msix_enabled: true if managed to enable MSI-X 378 * @shared_vec_mask: the type of causes the shared vector handles 379 * (see iwl_shared_irq_flags). 380 * @alloc_vecs: the number of interrupt vectors allocated by the OS 381 * @def_irq: default irq for non rx causes 382 * @fh_init_mask: initial unmasked fh causes 383 * @hw_init_mask: initial unmasked hw causes 384 * @fh_mask: current unmasked fh causes 385 * @hw_mask: current unmasked hw causes 386 * @in_rescan: true if we have triggered a device rescan 387 * @base_rb_stts: base virtual address of receive buffer status for all queues 388 * @base_rb_stts_dma: base physical address of receive buffer status 389 * @supported_dma_mask: DMA mask to validate the actual address against, 390 * will be DMA_BIT_MASK(11) or DMA_BIT_MASK(12) depending on the device 391 * @alloc_page_lock: spinlock for the page allocator 392 * @alloc_page: allocated page to still use parts of 393 * @alloc_page_used: how much of the allocated page was already used (bytes) 394 * @imr_status: imr dma state machine 395 * @imr_waitq: imr wait queue for dma completion 396 * @rf_name: name/version of the CRF, if any 397 * @use_ict: whether or not ICT (interrupt table) is used 398 * @ict_index: current ICT read index 399 * @ict_tbl: ICT table pointer 400 * @ict_tbl_dma: ICT table DMA address 401 * @inta_mask: interrupt (INT-A) mask 402 * @irq_lock: lock to synchronize IRQ handling 403 * @txq_memory: TXQ allocation array 404 * @sx_waitq: waitqueue for Sx transitions 405 * @sx_complete: completion for Sx transitions 406 * @pcie_dbg_dumped_once: indicates PCIe regs were dumped already 407 * @opmode_down: indicates opmode went away 408 * @num_rx_bufs: number of RX buffers to allocate/use 409 * @no_reclaim_cmds: special commands not using reclaim flow 410 * (firmware workaround) 411 * @n_no_reclaim_cmds: number of special commands not using reclaim flow 412 * @affinity_mask: IRQ affinity mask for each RX queue 413 * @debug_rfkill: RF-kill debugging state, -1 for unset, 0/1 for radio 414 * enable/disable 415 * @fw_reset_handshake: indicates FW reset handshake is needed 416 * @fw_reset_state: state of FW reset handshake 417 * @fw_reset_waitq: waitqueue for FW reset handshake 418 * @is_down: indicates the NIC is down 419 * @isr_stats: interrupt statistics 420 * @napi_dev: (fake) netdev for NAPI registration 421 * @txqs: transport tx queues data. 422 */ 423 struct iwl_trans_pcie { 424 struct iwl_rxq *rxq; 425 struct iwl_rx_mem_buffer *rx_pool; 426 struct iwl_rx_mem_buffer **global_table; 427 struct iwl_rb_allocator rba; 428 union { 429 struct iwl_context_info *ctxt_info; 430 struct iwl_context_info_gen3 *ctxt_info_gen3; 431 }; 432 struct iwl_prph_info *prph_info; 433 struct iwl_prph_scratch *prph_scratch; 434 void *iml; 435 dma_addr_t ctxt_info_dma_addr; 436 dma_addr_t prph_info_dma_addr; 437 dma_addr_t prph_scratch_dma_addr; 438 dma_addr_t iml_dma_addr; 439 struct iwl_trans *trans; 440 441 struct net_device *napi_dev; 442 443 /* INT ICT Table */ 444 __le32 *ict_tbl; 445 dma_addr_t ict_tbl_dma; 446 int ict_index; 447 bool use_ict; 448 bool is_down, opmode_down; 449 s8 debug_rfkill; 450 struct isr_statistics isr_stats; 451 452 spinlock_t irq_lock; 453 struct mutex mutex; 454 u32 inta_mask; 455 u32 scd_base_addr; 456 struct iwl_dma_ptr kw; 457 458 /* pnvm data */ 459 struct iwl_dram_regions pnvm_data; 460 struct iwl_dram_regions reduced_tables_data; 461 462 struct iwl_txq *txq_memory; 463 464 /* PCI bus related data */ 465 struct pci_dev *pci_dev; 466 u8 __iomem *hw_base; 467 468 bool ucode_write_complete; 469 bool sx_complete; 470 wait_queue_head_t ucode_write_waitq; 471 wait_queue_head_t sx_waitq; 472 473 u8 n_no_reclaim_cmds; 474 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 475 u16 num_rx_bufs; 476 477 enum iwl_amsdu_size rx_buf_size; 478 bool scd_set_active; 479 bool pcie_dbg_dumped_once; 480 u32 rx_page_order; 481 u32 rx_buf_bytes; 482 u32 supported_dma_mask; 483 484 /* allocator lock for the two values below */ 485 spinlock_t alloc_page_lock; 486 struct page *alloc_page; 487 u32 alloc_page_used; 488 489 /*protect hw register */ 490 spinlock_t reg_lock; 491 bool cmd_hold_nic_awake; 492 493 #ifdef CONFIG_IWLWIFI_DEBUGFS 494 struct cont_rec fw_mon_data; 495 #endif 496 497 struct msix_entry msix_entries[IWL_MAX_RX_HW_QUEUES]; 498 bool msix_enabled; 499 u8 shared_vec_mask; 500 u32 alloc_vecs; 501 u32 def_irq; 502 u32 fh_init_mask; 503 u32 hw_init_mask; 504 u32 fh_mask; 505 u32 hw_mask; 506 cpumask_t affinity_mask[IWL_MAX_RX_HW_QUEUES]; 507 u16 tx_cmd_queue_size; 508 bool in_rescan; 509 510 void *base_rb_stts; 511 dma_addr_t base_rb_stts_dma; 512 513 bool fw_reset_handshake; 514 enum iwl_pcie_fw_reset_state fw_reset_state; 515 wait_queue_head_t fw_reset_waitq; 516 enum iwl_pcie_imr_status imr_status; 517 wait_queue_head_t imr_waitq; 518 char rf_name[32]; 519 520 struct iwl_pcie_txqs txqs; 521 }; 522 523 static inline struct iwl_trans_pcie * IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans * trans)524 IWL_TRANS_GET_PCIE_TRANS(struct iwl_trans *trans) 525 { 526 return (void *)trans->trans_specific; 527 } 528 iwl_pcie_clear_irq(struct iwl_trans * trans,int queue)529 static inline void iwl_pcie_clear_irq(struct iwl_trans *trans, int queue) 530 { 531 /* 532 * Before sending the interrupt the HW disables it to prevent 533 * a nested interrupt. This is done by writing 1 to the corresponding 534 * bit in the mask register. After handling the interrupt, it should be 535 * re-enabled by clearing this bit. This register is defined as 536 * write 1 clear (W1C) register, meaning that it's being clear 537 * by writing 1 to the bit. 538 */ 539 iwl_write32(trans, CSR_MSIX_AUTOMASK_ST_AD, BIT(queue)); 540 } 541 542 static inline struct iwl_trans * iwl_trans_pcie_get_trans(struct iwl_trans_pcie * trans_pcie)543 iwl_trans_pcie_get_trans(struct iwl_trans_pcie *trans_pcie) 544 { 545 return container_of((void *)trans_pcie, struct iwl_trans, 546 trans_specific); 547 } 548 549 /* 550 * Convention: trans API functions: iwl_trans_pcie_XXX 551 * Other functions: iwl_pcie_XXX 552 */ 553 struct iwl_trans 554 *iwl_trans_pcie_alloc(struct pci_dev *pdev, 555 const struct pci_device_id *ent, 556 const struct iwl_cfg_trans_params *cfg_trans); 557 void iwl_trans_pcie_free(struct iwl_trans *trans); 558 void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 559 struct device *dev); 560 561 bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans); 562 #define _iwl_trans_pcie_grab_nic_access(trans) \ 563 __cond_lock(nic_access_nobh, \ 564 likely(__iwl_trans_pcie_grab_nic_access(trans))) 565 566 /***************************************************** 567 * RX 568 ******************************************************/ 569 int iwl_pcie_rx_init(struct iwl_trans *trans); 570 int iwl_pcie_gen2_rx_init(struct iwl_trans *trans); 571 irqreturn_t iwl_pcie_msix_isr(int irq, void *data); 572 irqreturn_t iwl_pcie_irq_handler(int irq, void *dev_id); 573 irqreturn_t iwl_pcie_irq_msix_handler(int irq, void *dev_id); 574 irqreturn_t iwl_pcie_irq_rx_msix_handler(int irq, void *dev_id); 575 int iwl_pcie_rx_stop(struct iwl_trans *trans); 576 void iwl_pcie_rx_free(struct iwl_trans *trans); 577 void iwl_pcie_free_rbs_pool(struct iwl_trans *trans); 578 void iwl_pcie_rx_init_rxb_lists(struct iwl_rxq *rxq); 579 void iwl_pcie_rx_napi_sync(struct iwl_trans *trans); 580 void iwl_pcie_rxq_alloc_rbs(struct iwl_trans *trans, gfp_t priority, 581 struct iwl_rxq *rxq); 582 583 /***************************************************** 584 * ICT - interrupt handling 585 ******************************************************/ 586 irqreturn_t iwl_pcie_isr(int irq, void *data); 587 int iwl_pcie_alloc_ict(struct iwl_trans *trans); 588 void iwl_pcie_free_ict(struct iwl_trans *trans); 589 void iwl_pcie_reset_ict(struct iwl_trans *trans); 590 void iwl_pcie_disable_ict(struct iwl_trans *trans); 591 592 /***************************************************** 593 * TX / HCMD 594 ******************************************************/ 595 /* We need 2 entries for the TX command and header, and another one might 596 * be needed for potential data in the SKB's head. The remaining ones can 597 * be used for frags. 598 */ 599 #define IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie) ((trans_pcie)->txqs.tfd.max_tbs - 3) 600 601 struct iwl_tso_hdr_page { 602 struct page *page; 603 u8 *pos; 604 }; 605 606 /* 607 * Note that we put this struct *last* in the page. By doing that, we ensure 608 * that no TB referencing this page can trigger the 32-bit boundary hardware 609 * bug. 610 */ 611 struct iwl_tso_page_info { 612 dma_addr_t dma_addr; 613 struct page *next; 614 refcount_t use_count; 615 }; 616 617 #define IWL_TSO_PAGE_DATA_SIZE (PAGE_SIZE - sizeof(struct iwl_tso_page_info)) 618 #define IWL_TSO_PAGE_INFO(addr) \ 619 ((struct iwl_tso_page_info *)(((unsigned long)addr & PAGE_MASK) + \ 620 IWL_TSO_PAGE_DATA_SIZE)) 621 622 int iwl_pcie_tx_init(struct iwl_trans *trans); 623 void iwl_pcie_tx_start(struct iwl_trans *trans, u32 scd_base_addr); 624 int iwl_pcie_tx_stop(struct iwl_trans *trans); 625 void iwl_pcie_tx_free(struct iwl_trans *trans); 626 bool iwl_trans_pcie_txq_enable(struct iwl_trans *trans, int queue, u16 ssn, 627 const struct iwl_trans_txq_scd_cfg *cfg, 628 unsigned int wdg_timeout); 629 void iwl_trans_pcie_txq_disable(struct iwl_trans *trans, int queue, 630 bool configure_scd); 631 void iwl_trans_pcie_txq_set_shared_mode(struct iwl_trans *trans, u32 txq_id, 632 bool shared_mode); 633 int iwl_trans_pcie_tx(struct iwl_trans *trans, struct sk_buff *skb, 634 struct iwl_device_tx_cmd *dev_cmd, int txq_id); 635 void iwl_pcie_txq_check_wrptrs(struct iwl_trans *trans); 636 void iwl_pcie_hcmd_complete(struct iwl_trans *trans, 637 struct iwl_rx_cmd_buffer *rxb); 638 void iwl_trans_pcie_tx_reset(struct iwl_trans *trans); 639 int iwl_pcie_txq_alloc(struct iwl_trans *trans, struct iwl_txq *txq, 640 int slots_num, bool cmd_queue); 641 642 dma_addr_t iwl_pcie_get_sgt_tb_phys(struct sg_table *sgt, unsigned int offset, 643 unsigned int len); 644 struct sg_table *iwl_pcie_prep_tso(struct iwl_trans *trans, struct sk_buff *skb, 645 struct iwl_cmd_meta *cmd_meta, 646 u8 **hdr, unsigned int hdr_room); 647 648 void iwl_pcie_free_tso_pages(struct iwl_trans *trans, struct sk_buff *skb, 649 struct iwl_cmd_meta *cmd_meta); 650 iwl_pcie_get_tso_page_phys(void * addr)651 static inline dma_addr_t iwl_pcie_get_tso_page_phys(void *addr) 652 { 653 dma_addr_t res; 654 655 res = IWL_TSO_PAGE_INFO(addr)->dma_addr; 656 res += (unsigned long)addr & ~PAGE_MASK; 657 658 return res; 659 } 660 661 static inline dma_addr_t iwl_txq_get_first_tb_dma(struct iwl_txq * txq,int idx)662 iwl_txq_get_first_tb_dma(struct iwl_txq *txq, int idx) 663 { 664 return txq->first_tb_dma + 665 sizeof(struct iwl_pcie_first_tb_buf) * idx; 666 } 667 iwl_txq_get_cmd_index(const struct iwl_txq * q,u32 index)668 static inline u16 iwl_txq_get_cmd_index(const struct iwl_txq *q, u32 index) 669 { 670 return index & (q->n_window - 1); 671 } 672 iwl_txq_get_tfd(struct iwl_trans * trans,struct iwl_txq * txq,int idx)673 static inline void *iwl_txq_get_tfd(struct iwl_trans *trans, 674 struct iwl_txq *txq, int idx) 675 { 676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 677 678 if (trans->trans_cfg->gen2) 679 idx = iwl_txq_get_cmd_index(txq, idx); 680 681 return (u8 *)txq->tfds + trans_pcie->txqs.tfd.size * idx; 682 } 683 684 /* 685 * We need this inline in case dma_addr_t is only 32-bits - since the 686 * hardware is always 64-bit, the issue can still occur in that case, 687 * so use u64 for 'phys' here to force the addition in 64-bit. 688 */ iwl_txq_crosses_4g_boundary(u64 phys,u16 len)689 static inline bool iwl_txq_crosses_4g_boundary(u64 phys, u16 len) 690 { 691 return upper_32_bits(phys) != upper_32_bits(phys + len); 692 } 693 694 int iwl_txq_space(struct iwl_trans *trans, const struct iwl_txq *q); 695 iwl_txq_stop(struct iwl_trans * trans,struct iwl_txq * txq)696 static inline void iwl_txq_stop(struct iwl_trans *trans, struct iwl_txq *txq) 697 { 698 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 699 700 if (!test_and_set_bit(txq->id, trans_pcie->txqs.queue_stopped)) { 701 iwl_op_mode_queue_full(trans->op_mode, txq->id); 702 IWL_DEBUG_TX_QUEUES(trans, "Stop hwq %d\n", txq->id); 703 } else { 704 IWL_DEBUG_TX_QUEUES(trans, "hwq %d already stopped\n", 705 txq->id); 706 } 707 } 708 709 /** 710 * iwl_txq_inc_wrap - increment queue index, wrap back to beginning 711 * @trans: the transport (for configuration data) 712 * @index: current index 713 */ iwl_txq_inc_wrap(struct iwl_trans * trans,int index)714 static inline int iwl_txq_inc_wrap(struct iwl_trans *trans, int index) 715 { 716 return ++index & 717 (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 718 } 719 720 /** 721 * iwl_txq_dec_wrap - decrement queue index, wrap back to end 722 * @trans: the transport (for configuration data) 723 * @index: current index 724 */ iwl_txq_dec_wrap(struct iwl_trans * trans,int index)725 static inline int iwl_txq_dec_wrap(struct iwl_trans *trans, int index) 726 { 727 return --index & 728 (trans->trans_cfg->base_params->max_tfd_queue_size - 1); 729 } 730 731 void iwl_txq_log_scd_error(struct iwl_trans *trans, struct iwl_txq *txq); 732 733 static inline void iwl_trans_pcie_wake_queue(struct iwl_trans * trans,struct iwl_txq * txq)734 iwl_trans_pcie_wake_queue(struct iwl_trans *trans, struct iwl_txq *txq) 735 { 736 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 737 738 if (test_and_clear_bit(txq->id, trans_pcie->txqs.queue_stopped)) { 739 IWL_DEBUG_TX_QUEUES(trans, "Wake hwq %d\n", txq->id); 740 iwl_op_mode_queue_not_full(trans->op_mode, txq->id); 741 } 742 } 743 744 int iwl_txq_gen2_set_tb(struct iwl_trans *trans, 745 struct iwl_tfh_tfd *tfd, dma_addr_t addr, 746 u16 len); 747 iwl_txq_set_tfd_invalid_gen2(struct iwl_trans * trans,struct iwl_tfh_tfd * tfd)748 static inline void iwl_txq_set_tfd_invalid_gen2(struct iwl_trans *trans, 749 struct iwl_tfh_tfd *tfd) 750 { 751 tfd->num_tbs = 0; 752 753 iwl_txq_gen2_set_tb(trans, tfd, trans->invalid_tx_cmd.dma, 754 trans->invalid_tx_cmd.size); 755 } 756 757 void iwl_txq_gen2_tfd_unmap(struct iwl_trans *trans, 758 struct iwl_cmd_meta *meta, 759 struct iwl_tfh_tfd *tfd); 760 761 int iwl_txq_dyn_alloc(struct iwl_trans *trans, u32 flags, 762 u32 sta_mask, u8 tid, 763 int size, unsigned int timeout); 764 765 int iwl_txq_gen2_tx(struct iwl_trans *trans, struct sk_buff *skb, 766 struct iwl_device_tx_cmd *dev_cmd, int txq_id); 767 768 void iwl_txq_dyn_free(struct iwl_trans *trans, int queue); 769 void iwl_txq_gen2_tx_free(struct iwl_trans *trans); 770 int iwl_txq_init(struct iwl_trans *trans, struct iwl_txq *txq, 771 int slots_num, bool cmd_queue); 772 int iwl_txq_gen2_init(struct iwl_trans *trans, int txq_id, 773 int queue_size); 774 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans * trans,void * _tfd,u8 idx)775 static inline u16 iwl_txq_gen1_tfd_tb_get_len(struct iwl_trans *trans, 776 void *_tfd, u8 idx) 777 { 778 struct iwl_tfd *tfd; 779 struct iwl_tfd_tb *tb; 780 781 if (trans->trans_cfg->gen2) { 782 struct iwl_tfh_tfd *tfh_tfd = _tfd; 783 struct iwl_tfh_tb *tfh_tb = &tfh_tfd->tbs[idx]; 784 785 return le16_to_cpu(tfh_tb->tb_len); 786 } 787 788 tfd = (struct iwl_tfd *)_tfd; 789 tb = &tfd->tbs[idx]; 790 791 return le16_to_cpu(tb->hi_n_len) >> 4; 792 } 793 794 void iwl_pcie_reclaim(struct iwl_trans *trans, int txq_id, int ssn, 795 struct sk_buff_head *skbs, bool is_flush); 796 void iwl_pcie_set_q_ptrs(struct iwl_trans *trans, int txq_id, int ptr); 797 void iwl_pcie_freeze_txq_timer(struct iwl_trans *trans, 798 unsigned long txqs, bool freeze); 799 int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx); 800 int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm); 801 802 /***************************************************** 803 * Error handling 804 ******************************************************/ 805 void iwl_pcie_dump_csr(struct iwl_trans *trans); 806 807 /***************************************************** 808 * Helpers 809 ******************************************************/ _iwl_disable_interrupts(struct iwl_trans * trans)810 static inline void _iwl_disable_interrupts(struct iwl_trans *trans) 811 { 812 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 813 814 clear_bit(STATUS_INT_ENABLED, &trans->status); 815 if (!trans_pcie->msix_enabled) { 816 /* disable interrupts from uCode/NIC to host */ 817 iwl_write32(trans, CSR_INT_MASK, 0x00000000); 818 819 /* acknowledge/clear/reset any interrupts still pending 820 * from uCode or flow handler (Rx/Tx DMA) */ 821 iwl_write32(trans, CSR_INT, 0xffffffff); 822 iwl_write32(trans, CSR_FH_INT_STATUS, 0xffffffff); 823 } else { 824 /* disable all the interrupt we might use */ 825 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 826 trans_pcie->fh_init_mask); 827 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 828 trans_pcie->hw_init_mask); 829 } 830 IWL_DEBUG_ISR(trans, "Disabled interrupts\n"); 831 } 832 iwl_pcie_get_num_sections(const struct fw_img * fw,int start)833 static inline int iwl_pcie_get_num_sections(const struct fw_img *fw, 834 int start) 835 { 836 int i = 0; 837 838 while (start < fw->num_sec && 839 fw->sec[start].offset != CPU1_CPU2_SEPARATOR_SECTION && 840 fw->sec[start].offset != PAGING_SEPARATOR_SECTION) { 841 start++; 842 i++; 843 } 844 845 return i; 846 } 847 iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans * trans)848 static inline void iwl_pcie_ctxt_info_free_fw_img(struct iwl_trans *trans) 849 { 850 struct iwl_self_init_dram *dram = &trans->init_dram; 851 int i; 852 853 if (!dram->fw) { 854 WARN_ON(dram->fw_cnt); 855 return; 856 } 857 858 for (i = 0; i < dram->fw_cnt; i++) 859 dma_free_coherent(trans->dev, dram->fw[i].size, 860 dram->fw[i].block, dram->fw[i].physical); 861 862 kfree(dram->fw); 863 dram->fw_cnt = 0; 864 dram->fw = NULL; 865 } 866 iwl_disable_interrupts(struct iwl_trans * trans)867 static inline void iwl_disable_interrupts(struct iwl_trans *trans) 868 { 869 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 870 871 spin_lock_bh(&trans_pcie->irq_lock); 872 _iwl_disable_interrupts(trans); 873 spin_unlock_bh(&trans_pcie->irq_lock); 874 } 875 _iwl_enable_interrupts(struct iwl_trans * trans)876 static inline void _iwl_enable_interrupts(struct iwl_trans *trans) 877 { 878 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 879 880 IWL_DEBUG_ISR(trans, "Enabling interrupts\n"); 881 set_bit(STATUS_INT_ENABLED, &trans->status); 882 if (!trans_pcie->msix_enabled) { 883 trans_pcie->inta_mask = CSR_INI_SET_MASK; 884 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 885 } else { 886 /* 887 * fh/hw_mask keeps all the unmasked causes. 888 * Unlike msi, in msix cause is enabled when it is unset. 889 */ 890 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 891 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 892 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 893 ~trans_pcie->fh_mask); 894 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 895 ~trans_pcie->hw_mask); 896 } 897 } 898 iwl_enable_interrupts(struct iwl_trans * trans)899 static inline void iwl_enable_interrupts(struct iwl_trans *trans) 900 { 901 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 902 903 spin_lock_bh(&trans_pcie->irq_lock); 904 _iwl_enable_interrupts(trans); 905 spin_unlock_bh(&trans_pcie->irq_lock); 906 } iwl_enable_hw_int_msk_msix(struct iwl_trans * trans,u32 msk)907 static inline void iwl_enable_hw_int_msk_msix(struct iwl_trans *trans, u32 msk) 908 { 909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 910 911 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, ~msk); 912 trans_pcie->hw_mask = msk; 913 } 914 iwl_enable_fh_int_msk_msix(struct iwl_trans * trans,u32 msk)915 static inline void iwl_enable_fh_int_msk_msix(struct iwl_trans *trans, u32 msk) 916 { 917 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 918 919 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~msk); 920 trans_pcie->fh_mask = msk; 921 } 922 iwl_enable_fw_load_int(struct iwl_trans * trans)923 static inline void iwl_enable_fw_load_int(struct iwl_trans *trans) 924 { 925 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 926 927 IWL_DEBUG_ISR(trans, "Enabling FW load interrupt\n"); 928 if (!trans_pcie->msix_enabled) { 929 trans_pcie->inta_mask = CSR_INT_BIT_FH_TX; 930 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 931 } else { 932 iwl_write32(trans, CSR_MSIX_HW_INT_MASK_AD, 933 trans_pcie->hw_init_mask); 934 iwl_enable_fh_int_msk_msix(trans, 935 MSIX_FH_INT_CAUSES_D2S_CH0_NUM); 936 } 937 } 938 iwl_enable_fw_load_int_ctx_info(struct iwl_trans * trans)939 static inline void iwl_enable_fw_load_int_ctx_info(struct iwl_trans *trans) 940 { 941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 942 943 IWL_DEBUG_ISR(trans, "Enabling ALIVE interrupt only\n"); 944 945 if (!trans_pcie->msix_enabled) { 946 /* 947 * When we'll receive the ALIVE interrupt, the ISR will call 948 * iwl_enable_fw_load_int_ctx_info again to set the ALIVE 949 * interrupt (which is not really needed anymore) but also the 950 * RX interrupt which will allow us to receive the ALIVE 951 * notification (which is Rx) and continue the flow. 952 */ 953 trans_pcie->inta_mask = CSR_INT_BIT_ALIVE | CSR_INT_BIT_FH_RX; 954 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 955 } else { 956 iwl_enable_hw_int_msk_msix(trans, 957 MSIX_HW_INT_CAUSES_REG_ALIVE); 958 /* 959 * Leave all the FH causes enabled to get the ALIVE 960 * notification. 961 */ 962 iwl_enable_fh_int_msk_msix(trans, trans_pcie->fh_init_mask); 963 } 964 } 965 queue_name(struct device * dev,struct iwl_trans_pcie * trans_p,int i)966 static inline const char *queue_name(struct device *dev, 967 struct iwl_trans_pcie *trans_p, int i) 968 { 969 if (trans_p->shared_vec_mask) { 970 int vec = trans_p->shared_vec_mask & 971 IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 972 973 if (i == 0) 974 return DRV_NAME ":shared_IRQ"; 975 976 return devm_kasprintf(dev, GFP_KERNEL, 977 DRV_NAME ":queue_%d", i + vec); 978 } 979 if (i == 0) 980 return DRV_NAME ":default_queue"; 981 982 if (i == trans_p->alloc_vecs - 1) 983 return DRV_NAME ":exception"; 984 985 return devm_kasprintf(dev, GFP_KERNEL, 986 DRV_NAME ":queue_%d", i); 987 } 988 iwl_enable_rfkill_int(struct iwl_trans * trans)989 static inline void iwl_enable_rfkill_int(struct iwl_trans *trans) 990 { 991 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 992 993 IWL_DEBUG_ISR(trans, "Enabling rfkill interrupt\n"); 994 if (!trans_pcie->msix_enabled) { 995 trans_pcie->inta_mask = CSR_INT_BIT_RF_KILL; 996 iwl_write32(trans, CSR_INT_MASK, trans_pcie->inta_mask); 997 } else { 998 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, 999 trans_pcie->fh_init_mask); 1000 iwl_enable_hw_int_msk_msix(trans, 1001 MSIX_HW_INT_CAUSES_REG_RF_KILL); 1002 } 1003 1004 if (trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_9000) { 1005 /* 1006 * On 9000-series devices this bit isn't enabled by default, so 1007 * when we power down the device we need set the bit to allow it 1008 * to wake up the PCI-E bus for RF-kill interrupts. 1009 */ 1010 iwl_set_bit(trans, CSR_GP_CNTRL, 1011 CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN); 1012 } 1013 } 1014 1015 void iwl_pcie_handle_rfkill_irq(struct iwl_trans *trans, bool from_irq); 1016 iwl_is_rfkill_set(struct iwl_trans * trans)1017 static inline bool iwl_is_rfkill_set(struct iwl_trans *trans) 1018 { 1019 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1020 1021 lockdep_assert_held(&trans_pcie->mutex); 1022 1023 if (trans_pcie->debug_rfkill == 1) 1024 return true; 1025 1026 return !(iwl_read32(trans, CSR_GP_CNTRL) & 1027 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW); 1028 } 1029 __iwl_trans_pcie_set_bits_mask(struct iwl_trans * trans,u32 reg,u32 mask,u32 value)1030 static inline void __iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, 1031 u32 reg, u32 mask, u32 value) 1032 { 1033 u32 v; 1034 1035 #ifdef CONFIG_IWLWIFI_DEBUG 1036 WARN_ON_ONCE(value & ~mask); 1037 #endif 1038 1039 v = iwl_read32(trans, reg); 1040 v &= ~mask; 1041 v |= value; 1042 iwl_write32(trans, reg, v); 1043 } 1044 __iwl_trans_pcie_clear_bit(struct iwl_trans * trans,u32 reg,u32 mask)1045 static inline void __iwl_trans_pcie_clear_bit(struct iwl_trans *trans, 1046 u32 reg, u32 mask) 1047 { 1048 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, 0); 1049 } 1050 __iwl_trans_pcie_set_bit(struct iwl_trans * trans,u32 reg,u32 mask)1051 static inline void __iwl_trans_pcie_set_bit(struct iwl_trans *trans, 1052 u32 reg, u32 mask) 1053 { 1054 __iwl_trans_pcie_set_bits_mask(trans, reg, mask, mask); 1055 } 1056 iwl_pcie_dbg_on(struct iwl_trans * trans)1057 static inline bool iwl_pcie_dbg_on(struct iwl_trans *trans) 1058 { 1059 return (trans->dbg.dest_tlv || iwl_trans_dbg_ini_valid(trans)); 1060 } 1061 1062 void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq); 1063 void iwl_trans_pcie_dump_regs(struct iwl_trans *trans); 1064 1065 #ifdef CONFIG_IWLWIFI_DEBUGFS 1066 void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans); 1067 void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans); 1068 #else iwl_trans_pcie_dbgfs_register(struct iwl_trans * trans)1069 static inline void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) { } 1070 #endif 1071 1072 void iwl_pcie_rx_allocator_work(struct work_struct *data); 1073 1074 /* common trans ops for all generations transports */ 1075 void iwl_trans_pcie_configure(struct iwl_trans *trans, 1076 const struct iwl_trans_config *trans_cfg); 1077 int iwl_trans_pcie_start_hw(struct iwl_trans *trans); 1078 void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans); 1079 void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val); 1080 void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val); 1081 u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs); 1082 u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg); 1083 void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val); 1084 int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 1085 void *buf, int dwords); 1086 int iwl_trans_pcie_write_mem(struct iwl_trans *trans, u32 addr, 1087 const void *buf, int dwords); 1088 int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership); 1089 struct iwl_trans_dump_data * 1090 iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, 1091 const struct iwl_dump_sanitize_ops *sanitize_ops, 1092 void *sanitize_ctx); 1093 int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1094 enum iwl_d3_status *status, 1095 bool test, bool reset); 1096 int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool test, bool reset); 1097 void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable); 1098 void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans); 1099 void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 1100 u32 mask, u32 value); 1101 int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 1102 u32 *val); 1103 bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans); 1104 void iwl_trans_pcie_release_nic_access(struct iwl_trans *trans); 1105 1106 /* transport gen 1 exported functions */ 1107 void iwl_trans_pcie_fw_alive(struct iwl_trans *trans, u32 scd_addr); 1108 int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1109 const struct fw_img *fw, bool run_in_rfkill); 1110 void iwl_trans_pcie_stop_device(struct iwl_trans *trans); 1111 1112 /* common functions that are used by gen2 transport */ 1113 int iwl_pcie_gen2_apm_init(struct iwl_trans *trans); 1114 void iwl_pcie_apm_config(struct iwl_trans *trans); 1115 int iwl_pcie_prepare_card_hw(struct iwl_trans *trans); 1116 void iwl_pcie_synchronize_irqs(struct iwl_trans *trans); 1117 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans); 1118 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1119 bool was_in_rfkill); 1120 void iwl_pcie_apm_stop_master(struct iwl_trans *trans); 1121 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie); 1122 int iwl_pcie_alloc_dma_ptr(struct iwl_trans *trans, 1123 struct iwl_dma_ptr *ptr, size_t size); 1124 void iwl_pcie_free_dma_ptr(struct iwl_trans *trans, struct iwl_dma_ptr *ptr); 1125 void iwl_pcie_apply_destination(struct iwl_trans *trans); 1126 1127 /* common functions that are used by gen3 transport */ 1128 void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power); 1129 1130 /* transport gen 2 exported functions */ 1131 int iwl_trans_pcie_gen2_start_fw(struct iwl_trans *trans, 1132 const struct fw_img *fw, bool run_in_rfkill); 1133 void iwl_trans_pcie_gen2_fw_alive(struct iwl_trans *trans); 1134 int iwl_trans_pcie_gen2_send_hcmd(struct iwl_trans *trans, 1135 struct iwl_host_cmd *cmd); 1136 void iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 1137 void _iwl_trans_pcie_gen2_stop_device(struct iwl_trans *trans); 1138 void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1139 bool test, bool reset); 1140 int iwl_pcie_gen2_enqueue_hcmd(struct iwl_trans *trans, 1141 struct iwl_host_cmd *cmd); 1142 int iwl_pcie_enqueue_hcmd(struct iwl_trans *trans, 1143 struct iwl_host_cmd *cmd); 1144 void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 1145 u32 dst_addr, u64 src_addr, u32 byte_cnt); 1146 int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 1147 u32 dst_addr, u64 src_addr, u32 byte_cnt); 1148 int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 1149 struct iwl_trans_rxq_dma_data *data); 1150 1151 #endif /* __iwl_trans_int_pcie_h__ */ 1152