1 /* 2 * Copyright 2019 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 24 #ifndef __AMDGPU_MES_H__ 25 #define __AMDGPU_MES_H__ 26 27 #include "amdgpu_irq.h" 28 #include "kgd_kfd_interface.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_doorbell.h" 31 #include <linux/sched/mm.h> 32 33 #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 34 #define AMDGPU_MES_MAX_GFX_PIPES 2 35 #define AMDGPU_MES_MAX_SDMA_PIPES 2 36 37 #define AMDGPU_MES_API_VERSION_SHIFT 12 38 #define AMDGPU_MES_FEAT_VERSION_SHIFT 24 39 40 #define AMDGPU_MES_VERSION_MASK 0x00000fff 41 #define AMDGPU_MES_API_VERSION_MASK 0x00fff000 42 #define AMDGPU_MES_FEAT_VERSION_MASK 0xff000000 43 44 enum amdgpu_mes_priority_level { 45 AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 46 AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 47 AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 48 AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 49 AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 50 AMDGPU_MES_PRIORITY_NUM_LEVELS 51 }; 52 53 #define AMDGPU_MES_PROC_CTX_SIZE 0x1000 /* one page area */ 54 #define AMDGPU_MES_GANG_CTX_SIZE 0x1000 /* one page area */ 55 56 struct amdgpu_mes_funcs; 57 58 enum admgpu_mes_pipe { 59 AMDGPU_MES_SCHED_PIPE = 0, 60 AMDGPU_MES_KIQ_PIPE, 61 AMDGPU_MAX_MES_PIPES = 2, 62 }; 63 64 struct amdgpu_mes { 65 struct amdgpu_device *adev; 66 67 struct mutex mutex_hidden; 68 69 struct idr pasid_idr; 70 struct idr gang_id_idr; 71 struct idr queue_id_idr; 72 struct ida doorbell_ida; 73 74 spinlock_t queue_id_lock; 75 76 uint32_t sched_version; 77 uint32_t kiq_version; 78 bool enable_legacy_queue_map; 79 80 uint32_t total_max_queue; 81 uint32_t max_doorbell_slices; 82 83 uint64_t default_process_quantum; 84 uint64_t default_gang_quantum; 85 86 struct amdgpu_ring ring[AMDGPU_MAX_MES_PIPES]; 87 spinlock_t ring_lock[AMDGPU_MAX_MES_PIPES]; 88 89 const struct firmware *fw[AMDGPU_MAX_MES_PIPES]; 90 91 /* mes ucode */ 92 struct amdgpu_bo *ucode_fw_obj[AMDGPU_MAX_MES_PIPES]; 93 uint64_t ucode_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 94 uint32_t *ucode_fw_ptr[AMDGPU_MAX_MES_PIPES]; 95 uint64_t uc_start_addr[AMDGPU_MAX_MES_PIPES]; 96 97 /* mes ucode data */ 98 struct amdgpu_bo *data_fw_obj[AMDGPU_MAX_MES_PIPES]; 99 uint64_t data_fw_gpu_addr[AMDGPU_MAX_MES_PIPES]; 100 uint32_t *data_fw_ptr[AMDGPU_MAX_MES_PIPES]; 101 uint64_t data_start_addr[AMDGPU_MAX_MES_PIPES]; 102 103 /* eop gpu obj */ 104 struct amdgpu_bo *eop_gpu_obj[AMDGPU_MAX_MES_PIPES]; 105 uint64_t eop_gpu_addr[AMDGPU_MAX_MES_PIPES]; 106 107 void *mqd_backup[AMDGPU_MAX_MES_PIPES]; 108 struct amdgpu_irq_src irq[AMDGPU_MAX_MES_PIPES]; 109 110 uint32_t vmid_mask_gfxhub; 111 uint32_t vmid_mask_mmhub; 112 uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 113 uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 114 uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 115 uint32_t aggregated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 116 uint32_t sch_ctx_offs[AMDGPU_MAX_MES_PIPES]; 117 uint64_t sch_ctx_gpu_addr[AMDGPU_MAX_MES_PIPES]; 118 uint64_t *sch_ctx_ptr[AMDGPU_MAX_MES_PIPES]; 119 uint32_t query_status_fence_offs[AMDGPU_MAX_MES_PIPES]; 120 uint64_t query_status_fence_gpu_addr[AMDGPU_MAX_MES_PIPES]; 121 uint64_t *query_status_fence_ptr[AMDGPU_MAX_MES_PIPES]; 122 uint32_t read_val_offs; 123 uint64_t read_val_gpu_addr; 124 uint32_t *read_val_ptr; 125 126 uint32_t saved_flags; 127 128 /* initialize kiq pipe */ 129 int (*kiq_hw_init)(struct amdgpu_device *adev); 130 int (*kiq_hw_fini)(struct amdgpu_device *adev); 131 132 /* MES doorbells */ 133 uint32_t db_start_dw_offset; 134 uint32_t num_mes_dbs; 135 unsigned long *doorbell_bitmap; 136 137 /* MES event log buffer */ 138 uint32_t event_log_size; 139 struct amdgpu_bo *event_log_gpu_obj; 140 uint64_t event_log_gpu_addr; 141 void *event_log_cpu_addr; 142 143 /* ip specific functions */ 144 const struct amdgpu_mes_funcs *funcs; 145 146 /* mes resource_1 bo*/ 147 struct amdgpu_bo *resource_1; 148 uint64_t resource_1_gpu_addr; 149 void *resource_1_addr; 150 151 }; 152 153 struct amdgpu_mes_process { 154 int pasid; 155 struct amdgpu_vm *vm; 156 uint64_t pd_gpu_addr; 157 struct amdgpu_bo *proc_ctx_bo; 158 uint64_t proc_ctx_gpu_addr; 159 void *proc_ctx_cpu_ptr; 160 uint64_t process_quantum; 161 struct list_head gang_list; 162 uint32_t doorbell_index; 163 struct mutex doorbell_lock; 164 }; 165 166 struct amdgpu_mes_gang { 167 int gang_id; 168 int priority; 169 int inprocess_gang_priority; 170 int global_priority_level; 171 struct list_head list; 172 struct amdgpu_mes_process *process; 173 struct amdgpu_bo *gang_ctx_bo; 174 uint64_t gang_ctx_gpu_addr; 175 void *gang_ctx_cpu_ptr; 176 uint64_t gang_quantum; 177 struct list_head queue_list; 178 }; 179 180 struct amdgpu_mes_queue { 181 struct list_head list; 182 struct amdgpu_mes_gang *gang; 183 int queue_id; 184 uint64_t doorbell_off; 185 struct amdgpu_bo *mqd_obj; 186 void *mqd_cpu_ptr; 187 uint64_t mqd_gpu_addr; 188 uint64_t wptr_gpu_addr; 189 int queue_type; 190 int paging; 191 struct amdgpu_ring *ring; 192 }; 193 194 struct amdgpu_mes_queue_properties { 195 int queue_type; 196 uint64_t hqd_base_gpu_addr; 197 uint64_t rptr_gpu_addr; 198 uint64_t wptr_gpu_addr; 199 uint64_t wptr_mc_addr; 200 uint32_t queue_size; 201 uint64_t eop_gpu_addr; 202 uint32_t hqd_pipe_priority; 203 uint32_t hqd_queue_priority; 204 bool paging; 205 struct amdgpu_ring *ring; 206 /* out */ 207 uint64_t doorbell_off; 208 }; 209 210 struct amdgpu_mes_gang_properties { 211 uint32_t priority; 212 uint32_t gang_quantum; 213 uint32_t inprocess_gang_priority; 214 uint32_t priority_level; 215 int global_priority_level; 216 }; 217 218 struct mes_add_queue_input { 219 uint32_t process_id; 220 uint64_t page_table_base_addr; 221 uint64_t process_va_start; 222 uint64_t process_va_end; 223 uint64_t process_quantum; 224 uint64_t process_context_addr; 225 uint64_t gang_quantum; 226 uint64_t gang_context_addr; 227 uint32_t inprocess_gang_priority; 228 uint32_t gang_global_priority_level; 229 uint32_t doorbell_offset; 230 uint64_t mqd_addr; 231 uint64_t wptr_addr; 232 uint64_t wptr_mc_addr; 233 uint32_t queue_type; 234 uint32_t paging; 235 uint32_t gws_base; 236 uint32_t gws_size; 237 uint64_t tba_addr; 238 uint64_t tma_addr; 239 uint32_t trap_en; 240 uint32_t skip_process_ctx_clear; 241 uint32_t is_kfd_process; 242 uint32_t is_aql_queue; 243 uint32_t queue_size; 244 uint32_t exclusively_scheduled; 245 }; 246 247 struct mes_remove_queue_input { 248 uint32_t doorbell_offset; 249 uint64_t gang_context_addr; 250 }; 251 252 struct mes_reset_queue_input { 253 uint32_t doorbell_offset; 254 uint64_t gang_context_addr; 255 bool use_mmio; 256 uint32_t queue_type; 257 uint32_t me_id; 258 uint32_t pipe_id; 259 uint32_t queue_id; 260 uint32_t xcc_id; 261 uint32_t vmid; 262 }; 263 264 struct mes_map_legacy_queue_input { 265 uint32_t queue_type; 266 uint32_t doorbell_offset; 267 uint32_t pipe_id; 268 uint32_t queue_id; 269 uint64_t mqd_addr; 270 uint64_t wptr_addr; 271 }; 272 273 struct mes_unmap_legacy_queue_input { 274 enum amdgpu_unmap_queues_action action; 275 uint32_t queue_type; 276 uint32_t doorbell_offset; 277 uint32_t pipe_id; 278 uint32_t queue_id; 279 uint64_t trail_fence_addr; 280 uint64_t trail_fence_data; 281 }; 282 283 struct mes_suspend_gang_input { 284 bool suspend_all_gangs; 285 uint64_t gang_context_addr; 286 uint64_t suspend_fence_addr; 287 uint32_t suspend_fence_value; 288 }; 289 290 struct mes_resume_gang_input { 291 bool resume_all_gangs; 292 uint64_t gang_context_addr; 293 }; 294 295 struct mes_reset_legacy_queue_input { 296 uint32_t queue_type; 297 uint32_t doorbell_offset; 298 bool use_mmio; 299 uint32_t me_id; 300 uint32_t pipe_id; 301 uint32_t queue_id; 302 uint64_t mqd_addr; 303 uint64_t wptr_addr; 304 uint32_t vmid; 305 }; 306 307 enum mes_misc_opcode { 308 MES_MISC_OP_WRITE_REG, 309 MES_MISC_OP_READ_REG, 310 MES_MISC_OP_WRM_REG_WAIT, 311 MES_MISC_OP_WRM_REG_WR_WAIT, 312 MES_MISC_OP_SET_SHADER_DEBUGGER, 313 }; 314 315 struct mes_misc_op_input { 316 enum mes_misc_opcode op; 317 318 union { 319 struct { 320 uint32_t reg_offset; 321 uint64_t buffer_addr; 322 } read_reg; 323 324 struct { 325 uint32_t reg_offset; 326 uint32_t reg_value; 327 } write_reg; 328 329 struct { 330 uint32_t ref; 331 uint32_t mask; 332 uint32_t reg0; 333 uint32_t reg1; 334 } wrm_reg; 335 336 struct { 337 uint64_t process_context_addr; 338 union { 339 struct { 340 uint32_t single_memop : 1; 341 uint32_t single_alu_op : 1; 342 uint32_t reserved: 29; 343 uint32_t process_ctx_flush: 1; 344 }; 345 uint32_t u32all; 346 } flags; 347 uint32_t spi_gdbg_per_vmid_cntl; 348 uint32_t tcp_watch_cntl[4]; 349 uint32_t trap_en; 350 } set_shader_debugger; 351 }; 352 }; 353 354 struct amdgpu_mes_funcs { 355 int (*add_hw_queue)(struct amdgpu_mes *mes, 356 struct mes_add_queue_input *input); 357 358 int (*remove_hw_queue)(struct amdgpu_mes *mes, 359 struct mes_remove_queue_input *input); 360 361 int (*map_legacy_queue)(struct amdgpu_mes *mes, 362 struct mes_map_legacy_queue_input *input); 363 364 int (*unmap_legacy_queue)(struct amdgpu_mes *mes, 365 struct mes_unmap_legacy_queue_input *input); 366 367 int (*suspend_gang)(struct amdgpu_mes *mes, 368 struct mes_suspend_gang_input *input); 369 370 int (*resume_gang)(struct amdgpu_mes *mes, 371 struct mes_resume_gang_input *input); 372 373 int (*misc_op)(struct amdgpu_mes *mes, 374 struct mes_misc_op_input *input); 375 376 int (*reset_legacy_queue)(struct amdgpu_mes *mes, 377 struct mes_reset_legacy_queue_input *input); 378 379 int (*reset_hw_queue)(struct amdgpu_mes *mes, 380 struct mes_reset_queue_input *input); 381 }; 382 383 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev)) 384 #define amdgpu_mes_kiq_hw_fini(adev) (adev)->mes.kiq_hw_fini((adev)) 385 386 int amdgpu_mes_ctx_get_offs(struct amdgpu_ring *ring, unsigned int id_offs); 387 388 int amdgpu_mes_init_microcode(struct amdgpu_device *adev, int pipe); 389 int amdgpu_mes_init(struct amdgpu_device *adev); 390 void amdgpu_mes_fini(struct amdgpu_device *adev); 391 392 int amdgpu_mes_create_process(struct amdgpu_device *adev, int pasid, 393 struct amdgpu_vm *vm); 394 void amdgpu_mes_destroy_process(struct amdgpu_device *adev, int pasid); 395 396 int amdgpu_mes_add_gang(struct amdgpu_device *adev, int pasid, 397 struct amdgpu_mes_gang_properties *gprops, 398 int *gang_id); 399 int amdgpu_mes_remove_gang(struct amdgpu_device *adev, int gang_id); 400 401 int amdgpu_mes_suspend(struct amdgpu_device *adev); 402 int amdgpu_mes_resume(struct amdgpu_device *adev); 403 404 int amdgpu_mes_add_hw_queue(struct amdgpu_device *adev, int gang_id, 405 struct amdgpu_mes_queue_properties *qprops, 406 int *queue_id); 407 int amdgpu_mes_remove_hw_queue(struct amdgpu_device *adev, int queue_id); 408 int amdgpu_mes_reset_hw_queue(struct amdgpu_device *adev, int queue_id); 409 int amdgpu_mes_reset_hw_queue_mmio(struct amdgpu_device *adev, int queue_type, 410 int me_id, int pipe_id, int queue_id, int vmid); 411 412 int amdgpu_mes_map_legacy_queue(struct amdgpu_device *adev, 413 struct amdgpu_ring *ring); 414 int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev, 415 struct amdgpu_ring *ring, 416 enum amdgpu_unmap_queues_action action, 417 u64 gpu_addr, u64 seq); 418 int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev, 419 struct amdgpu_ring *ring, 420 unsigned int vmid, 421 bool use_mmio); 422 423 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg); 424 int amdgpu_mes_wreg(struct amdgpu_device *adev, 425 uint32_t reg, uint32_t val); 426 int amdgpu_mes_reg_wait(struct amdgpu_device *adev, uint32_t reg, 427 uint32_t val, uint32_t mask); 428 int amdgpu_mes_reg_write_reg_wait(struct amdgpu_device *adev, 429 uint32_t reg0, uint32_t reg1, 430 uint32_t ref, uint32_t mask); 431 int amdgpu_mes_set_shader_debugger(struct amdgpu_device *adev, 432 uint64_t process_context_addr, 433 uint32_t spi_gdbg_per_vmid_cntl, 434 const uint32_t *tcp_watch_cntl, 435 uint32_t flags, 436 bool trap_en); 437 int amdgpu_mes_flush_shader_debugger(struct amdgpu_device *adev, 438 uint64_t process_context_addr); 439 int amdgpu_mes_add_ring(struct amdgpu_device *adev, int gang_id, 440 int queue_type, int idx, 441 struct amdgpu_mes_ctx_data *ctx_data, 442 struct amdgpu_ring **out); 443 void amdgpu_mes_remove_ring(struct amdgpu_device *adev, 444 struct amdgpu_ring *ring); 445 446 uint32_t amdgpu_mes_get_aggregated_doorbell_index(struct amdgpu_device *adev, 447 enum amdgpu_mes_priority_level prio); 448 449 int amdgpu_mes_ctx_alloc_meta_data(struct amdgpu_device *adev, 450 struct amdgpu_mes_ctx_data *ctx_data); 451 void amdgpu_mes_ctx_free_meta_data(struct amdgpu_mes_ctx_data *ctx_data); 452 int amdgpu_mes_ctx_map_meta_data(struct amdgpu_device *adev, 453 struct amdgpu_vm *vm, 454 struct amdgpu_mes_ctx_data *ctx_data); 455 int amdgpu_mes_ctx_unmap_meta_data(struct amdgpu_device *adev, 456 struct amdgpu_mes_ctx_data *ctx_data); 457 458 int amdgpu_mes_self_test(struct amdgpu_device *adev); 459 460 int amdgpu_mes_doorbell_process_slice(struct amdgpu_device *adev); 461 462 /* 463 * MES lock can be taken in MMU notifiers. 464 * 465 * A bit more detail about why to set no-FS reclaim with MES lock: 466 * 467 * The purpose of the MMU notifier is to stop GPU access to memory so 468 * that the Linux VM subsystem can move pages around safely. This is 469 * done by preempting user mode queues for the affected process. When 470 * MES is used, MES lock needs to be taken to preempt the queues. 471 * 472 * The MMU notifier callback entry point in the driver is 473 * amdgpu_mn_invalidate_range_start_hsa. The relevant call chain from 474 * there is: 475 * amdgpu_amdkfd_evict_userptr -> kgd2kfd_quiesce_mm -> 476 * kfd_process_evict_queues -> pdd->dev->dqm->ops.evict_process_queues 477 * 478 * The last part of the chain is a function pointer where we take the 479 * MES lock. 480 * 481 * The problem with taking locks in the MMU notifier is, that MMU 482 * notifiers can be called in reclaim-FS context. That's where the 483 * kernel frees up pages to make room for new page allocations under 484 * memory pressure. While we are running in reclaim-FS context, we must 485 * not trigger another memory reclaim operation because that would 486 * recursively reenter the reclaim code and cause a deadlock. The 487 * memalloc_nofs_save/restore calls guarantee that. 488 * 489 * In addition we also need to avoid lock dependencies on other locks taken 490 * under the MES lock, for example reservation locks. Here is a possible 491 * scenario of a deadlock: 492 * Thread A: takes and holds reservation lock | triggers reclaim-FS | 493 * MMU notifier | blocks trying to take MES lock 494 * Thread B: takes and holds MES lock | blocks trying to take reservation lock 495 * 496 * In this scenario Thread B gets involved in a deadlock even without 497 * triggering a reclaim-FS operation itself. 498 * To fix this and break the lock dependency chain you'd need to either: 499 * 1. protect reservation locks with memalloc_nofs_save/restore, or 500 * 2. avoid taking reservation locks under the MES lock. 501 * 502 * Reservation locks are taken all over the kernel in different subsystems, we 503 * have no control over them and their lock dependencies.So the only workable 504 * solution is to avoid taking other locks under the MES lock. 505 * As a result, make sure no reclaim-FS happens while holding this lock anywhere 506 * to prevent deadlocks when an MMU notifier runs in reclaim-FS context. 507 */ amdgpu_mes_lock(struct amdgpu_mes * mes)508 static inline void amdgpu_mes_lock(struct amdgpu_mes *mes) 509 { 510 mutex_lock(&mes->mutex_hidden); 511 mes->saved_flags = memalloc_noreclaim_save(); 512 } 513 amdgpu_mes_unlock(struct amdgpu_mes * mes)514 static inline void amdgpu_mes_unlock(struct amdgpu_mes *mes) 515 { 516 memalloc_noreclaim_restore(mes->saved_flags); 517 mutex_unlock(&mes->mutex_hidden); 518 } 519 520 bool amdgpu_mes_suspend_resume_all_supported(struct amdgpu_device *adev); 521 #endif /* __AMDGPU_MES_H__ */ 522