1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3  *  cx18 System Control Block initialization
4  *
5  *  Copyright (C) 2007  Hans Verkuil <hverkuil@xs4all.nl>
6  *  Copyright (C) 2008  Andy Walls <awalls@md.metrocast.net>
7  */
8 
9 #ifndef CX18_SCB_H
10 #define CX18_SCB_H
11 
12 #include "cx18-mailbox.h"
13 
14 /* NOTE: All ACK interrupts are in the SW2 register.  All non-ACK interrupts
15    are in the SW1 register. */
16 
17 #define IRQ_APU_TO_CPU         0x00000001
18 #define IRQ_CPU_TO_APU_ACK     0x00000001
19 #define IRQ_HPU_TO_CPU         0x00000002
20 #define IRQ_CPU_TO_HPU_ACK     0x00000002
21 #define IRQ_PPU_TO_CPU         0x00000004
22 #define IRQ_CPU_TO_PPU_ACK     0x00000004
23 #define IRQ_EPU_TO_CPU         0x00000008
24 #define IRQ_CPU_TO_EPU_ACK     0x00000008
25 
26 #define IRQ_CPU_TO_APU         0x00000010
27 #define IRQ_APU_TO_CPU_ACK     0x00000010
28 #define IRQ_HPU_TO_APU         0x00000020
29 #define IRQ_APU_TO_HPU_ACK     0x00000020
30 #define IRQ_PPU_TO_APU         0x00000040
31 #define IRQ_APU_TO_PPU_ACK     0x00000040
32 #define IRQ_EPU_TO_APU         0x00000080
33 #define IRQ_APU_TO_EPU_ACK     0x00000080
34 
35 #define IRQ_CPU_TO_HPU         0x00000100
36 #define IRQ_HPU_TO_CPU_ACK     0x00000100
37 #define IRQ_APU_TO_HPU         0x00000200
38 #define IRQ_HPU_TO_APU_ACK     0x00000200
39 #define IRQ_PPU_TO_HPU         0x00000400
40 #define IRQ_HPU_TO_PPU_ACK     0x00000400
41 #define IRQ_EPU_TO_HPU         0x00000800
42 #define IRQ_HPU_TO_EPU_ACK     0x00000800
43 
44 #define IRQ_CPU_TO_PPU         0x00001000
45 #define IRQ_PPU_TO_CPU_ACK     0x00001000
46 #define IRQ_APU_TO_PPU         0x00002000
47 #define IRQ_PPU_TO_APU_ACK     0x00002000
48 #define IRQ_HPU_TO_PPU         0x00004000
49 #define IRQ_PPU_TO_HPU_ACK     0x00004000
50 #define IRQ_EPU_TO_PPU         0x00008000
51 #define IRQ_PPU_TO_EPU_ACK     0x00008000
52 
53 #define IRQ_CPU_TO_EPU         0x00010000
54 #define IRQ_EPU_TO_CPU_ACK     0x00010000
55 #define IRQ_APU_TO_EPU         0x00020000
56 #define IRQ_EPU_TO_APU_ACK     0x00020000
57 #define IRQ_HPU_TO_EPU         0x00040000
58 #define IRQ_EPU_TO_HPU_ACK     0x00040000
59 #define IRQ_PPU_TO_EPU         0x00080000
60 #define IRQ_EPU_TO_PPU_ACK     0x00080000
61 
62 #define SCB_OFFSET  0xDC0000
63 
64 /* If Firmware uses fixed memory map, it shall not allocate the area
65    between SCB_OFFSET and SCB_OFFSET+SCB_RESERVED_SIZE-1 inclusive */
66 #define SCB_RESERVED_SIZE 0x10000
67 
68 
69 /* This structure is used by EPU to provide memory descriptors in its memory */
70 struct cx18_mdl_ent {
71     u32 paddr;  /* Physical address of a buffer segment */
72     u32 length; /* Length of the buffer segment */
73 };
74 
75 struct cx18_scb {
76 	/* These fields form the System Control Block which is used at boot time
77 	   for localizing the IPC data as well as the code positions for all
78 	   processors. The offsets are from the start of this struct. */
79 
80 	/* Offset where to find the Inter-Processor Communication data */
81 	u32 ipc_offset;
82 	u32 reserved01[7];
83 	/* Offset where to find the start of the CPU code */
84 	u32 cpu_code_offset;
85 	u32 reserved02[3];
86 	/* Offset where to find the start of the APU code */
87 	u32 apu_code_offset;
88 	u32 reserved03[3];
89 	/* Offset where to find the start of the HPU code */
90 	u32 hpu_code_offset;
91 	u32 reserved04[3];
92 	/* Offset where to find the start of the PPU code */
93 	u32 ppu_code_offset;
94 	u32 reserved05[3];
95 
96 	/* These fields form Inter-Processor Communication data which is used
97 	   by all processors to locate the information needed for communicating
98 	   with other processors */
99 
100 	/* Fields for CPU: */
101 
102 	/* bit 0: 1/0 processor ready/not ready. Set other bits to 0. */
103 	u32 cpu_state;
104 	u32 reserved1[7];
105 	/* Offset to the mailbox used for sending commands from APU to CPU */
106 	u32 apu2cpu_mb_offset;
107 	/* Value to write to register SW1 register set (0xC7003100) after the
108 	   command is ready */
109 	u32 apu2cpu_irq;
110 	/* Value to write to register SW2 register set (0xC7003140) after the
111 	   command is cleared */
112 	u32 cpu2apu_irq_ack;
113 	u32 reserved2[13];
114 
115 	u32 hpu2cpu_mb_offset;
116 	u32 hpu2cpu_irq;
117 	u32 cpu2hpu_irq_ack;
118 	u32 reserved3[13];
119 
120 	u32 ppu2cpu_mb_offset;
121 	u32 ppu2cpu_irq;
122 	u32 cpu2ppu_irq_ack;
123 	u32 reserved4[13];
124 
125 	u32 epu2cpu_mb_offset;
126 	u32 epu2cpu_irq;
127 	u32 cpu2epu_irq_ack;
128 	u32 reserved5[13];
129 	u32 reserved6[8];
130 
131 	/* Fields for APU: */
132 
133 	u32 apu_state;
134 	u32 reserved11[7];
135 	u32 cpu2apu_mb_offset;
136 	u32 cpu2apu_irq;
137 	u32 apu2cpu_irq_ack;
138 	u32 reserved12[13];
139 
140 	u32 hpu2apu_mb_offset;
141 	u32 hpu2apu_irq;
142 	u32 apu2hpu_irq_ack;
143 	u32 reserved13[13];
144 
145 	u32 ppu2apu_mb_offset;
146 	u32 ppu2apu_irq;
147 	u32 apu2ppu_irq_ack;
148 	u32 reserved14[13];
149 
150 	u32 epu2apu_mb_offset;
151 	u32 epu2apu_irq;
152 	u32 apu2epu_irq_ack;
153 	u32 reserved15[13];
154 	u32 reserved16[8];
155 
156 	/* Fields for HPU: */
157 
158 	u32 hpu_state;
159 	u32 reserved21[7];
160 	u32 cpu2hpu_mb_offset;
161 	u32 cpu2hpu_irq;
162 	u32 hpu2cpu_irq_ack;
163 	u32 reserved22[13];
164 
165 	u32 apu2hpu_mb_offset;
166 	u32 apu2hpu_irq;
167 	u32 hpu2apu_irq_ack;
168 	u32 reserved23[13];
169 
170 	u32 ppu2hpu_mb_offset;
171 	u32 ppu2hpu_irq;
172 	u32 hpu2ppu_irq_ack;
173 	u32 reserved24[13];
174 
175 	u32 epu2hpu_mb_offset;
176 	u32 epu2hpu_irq;
177 	u32 hpu2epu_irq_ack;
178 	u32 reserved25[13];
179 	u32 reserved26[8];
180 
181 	/* Fields for PPU: */
182 
183 	u32 ppu_state;
184 	u32 reserved31[7];
185 	u32 cpu2ppu_mb_offset;
186 	u32 cpu2ppu_irq;
187 	u32 ppu2cpu_irq_ack;
188 	u32 reserved32[13];
189 
190 	u32 apu2ppu_mb_offset;
191 	u32 apu2ppu_irq;
192 	u32 ppu2apu_irq_ack;
193 	u32 reserved33[13];
194 
195 	u32 hpu2ppu_mb_offset;
196 	u32 hpu2ppu_irq;
197 	u32 ppu2hpu_irq_ack;
198 	u32 reserved34[13];
199 
200 	u32 epu2ppu_mb_offset;
201 	u32 epu2ppu_irq;
202 	u32 ppu2epu_irq_ack;
203 	u32 reserved35[13];
204 	u32 reserved36[8];
205 
206 	/* Fields for EPU: */
207 
208 	u32 epu_state;
209 	u32 reserved41[7];
210 	u32 cpu2epu_mb_offset;
211 	u32 cpu2epu_irq;
212 	u32 epu2cpu_irq_ack;
213 	u32 reserved42[13];
214 
215 	u32 apu2epu_mb_offset;
216 	u32 apu2epu_irq;
217 	u32 epu2apu_irq_ack;
218 	u32 reserved43[13];
219 
220 	u32 hpu2epu_mb_offset;
221 	u32 hpu2epu_irq;
222 	u32 epu2hpu_irq_ack;
223 	u32 reserved44[13];
224 
225 	u32 ppu2epu_mb_offset;
226 	u32 ppu2epu_irq;
227 	u32 epu2ppu_irq_ack;
228 	u32 reserved45[13];
229 	u32 reserved46[8];
230 
231 	u32 semaphores[8];  /* Semaphores */
232 
233 	u32 reserved50[32]; /* Reserved for future use */
234 
235 	struct cx18_mailbox  apu2cpu_mb;
236 	struct cx18_mailbox  hpu2cpu_mb;
237 	struct cx18_mailbox  ppu2cpu_mb;
238 	struct cx18_mailbox  epu2cpu_mb;
239 
240 	struct cx18_mailbox  cpu2apu_mb;
241 	struct cx18_mailbox  hpu2apu_mb;
242 	struct cx18_mailbox  ppu2apu_mb;
243 	struct cx18_mailbox  epu2apu_mb;
244 
245 	struct cx18_mailbox  cpu2hpu_mb;
246 	struct cx18_mailbox  apu2hpu_mb;
247 	struct cx18_mailbox  ppu2hpu_mb;
248 	struct cx18_mailbox  epu2hpu_mb;
249 
250 	struct cx18_mailbox  cpu2ppu_mb;
251 	struct cx18_mailbox  apu2ppu_mb;
252 	struct cx18_mailbox  hpu2ppu_mb;
253 	struct cx18_mailbox  epu2ppu_mb;
254 
255 	struct cx18_mailbox  cpu2epu_mb;
256 	struct cx18_mailbox  apu2epu_mb;
257 	struct cx18_mailbox  hpu2epu_mb;
258 	struct cx18_mailbox  ppu2epu_mb;
259 
260 	struct cx18_mdl_ack  cpu_mdl_ack[CX18_MAX_STREAMS][CX18_MAX_MDL_ACKS];
261 	struct cx18_mdl_ent  cpu_mdl[];
262 };
263 
264 void cx18_init_scb(struct cx18 *cx);
265 
266 #endif
267