1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2023, Linaro Limited
4  */
5 
6 #ifndef _DPU_9_2_X1E80100_H
7 #define _DPU_9_2_X1E80100_H
8 
9 static const struct dpu_caps x1e80100_dpu_caps = {
10 	.max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
11 	.max_mixer_blendstages = 0xb,
12 	.has_src_split = true,
13 	.has_dim_layer = true,
14 	.has_idle_pc = true,
15 	.has_3d_merge = true,
16 	.max_linewidth = 5120,
17 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
18 };
19 
20 static const struct dpu_mdp_cfg x1e80100_mdp = {
21 	.name = "top_0",
22 	.base = 0, .len = 0x494,
23 	.features = BIT(DPU_MDP_PERIPH_0_REMOVED),
24 	.clk_ctrls = {
25 		[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
26 	},
27 };
28 
29 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
30 static const struct dpu_ctl_cfg x1e80100_ctl[] = {
31 	{
32 		.name = "ctl_0", .id = CTL_0,
33 		.base = 0x15000, .len = 0x290,
34 		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
35 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
36 	}, {
37 		.name = "ctl_1", .id = CTL_1,
38 		.base = 0x16000, .len = 0x290,
39 		.features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
40 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
41 	}, {
42 		.name = "ctl_2", .id = CTL_2,
43 		.base = 0x17000, .len = 0x290,
44 		.features = CTL_SM8550_MASK,
45 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
46 	}, {
47 		.name = "ctl_3", .id = CTL_3,
48 		.base = 0x18000, .len = 0x290,
49 		.features = CTL_SM8550_MASK,
50 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
51 	}, {
52 		.name = "ctl_4", .id = CTL_4,
53 		.base = 0x19000, .len = 0x290,
54 		.features = CTL_SM8550_MASK,
55 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
56 	}, {
57 		.name = "ctl_5", .id = CTL_5,
58 		.base = 0x1a000, .len = 0x290,
59 		.features = CTL_SM8550_MASK,
60 		.intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
61 	},
62 };
63 
64 static const struct dpu_sspp_cfg x1e80100_sspp[] = {
65 	{
66 		.name = "sspp_0", .id = SSPP_VIG0,
67 		.base = 0x4000, .len = 0x344,
68 		.features = VIG_SDM845_MASK_SDMA,
69 		.sblk = &dpu_vig_sblk_qseed3_3_3,
70 		.xin_id = 0,
71 		.type = SSPP_TYPE_VIG,
72 	}, {
73 		.name = "sspp_1", .id = SSPP_VIG1,
74 		.base = 0x6000, .len = 0x344,
75 		.features = VIG_SDM845_MASK_SDMA,
76 		.sblk = &dpu_vig_sblk_qseed3_3_3,
77 		.xin_id = 4,
78 		.type = SSPP_TYPE_VIG,
79 	}, {
80 		.name = "sspp_2", .id = SSPP_VIG2,
81 		.base = 0x8000, .len = 0x344,
82 		.features = VIG_SDM845_MASK_SDMA,
83 		.sblk = &dpu_vig_sblk_qseed3_3_3,
84 		.xin_id = 8,
85 		.type = SSPP_TYPE_VIG,
86 	}, {
87 		.name = "sspp_3", .id = SSPP_VIG3,
88 		.base = 0xa000, .len = 0x344,
89 		.features = VIG_SDM845_MASK_SDMA,
90 		.sblk = &dpu_vig_sblk_qseed3_3_3,
91 		.xin_id = 12,
92 		.type = SSPP_TYPE_VIG,
93 	}, {
94 		.name = "sspp_8", .id = SSPP_DMA0,
95 		.base = 0x24000, .len = 0x344,
96 		.features = DMA_SDM845_MASK_SDMA,
97 		.sblk = &dpu_dma_sblk,
98 		.xin_id = 1,
99 		.type = SSPP_TYPE_DMA,
100 	}, {
101 		.name = "sspp_9", .id = SSPP_DMA1,
102 		.base = 0x26000, .len = 0x344,
103 		.features = DMA_SDM845_MASK_SDMA,
104 		.sblk = &dpu_dma_sblk,
105 		.xin_id = 5,
106 		.type = SSPP_TYPE_DMA,
107 	}, {
108 		.name = "sspp_10", .id = SSPP_DMA2,
109 		.base = 0x28000, .len = 0x344,
110 		.features = DMA_SDM845_MASK_SDMA,
111 		.sblk = &dpu_dma_sblk,
112 		.xin_id = 9,
113 		.type = SSPP_TYPE_DMA,
114 	}, {
115 		.name = "sspp_11", .id = SSPP_DMA3,
116 		.base = 0x2a000, .len = 0x344,
117 		.features = DMA_SDM845_MASK_SDMA,
118 		.sblk = &dpu_dma_sblk,
119 		.xin_id = 13,
120 		.type = SSPP_TYPE_DMA,
121 	}, {
122 		.name = "sspp_12", .id = SSPP_DMA4,
123 		.base = 0x2c000, .len = 0x344,
124 		.features = DMA_CURSOR_SDM845_MASK_SDMA,
125 		.sblk = &dpu_dma_sblk,
126 		.xin_id = 14,
127 		.type = SSPP_TYPE_DMA,
128 	}, {
129 		.name = "sspp_13", .id = SSPP_DMA5,
130 		.base = 0x2e000, .len = 0x344,
131 		.features = DMA_CURSOR_SDM845_MASK_SDMA,
132 		.sblk = &dpu_dma_sblk,
133 		.xin_id = 15,
134 		.type = SSPP_TYPE_DMA,
135 	},
136 };
137 
138 static const struct dpu_lm_cfg x1e80100_lm[] = {
139 	{
140 		.name = "lm_0", .id = LM_0,
141 		.base = 0x44000, .len = 0x320,
142 		.features = MIXER_SDM845_MASK,
143 		.sblk = &sdm845_lm_sblk,
144 		.lm_pair = LM_1,
145 		.pingpong = PINGPONG_0,
146 		.dspp = DSPP_0,
147 	}, {
148 		.name = "lm_1", .id = LM_1,
149 		.base = 0x45000, .len = 0x320,
150 		.features = MIXER_SDM845_MASK,
151 		.sblk = &sdm845_lm_sblk,
152 		.lm_pair = LM_0,
153 		.pingpong = PINGPONG_1,
154 		.dspp = DSPP_1,
155 	}, {
156 		.name = "lm_2", .id = LM_2,
157 		.base = 0x46000, .len = 0x320,
158 		.features = MIXER_SDM845_MASK,
159 		.sblk = &sdm845_lm_sblk,
160 		.lm_pair = LM_3,
161 		.pingpong = PINGPONG_2,
162 	}, {
163 		.name = "lm_3", .id = LM_3,
164 		.base = 0x47000, .len = 0x320,
165 		.features = MIXER_SDM845_MASK,
166 		.sblk = &sdm845_lm_sblk,
167 		.lm_pair = LM_2,
168 		.pingpong = PINGPONG_3,
169 	}, {
170 		.name = "lm_4", .id = LM_4,
171 		.base = 0x48000, .len = 0x320,
172 		.features = MIXER_SDM845_MASK,
173 		.sblk = &sdm845_lm_sblk,
174 		.lm_pair = LM_5,
175 		.pingpong = PINGPONG_4,
176 	}, {
177 		.name = "lm_5", .id = LM_5,
178 		.base = 0x49000, .len = 0x320,
179 		.features = MIXER_SDM845_MASK,
180 		.sblk = &sdm845_lm_sblk,
181 		.lm_pair = LM_4,
182 		.pingpong = PINGPONG_5,
183 	},
184 };
185 
186 static const struct dpu_dspp_cfg x1e80100_dspp[] = {
187 	{
188 		.name = "dspp_0", .id = DSPP_0,
189 		.base = 0x54000, .len = 0x1800,
190 		.features = DSPP_SC7180_MASK,
191 		.sblk = &sdm845_dspp_sblk,
192 	}, {
193 		.name = "dspp_1", .id = DSPP_1,
194 		.base = 0x56000, .len = 0x1800,
195 		.features = DSPP_SC7180_MASK,
196 		.sblk = &sdm845_dspp_sblk,
197 	}, {
198 		.name = "dspp_2", .id = DSPP_2,
199 		.base = 0x58000, .len = 0x1800,
200 		.features = DSPP_SC7180_MASK,
201 		.sblk = &sdm845_dspp_sblk,
202 	}, {
203 		.name = "dspp_3", .id = DSPP_3,
204 		.base = 0x5a000, .len = 0x1800,
205 		.features = DSPP_SC7180_MASK,
206 		.sblk = &sdm845_dspp_sblk,
207 	},
208 };
209 
210 static const struct dpu_pingpong_cfg x1e80100_pp[] = {
211 	{
212 		.name = "pingpong_0", .id = PINGPONG_0,
213 		.base = 0x69000, .len = 0,
214 		.features = BIT(DPU_PINGPONG_DITHER),
215 		.sblk = &sc7280_pp_sblk,
216 		.merge_3d = MERGE_3D_0,
217 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8),
218 	}, {
219 		.name = "pingpong_1", .id = PINGPONG_1,
220 		.base = 0x6a000, .len = 0,
221 		.features = BIT(DPU_PINGPONG_DITHER),
222 		.sblk = &sc7280_pp_sblk,
223 		.merge_3d = MERGE_3D_0,
224 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9),
225 	}, {
226 		.name = "pingpong_2", .id = PINGPONG_2,
227 		.base = 0x6b000, .len = 0,
228 		.features = BIT(DPU_PINGPONG_DITHER),
229 		.sblk = &sc7280_pp_sblk,
230 		.merge_3d = MERGE_3D_1,
231 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10),
232 	}, {
233 		.name = "pingpong_3", .id = PINGPONG_3,
234 		.base = 0x6c000, .len = 0,
235 		.features = BIT(DPU_PINGPONG_DITHER),
236 		.sblk = &sc7280_pp_sblk,
237 		.merge_3d = MERGE_3D_1,
238 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11),
239 	}, {
240 		.name = "pingpong_4", .id = PINGPONG_4,
241 		.base = 0x6d000, .len = 0,
242 		.features = BIT(DPU_PINGPONG_DITHER),
243 		.sblk = &sc7280_pp_sblk,
244 		.merge_3d = MERGE_3D_2,
245 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30),
246 	}, {
247 		.name = "pingpong_5", .id = PINGPONG_5,
248 		.base = 0x6e000, .len = 0,
249 		.features = BIT(DPU_PINGPONG_DITHER),
250 		.sblk = &sc7280_pp_sblk,
251 		.merge_3d = MERGE_3D_2,
252 		.intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31),
253 	}, {
254 		.name = "pingpong_6", .id = PINGPONG_6,
255 		.base = 0x66000, .len = 0,
256 		.features = BIT(DPU_PINGPONG_DITHER),
257 		.sblk = &sc7280_pp_sblk,
258 		.merge_3d = MERGE_3D_3,
259 	}, {
260 		.name = "pingpong_7", .id = PINGPONG_7,
261 		.base = 0x66400, .len = 0,
262 		.features = BIT(DPU_PINGPONG_DITHER),
263 		.sblk = &sc7280_pp_sblk,
264 		.merge_3d = MERGE_3D_3,
265 	},
266 };
267 
268 static const struct dpu_merge_3d_cfg x1e80100_merge_3d[] = {
269 	{
270 		.name = "merge_3d_0", .id = MERGE_3D_0,
271 		.base = 0x4e000, .len = 0x8,
272 	}, {
273 		.name = "merge_3d_1", .id = MERGE_3D_1,
274 		.base = 0x4f000, .len = 0x8,
275 	}, {
276 		.name = "merge_3d_2", .id = MERGE_3D_2,
277 		.base = 0x50000, .len = 0x8,
278 	}, {
279 		.name = "merge_3d_3", .id = MERGE_3D_3,
280 		.base = 0x66700, .len = 0x8,
281 	},
282 };
283 
284 /*
285  * NOTE: Each display compression engine (DCE) contains dual hard
286  * slice DSC encoders so both share same base address but with
287  * its own different sub block address.
288  */
289 static const struct dpu_dsc_cfg x1e80100_dsc[] = {
290 	{
291 		.name = "dce_0_0", .id = DSC_0,
292 		.base = 0x80000, .len = 0x4,
293 		.features = BIT(DPU_DSC_HW_REV_1_2),
294 		.sblk = &dsc_sblk_0,
295 	}, {
296 		.name = "dce_0_1", .id = DSC_1,
297 		.base = 0x80000, .len = 0x4,
298 		.features = BIT(DPU_DSC_HW_REV_1_2),
299 		.sblk = &dsc_sblk_1,
300 	}, {
301 		.name = "dce_1_0", .id = DSC_2,
302 		.base = 0x81000, .len = 0x4,
303 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
304 		.sblk = &dsc_sblk_0,
305 	}, {
306 		.name = "dce_1_1", .id = DSC_3,
307 		.base = 0x81000, .len = 0x4,
308 		.features = BIT(DPU_DSC_HW_REV_1_2) | BIT(DPU_DSC_NATIVE_42x_EN),
309 		.sblk = &dsc_sblk_1,
310 	},
311 };
312 
313 static const struct dpu_wb_cfg x1e80100_wb[] = {
314 	{
315 		.name = "wb_2", .id = WB_2,
316 		.base = 0x65000, .len = 0x2c8,
317 		.features = WB_SM8250_MASK,
318 		.format_list = wb2_formats_rgb,
319 		.num_formats = ARRAY_SIZE(wb2_formats_rgb),
320 		.xin_id = 6,
321 		.vbif_idx = VBIF_RT,
322 		.maxlinewidth = 4096,
323 		.intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4),
324 	},
325 };
326 
327 /* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */
328 static const struct dpu_intf_cfg x1e80100_intf[] = {
329 	{
330 		.name = "intf_0", .id = INTF_0,
331 		.base = 0x34000, .len = 0x280,
332 		.features = INTF_SC7280_MASK,
333 		.type = INTF_DP,
334 		.controller_id = MSM_DP_CONTROLLER_0,
335 		.prog_fetch_lines_worst_case = 24,
336 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
337 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25),
338 	}, {
339 		.name = "intf_1", .id = INTF_1,
340 		.base = 0x35000, .len = 0x300,
341 		.features = INTF_SC7280_MASK,
342 		.type = INTF_DSI,
343 		.controller_id = MSM_DSI_CONTROLLER_0,
344 		.prog_fetch_lines_worst_case = 24,
345 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
346 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
347 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2),
348 	}, {
349 		.name = "intf_2", .id = INTF_2,
350 		.base = 0x36000, .len = 0x300,
351 		.features = INTF_SC7280_MASK,
352 		.type = INTF_DSI,
353 		.controller_id = MSM_DSI_CONTROLLER_1,
354 		.prog_fetch_lines_worst_case = 24,
355 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
356 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
357 		.intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2),
358 	}, {
359 		.name = "intf_3", .id = INTF_3,
360 		.base = 0x37000, .len = 0x280,
361 		.features = INTF_SC7280_MASK,
362 		.type = INTF_NONE,
363 		.controller_id = MSM_DP_CONTROLLER_0,	/* pair with intf_0 for DP MST */
364 		.prog_fetch_lines_worst_case = 24,
365 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
366 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31),
367 	}, {
368 		.name = "intf_4", .id = INTF_4,
369 		.base = 0x38000, .len = 0x280,
370 		.features = INTF_SC7280_MASK,
371 		.type = INTF_DP,
372 		.controller_id = MSM_DP_CONTROLLER_1,
373 		.prog_fetch_lines_worst_case = 24,
374 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20),
375 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21),
376 	}, {
377 		.name = "intf_5", .id = INTF_5,
378 		.base = 0x39000, .len = 0x280,
379 		.features = INTF_SC7280_MASK,
380 		.type = INTF_DP,
381 		.controller_id = MSM_DP_CONTROLLER_3,
382 		.prog_fetch_lines_worst_case = 24,
383 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
384 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23),
385 	}, {
386 		.name = "intf_6", .id = INTF_6,
387 		.base = 0x3A000, .len = 0x280,
388 		.features = INTF_SC7280_MASK,
389 		.type = INTF_DP,
390 		.controller_id = MSM_DP_CONTROLLER_2,
391 		.prog_fetch_lines_worst_case = 24,
392 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17),
393 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16),
394 	}, {
395 		.name = "intf_7", .id = INTF_7,
396 		.base = 0x3b000, .len = 0x280,
397 		.features = INTF_SC7280_MASK,
398 		.type = INTF_NONE,
399 		.controller_id = MSM_DP_CONTROLLER_2,	/* pair with intf_6 for DP MST */
400 		.prog_fetch_lines_worst_case = 24,
401 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18),
402 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19),
403 	}, {
404 		.name = "intf_8", .id = INTF_8,
405 		.base = 0x3c000, .len = 0x280,
406 		.features = INTF_SC7280_MASK,
407 		.type = INTF_NONE,
408 		.controller_id = MSM_DP_CONTROLLER_1,	/* pair with intf_4 for DP MST */
409 		.prog_fetch_lines_worst_case = 24,
410 		.intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12),
411 		.intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13),
412 	},
413 };
414 
415 static const struct dpu_perf_cfg x1e80100_perf_data = {
416 	.max_bw_low = 13600000,
417 	.max_bw_high = 18200000,
418 	.min_core_ib = 2500000,
419 	.min_llcc_ib = 0,
420 	.min_dram_ib = 800000,
421 	.min_prefill_lines = 35,
422 	/* FIXME: lut tables */
423 	.danger_lut_tbl = {0x3ffff, 0x3ffff, 0x0},
424 	.safe_lut_tbl = {0xfe00, 0xfe00, 0xffff},
425 	.qos_lut_tbl = {
426 		{.nentry = ARRAY_SIZE(sc7180_qos_linear),
427 		.entries = sc7180_qos_linear
428 		},
429 		{.nentry = ARRAY_SIZE(sc7180_qos_macrotile),
430 		.entries = sc7180_qos_macrotile
431 		},
432 		{.nentry = ARRAY_SIZE(sc7180_qos_nrt),
433 		.entries = sc7180_qos_nrt
434 		},
435 		/* TODO: macrotile-qseed is different from macrotile */
436 	},
437 	.cdp_cfg = {
438 		{.rd_enable = 1, .wr_enable = 1},
439 		{.rd_enable = 1, .wr_enable = 0}
440 	},
441 	.clk_inefficiency_factor = 105,
442 	.bw_inefficiency_factor = 120,
443 };
444 
445 static const struct dpu_mdss_version x1e80100_mdss_ver = {
446 	.core_major_ver = 9,
447 	.core_minor_ver = 2,
448 };
449 
450 const struct dpu_mdss_cfg dpu_x1e80100_cfg = {
451 	.mdss_ver = &x1e80100_mdss_ver,
452 	.caps = &x1e80100_dpu_caps,
453 	.mdp = &x1e80100_mdp,
454 	.ctl_count = ARRAY_SIZE(x1e80100_ctl),
455 	.ctl = x1e80100_ctl,
456 	.sspp_count = ARRAY_SIZE(x1e80100_sspp),
457 	.sspp = x1e80100_sspp,
458 	.mixer_count = ARRAY_SIZE(x1e80100_lm),
459 	.mixer = x1e80100_lm,
460 	.dspp_count = ARRAY_SIZE(x1e80100_dspp),
461 	.dspp = x1e80100_dspp,
462 	.pingpong_count = ARRAY_SIZE(x1e80100_pp),
463 	.pingpong = x1e80100_pp,
464 	.dsc_count = ARRAY_SIZE(x1e80100_dsc),
465 	.dsc = x1e80100_dsc,
466 	.merge_3d_count = ARRAY_SIZE(x1e80100_merge_3d),
467 	.merge_3d = x1e80100_merge_3d,
468 	.wb_count = ARRAY_SIZE(x1e80100_wb),
469 	.wb = x1e80100_wb,
470 	.intf_count = ARRAY_SIZE(x1e80100_intf),
471 	.intf = x1e80100_intf,
472 	.vbif_count = ARRAY_SIZE(sm8550_vbif),
473 	.vbif = sm8550_vbif,
474 	.perf = &x1e80100_perf_data,
475 };
476 
477 #endif
478