1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_5_0_SM8150_H 8 #define _DPU_5_0_SM8150_H 9 10 static const struct dpu_caps sm8150_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = 4096, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sm8150_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .features = BIT(DPU_MDP_AUDIO_SELECT), 27 .clk_ctrls = { 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 37 }, 38 }; 39 40 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */ 41 static const struct dpu_ctl_cfg sm8150_ctl[] = { 42 { 43 .name = "ctl_0", .id = CTL_0, 44 .base = 0x1000, .len = 0x1e0, 45 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 47 }, { 48 .name = "ctl_1", .id = CTL_1, 49 .base = 0x1200, .len = 0x1e0, 50 .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY), 51 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 52 }, { 53 .name = "ctl_2", .id = CTL_2, 54 .base = 0x1400, .len = 0x1e0, 55 .features = BIT(DPU_CTL_ACTIVE_CFG), 56 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 57 }, { 58 .name = "ctl_3", .id = CTL_3, 59 .base = 0x1600, .len = 0x1e0, 60 .features = BIT(DPU_CTL_ACTIVE_CFG), 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 62 }, { 63 .name = "ctl_4", .id = CTL_4, 64 .base = 0x1800, .len = 0x1e0, 65 .features = BIT(DPU_CTL_ACTIVE_CFG), 66 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 67 }, { 68 .name = "ctl_5", .id = CTL_5, 69 .base = 0x1a00, .len = 0x1e0, 70 .features = BIT(DPU_CTL_ACTIVE_CFG), 71 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 72 }, 73 }; 74 75 static const struct dpu_sspp_cfg sm8150_sspp[] = { 76 { 77 .name = "sspp_0", .id = SSPP_VIG0, 78 .base = 0x4000, .len = 0x1f0, 79 .features = VIG_SDM845_MASK, 80 .sblk = &dpu_vig_sblk_qseed3_1_4, 81 .xin_id = 0, 82 .type = SSPP_TYPE_VIG, 83 .clk_ctrl = DPU_CLK_CTRL_VIG0, 84 }, { 85 .name = "sspp_1", .id = SSPP_VIG1, 86 .base = 0x6000, .len = 0x1f0, 87 .features = VIG_SDM845_MASK, 88 .sblk = &dpu_vig_sblk_qseed3_1_4, 89 .xin_id = 4, 90 .type = SSPP_TYPE_VIG, 91 .clk_ctrl = DPU_CLK_CTRL_VIG1, 92 }, { 93 .name = "sspp_2", .id = SSPP_VIG2, 94 .base = 0x8000, .len = 0x1f0, 95 .features = VIG_SDM845_MASK, 96 .sblk = &dpu_vig_sblk_qseed3_1_4, 97 .xin_id = 8, 98 .type = SSPP_TYPE_VIG, 99 .clk_ctrl = DPU_CLK_CTRL_VIG2, 100 }, { 101 .name = "sspp_3", .id = SSPP_VIG3, 102 .base = 0xa000, .len = 0x1f0, 103 .features = VIG_SDM845_MASK, 104 .sblk = &dpu_vig_sblk_qseed3_1_4, 105 .xin_id = 12, 106 .type = SSPP_TYPE_VIG, 107 .clk_ctrl = DPU_CLK_CTRL_VIG3, 108 }, { 109 .name = "sspp_8", .id = SSPP_DMA0, 110 .base = 0x24000, .len = 0x1f0, 111 .features = DMA_SDM845_MASK, 112 .sblk = &dpu_dma_sblk, 113 .xin_id = 1, 114 .type = SSPP_TYPE_DMA, 115 .clk_ctrl = DPU_CLK_CTRL_DMA0, 116 }, { 117 .name = "sspp_9", .id = SSPP_DMA1, 118 .base = 0x26000, .len = 0x1f0, 119 .features = DMA_SDM845_MASK, 120 .sblk = &dpu_dma_sblk, 121 .xin_id = 5, 122 .type = SSPP_TYPE_DMA, 123 .clk_ctrl = DPU_CLK_CTRL_DMA1, 124 }, { 125 .name = "sspp_10", .id = SSPP_DMA2, 126 .base = 0x28000, .len = 0x1f0, 127 .features = DMA_CURSOR_SDM845_MASK, 128 .sblk = &dpu_dma_sblk, 129 .xin_id = 9, 130 .type = SSPP_TYPE_DMA, 131 .clk_ctrl = DPU_CLK_CTRL_DMA2, 132 }, { 133 .name = "sspp_11", .id = SSPP_DMA3, 134 .base = 0x2a000, .len = 0x1f0, 135 .features = DMA_CURSOR_SDM845_MASK, 136 .sblk = &dpu_dma_sblk, 137 .xin_id = 13, 138 .type = SSPP_TYPE_DMA, 139 .clk_ctrl = DPU_CLK_CTRL_DMA3, 140 }, 141 }; 142 143 static const struct dpu_lm_cfg sm8150_lm[] = { 144 { 145 .name = "lm_0", .id = LM_0, 146 .base = 0x44000, .len = 0x320, 147 .features = MIXER_SDM845_MASK, 148 .sblk = &sdm845_lm_sblk, 149 .lm_pair = LM_1, 150 .pingpong = PINGPONG_0, 151 .dspp = DSPP_0, 152 }, { 153 .name = "lm_1", .id = LM_1, 154 .base = 0x45000, .len = 0x320, 155 .features = MIXER_SDM845_MASK, 156 .sblk = &sdm845_lm_sblk, 157 .lm_pair = LM_0, 158 .pingpong = PINGPONG_1, 159 .dspp = DSPP_1, 160 }, { 161 .name = "lm_2", .id = LM_2, 162 .base = 0x46000, .len = 0x320, 163 .features = MIXER_SDM845_MASK, 164 .sblk = &sdm845_lm_sblk, 165 .lm_pair = LM_3, 166 .pingpong = PINGPONG_2, 167 }, { 168 .name = "lm_3", .id = LM_3, 169 .base = 0x47000, .len = 0x320, 170 .features = MIXER_SDM845_MASK, 171 .sblk = &sdm845_lm_sblk, 172 .lm_pair = LM_2, 173 .pingpong = PINGPONG_3, 174 }, { 175 .name = "lm_4", .id = LM_4, 176 .base = 0x48000, .len = 0x320, 177 .features = MIXER_SDM845_MASK, 178 .sblk = &sdm845_lm_sblk, 179 .lm_pair = LM_5, 180 .pingpong = PINGPONG_4, 181 }, { 182 .name = "lm_5", .id = LM_5, 183 .base = 0x49000, .len = 0x320, 184 .features = MIXER_SDM845_MASK, 185 .sblk = &sdm845_lm_sblk, 186 .lm_pair = LM_4, 187 .pingpong = PINGPONG_5, 188 }, 189 }; 190 191 static const struct dpu_dspp_cfg sm8150_dspp[] = { 192 { 193 .name = "dspp_0", .id = DSPP_0, 194 .base = 0x54000, .len = 0x1800, 195 .features = DSPP_SC7180_MASK, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_1", .id = DSPP_1, 199 .base = 0x56000, .len = 0x1800, 200 .features = DSPP_SC7180_MASK, 201 .sblk = &sdm845_dspp_sblk, 202 }, { 203 .name = "dspp_2", .id = DSPP_2, 204 .base = 0x58000, .len = 0x1800, 205 .features = DSPP_SC7180_MASK, 206 .sblk = &sdm845_dspp_sblk, 207 }, { 208 .name = "dspp_3", .id = DSPP_3, 209 .base = 0x5a000, .len = 0x1800, 210 .features = DSPP_SC7180_MASK, 211 .sblk = &sdm845_dspp_sblk, 212 }, 213 }; 214 215 static const struct dpu_pingpong_cfg sm8150_pp[] = { 216 { 217 .name = "pingpong_0", .id = PINGPONG_0, 218 .base = 0x70000, .len = 0xd4, 219 .features = PINGPONG_SM8150_MASK, 220 .sblk = &sdm845_pp_sblk, 221 .merge_3d = MERGE_3D_0, 222 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 223 }, { 224 .name = "pingpong_1", .id = PINGPONG_1, 225 .base = 0x70800, .len = 0xd4, 226 .features = PINGPONG_SM8150_MASK, 227 .sblk = &sdm845_pp_sblk, 228 .merge_3d = MERGE_3D_0, 229 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 230 }, { 231 .name = "pingpong_2", .id = PINGPONG_2, 232 .base = 0x71000, .len = 0xd4, 233 .features = PINGPONG_SM8150_MASK, 234 .sblk = &sdm845_pp_sblk, 235 .merge_3d = MERGE_3D_1, 236 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 237 }, { 238 .name = "pingpong_3", .id = PINGPONG_3, 239 .base = 0x71800, .len = 0xd4, 240 .features = PINGPONG_SM8150_MASK, 241 .sblk = &sdm845_pp_sblk, 242 .merge_3d = MERGE_3D_1, 243 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 244 }, { 245 .name = "pingpong_4", .id = PINGPONG_4, 246 .base = 0x72000, .len = 0xd4, 247 .features = PINGPONG_SM8150_MASK, 248 .sblk = &sdm845_pp_sblk, 249 .merge_3d = MERGE_3D_2, 250 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), 251 }, { 252 .name = "pingpong_5", .id = PINGPONG_5, 253 .base = 0x72800, .len = 0xd4, 254 .features = PINGPONG_SM8150_MASK, 255 .sblk = &sdm845_pp_sblk, 256 .merge_3d = MERGE_3D_2, 257 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), 258 }, 259 }; 260 261 static const struct dpu_merge_3d_cfg sm8150_merge_3d[] = { 262 { 263 .name = "merge_3d_0", .id = MERGE_3D_0, 264 .base = 0x83000, .len = 0x8, 265 }, { 266 .name = "merge_3d_1", .id = MERGE_3D_1, 267 .base = 0x83100, .len = 0x8, 268 }, { 269 .name = "merge_3d_2", .id = MERGE_3D_2, 270 .base = 0x83200, .len = 0x8, 271 }, 272 }; 273 274 static const struct dpu_dsc_cfg sm8150_dsc[] = { 275 { 276 .name = "dsc_0", .id = DSC_0, 277 .base = 0x80000, .len = 0x140, 278 .features = BIT(DPU_DSC_OUTPUT_CTRL), 279 }, { 280 .name = "dsc_1", .id = DSC_1, 281 .base = 0x80400, .len = 0x140, 282 .features = BIT(DPU_DSC_OUTPUT_CTRL), 283 }, { 284 .name = "dsc_2", .id = DSC_2, 285 .base = 0x80800, .len = 0x140, 286 .features = BIT(DPU_DSC_OUTPUT_CTRL), 287 }, { 288 .name = "dsc_3", .id = DSC_3, 289 .base = 0x80c00, .len = 0x140, 290 .features = BIT(DPU_DSC_OUTPUT_CTRL), 291 }, 292 }; 293 294 static const struct dpu_wb_cfg sm8150_wb[] = { 295 { 296 .name = "wb_2", .id = WB_2, 297 .base = 0x65000, .len = 0x2c8, 298 .features = WB_SDM845_MASK, 299 .format_list = wb2_formats_rgb, 300 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 301 .clk_ctrl = DPU_CLK_CTRL_WB2, 302 .xin_id = 6, 303 .vbif_idx = VBIF_RT, 304 .maxlinewidth = 4096, 305 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 306 }, 307 }; 308 309 static const struct dpu_intf_cfg sm8150_intf[] = { 310 { 311 .name = "intf_0", .id = INTF_0, 312 .base = 0x6a000, .len = 0x280, 313 .features = INTF_SC7180_MASK, 314 .type = INTF_DP, 315 .controller_id = MSM_DP_CONTROLLER_0, 316 .prog_fetch_lines_worst_case = 24, 317 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 318 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 319 }, { 320 .name = "intf_1", .id = INTF_1, 321 .base = 0x6a800, .len = 0x2bc, 322 .features = INTF_SC7180_MASK, 323 .type = INTF_DSI, 324 .controller_id = MSM_DSI_CONTROLLER_0, 325 .prog_fetch_lines_worst_case = 24, 326 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 327 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 328 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 329 }, { 330 .name = "intf_2", .id = INTF_2, 331 .base = 0x6b000, .len = 0x2bc, 332 .features = INTF_SC7180_MASK, 333 .type = INTF_DSI, 334 .controller_id = MSM_DSI_CONTROLLER_1, 335 .prog_fetch_lines_worst_case = 24, 336 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 337 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 338 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), 339 }, { 340 .name = "intf_3", .id = INTF_3, 341 .base = 0x6b800, .len = 0x280, 342 .features = INTF_SC7180_MASK, 343 .type = INTF_DP, 344 .controller_id = MSM_DP_CONTROLLER_1, 345 .prog_fetch_lines_worst_case = 24, 346 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 347 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 348 }, 349 }; 350 351 static const struct dpu_perf_cfg sm8150_perf_data = { 352 .max_bw_low = 12800000, 353 .max_bw_high = 12800000, 354 .min_core_ib = 2400000, 355 .min_llcc_ib = 800000, 356 .min_dram_ib = 800000, 357 .min_prefill_lines = 24, 358 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 359 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 360 .qos_lut_tbl = { 361 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 362 .entries = sm8150_qos_linear 363 }, 364 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 365 .entries = sc7180_qos_macrotile 366 }, 367 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 368 .entries = sc7180_qos_nrt 369 }, 370 /* TODO: macrotile-qseed is different from macrotile */ 371 }, 372 .cdp_cfg = { 373 {.rd_enable = 1, .wr_enable = 1}, 374 {.rd_enable = 1, .wr_enable = 0} 375 }, 376 .clk_inefficiency_factor = 105, 377 .bw_inefficiency_factor = 120, 378 }; 379 380 static const struct dpu_mdss_version sm8150_mdss_ver = { 381 .core_major_ver = 5, 382 .core_minor_ver = 0, 383 }; 384 385 const struct dpu_mdss_cfg dpu_sm8150_cfg = { 386 .mdss_ver = &sm8150_mdss_ver, 387 .caps = &sm8150_dpu_caps, 388 .mdp = &sm8150_mdp, 389 .ctl_count = ARRAY_SIZE(sm8150_ctl), 390 .ctl = sm8150_ctl, 391 .sspp_count = ARRAY_SIZE(sm8150_sspp), 392 .sspp = sm8150_sspp, 393 .mixer_count = ARRAY_SIZE(sm8150_lm), 394 .mixer = sm8150_lm, 395 .dspp_count = ARRAY_SIZE(sm8150_dspp), 396 .dspp = sm8150_dspp, 397 .dsc_count = ARRAY_SIZE(sm8150_dsc), 398 .dsc = sm8150_dsc, 399 .pingpong_count = ARRAY_SIZE(sm8150_pp), 400 .pingpong = sm8150_pp, 401 .merge_3d_count = ARRAY_SIZE(sm8150_merge_3d), 402 .merge_3d = sm8150_merge_3d, 403 .wb_count = ARRAY_SIZE(sm8150_wb), 404 .wb = sm8150_wb, 405 .intf_count = ARRAY_SIZE(sm8150_intf), 406 .intf = sm8150_intf, 407 .vbif_count = ARRAY_SIZE(sdm845_vbif), 408 .vbif = sdm845_vbif, 409 .perf = &sm8150_perf_data, 410 }; 411 412 #endif 413