1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 * Copyright (c) 2023, Linaro Limited 6 */ 7 8 #ifndef _DPU_6_9_SM6375_H 9 #define _DPU_6_9_SM6375_H 10 11 static const struct dpu_caps sm6375_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_LINE_WIDTH, 13 .max_mixer_blendstages = 0x4, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 }; 19 20 static const struct dpu_mdp_cfg sm6375_mdp = { 21 .name = "top_0", 22 .base = 0x0, .len = 0x494, 23 .clk_ctrls = { 24 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 25 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 26 }, 27 }; 28 29 static const struct dpu_ctl_cfg sm6375_ctl[] = { 30 { 31 .name = "ctl_0", .id = CTL_0, 32 .base = 0x1000, .len = 0x1dc, 33 .features = BIT(DPU_CTL_ACTIVE_CFG), 34 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 35 }, 36 }; 37 38 static const struct dpu_sspp_cfg sm6375_sspp[] = { 39 { 40 .name = "sspp_0", .id = SSPP_VIG0, 41 .base = 0x4000, .len = 0x1f8, 42 .features = VIG_SDM845_MASK, 43 .sblk = &dpu_vig_sblk_qseed3_3_0, 44 .xin_id = 0, 45 .type = SSPP_TYPE_VIG, 46 .clk_ctrl = DPU_CLK_CTRL_VIG0, 47 }, { 48 .name = "sspp_8", .id = SSPP_DMA0, 49 .base = 0x24000, .len = 0x1f8, 50 .features = DMA_SDM845_MASK, 51 .sblk = &dpu_dma_sblk, 52 .xin_id = 1, 53 .type = SSPP_TYPE_DMA, 54 .clk_ctrl = DPU_CLK_CTRL_DMA0, 55 }, 56 }; 57 58 static const struct dpu_lm_cfg sm6375_lm[] = { 59 { 60 .name = "lm_0", .id = LM_0, 61 .base = 0x44000, .len = 0x320, 62 .features = MIXER_QCM2290_MASK, 63 .sblk = &qcm2290_lm_sblk, 64 .lm_pair = 0, 65 .pingpong = PINGPONG_0, 66 .dspp = DSPP_0, 67 }, 68 }; 69 70 static const struct dpu_dspp_cfg sm6375_dspp[] = { 71 { 72 .name = "dspp_0", .id = DSPP_0, 73 .base = 0x54000, .len = 0x1800, 74 .features = DSPP_SC7180_MASK, 75 .sblk = &sdm845_dspp_sblk, 76 }, 77 }; 78 79 static const struct dpu_pingpong_cfg sm6375_pp[] = { 80 { 81 .name = "pingpong_0", .id = PINGPONG_0, 82 .base = 0x70000, .len = 0xd4, 83 .features = PINGPONG_SM8150_MASK, 84 .sblk = &sdm845_pp_sblk, 85 .merge_3d = 0, 86 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 87 }, 88 }; 89 90 static const struct dpu_dsc_cfg sm6375_dsc[] = { 91 { 92 .name = "dsc_0", .id = DSC_0, 93 .base = 0x80000, .len = 0x140, 94 .features = BIT(DPU_DSC_OUTPUT_CTRL), 95 }, 96 }; 97 98 static const struct dpu_intf_cfg sm6375_intf[] = { 99 { 100 .name = "intf_1", .id = INTF_1, 101 .base = 0x6a800, .len = 0x2c0, 102 .features = INTF_SC7180_MASK, 103 .type = INTF_DSI, 104 .controller_id = MSM_DSI_CONTROLLER_0, 105 .prog_fetch_lines_worst_case = 24, 106 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 107 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 108 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 109 }, 110 }; 111 112 static const struct dpu_perf_cfg sm6375_perf_data = { 113 .max_bw_low = 5200000, 114 .max_bw_high = 6200000, 115 .min_core_ib = 2500000, 116 .min_llcc_ib = 0, /* No LLCC on this SoC */ 117 .min_dram_ib = 1600000, 118 .min_prefill_lines = 24, 119 /* TODO: confirm danger_lut_tbl */ 120 .danger_lut_tbl = {0xffff, 0xffff, 0x0}, 121 .safe_lut_tbl = {0xfe00, 0xfe00, 0xffff}, 122 .qos_lut_tbl = { 123 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 124 .entries = sm6350_qos_linear_macrotile 125 }, 126 {.nentry = ARRAY_SIZE(sm6350_qos_linear_macrotile), 127 .entries = sm6350_qos_linear_macrotile 128 }, 129 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 130 .entries = sc7180_qos_nrt 131 }, 132 }, 133 .cdp_cfg = { 134 {.rd_enable = 1, .wr_enable = 1}, 135 {.rd_enable = 1, .wr_enable = 0} 136 }, 137 .clk_inefficiency_factor = 105, 138 .bw_inefficiency_factor = 120, 139 }; 140 141 static const struct dpu_mdss_version sm6375_mdss_ver = { 142 .core_major_ver = 6, 143 .core_minor_ver = 9, 144 }; 145 146 const struct dpu_mdss_cfg dpu_sm6375_cfg = { 147 .mdss_ver = &sm6375_mdss_ver, 148 .caps = &sm6375_dpu_caps, 149 .mdp = &sm6375_mdp, 150 .ctl_count = ARRAY_SIZE(sm6375_ctl), 151 .ctl = sm6375_ctl, 152 .sspp_count = ARRAY_SIZE(sm6375_sspp), 153 .sspp = sm6375_sspp, 154 .mixer_count = ARRAY_SIZE(sm6375_lm), 155 .mixer = sm6375_lm, 156 .dspp_count = ARRAY_SIZE(sm6375_dspp), 157 .dspp = sm6375_dspp, 158 .dsc_count = ARRAY_SIZE(sm6375_dsc), 159 .dsc = sm6375_dsc, 160 .pingpong_count = ARRAY_SIZE(sm6375_pp), 161 .pingpong = sm6375_pp, 162 .intf_count = ARRAY_SIZE(sm6375_intf), 163 .intf = sm6375_intf, 164 .vbif_count = ARRAY_SIZE(sdm845_vbif), 165 .vbif = sdm845_vbif, 166 .perf = &sm6375_perf_data, 167 }; 168 169 #endif 170