1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023 Marijn Suijten <marijn.suijten@somainline.org>. All rights reserved. 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 6 */ 7 8 #ifndef _DPU_5_4_SM6125_H 9 #define _DPU_5_4_SM6125_H 10 11 static const struct dpu_caps sm6125_dpu_caps = { 12 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 13 .max_mixer_blendstages = 0x6, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .max_linewidth = 2160, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_mdp_cfg sm6125_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x45c, 25 .features = 0, 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 29 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 30 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 31 }, 32 }; 33 34 static const struct dpu_ctl_cfg sm6125_ctl[] = { 35 { 36 .name = "ctl_0", .id = CTL_0, 37 .base = 0x1000, .len = 0x1e0, 38 .features = BIT(DPU_CTL_ACTIVE_CFG), 39 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 40 }, { 41 .name = "ctl_1", .id = CTL_1, 42 .base = 0x1200, .len = 0x1e0, 43 .features = BIT(DPU_CTL_ACTIVE_CFG), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 45 }, { 46 .name = "ctl_2", .id = CTL_2, 47 .base = 0x1400, .len = 0x1e0, 48 .features = BIT(DPU_CTL_ACTIVE_CFG), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 50 }, { 51 .name = "ctl_3", .id = CTL_3, 52 .base = 0x1600, .len = 0x1e0, 53 .features = BIT(DPU_CTL_ACTIVE_CFG), 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 55 }, { 56 .name = "ctl_4", .id = CTL_4, 57 .base = 0x1800, .len = 0x1e0, 58 .features = BIT(DPU_CTL_ACTIVE_CFG), 59 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 60 }, { 61 .name = "ctl_5", .id = CTL_5, 62 .base = 0x1a00, .len = 0x1e0, 63 .features = BIT(DPU_CTL_ACTIVE_CFG), 64 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), 65 }, 66 }; 67 68 static const struct dpu_sspp_cfg sm6125_sspp[] = { 69 { 70 .name = "sspp_0", .id = SSPP_VIG0, 71 .base = 0x4000, .len = 0x1f0, 72 .features = VIG_SDM845_MASK, 73 .sblk = &dpu_vig_sblk_qseed3_2_4, 74 .xin_id = 0, 75 .type = SSPP_TYPE_VIG, 76 .clk_ctrl = DPU_CLK_CTRL_VIG0, 77 }, { 78 .name = "sspp_8", .id = SSPP_DMA0, 79 .base = 0x24000, .len = 0x1f0, 80 .features = DMA_SDM845_MASK, 81 .sblk = &dpu_dma_sblk, 82 .xin_id = 1, 83 .type = SSPP_TYPE_DMA, 84 .clk_ctrl = DPU_CLK_CTRL_DMA0, 85 }, { 86 .name = "sspp_9", .id = SSPP_DMA1, 87 .base = 0x26000, .len = 0x1f0, 88 .features = DMA_SDM845_MASK, 89 .sblk = &dpu_dma_sblk, 90 .xin_id = 5, 91 .type = SSPP_TYPE_DMA, 92 .clk_ctrl = DPU_CLK_CTRL_DMA1, 93 }, 94 }; 95 96 static const struct dpu_lm_cfg sm6125_lm[] = { 97 { 98 .name = "lm_0", .id = LM_0, 99 .base = 0x44000, .len = 0x320, 100 .features = MIXER_QCM2290_MASK, 101 .sblk = &sdm845_lm_sblk, 102 .pingpong = PINGPONG_0, 103 .dspp = DSPP_0, 104 .lm_pair = LM_1, 105 }, { 106 .name = "lm_1", .id = LM_1, 107 .base = 0x45000, .len = 0x320, 108 .features = MIXER_QCM2290_MASK, 109 .sblk = &sdm845_lm_sblk, 110 .pingpong = PINGPONG_1, 111 .dspp = 0, 112 .lm_pair = LM_0, 113 }, 114 }; 115 116 static const struct dpu_dspp_cfg sm6125_dspp[] = { 117 { 118 .name = "dspp_0", .id = DSPP_0, 119 .base = 0x54000, .len = 0x1800, 120 .features = DSPP_SC7180_MASK, 121 .sblk = &sdm845_dspp_sblk, 122 }, 123 }; 124 125 static const struct dpu_pingpong_cfg sm6125_pp[] = { 126 { 127 .name = "pingpong_0", .id = PINGPONG_0, 128 .base = 0x70000, .len = 0xd4, 129 .features = PINGPONG_SM8150_MASK, 130 .merge_3d = 0, 131 .sblk = &sdm845_pp_sblk, 132 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 133 }, { 134 .name = "pingpong_1", .id = PINGPONG_1, 135 .base = 0x70800, .len = 0xd4, 136 .features = PINGPONG_SM8150_MASK, 137 .merge_3d = 0, 138 .sblk = &sdm845_pp_sblk, 139 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 140 }, 141 }; 142 143 static const struct dpu_wb_cfg sm6125_wb[] = { 144 { 145 .name = "wb_2", .id = WB_2, 146 .base = 0x65000, .len = 0x2c8, 147 .features = WB_SDM845_MASK, 148 .format_list = wb2_formats_rgb, 149 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 150 .clk_ctrl = DPU_CLK_CTRL_WB2, 151 .xin_id = 6, 152 .vbif_idx = VBIF_RT, 153 .maxlinewidth = 2160, 154 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 155 }, 156 }; 157 158 static const struct dpu_intf_cfg sm6125_intf[] = { 159 { 160 .name = "intf_0", .id = INTF_0, 161 .base = 0x6a000, .len = 0x280, 162 .features = INTF_SC7180_MASK, 163 .type = INTF_DP, 164 .controller_id = MSM_DP_CONTROLLER_0, 165 .prog_fetch_lines_worst_case = 24, 166 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 167 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 168 }, { 169 .name = "intf_1", .id = INTF_1, 170 .base = 0x6a800, .len = 0x2c0, 171 .features = INTF_SC7180_MASK, 172 .type = INTF_DSI, 173 .controller_id = 0, 174 .prog_fetch_lines_worst_case = 24, 175 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 176 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 177 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 178 }, 179 }; 180 181 static const struct dpu_perf_cfg sm6125_perf_data = { 182 .max_bw_low = 4100000, 183 .max_bw_high = 4100000, 184 .min_core_ib = 2400000, 185 .min_llcc_ib = 0, /* No LLCC on this SoC */ 186 .min_dram_ib = 800000, 187 .min_prefill_lines = 24, 188 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 189 .safe_lut_tbl = {0xfff8, 0xf000, 0xffff}, 190 .qos_lut_tbl = { 191 {.nentry = ARRAY_SIZE(sm8150_qos_linear), 192 .entries = sm8150_qos_linear 193 }, 194 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 195 .entries = sc7180_qos_macrotile 196 }, 197 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 198 .entries = sc7180_qos_nrt 199 }, 200 /* TODO: macrotile-qseed is different from macrotile */ 201 }, 202 .cdp_cfg = { 203 {.rd_enable = 1, .wr_enable = 1}, 204 {.rd_enable = 1, .wr_enable = 0} 205 }, 206 .clk_inefficiency_factor = 105, 207 .bw_inefficiency_factor = 120, 208 }; 209 210 static const struct dpu_mdss_version sm6125_mdss_ver = { 211 .core_major_ver = 5, 212 .core_minor_ver = 4, 213 }; 214 215 const struct dpu_mdss_cfg dpu_sm6125_cfg = { 216 .mdss_ver = &sm6125_mdss_ver, 217 .caps = &sm6125_dpu_caps, 218 .mdp = &sm6125_mdp, 219 .ctl_count = ARRAY_SIZE(sm6125_ctl), 220 .ctl = sm6125_ctl, 221 .sspp_count = ARRAY_SIZE(sm6125_sspp), 222 .sspp = sm6125_sspp, 223 .mixer_count = ARRAY_SIZE(sm6125_lm), 224 .mixer = sm6125_lm, 225 .dspp_count = ARRAY_SIZE(sm6125_dspp), 226 .dspp = sm6125_dspp, 227 .pingpong_count = ARRAY_SIZE(sm6125_pp), 228 .pingpong = sm6125_pp, 229 .wb_count = ARRAY_SIZE(sm6125_wb), 230 .wb = sm6125_wb, 231 .intf_count = ARRAY_SIZE(sm6125_intf), 232 .intf = sm6125_intf, 233 .vbif_count = ARRAY_SIZE(sdm845_vbif), 234 .vbif = sdm845_vbif, 235 .perf = &sm6125_perf_data, 236 }; 237 238 #endif 239