1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_4_0_SDM845_H 8 #define _DPU_4_0_SDM845_H 9 10 static const struct dpu_caps sdm845_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0xb, 13 .has_src_split = true, 14 .has_dim_layer = true, 15 .has_idle_pc = true, 16 .has_3d_merge = true, 17 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 18 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 19 .max_hdeci_exp = MAX_HORZ_DECIMATION, 20 .max_vdeci_exp = MAX_VERT_DECIMATION, 21 }; 22 23 static const struct dpu_mdp_cfg sdm845_mdp = { 24 .name = "top_0", 25 .base = 0x0, .len = 0x45c, 26 .features = BIT(DPU_MDP_AUDIO_SELECT) | BIT(DPU_MDP_VSYNC_SEL), 27 .clk_ctrls = { 28 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 29 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 30 [DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 }, 31 [DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 }, 32 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 33 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 34 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 35 [DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 }, 36 }, 37 }; 38 39 static const struct dpu_ctl_cfg sdm845_ctl[] = { 40 { 41 .name = "ctl_0", .id = CTL_0, 42 .base = 0x1000, .len = 0xe4, 43 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 44 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 45 }, { 46 .name = "ctl_1", .id = CTL_1, 47 .base = 0x1200, .len = 0xe4, 48 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 49 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 50 }, { 51 .name = "ctl_2", .id = CTL_2, 52 .base = 0x1400, .len = 0xe4, 53 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 54 }, { 55 .name = "ctl_3", .id = CTL_3, 56 .base = 0x1600, .len = 0xe4, 57 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 58 }, { 59 .name = "ctl_4", .id = CTL_4, 60 .base = 0x1800, .len = 0xe4, 61 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 62 }, 63 }; 64 65 static const struct dpu_sspp_cfg sdm845_sspp[] = { 66 { 67 .name = "sspp_0", .id = SSPP_VIG0, 68 .base = 0x4000, .len = 0x1c8, 69 .features = VIG_SDM845_MASK_SDMA, 70 .sblk = &dpu_vig_sblk_qseed3_1_3, 71 .xin_id = 0, 72 .type = SSPP_TYPE_VIG, 73 .clk_ctrl = DPU_CLK_CTRL_VIG0, 74 }, { 75 .name = "sspp_1", .id = SSPP_VIG1, 76 .base = 0x6000, .len = 0x1c8, 77 .features = VIG_SDM845_MASK_SDMA, 78 .sblk = &dpu_vig_sblk_qseed3_1_3, 79 .xin_id = 4, 80 .type = SSPP_TYPE_VIG, 81 .clk_ctrl = DPU_CLK_CTRL_VIG1, 82 }, { 83 .name = "sspp_2", .id = SSPP_VIG2, 84 .base = 0x8000, .len = 0x1c8, 85 .features = VIG_SDM845_MASK_SDMA, 86 .sblk = &dpu_vig_sblk_qseed3_1_3, 87 .xin_id = 8, 88 .type = SSPP_TYPE_VIG, 89 .clk_ctrl = DPU_CLK_CTRL_VIG2, 90 }, { 91 .name = "sspp_3", .id = SSPP_VIG3, 92 .base = 0xa000, .len = 0x1c8, 93 .features = VIG_SDM845_MASK_SDMA, 94 .sblk = &dpu_vig_sblk_qseed3_1_3, 95 .xin_id = 12, 96 .type = SSPP_TYPE_VIG, 97 .clk_ctrl = DPU_CLK_CTRL_VIG3, 98 }, { 99 .name = "sspp_8", .id = SSPP_DMA0, 100 .base = 0x24000, .len = 0x1c8, 101 .features = DMA_SDM845_MASK_SDMA, 102 .sblk = &dpu_dma_sblk, 103 .xin_id = 1, 104 .type = SSPP_TYPE_DMA, 105 .clk_ctrl = DPU_CLK_CTRL_DMA0, 106 }, { 107 .name = "sspp_9", .id = SSPP_DMA1, 108 .base = 0x26000, .len = 0x1c8, 109 .features = DMA_SDM845_MASK_SDMA, 110 .sblk = &dpu_dma_sblk, 111 .xin_id = 5, 112 .type = SSPP_TYPE_DMA, 113 .clk_ctrl = DPU_CLK_CTRL_DMA1, 114 }, { 115 .name = "sspp_10", .id = SSPP_DMA2, 116 .base = 0x28000, .len = 0x1c8, 117 .features = DMA_CURSOR_SDM845_MASK_SDMA, 118 .sblk = &dpu_dma_sblk, 119 .xin_id = 9, 120 .type = SSPP_TYPE_DMA, 121 .clk_ctrl = DPU_CLK_CTRL_DMA2, 122 }, { 123 .name = "sspp_11", .id = SSPP_DMA3, 124 .base = 0x2a000, .len = 0x1c8, 125 .features = DMA_CURSOR_SDM845_MASK_SDMA, 126 .sblk = &dpu_dma_sblk, 127 .xin_id = 13, 128 .type = SSPP_TYPE_DMA, 129 .clk_ctrl = DPU_CLK_CTRL_DMA3, 130 }, 131 }; 132 133 static const struct dpu_lm_cfg sdm845_lm[] = { 134 { 135 .name = "lm_0", .id = LM_0, 136 .base = 0x44000, .len = 0x320, 137 .features = MIXER_SDM845_MASK, 138 .sblk = &sdm845_lm_sblk, 139 .lm_pair = LM_1, 140 .pingpong = PINGPONG_0, 141 .dspp = DSPP_0, 142 }, { 143 .name = "lm_1", .id = LM_1, 144 .base = 0x45000, .len = 0x320, 145 .features = MIXER_SDM845_MASK, 146 .sblk = &sdm845_lm_sblk, 147 .lm_pair = LM_0, 148 .pingpong = PINGPONG_1, 149 .dspp = DSPP_1, 150 }, { 151 .name = "lm_2", .id = LM_2, 152 .base = 0x46000, .len = 0x320, 153 .features = MIXER_SDM845_MASK, 154 .sblk = &sdm845_lm_sblk, 155 .lm_pair = LM_5, 156 .pingpong = PINGPONG_2, 157 .dspp = DSPP_2, 158 }, { 159 .name = "lm_3", .id = LM_3, 160 .base = 0x0, .len = 0x320, 161 .features = MIXER_SDM845_MASK, 162 .sblk = &sdm845_lm_sblk, 163 .pingpong = PINGPONG_NONE, 164 .dspp = DSPP_3, 165 }, { 166 .name = "lm_4", .id = LM_4, 167 .base = 0x0, .len = 0x320, 168 .features = MIXER_SDM845_MASK, 169 .sblk = &sdm845_lm_sblk, 170 .pingpong = PINGPONG_NONE, 171 }, { 172 .name = "lm_5", .id = LM_5, 173 .base = 0x49000, .len = 0x320, 174 .features = MIXER_SDM845_MASK, 175 .sblk = &sdm845_lm_sblk, 176 .lm_pair = LM_2, 177 .pingpong = PINGPONG_3, 178 }, 179 }; 180 181 static const struct dpu_dspp_cfg sdm845_dspp[] = { 182 { 183 .name = "dspp_0", .id = DSPP_0, 184 .base = 0x54000, .len = 0x1800, 185 .features = DSPP_SC7180_MASK, 186 .sblk = &sdm845_dspp_sblk, 187 }, { 188 .name = "dspp_1", .id = DSPP_1, 189 .base = 0x56000, .len = 0x1800, 190 .features = DSPP_SC7180_MASK, 191 .sblk = &sdm845_dspp_sblk, 192 }, { 193 .name = "dspp_2", .id = DSPP_2, 194 .base = 0x58000, .len = 0x1800, 195 .features = DSPP_SC7180_MASK, 196 .sblk = &sdm845_dspp_sblk, 197 }, { 198 .name = "dspp_3", .id = DSPP_3, 199 .base = 0x5a000, .len = 0x1800, 200 .features = DSPP_SC7180_MASK, 201 .sblk = &sdm845_dspp_sblk, 202 }, 203 }; 204 205 static const struct dpu_pingpong_cfg sdm845_pp[] = { 206 { 207 .name = "pingpong_0", .id = PINGPONG_0, 208 .base = 0x70000, .len = 0xd4, 209 .features = PINGPONG_SDM845_TE2_MASK, 210 .sblk = &sdm845_pp_sblk_te, 211 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 212 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 213 }, { 214 .name = "pingpong_1", .id = PINGPONG_1, 215 .base = 0x70800, .len = 0xd4, 216 .features = PINGPONG_SDM845_TE2_MASK, 217 .sblk = &sdm845_pp_sblk_te, 218 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 219 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 220 }, { 221 .name = "pingpong_2", .id = PINGPONG_2, 222 .base = 0x71000, .len = 0xd4, 223 .features = PINGPONG_SDM845_MASK, 224 .sblk = &sdm845_pp_sblk, 225 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 226 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 227 }, { 228 .name = "pingpong_3", .id = PINGPONG_3, 229 .base = 0x71800, .len = 0xd4, 230 .features = PINGPONG_SDM845_MASK, 231 .sblk = &sdm845_pp_sblk, 232 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 233 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 234 }, 235 }; 236 237 static const struct dpu_dsc_cfg sdm845_dsc[] = { 238 { 239 .name = "dsc_0", .id = DSC_0, 240 .base = 0x80000, .len = 0x140, 241 }, { 242 .name = "dsc_1", .id = DSC_1, 243 .base = 0x80400, .len = 0x140, 244 }, { 245 .name = "dsc_2", .id = DSC_2, 246 .base = 0x80800, .len = 0x140, 247 }, { 248 .name = "dsc_3", .id = DSC_3, 249 .base = 0x80c00, .len = 0x140, 250 }, 251 }; 252 253 static const struct dpu_intf_cfg sdm845_intf[] = { 254 { 255 .name = "intf_0", .id = INTF_0, 256 .base = 0x6a000, .len = 0x280, 257 .type = INTF_DP, 258 .controller_id = MSM_DP_CONTROLLER_0, 259 .prog_fetch_lines_worst_case = 24, 260 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 261 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 262 }, { 263 .name = "intf_1", .id = INTF_1, 264 .base = 0x6a800, .len = 0x280, 265 .type = INTF_DSI, 266 .controller_id = MSM_DSI_CONTROLLER_0, 267 .prog_fetch_lines_worst_case = 24, 268 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 269 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 270 }, { 271 .name = "intf_2", .id = INTF_2, 272 .base = 0x6b000, .len = 0x280, 273 .type = INTF_DSI, 274 .controller_id = MSM_DSI_CONTROLLER_1, 275 .prog_fetch_lines_worst_case = 24, 276 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 277 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 278 }, { 279 .name = "intf_3", .id = INTF_3, 280 .base = 0x6b800, .len = 0x280, 281 .type = INTF_DP, 282 .controller_id = MSM_DP_CONTROLLER_1, 283 .prog_fetch_lines_worst_case = 24, 284 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), 285 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), 286 }, 287 }; 288 289 static const struct dpu_perf_cfg sdm845_perf_data = { 290 .max_bw_low = 6800000, 291 .max_bw_high = 6800000, 292 .min_core_ib = 2400000, 293 .min_llcc_ib = 800000, 294 .min_dram_ib = 800000, 295 .undersized_prefill_lines = 2, 296 .xtra_prefill_lines = 2, 297 .dest_scale_prefill_lines = 3, 298 .macrotile_prefill_lines = 4, 299 .yuv_nv12_prefill_lines = 8, 300 .linear_prefill_lines = 1, 301 .downscaling_prefill_lines = 1, 302 .amortizable_threshold = 25, 303 .min_prefill_lines = 24, 304 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 305 .safe_lut_tbl = {0xfff0, 0xf000, 0xffff}, 306 .qos_lut_tbl = { 307 {.nentry = ARRAY_SIZE(sdm845_qos_linear), 308 .entries = sdm845_qos_linear 309 }, 310 {.nentry = ARRAY_SIZE(sdm845_qos_macrotile), 311 .entries = sdm845_qos_macrotile 312 }, 313 {.nentry = ARRAY_SIZE(sdm845_qos_nrt), 314 .entries = sdm845_qos_nrt 315 }, 316 }, 317 .cdp_cfg = { 318 {.rd_enable = 1, .wr_enable = 1}, 319 {.rd_enable = 1, .wr_enable = 0} 320 }, 321 .clk_inefficiency_factor = 105, 322 .bw_inefficiency_factor = 120, 323 }; 324 325 static const struct dpu_mdss_version sdm845_mdss_ver = { 326 .core_major_ver = 4, 327 .core_minor_ver = 0, 328 }; 329 330 const struct dpu_mdss_cfg dpu_sdm845_cfg = { 331 .mdss_ver = &sdm845_mdss_ver, 332 .caps = &sdm845_dpu_caps, 333 .mdp = &sdm845_mdp, 334 .ctl_count = ARRAY_SIZE(sdm845_ctl), 335 .ctl = sdm845_ctl, 336 .sspp_count = ARRAY_SIZE(sdm845_sspp), 337 .sspp = sdm845_sspp, 338 .mixer_count = ARRAY_SIZE(sdm845_lm), 339 .mixer = sdm845_lm, 340 .dspp_count = ARRAY_SIZE(sdm845_dspp), 341 .dspp = sdm845_dspp, 342 .pingpong_count = ARRAY_SIZE(sdm845_pp), 343 .pingpong = sdm845_pp, 344 .dsc_count = ARRAY_SIZE(sdm845_dsc), 345 .dsc = sdm845_dsc, 346 .intf_count = ARRAY_SIZE(sdm845_intf), 347 .intf = sdm845_intf, 348 .vbif_count = ARRAY_SIZE(sdm845_vbif), 349 .vbif = sdm845_vbif, 350 .perf = &sdm845_perf_data, 351 }; 352 353 #endif 354