1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 5 * Copyright (c) 2023, Richard Acayan. All rights reserved. 6 */ 7 8 #ifndef _DPU_4_1_SDM670_H 9 #define _DPU_4_1_SDM670_H 10 11 static const struct dpu_mdp_cfg sdm670_mdp = { 12 .name = "top_0", 13 .base = 0x0, .len = 0x45c, 14 .features = BIT(DPU_MDP_AUDIO_SELECT), 15 .clk_ctrls = { 16 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 17 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 18 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 19 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 20 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 }, 21 }, 22 }; 23 24 static const struct dpu_sspp_cfg sdm670_sspp[] = { 25 { 26 .name = "sspp_0", .id = SSPP_VIG0, 27 .base = 0x4000, .len = 0x1c8, 28 .features = VIG_SDM845_MASK_SDMA, 29 .sblk = &dpu_vig_sblk_qseed3_1_3, 30 .xin_id = 0, 31 .type = SSPP_TYPE_VIG, 32 .clk_ctrl = DPU_CLK_CTRL_VIG0, 33 }, { 34 .name = "sspp_1", .id = SSPP_VIG1, 35 .base = 0x6000, .len = 0x1c8, 36 .features = VIG_SDM845_MASK_SDMA, 37 .sblk = &dpu_vig_sblk_qseed3_1_3, 38 .xin_id = 4, 39 .type = SSPP_TYPE_VIG, 40 .clk_ctrl = DPU_CLK_CTRL_VIG0, 41 }, { 42 .name = "sspp_8", .id = SSPP_DMA0, 43 .base = 0x24000, .len = 0x1c8, 44 .features = DMA_SDM845_MASK_SDMA, 45 .sblk = &dpu_dma_sblk, 46 .xin_id = 1, 47 .type = SSPP_TYPE_DMA, 48 .clk_ctrl = DPU_CLK_CTRL_DMA0, 49 }, { 50 .name = "sspp_9", .id = SSPP_DMA1, 51 .base = 0x26000, .len = 0x1c8, 52 .features = DMA_CURSOR_SDM845_MASK_SDMA, 53 .sblk = &dpu_dma_sblk, 54 .xin_id = 5, 55 .type = SSPP_TYPE_DMA, 56 .clk_ctrl = DPU_CLK_CTRL_DMA1, 57 }, { 58 .name = "sspp_10", .id = SSPP_DMA2, 59 .base = 0x28000, .len = 0x1c8, 60 .features = DMA_CURSOR_SDM845_MASK_SDMA, 61 .sblk = &dpu_dma_sblk, 62 .xin_id = 9, 63 .type = SSPP_TYPE_DMA, 64 .clk_ctrl = DPU_CLK_CTRL_DMA2, 65 }, 66 }; 67 68 static const struct dpu_dsc_cfg sdm670_dsc[] = { 69 { 70 .name = "dsc_0", .id = DSC_0, 71 .base = 0x80000, .len = 0x140, 72 }, { 73 .name = "dsc_1", .id = DSC_1, 74 .base = 0x80400, .len = 0x140, 75 }, 76 }; 77 78 static const struct dpu_mdss_version sdm670_mdss_ver = { 79 .core_major_ver = 4, 80 .core_minor_ver = 1, 81 }; 82 83 const struct dpu_mdss_cfg dpu_sdm670_cfg = { 84 .mdss_ver = &sdm670_mdss_ver, 85 .caps = &sdm845_dpu_caps, 86 .mdp = &sdm670_mdp, 87 .ctl_count = ARRAY_SIZE(sdm845_ctl), 88 .ctl = sdm845_ctl, 89 .sspp_count = ARRAY_SIZE(sdm670_sspp), 90 .sspp = sdm670_sspp, 91 .mixer_count = ARRAY_SIZE(sdm845_lm), 92 .mixer = sdm845_lm, 93 .pingpong_count = ARRAY_SIZE(sdm845_pp), 94 .pingpong = sdm845_pp, 95 .dsc_count = ARRAY_SIZE(sdm670_dsc), 96 .dsc = sdm670_dsc, 97 .intf_count = ARRAY_SIZE(sdm845_intf), 98 .intf = sdm845_intf, 99 .vbif_count = ARRAY_SIZE(sdm845_vbif), 100 .vbif = sdm845_vbif, 101 .perf = &sdm845_perf_data, 102 }; 103 104 #endif 105