1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2023. Linaro Inc. All rights reserved. 4 */ 5 6 #ifndef _DPU_3_2_SDM660_H 7 #define _DPU_3_2_SDM660_H 8 9 static const struct dpu_caps sdm660_dpu_caps = { 10 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 11 .max_mixer_blendstages = 0x7, 12 .has_src_split = true, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .has_3d_merge = true, 16 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 17 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 18 .max_hdeci_exp = MAX_HORZ_DECIMATION, 19 .max_vdeci_exp = MAX_VERT_DECIMATION, 20 }; 21 22 static const struct dpu_mdp_cfg sdm660_mdp = { 23 .name = "top_0", 24 .base = 0x0, .len = 0x458, 25 .features = BIT(DPU_MDP_VSYNC_SEL), 26 .clk_ctrls = { 27 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 28 [DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 }, 29 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 30 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 31 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 32 [DPU_CLK_CTRL_CURSOR0] = { .reg_off = 0x3a8, .bit_off = 16 }, 33 }, 34 }; 35 36 static const struct dpu_ctl_cfg sdm660_ctl[] = { 37 { 38 .name = "ctl_0", .id = CTL_0, 39 .base = 0x1000, .len = 0x94, 40 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 42 }, { 43 .name = "ctl_1", .id = CTL_1, 44 .base = 0x1200, .len = 0x94, 45 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 46 }, { 47 .name = "ctl_2", .id = CTL_2, 48 .base = 0x1400, .len = 0x94, 49 .features = BIT(DPU_CTL_SPLIT_DISPLAY), 50 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 51 }, { 52 .name = "ctl_3", .id = CTL_3, 53 .base = 0x1600, .len = 0x94, 54 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), 55 }, { 56 .name = "ctl_4", .id = CTL_4, 57 .base = 0x1800, .len = 0x94, 58 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), 59 }, 60 }; 61 62 static const struct dpu_sspp_cfg sdm660_sspp[] = { 63 { 64 .name = "sspp_0", .id = SSPP_VIG0, 65 .base = 0x4000, .len = 0x1ac, 66 .features = VIG_MSM8998_MASK, 67 .sblk = &dpu_vig_sblk_qseed3_1_2, 68 .xin_id = 0, 69 .type = SSPP_TYPE_VIG, 70 .clk_ctrl = DPU_CLK_CTRL_VIG0, 71 }, { 72 .name = "sspp_1", .id = SSPP_VIG1, 73 .base = 0x6000, .len = 0x1ac, 74 .features = VIG_MSM8998_MASK, 75 .sblk = &dpu_vig_sblk_qseed3_1_2, 76 .xin_id = 4, 77 .type = SSPP_TYPE_VIG, 78 .clk_ctrl = DPU_CLK_CTRL_VIG1, 79 }, { 80 .name = "sspp_8", .id = SSPP_DMA0, 81 .base = 0x24000, .len = 0x1ac, 82 .features = DMA_MSM8998_MASK, 83 .sblk = &dpu_dma_sblk, 84 .xin_id = 1, 85 .type = SSPP_TYPE_DMA, 86 .clk_ctrl = DPU_CLK_CTRL_DMA0, 87 }, { 88 .name = "sspp_9", .id = SSPP_DMA1, 89 .base = 0x26000, .len = 0x1ac, 90 .features = DMA_MSM8998_MASK, 91 .sblk = &dpu_dma_sblk, 92 .xin_id = 5, 93 .type = SSPP_TYPE_DMA, 94 .clk_ctrl = DPU_CLK_CTRL_DMA1, 95 }, { 96 .name = "sspp_10", .id = SSPP_DMA2, 97 .base = 0x28000, .len = 0x1ac, 98 .features = DMA_CURSOR_MSM8998_MASK, 99 .sblk = &dpu_dma_sblk, 100 .xin_id = 9, 101 .type = SSPP_TYPE_DMA, 102 .clk_ctrl = DPU_CLK_CTRL_DMA2, 103 }, 104 }; 105 106 static const struct dpu_lm_cfg sdm660_lm[] = { 107 { 108 .name = "lm_0", .id = LM_0, 109 .base = 0x44000, .len = 0x320, 110 .features = MIXER_MSM8998_MASK, 111 .sblk = &msm8998_lm_sblk, 112 .lm_pair = LM_1, 113 .pingpong = PINGPONG_0, 114 .dspp = DSPP_0, 115 }, { 116 .name = "lm_1", .id = LM_1, 117 .base = 0x45000, .len = 0x320, 118 .features = MIXER_MSM8998_MASK, 119 .sblk = &msm8998_lm_sblk, 120 .lm_pair = LM_0, 121 .pingpong = PINGPONG_1, 122 .dspp = DSPP_1, 123 }, { 124 .name = "lm_2", .id = LM_2, 125 .base = 0x46000, .len = 0x320, 126 .features = MIXER_MSM8998_MASK, 127 .sblk = &msm8998_lm_sblk, 128 .lm_pair = LM_5, 129 .pingpong = PINGPONG_2, 130 }, { 131 .name = "lm_5", .id = LM_5, 132 .base = 0x49000, .len = 0x320, 133 .features = MIXER_MSM8998_MASK, 134 .sblk = &msm8998_lm_sblk, 135 .lm_pair = LM_2, 136 .pingpong = PINGPONG_3, 137 }, 138 }; 139 140 static const struct dpu_pingpong_cfg sdm660_pp[] = { 141 { 142 .name = "pingpong_0", .id = PINGPONG_0, 143 .base = 0x70000, .len = 0xd4, 144 .features = PINGPONG_SDM845_TE2_MASK, 145 .sblk = &sdm845_pp_sblk_te, 146 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 147 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), 148 }, { 149 .name = "pingpong_1", .id = PINGPONG_1, 150 .base = 0x70800, .len = 0xd4, 151 .features = PINGPONG_SDM845_TE2_MASK, 152 .sblk = &sdm845_pp_sblk_te, 153 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 154 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), 155 }, { 156 .name = "pingpong_2", .id = PINGPONG_2, 157 .base = 0x71000, .len = 0xd4, 158 .features = PINGPONG_SDM845_MASK, 159 .sblk = &sdm845_pp_sblk, 160 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), 161 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 14), 162 }, { 163 .name = "pingpong_3", .id = PINGPONG_3, 164 .base = 0x71800, .len = 0xd4, 165 .features = PINGPONG_SDM845_MASK, 166 .sblk = &sdm845_pp_sblk, 167 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), 168 .intr_rdptr = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 15), 169 }, 170 }; 171 172 static const struct dpu_dsc_cfg sdm660_dsc[] = { 173 { 174 .name = "dsc_0", .id = DSC_0, 175 .base = 0x80000, .len = 0x140, 176 }, { 177 .name = "dsc_1", .id = DSC_1, 178 .base = 0x80400, .len = 0x140, 179 }, 180 }; 181 182 static const struct dpu_dspp_cfg sdm660_dspp[] = { 183 { 184 .name = "dspp_0", .id = DSPP_0, 185 .base = 0x54000, .len = 0x1800, 186 .features = DSPP_SC7180_MASK, 187 .sblk = &msm8998_dspp_sblk, 188 }, { 189 .name = "dspp_1", .id = DSPP_1, 190 .base = 0x56000, .len = 0x1800, 191 .features = DSPP_SC7180_MASK, 192 .sblk = &msm8998_dspp_sblk, 193 }, 194 }; 195 196 static const struct dpu_intf_cfg sdm660_intf[] = { 197 { 198 .name = "intf_0", .id = INTF_0, 199 .base = 0x6a000, .len = 0x280, 200 .type = INTF_DP, 201 .controller_id = MSM_DP_CONTROLLER_0, 202 .prog_fetch_lines_worst_case = 21, 203 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 204 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 205 .intr_tear_rd_ptr = -1, 206 }, { 207 .name = "intf_1", .id = INTF_1, 208 .base = 0x6a800, .len = 0x280, 209 .type = INTF_DSI, 210 .controller_id = MSM_DSI_CONTROLLER_0, 211 .prog_fetch_lines_worst_case = 21, 212 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 213 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 214 .intr_tear_rd_ptr = -1, 215 }, { 216 .name = "intf_2", .id = INTF_2, 217 .base = 0x6b000, .len = 0x280, 218 .type = INTF_DSI, 219 .controller_id = MSM_DSI_CONTROLLER_1, 220 .prog_fetch_lines_worst_case = 21, 221 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), 222 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), 223 .intr_tear_rd_ptr = -1, 224 }, 225 }; 226 227 static const struct dpu_perf_cfg sdm660_perf_data = { 228 .max_bw_low = 6600000, 229 .max_bw_high = 6600000, 230 .min_core_ib = 3100000, 231 .min_llcc_ib = 800000, 232 .min_dram_ib = 800000, 233 .undersized_prefill_lines = 2, 234 .xtra_prefill_lines = 2, 235 .dest_scale_prefill_lines = 3, 236 .macrotile_prefill_lines = 4, 237 .yuv_nv12_prefill_lines = 8, 238 .linear_prefill_lines = 1, 239 .downscaling_prefill_lines = 1, 240 .amortizable_threshold = 25, 241 .min_prefill_lines = 25, 242 .danger_lut_tbl = {0xf, 0xffff, 0x0}, 243 .safe_lut_tbl = {0xfffc, 0xff00, 0xffff}, 244 .qos_lut_tbl = { 245 {.nentry = ARRAY_SIZE(msm8998_qos_linear), 246 .entries = msm8998_qos_linear 247 }, 248 {.nentry = ARRAY_SIZE(msm8998_qos_macrotile), 249 .entries = msm8998_qos_macrotile 250 }, 251 {.nentry = ARRAY_SIZE(msm8998_qos_nrt), 252 .entries = msm8998_qos_nrt 253 }, 254 }, 255 .cdp_cfg = { 256 {.rd_enable = 1, .wr_enable = 1}, 257 {.rd_enable = 1, .wr_enable = 0} 258 }, 259 .clk_inefficiency_factor = 200, 260 .bw_inefficiency_factor = 120, 261 }; 262 263 static const struct dpu_mdss_version sdm660_mdss_ver = { 264 .core_major_ver = 3, 265 .core_minor_ver = 2, 266 }; 267 268 const struct dpu_mdss_cfg dpu_sdm660_cfg = { 269 .mdss_ver = &sdm660_mdss_ver, 270 .caps = &sdm660_dpu_caps, 271 .mdp = &sdm660_mdp, 272 .ctl_count = ARRAY_SIZE(sdm660_ctl), 273 .ctl = sdm660_ctl, 274 .sspp_count = ARRAY_SIZE(sdm660_sspp), 275 .sspp = sdm660_sspp, 276 .mixer_count = ARRAY_SIZE(sdm660_lm), 277 .mixer = sdm660_lm, 278 .dspp_count = ARRAY_SIZE(sdm660_dspp), 279 .dspp = sdm660_dspp, 280 .pingpong_count = ARRAY_SIZE(sdm660_pp), 281 .pingpong = sdm660_pp, 282 .dsc_count = ARRAY_SIZE(sdm660_dsc), 283 .dsc = sdm660_dsc, 284 .intf_count = ARRAY_SIZE(sdm660_intf), 285 .intf = sdm660_intf, 286 .vbif_count = ARRAY_SIZE(msm8998_vbif), 287 .vbif = msm8998_vbif, 288 .perf = &sdm660_perf_data, 289 }; 290 291 #endif 292