1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved. 4 * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. 5 */ 6 7 #ifndef _DPU_6_2_SC7180_H 8 #define _DPU_6_2_SC7180_H 9 10 static const struct dpu_caps sc7180_dpu_caps = { 11 .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 12 .max_mixer_blendstages = 0x9, 13 .has_dim_layer = true, 14 .has_idle_pc = true, 15 .max_linewidth = DEFAULT_DPU_OUTPUT_LINE_WIDTH, 16 .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, 17 }; 18 19 static const struct dpu_mdp_cfg sc7180_mdp = { 20 .name = "top_0", 21 .base = 0x0, .len = 0x494, 22 .clk_ctrls = { 23 [DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 }, 24 [DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 }, 25 [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, 26 [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, 27 [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, 28 }, 29 }; 30 31 static const struct dpu_ctl_cfg sc7180_ctl[] = { 32 { 33 .name = "ctl_0", .id = CTL_0, 34 .base = 0x1000, .len = 0x1dc, 35 .features = BIT(DPU_CTL_ACTIVE_CFG), 36 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), 37 }, { 38 .name = "ctl_1", .id = CTL_1, 39 .base = 0x1200, .len = 0x1dc, 40 .features = BIT(DPU_CTL_ACTIVE_CFG), 41 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), 42 }, { 43 .name = "ctl_2", .id = CTL_2, 44 .base = 0x1400, .len = 0x1dc, 45 .features = BIT(DPU_CTL_ACTIVE_CFG), 46 .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), 47 }, 48 }; 49 50 static const struct dpu_sspp_cfg sc7180_sspp[] = { 51 { 52 .name = "sspp_0", .id = SSPP_VIG0, 53 .base = 0x4000, .len = 0x1f8, 54 .features = VIG_SDM845_MASK, 55 .sblk = &dpu_vig_sblk_qseed3_3_0, 56 .xin_id = 0, 57 .type = SSPP_TYPE_VIG, 58 .clk_ctrl = DPU_CLK_CTRL_VIG0, 59 }, { 60 .name = "sspp_8", .id = SSPP_DMA0, 61 .base = 0x24000, .len = 0x1f8, 62 .features = DMA_SDM845_MASK, 63 .sblk = &dpu_dma_sblk, 64 .xin_id = 1, 65 .type = SSPP_TYPE_DMA, 66 .clk_ctrl = DPU_CLK_CTRL_DMA0, 67 }, { 68 .name = "sspp_9", .id = SSPP_DMA1, 69 .base = 0x26000, .len = 0x1f8, 70 .features = DMA_CURSOR_SDM845_MASK, 71 .sblk = &dpu_dma_sblk, 72 .xin_id = 5, 73 .type = SSPP_TYPE_DMA, 74 .clk_ctrl = DPU_CLK_CTRL_DMA1, 75 }, { 76 .name = "sspp_10", .id = SSPP_DMA2, 77 .base = 0x28000, .len = 0x1f8, 78 .features = DMA_CURSOR_SDM845_MASK, 79 .sblk = &dpu_dma_sblk, 80 .xin_id = 9, 81 .type = SSPP_TYPE_DMA, 82 .clk_ctrl = DPU_CLK_CTRL_DMA2, 83 }, 84 }; 85 86 static const struct dpu_lm_cfg sc7180_lm[] = { 87 { 88 .name = "lm_0", .id = LM_0, 89 .base = 0x44000, .len = 0x320, 90 .features = MIXER_SDM845_MASK, 91 .sblk = &sc7180_lm_sblk, 92 .lm_pair = LM_1, 93 .pingpong = PINGPONG_0, 94 .dspp = DSPP_0, 95 }, { 96 .name = "lm_1", .id = LM_1, 97 .base = 0x45000, .len = 0x320, 98 .features = MIXER_SDM845_MASK, 99 .sblk = &sc7180_lm_sblk, 100 .lm_pair = LM_0, 101 .pingpong = PINGPONG_1, 102 }, 103 }; 104 105 static const struct dpu_dspp_cfg sc7180_dspp[] = { 106 { 107 .name = "dspp_0", .id = DSPP_0, 108 .base = 0x54000, .len = 0x1800, 109 .features = DSPP_SC7180_MASK, 110 .sblk = &sdm845_dspp_sblk, 111 }, 112 }; 113 114 static const struct dpu_pingpong_cfg sc7180_pp[] = { 115 { 116 .name = "pingpong_0", .id = PINGPONG_0, 117 .base = 0x70000, .len = 0xd4, 118 .features = PINGPONG_SM8150_MASK, 119 .sblk = &sdm845_pp_sblk, 120 .merge_3d = 0, 121 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), 122 }, { 123 .name = "pingpong_1", .id = PINGPONG_1, 124 .base = 0x70800, .len = 0xd4, 125 .features = PINGPONG_SM8150_MASK, 126 .sblk = &sdm845_pp_sblk, 127 .merge_3d = 0, 128 .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), 129 }, 130 }; 131 132 static const struct dpu_intf_cfg sc7180_intf[] = { 133 { 134 .name = "intf_0", .id = INTF_0, 135 .base = 0x6a000, .len = 0x280, 136 .features = INTF_SC7180_MASK, 137 .type = INTF_DP, 138 .controller_id = MSM_DP_CONTROLLER_0, 139 .prog_fetch_lines_worst_case = 24, 140 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), 141 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), 142 }, { 143 .name = "intf_1", .id = INTF_1, 144 .base = 0x6a800, .len = 0x2c0, 145 .features = INTF_SC7180_MASK, 146 .type = INTF_DSI, 147 .controller_id = MSM_DSI_CONTROLLER_0, 148 .prog_fetch_lines_worst_case = 24, 149 .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), 150 .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), 151 .intr_tear_rd_ptr = DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), 152 }, 153 }; 154 155 static const struct dpu_wb_cfg sc7180_wb[] = { 156 { 157 .name = "wb_2", .id = WB_2, 158 .base = 0x65000, .len = 0x2c8, 159 .features = WB_SM8250_MASK, 160 .format_list = wb2_formats_rgb, 161 .num_formats = ARRAY_SIZE(wb2_formats_rgb), 162 .clk_ctrl = DPU_CLK_CTRL_WB2, 163 .xin_id = 6, 164 .vbif_idx = VBIF_RT, 165 .maxlinewidth = 4096, 166 .intr_wb_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), 167 }, 168 }; 169 170 static const struct dpu_perf_cfg sc7180_perf_data = { 171 .max_bw_low = 6800000, 172 .max_bw_high = 6800000, 173 .min_core_ib = 2400000, 174 .min_llcc_ib = 800000, 175 .min_dram_ib = 1600000, 176 .min_prefill_lines = 24, 177 .danger_lut_tbl = {0xff, 0xffff, 0x0}, 178 .safe_lut_tbl = {0xfff0, 0xff00, 0xffff}, 179 .qos_lut_tbl = { 180 {.nentry = ARRAY_SIZE(sc7180_qos_linear), 181 .entries = sc7180_qos_linear 182 }, 183 {.nentry = ARRAY_SIZE(sc7180_qos_macrotile), 184 .entries = sc7180_qos_macrotile 185 }, 186 {.nentry = ARRAY_SIZE(sc7180_qos_nrt), 187 .entries = sc7180_qos_nrt 188 }, 189 }, 190 .cdp_cfg = { 191 {.rd_enable = 1, .wr_enable = 1}, 192 {.rd_enable = 1, .wr_enable = 0} 193 }, 194 .clk_inefficiency_factor = 105, 195 .bw_inefficiency_factor = 120, 196 }; 197 198 static const struct dpu_mdss_version sc7180_mdss_ver = { 199 .core_major_ver = 6, 200 .core_minor_ver = 2, 201 }; 202 203 const struct dpu_mdss_cfg dpu_sc7180_cfg = { 204 .mdss_ver = &sc7180_mdss_ver, 205 .caps = &sc7180_dpu_caps, 206 .mdp = &sc7180_mdp, 207 .ctl_count = ARRAY_SIZE(sc7180_ctl), 208 .ctl = sc7180_ctl, 209 .sspp_count = ARRAY_SIZE(sc7180_sspp), 210 .sspp = sc7180_sspp, 211 .mixer_count = ARRAY_SIZE(sc7180_lm), 212 .mixer = sc7180_lm, 213 .dspp_count = ARRAY_SIZE(sc7180_dspp), 214 .dspp = sc7180_dspp, 215 .pingpong_count = ARRAY_SIZE(sc7180_pp), 216 .pingpong = sc7180_pp, 217 .intf_count = ARRAY_SIZE(sc7180_intf), 218 .intf = sc7180_intf, 219 .wb_count = ARRAY_SIZE(sc7180_wb), 220 .wb = sc7180_wb, 221 .vbif_count = ARRAY_SIZE(sdm845_vbif), 222 .vbif = sdm845_vbif, 223 .perf = &sc7180_perf_data, 224 }; 225 226 #endif 227