1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dm_services.h"
27 #include "core_types.h"
28 #include "reg_helper.h"
29 #include "dcn401/dcn401_dpp.h"
30 #include "basics/conversion.h"
31 #include "dcn30/dcn30_cm_common.h"
32 #include "dcn32/dcn32_dpp.h"
33 #include "dcn35/dcn35_dpp.h"
34
35 #define REG(reg)\
36 dpp->tf_regs->reg
37
38 #define CTX \
39 dpp->base.ctx
40
41 #undef FN
42 #define FN(reg_name, field_name) \
43 dpp->tf_shift->field_name, dpp->tf_mask->field_name
44
dpp401_read_state(struct dpp * dpp_base,struct dcn_dpp_state * s)45 void dpp401_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
46 {
47 struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
48
49 REG_GET(DPP_CONTROL,
50 DPP_CLOCK_ENABLE, &s->is_enabled);
51
52 // TODO: Implement for DCN4
53 }
54
dpp401_dpp_setup(struct dpp * dpp_base,enum surface_pixel_format format,enum expansion_mode mode,struct dc_csc_transform input_csc_color_matrix,enum dc_color_space input_color_space,struct cnv_alpha_2bit_lut * alpha_2bit_lut)55 void dpp401_dpp_setup(
56 struct dpp *dpp_base,
57 enum surface_pixel_format format,
58 enum expansion_mode mode,
59 struct dc_csc_transform input_csc_color_matrix,
60 enum dc_color_space input_color_space,
61 struct cnv_alpha_2bit_lut *alpha_2bit_lut)
62 {
63 struct dcn401_dpp *dpp = TO_DCN401_DPP(dpp_base);
64 uint32_t pixel_format = 0;
65 uint32_t alpha_en = 1;
66 enum dc_color_space color_space = COLOR_SPACE_SRGB;
67 enum dcn10_input_csc_select select = INPUT_CSC_SELECT_BYPASS;
68 uint32_t is_2bit = 0;
69 uint32_t alpha_plane_enable = 0;
70 uint32_t dealpha_en = 0, dealpha_ablnd_en = 0;
71 uint32_t realpha_en = 0, realpha_ablnd_en = 0;
72 struct out_csc_color_matrix tbl_entry;
73 int i;
74
75 REG_SET_2(FORMAT_CONTROL, 0,
76 CNVC_BYPASS, 0,
77 FORMAT_EXPANSION_MODE, mode);
78
79 REG_UPDATE(FORMAT_CONTROL, FORMAT_CNV16, 0);
80 REG_UPDATE(FORMAT_CONTROL, CNVC_BYPASS_MSB_ALIGN, 0);
81 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE, 0);
82 REG_UPDATE(FORMAT_CONTROL, CLAMP_POSITIVE_C, 0);
83
84 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_R, 0);
85 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_G, 1);
86 REG_UPDATE(FORMAT_CONTROL, FORMAT_CROSSBAR_B, 2);
87
88 switch (format) {
89 case SURFACE_PIXEL_FORMAT_GRPH_ARGB1555:
90 pixel_format = 1;
91 break;
92 case SURFACE_PIXEL_FORMAT_GRPH_RGB565:
93 pixel_format = 3;
94 alpha_en = 0;
95 break;
96 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888:
97 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888:
98 pixel_format = 8;
99 break;
100 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010:
101 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010:
102 pixel_format = 10;
103 is_2bit = 1;
104 break;
105 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr:
106 pixel_format = 65;
107 color_space = COLOR_SPACE_YCBCR709;
108 select = INPUT_CSC_SELECT_ICSC;
109 break;
110 case SURFACE_PIXEL_FORMAT_VIDEO_420_YCrCb:
111 pixel_format = 64;
112 color_space = COLOR_SPACE_YCBCR709;
113 select = INPUT_CSC_SELECT_ICSC;
114 break;
115 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCbCr:
116 pixel_format = 67;
117 color_space = COLOR_SPACE_YCBCR709;
118 select = INPUT_CSC_SELECT_ICSC;
119 break;
120 case SURFACE_PIXEL_FORMAT_VIDEO_420_10bpc_YCrCb:
121 pixel_format = 66;
122 color_space = COLOR_SPACE_YCBCR709;
123 select = INPUT_CSC_SELECT_ICSC;
124 break;
125 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616:
126 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616:
127 pixel_format = 26; /* ARGB16161616_UNORM */
128 break;
129 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616F:
130 pixel_format = 24;
131 break;
132 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F:
133 pixel_format = 25;
134 break;
135 case SURFACE_PIXEL_FORMAT_VIDEO_AYCrCb8888:
136 pixel_format = 12;
137 color_space = COLOR_SPACE_YCBCR709;
138 select = INPUT_CSC_SELECT_ICSC;
139 break;
140 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FIX:
141 pixel_format = 112;
142 alpha_en = 0;
143 break;
144 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FIX:
145 pixel_format = 113;
146 alpha_en = 0;
147 break;
148 case SURFACE_PIXEL_FORMAT_VIDEO_ACrYCb2101010:
149 pixel_format = 114;
150 color_space = COLOR_SPACE_YCBCR709;
151 select = INPUT_CSC_SELECT_ICSC;
152 is_2bit = 1;
153 break;
154 case SURFACE_PIXEL_FORMAT_VIDEO_CrYCbA1010102:
155 pixel_format = 115;
156 color_space = COLOR_SPACE_YCBCR709;
157 select = INPUT_CSC_SELECT_ICSC;
158 is_2bit = 1;
159 break;
160 case SURFACE_PIXEL_FORMAT_GRPH_RGBE:
161 pixel_format = 116;
162 alpha_plane_enable = 0;
163 break;
164 case SURFACE_PIXEL_FORMAT_GRPH_RGBE_ALPHA:
165 pixel_format = 116;
166 alpha_plane_enable = 1;
167 break;
168 case SURFACE_PIXEL_FORMAT_GRPH_RGB111110_FLOAT:
169 pixel_format = 118;
170 alpha_en = 0;
171 break;
172 case SURFACE_PIXEL_FORMAT_GRPH_BGR101111_FLOAT:
173 pixel_format = 119;
174 alpha_en = 0;
175 break;
176 default:
177 break;
178 }
179
180 /* Set default color space based on format if none is given. */
181 color_space = input_color_space ? input_color_space : color_space;
182
183 if (is_2bit == 1 && alpha_2bit_lut != NULL) {
184 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT0, alpha_2bit_lut->lut0);
185 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT1, alpha_2bit_lut->lut1);
186 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT2, alpha_2bit_lut->lut2);
187 REG_UPDATE(ALPHA_2BIT_LUT, ALPHA_2BIT_LUT3, alpha_2bit_lut->lut3);
188 }
189
190 REG_SET_2(CNVC_SURFACE_PIXEL_FORMAT, 0,
191 CNVC_SURFACE_PIXEL_FORMAT, pixel_format,
192 CNVC_ALPHA_PLANE_ENABLE, alpha_plane_enable);
193 REG_UPDATE(FORMAT_CONTROL, FORMAT_CONTROL__ALPHA_EN, alpha_en);
194
195 REG_SET_2(PRE_DEALPHA, 0,
196 PRE_DEALPHA_EN, dealpha_en,
197 PRE_DEALPHA_ABLND_EN, dealpha_ablnd_en);
198 REG_SET_2(PRE_REALPHA, 0,
199 PRE_REALPHA_EN, realpha_en,
200 PRE_REALPHA_ABLND_EN, realpha_ablnd_en);
201
202 /* If input adjustment exists, program the ICSC with those values. */
203 if (input_csc_color_matrix.enable_adjustment == true) {
204 for (i = 0; i < 12; i++)
205 tbl_entry.regval[i] = input_csc_color_matrix.matrix[i];
206
207 tbl_entry.color_space = input_color_space;
208
209 if (color_space >= COLOR_SPACE_YCBCR601)
210 select = INPUT_CSC_SELECT_ICSC;
211 else
212 select = INPUT_CSC_SELECT_BYPASS;
213
214 dpp3_program_post_csc(dpp_base, color_space, select,
215 &tbl_entry);
216 } else {
217 dpp3_program_post_csc(dpp_base, color_space, select, NULL);
218 }
219 }
220
221
222 static struct dpp_funcs dcn401_dpp_funcs = {
223 .dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
224 .dpp_read_state = dpp401_read_state,
225 .dpp_reset = dpp_reset,
226 .dpp_set_scaler = dpp401_dscl_set_scaler_manual_scale,
227 .dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
228 .dpp_set_gamut_remap = NULL,
229 .dpp_set_csc_adjustment = NULL,
230 .dpp_set_csc_default = NULL,
231 .dpp_program_regamma_pwl = NULL,
232 .dpp_set_pre_degam = dpp3_set_pre_degam,
233 .dpp_program_input_lut = NULL,
234 .dpp_full_bypass = dpp401_full_bypass,
235 .dpp_setup = dpp401_dpp_setup,
236 .dpp_program_degamma_pwl = NULL,
237 .dpp_program_cm_dealpha = dpp3_program_cm_dealpha,
238 .dpp_program_cm_bias = dpp3_program_cm_bias,
239
240 .dpp_program_blnd_lut = NULL, // BLNDGAM is removed completely in DCN3.2 DPP
241 .dpp_program_shaper_lut = NULL, // CM SHAPER block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
242 .dpp_program_3dlut = NULL, // CM 3DLUT block is removed in DCN3.2 DPP, (it is in MPCC, programmable before or after BLND)
243
244 .dpp_program_bias_and_scale = dpp35_program_bias_and_scale_fcnv,
245 .dpp_cnv_set_alpha_keyer = dpp2_cnv_set_alpha_keyer,
246 .set_cursor_attributes = dpp401_set_cursor_attributes,
247 .set_cursor_position = dpp401_set_cursor_position,
248 .set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes,
249 .dpp_dppclk_control = dpp1_dppclk_control,
250 .dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
251 .set_cursor_matrix = dpp401_set_cursor_matrix,
252 };
253
254
255 static struct dpp_caps dcn401_dpp_cap = {
256 .dscl_data_proc_format = DSCL_DATA_PRCESSING_FLOAT_FORMAT,
257 .max_lb_partitions = 63,
258 .dscl_calc_lb_num_partitions = dscl401_calc_lb_num_partitions,
259 };
260
dpp401_construct(struct dcn401_dpp * dpp,struct dc_context * ctx,uint32_t inst,const struct dcn401_dpp_registers * tf_regs,const struct dcn401_dpp_shift * tf_shift,const struct dcn401_dpp_mask * tf_mask)261 bool dpp401_construct(
262 struct dcn401_dpp *dpp,
263 struct dc_context *ctx,
264 uint32_t inst,
265 const struct dcn401_dpp_registers *tf_regs,
266 const struct dcn401_dpp_shift *tf_shift,
267 const struct dcn401_dpp_mask *tf_mask)
268 {
269 dpp->base.ctx = ctx;
270
271 dpp->base.inst = inst;
272 dpp->base.funcs = &dcn401_dpp_funcs;
273 dpp->base.caps = &dcn401_dpp_cap;
274
275 dpp->tf_regs = tf_regs;
276 dpp->tf_shift = tf_shift;
277 dpp->tf_mask = tf_mask;
278
279 return true;
280 }
281 /* Compute the maximum number of lines that we can fit in the line buffer */
282
dscl401_calc_lb_num_partitions(const struct scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)283 void dscl401_calc_lb_num_partitions(
284 const struct scaler_data *scl_data,
285 enum lb_memory_config lb_config,
286 int *num_part_y,
287 int *num_part_c)
288 {
289 int memory_line_size_y, memory_line_size_c, memory_line_size_a,
290 lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
291
292 int line_size = scl_data->viewport.width < scl_data->recout.width ?
293 scl_data->viewport.width : scl_data->recout.width;
294 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
295 scl_data->viewport_c.width : scl_data->recout.width;
296
297 if (line_size == 0)
298 line_size = 1;
299
300 if (line_size_c == 0)
301 line_size_c = 1;
302
303 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
304 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
305 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
306
307 if (lb_config == LB_MEMORY_CONFIG_1) {
308 lb_memory_size = 970;
309 lb_memory_size_c = 970;
310 lb_memory_size_a = 970;
311 } else if (lb_config == LB_MEMORY_CONFIG_2) {
312 lb_memory_size = 1290;
313 lb_memory_size_c = 1290;
314 lb_memory_size_a = 1290;
315 } else if (lb_config == LB_MEMORY_CONFIG_3) {
316 if (scl_data->viewport.width == scl_data->h_active &&
317 scl_data->viewport.height == scl_data->v_active) {
318 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
319 /* use increased LB size for calculation only if Scaler not enabled */
320 lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;
321 lb_memory_size_c = 970 + 1290;
322 lb_memory_size_a = 970 + 1290 + 1170;
323 } else {
324 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
325 lb_memory_size = 970 + 1290 + 484 + 484 + 484;
326 lb_memory_size_c = 970 + 1290;
327 lb_memory_size_a = 970 + 1290 + 484;
328 }
329 } else {
330 if (scl_data->viewport.width == scl_data->h_active &&
331 scl_data->viewport.height == scl_data->v_active) {
332 /* use increased LB size for calculation only if Scaler not enabled */
333 lb_memory_size = 970 + 1290 + 1170;
334 lb_memory_size_c = 970 + 1290 + 1170;
335 lb_memory_size_a = 970 + 1290 + 1170;
336 } else {
337 lb_memory_size = 970 + 1290 + 484;
338 lb_memory_size_c = 970 + 1290 + 484;
339 lb_memory_size_a = 970 + 1290 + 484;
340 }
341 }
342 *num_part_y = lb_memory_size / memory_line_size_y;
343 *num_part_c = lb_memory_size_c / memory_line_size_c;
344 num_partitions_a = lb_memory_size_a / memory_line_size_a;
345
346 if (scl_data->lb_params.alpha_en
347 && (num_partitions_a < *num_part_y))
348 *num_part_y = num_partitions_a;
349
350 if (*num_part_y > 64)
351 *num_part_y = 64;
352 if (*num_part_c > 64)
353 *num_part_c = 64;
354 }
355
356 /* Compute the maximum number of lines that we can fit in the line buffer */
dscl401_spl_calc_lb_num_partitions(bool alpha_en,const struct spl_scaler_data * scl_data,enum lb_memory_config lb_config,int * num_part_y,int * num_part_c)357 void dscl401_spl_calc_lb_num_partitions(
358 bool alpha_en,
359 const struct spl_scaler_data *scl_data,
360 enum lb_memory_config lb_config,
361 int *num_part_y,
362 int *num_part_c)
363 {
364 int memory_line_size_y, memory_line_size_c, memory_line_size_a,
365 lb_memory_size, lb_memory_size_c, lb_memory_size_a, num_partitions_a;
366
367 int line_size = scl_data->viewport.width < scl_data->recout.width ?
368 scl_data->viewport.width : scl_data->recout.width;
369 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ?
370 scl_data->viewport_c.width : scl_data->recout.width;
371
372 if (line_size == 0)
373 line_size = 1;
374
375 if (line_size_c == 0)
376 line_size_c = 1;
377
378 memory_line_size_y = (line_size + 5) / 6; /* +5 to ceil */
379 memory_line_size_c = (line_size_c + 5) / 6; /* +5 to ceil */
380 memory_line_size_a = (line_size + 5) / 6; /* +5 to ceil */
381
382 if (lb_config == LB_MEMORY_CONFIG_1) {
383 lb_memory_size = 970;
384 lb_memory_size_c = 970;
385 lb_memory_size_a = 970;
386 } else if (lb_config == LB_MEMORY_CONFIG_2) {
387 lb_memory_size = 1290;
388 lb_memory_size_c = 1290;
389 lb_memory_size_a = 1290;
390 } else if (lb_config == LB_MEMORY_CONFIG_3) {
391 if (scl_data->viewport.width == scl_data->h_active &&
392 scl_data->viewport.height == scl_data->v_active) {
393 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
394 /* use increased LB size for calculation only if Scaler not enabled */
395 lb_memory_size = 970 + 1290 + 1170 + 1170 + 1170;
396 lb_memory_size_c = 970 + 1290;
397 lb_memory_size_a = 970 + 1290 + 1170;
398 } else {
399 /* 420 mode: luma using all 3 mem from Y, plus 3rd mem from Cr and Cb */
400 lb_memory_size = 970 + 1290 + 484 + 484 + 484;
401 lb_memory_size_c = 970 + 1290;
402 lb_memory_size_a = 970 + 1290 + 484;
403 }
404 } else {
405 if (scl_data->viewport.width == scl_data->h_active &&
406 scl_data->viewport.height == scl_data->v_active) {
407 /* use increased LB size for calculation only if Scaler not enabled */
408 lb_memory_size = 970 + 1290 + 1170;
409 lb_memory_size_c = 970 + 1290 + 1170;
410 lb_memory_size_a = 970 + 1290 + 1170;
411 } else {
412 lb_memory_size = 970 + 1290 + 484;
413 lb_memory_size_c = 970 + 1290 + 484;
414 lb_memory_size_a = 970 + 1290 + 484;
415 }
416 }
417 *num_part_y = lb_memory_size / memory_line_size_y;
418 *num_part_c = lb_memory_size_c / memory_line_size_c;
419 num_partitions_a = lb_memory_size_a / memory_line_size_a;
420
421 if (alpha_en && (num_partitions_a < *num_part_y))
422 *num_part_y = num_partitions_a;
423
424 if (*num_part_y > 64)
425 *num_part_y = 64;
426 if (*num_part_c > 64)
427 *num_part_c = 64;
428 }
429