1 // SPDX-License-Identifier: MIT
2 //
3 // Copyright 2024 Advanced Micro Devices, Inc.
4
5 #include "dm_services.h"
6 #include "dc.h"
7
8 #include "dcn32/dcn32_init.h"
9 #include "dcn401/dcn401_init.h"
10
11 #include "resource.h"
12 #include "include/irq_service_interface.h"
13 #include "dcn401_resource.h"
14
15 #include "dcn20/dcn20_resource.h"
16 #include "dcn30/dcn30_resource.h"
17 #include "dcn32/dcn32_resource.h"
18 #include "dcn321/dcn321_resource.h"
19
20 #include "dcn10/dcn10_ipp.h"
21 #include "dcn401/dcn401_hubbub.h"
22 #include "dcn401/dcn401_mpc.h"
23 #include "dcn401/dcn401_hubp.h"
24 #include "irq/dcn401/irq_service_dcn401.h"
25 #include "dcn401/dcn401_dpp.h"
26 #include "dcn401/dcn401_optc.h"
27 #include "dcn20/dcn20_hwseq.h"
28 #include "dcn30/dcn30_hwseq.h"
29 #include "dce110/dce110_hwseq.h"
30 #include "dcn20/dcn20_opp.h"
31 #include "dcn401/dcn401_dsc.h"
32 #include "dcn30/dcn30_vpg.h"
33 #include "dcn31/dcn31_vpg.h"
34 #include "dcn30/dcn30_afmt.h"
35 #include "dcn30/dcn30_dio_stream_encoder.h"
36 #include "dcn401/dcn401_dio_stream_encoder.h"
37 #include "dcn31/dcn31_hpo_dp_stream_encoder.h"
38 #include "dcn31/dcn31_hpo_dp_link_encoder.h"
39 #include "dcn32/dcn32_hpo_dp_link_encoder.h"
40 #include "dcn31/dcn31_apg.h"
41 #include "dcn31/dcn31_dio_link_encoder.h"
42 #include "dcn401/dcn401_dio_link_encoder.h"
43 #include "dcn10/dcn10_link_encoder.h"
44 #include "dcn321/dcn321_dio_link_encoder.h"
45 #include "dce/dce_clock_source.h"
46 #include "dce/dce_audio.h"
47 #include "dce/dce_hwseq.h"
48 #include "clk_mgr.h"
49 #include "virtual/virtual_stream_encoder.h"
50 #include "dml/display_mode_vba.h"
51 #include "dcn401/dcn401_dccg.h"
52 #include "dcn10/dcn10_resource.h"
53 #include "link.h"
54 #include "link_enc_cfg.h"
55 #include "dcn31/dcn31_panel_cntl.h"
56
57 #include "dcn30/dcn30_dwb.h"
58 #include "dcn32/dcn32_mmhubbub.h"
59
60 #include "dcn/dcn_4_1_0_offset.h"
61 #include "dcn/dcn_4_1_0_sh_mask.h"
62 #include "nbif/nbif_6_3_1_offset.h"
63
64 #include "reg_helper.h"
65 #include "dce/dmub_abm.h"
66 #include "dce/dmub_psr.h"
67 #include "dce/dce_aux.h"
68 #include "dce/dce_i2c.h"
69
70 #include "dml/dcn30/display_mode_vba_30.h"
71 #include "vm_helper.h"
72 #include "dcn20/dcn20_vmid.h"
73 #include "dml/dcn401/dcn401_fpu.h"
74
75 #include "dc_state_priv.h"
76
77 #include "dml2/dml2_wrapper.h"
78
79 #include "spl/dc_spl_scl_easf_filters.h"
80 #include "spl/dc_spl_isharp_filters.h"
81
82 #define DC_LOGGER_INIT(logger)
83
84 enum dcn401_clk_src_array_id {
85 DCN401_CLK_SRC_PLL0,
86 DCN401_CLK_SRC_PLL1,
87 DCN401_CLK_SRC_PLL2,
88 DCN401_CLK_SRC_PLL3,
89 //DCN401_CLK_SRC_PLL4,
90 DCN401_CLK_SRC_TOTAL
91 };
92
93 /* begin *********************
94 * macros to expend register list macro defined in HW object header file
95 */
96
97 /* DCN */
98 #define BASE_INNER(seg) ctx->dcn_reg_offsets[seg]
99
100 #define BASE(seg) BASE_INNER(seg)
101
102 #define SR(reg_name)\
103 REG_STRUCT.reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
104 reg ## reg_name
105 #define SR_ARR(reg_name, id)\
106 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
107 reg ## reg_name
108 #define SR_ARR_INIT(reg_name, id, value)\
109 REG_STRUCT[id].reg_name = value
110
111 #define SRI(reg_name, block, id)\
112 REG_STRUCT.reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
113 reg ## block ## id ## _ ## reg_name
114
115 #define SRI_ARR(reg_name, block, id)\
116 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
117 reg ## block ## id ## _ ## reg_name
118
119 /*
120 * Used when a reg_name would otherwise begin with an integer
121 */
122 #define SRI_ARR_US(reg_name, block, id)\
123 REG_STRUCT[id].reg_name = BASE(reg ## block ## id ## reg_name ## _BASE_IDX) + \
124 reg ## block ## id ## reg_name
125 #define SR_ARR_I2C(reg_name, id) \
126 REG_STRUCT[id-1].reg_name = BASE(reg##reg_name##_BASE_IDX) + reg##reg_name
127
128 #define SRI_ARR_I2C(reg_name, block, id)\
129 REG_STRUCT[id-1].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
130 reg ## block ## id ## _ ## reg_name
131
132 #define SRI_ARR_ALPHABET(reg_name, block, index, id)\
133 REG_STRUCT[index].reg_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
134 reg ## block ## id ## _ ## reg_name
135
136 #define SRI2(reg_name, block, id)\
137 .reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
138 reg ## reg_name
139 #define SRI2_ARR(reg_name, block, id)\
140 REG_STRUCT[id].reg_name = BASE(reg ## reg_name ## _BASE_IDX) + \
141 reg ## reg_name
142
143 #define SRIR(var_name, reg_name, block, id)\
144 .var_name = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
145 reg ## block ## id ## _ ## reg_name
146
147 #define SRII(reg_name, block, id)\
148 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
149 reg ## block ## id ## _ ## reg_name
150
151 #define SRII_ARR_2(reg_name, block, id, inst)\
152 REG_STRUCT[inst].reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
153 reg ## block ## id ## _ ## reg_name
154
155 #define SRII_MPC_RMU(reg_name, block, id)\
156 .RMU##_##reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
157 reg ## block ## id ## _ ## reg_name
158
159 #define SRII_DWB(reg_name, temp_name, block, id)\
160 REG_STRUCT.reg_name[id] = BASE(reg ## block ## id ## _ ## temp_name ## _BASE_IDX) + \
161 reg ## block ## id ## _ ## temp_name
162
163 #define DCCG_SRII(reg_name, block, id)\
164 REG_STRUCT.block ## _ ## reg_name[id] = BASE(reg ## block ## id ## _ ## reg_name ## _BASE_IDX) + \
165 reg ## block ## id ## _ ## reg_name
166
167 #define SF_DWB2(reg_name, block, id, field_name, post_fix) \
168 .field_name = reg_name ## __ ## field_name ## post_fix
169
170 #define VUPDATE_SRII(reg_name, block, id)\
171 REG_STRUCT.reg_name[id] = BASE(reg ## reg_name ## _ ## block ## id ## _BASE_IDX) + \
172 reg ## reg_name ## _ ## block ## id
173
174 /* NBIO */
175 #define NBIO_BASE_INNER(seg) ctx->nbio_reg_offsets[seg]
176
177 #define NBIO_BASE(seg) \
178 NBIO_BASE_INNER(seg)
179
180 #define NBIO_SR(reg_name)\
181 REG_STRUCT.reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
182 regBIF_BX0_ ## reg_name
183 #define NBIO_SR_ARR(reg_name, id)\
184 REG_STRUCT[id].reg_name = NBIO_BASE(regBIF_BX0_ ## reg_name ## _BASE_IDX) + \
185 regBIF_BX0_ ## reg_name
186
187 #define CTX ctx
188 #define REG(reg_name) \
189 (ctx->dcn_reg_offsets[reg ## reg_name ## _BASE_IDX] + reg ## reg_name)
190
191 static struct bios_registers bios_regs;
192
193 #define bios_regs_init() \
194 NBIO_SR(BIOS_SCRATCH_3),\
195 NBIO_SR(BIOS_SCRATCH_6)
196
197 #define clk_src_regs_init(index, pllid)\
198 CS_COMMON_REG_LIST_DCN3_0_RI(index, pllid)
199
200 static struct dce110_clk_src_regs clk_src_regs[5];
201
202 static const struct dce110_clk_src_shift cs_shift = {
203 CS_COMMON_MASK_SH_LIST_DCN3_2(__SHIFT)
204 };
205
206 static const struct dce110_clk_src_mask cs_mask = {
207 CS_COMMON_MASK_SH_LIST_DCN3_2(_MASK)
208 };
209
210 #define abm_regs_init(id)\
211 ABM_DCN401_REG_LIST_RI(id)
212
213 static struct dce_abm_registers abm_regs[4];
214
215 static const struct dce_abm_shift abm_shift = {
216 ABM_MASK_SH_LIST_DCN401(__SHIFT)
217 };
218
219 static const struct dce_abm_mask abm_mask = {
220 ABM_MASK_SH_LIST_DCN401(_MASK)
221 };
222
223 #define audio_regs_init(id)\
224 AUD_COMMON_REG_LIST_RI(id)
225
226 static struct dce_audio_registers audio_regs[5];
227
228 #define DCE120_AUD_COMMON_MASK_SH_LIST(mask_sh)\
229 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_INDEX, AZALIA_ENDPOINT_REG_INDEX, mask_sh),\
230 SF(AZF0ENDPOINT0_AZALIA_F0_CODEC_ENDPOINT_DATA, AZALIA_ENDPOINT_REG_DATA, mask_sh),\
231 AUD_COMMON_MASK_SH_LIST_BASE(mask_sh)
232
233 static const struct dce_audio_shift audio_shift = {
234 DCE120_AUD_COMMON_MASK_SH_LIST(__SHIFT)
235 };
236
237 static const struct dce_audio_mask audio_mask = {
238 DCE120_AUD_COMMON_MASK_SH_LIST(_MASK)
239 };
240
241 #define vpg_regs_init(id)\
242 VPG_DCN401_REG_LIST_RI(id)
243
244 static struct dcn31_vpg_registers vpg_regs[9];
245
246 static const struct dcn31_vpg_shift vpg_shift = {
247 DCN31_VPG_MASK_SH_LIST(__SHIFT)
248 };
249
250 static const struct dcn31_vpg_mask vpg_mask = {
251 DCN31_VPG_MASK_SH_LIST(_MASK)
252 };
253
254 #define afmt_regs_init(id)\
255 AFMT_DCN3_REG_LIST_RI(id)
256
257 static struct dcn30_afmt_registers afmt_regs[5];
258
259 static const struct dcn30_afmt_shift afmt_shift = {
260 DCN3_AFMT_MASK_SH_LIST(__SHIFT)
261 };
262
263 static const struct dcn30_afmt_mask afmt_mask = {
264 DCN3_AFMT_MASK_SH_LIST(_MASK)
265 };
266
267 #define apg_regs_init(id)\
268 APG_DCN31_REG_LIST_RI(id)
269
270 static struct dcn31_apg_registers apg_regs[4];
271
272 static const struct dcn31_apg_shift apg_shift = {
273 DCN31_APG_MASK_SH_LIST(__SHIFT)
274 };
275
276 static const struct dcn31_apg_mask apg_mask = {
277 DCN31_APG_MASK_SH_LIST(_MASK)
278 };
279
280 #define stream_enc_regs_init(id)\
281 SE_DCN4_01_REG_LIST_RI(id)
282
283 static struct dcn10_stream_enc_registers stream_enc_regs[4];
284
285 static const struct dcn10_stream_encoder_shift se_shift = {
286 SE_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
287 };
288
289 static const struct dcn10_stream_encoder_mask se_mask = {
290 SE_COMMON_MASK_SH_LIST_DCN401(_MASK)
291 };
292
293 #define aux_regs_init(id)\
294 DCN2_AUX_REG_LIST_RI(id)
295
296 static struct dcn10_link_enc_aux_registers link_enc_aux_regs[5];
297
298 #define hpd_regs_init(id)\
299 HPD_REG_LIST_RI(id)
300
301 static struct dcn10_link_enc_hpd_registers link_enc_hpd_regs[5];
302
303 #define link_regs_init(id, phyid)\
304 LE_DCN401_REG_LIST_RI(id)
305
306 static struct dcn10_link_enc_registers link_enc_regs[4];
307
308
309 static const struct dcn10_link_enc_shift le_shift = {
310 LINK_ENCODER_MASK_SH_LIST_DCN401(__SHIFT)
311 };
312
313
314 static const struct dcn10_link_enc_mask le_mask = {
315 LINK_ENCODER_MASK_SH_LIST_DCN401(_MASK)
316 };
317
318
319 #define hpo_dp_stream_encoder_reg_init(id)\
320 DCN3_1_HPO_DP_STREAM_ENC_REG_LIST_RI(id)
321
322 static struct dcn31_hpo_dp_stream_encoder_registers hpo_dp_stream_enc_regs[4];
323
324 static const struct dcn31_hpo_dp_stream_encoder_shift hpo_dp_se_shift = {
325 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(__SHIFT)
326 };
327
328 static const struct dcn31_hpo_dp_stream_encoder_mask hpo_dp_se_mask = {
329 DCN3_1_HPO_DP_STREAM_ENC_MASK_SH_LIST(_MASK)
330 };
331
332
333 #define hpo_dp_link_encoder_reg_init(id)\
334 DCN3_1_HPO_DP_LINK_ENC_REG_LIST_RI(id)
335 /*DCN3_1_RDPCSTX_REG_LIST(0),*/
336 /*DCN3_1_RDPCSTX_REG_LIST(1),*/
337 /*DCN3_1_RDPCSTX_REG_LIST(2),*/
338 /*DCN3_1_RDPCSTX_REG_LIST(3),*/
339
340 static struct dcn31_hpo_dp_link_encoder_registers hpo_dp_link_enc_regs[4];
341
342 static const struct dcn31_hpo_dp_link_encoder_shift hpo_dp_le_shift = {
343 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(__SHIFT)
344 };
345
346 static const struct dcn31_hpo_dp_link_encoder_mask hpo_dp_le_mask = {
347 DCN3_2_HPO_DP_LINK_ENC_MASK_SH_LIST(_MASK)
348 };
349
350 #define dpp_regs_init(id)\
351 DPP_REG_LIST_DCN401_COMMON_RI(id)
352
353 static struct dcn401_dpp_registers dpp_regs[4];
354
355 static const struct dcn401_dpp_shift tf_shift = {
356 DPP_REG_LIST_SH_MASK_DCN401_COMMON(__SHIFT)
357 };
358
359 static const struct dcn401_dpp_mask tf_mask = {
360 DPP_REG_LIST_SH_MASK_DCN401_COMMON(_MASK)
361 };
362
363 #define opp_regs_init(id)\
364 OPP_REG_LIST_DCN401_RI(id)
365
366 static struct dcn20_opp_registers opp_regs[4];
367
368 static const struct dcn20_opp_shift opp_shift = {
369 OPP_MASK_SH_LIST_DCN20(__SHIFT)
370 };
371
372 static const struct dcn20_opp_mask opp_mask = {
373 OPP_MASK_SH_LIST_DCN20(_MASK)
374 };
375
376 #define aux_engine_regs_init(id) \
377 AUX_COMMON_REG_LIST0_RI(id), SR_ARR_INIT(AUXN_IMPCAL, id, 0), \
378 SR_ARR_INIT(AUXP_IMPCAL, id, 0), \
379 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK), \
380 SR_ARR_INIT(AUX_RESET_MASK, id, DP_AUX0_AUX_CONTROL__AUX_RESET_MASK)
381
382 static struct dce110_aux_registers aux_engine_regs[5];
383
384 static const struct dce110_aux_registers_shift aux_shift = {
385 DCN_AUX_MASK_SH_LIST(__SHIFT)
386 };
387
388 static const struct dce110_aux_registers_mask aux_mask = {
389 DCN_AUX_MASK_SH_LIST(_MASK)
390 };
391
392 #define dwbc_regs_dcn401_init(id)\
393 DWBC_COMMON_REG_LIST_DCN30_RI(id)
394
395 static struct dcn30_dwbc_registers dwbc401_regs[1];
396
397 static const struct dcn30_dwbc_shift dwbc401_shift = {
398 DWBC_COMMON_MASK_SH_LIST_DCN30(__SHIFT)
399 };
400
401 static const struct dcn30_dwbc_mask dwbc401_mask = {
402 DWBC_COMMON_MASK_SH_LIST_DCN30(_MASK)
403 };
404
405
406 #define mcif_wb_regs_dcn3_init(id)\
407 MCIF_WB_COMMON_REG_LIST_DCN32_RI(id)
408
409 static struct dcn30_mmhubbub_registers mcif_wb30_regs[1];
410
411 static const struct dcn30_mmhubbub_shift mcif_wb30_shift = {
412 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(__SHIFT)
413 };
414
415 static const struct dcn30_mmhubbub_mask mcif_wb30_mask = {
416 MCIF_WB_COMMON_MASK_SH_LIST_DCN32(_MASK)
417 };
418
419 #define dsc_regs_init(id)\
420 DSC_REG_LIST_DCN401_RI(id)
421
422 static struct dcn401_dsc_registers dsc_regs[4];
423
424 static const struct dcn401_dsc_shift dsc_shift = {
425 DSC_REG_LIST_SH_MASK_DCN401(__SHIFT)
426 };
427
428 static const struct dcn401_dsc_mask dsc_mask = {
429 DSC_REG_LIST_SH_MASK_DCN401(_MASK)
430 };
431
432 static struct dcn401_mpc_registers mpc_regs;
433
434 #define dcn_mpc_regs_init()\
435 MPC_REG_LIST_DCN4_01_RI(0),\
436 MPC_REG_LIST_DCN4_01_RI(1),\
437 MPC_REG_LIST_DCN4_01_RI(2),\
438 MPC_REG_LIST_DCN4_01_RI(3),\
439 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(0),\
440 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(1),\
441 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(2),\
442 MPC_OUT_MUX_REG_LIST_DCN3_0_RI(3),\
443 MPC_DWB_MUX_REG_LIST_DCN3_0_RI(0)
444
445 static const struct dcn401_mpc_shift mpc_shift = {
446 MPC_COMMON_MASK_SH_LIST_DCN4_01(__SHIFT)
447 };
448
449 static const struct dcn401_mpc_mask mpc_mask = {
450 MPC_COMMON_MASK_SH_LIST_DCN4_01(_MASK)
451 };
452
453 #define optc_regs_init(id)\
454 OPTC_COMMON_REG_LIST_DCN401_RI(id)
455
456 static struct dcn_optc_registers optc_regs[4];
457
458 static const struct dcn_optc_shift optc_shift = {
459 OPTC_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
460 };
461
462 static const struct dcn_optc_mask optc_mask = {
463 OPTC_COMMON_MASK_SH_LIST_DCN401(_MASK)
464 };
465
466 #define hubp_regs_init(id)\
467 HUBP_REG_LIST_DCN401_RI(id)
468
469 static struct dcn_hubp2_registers hubp_regs[4];
470
471 static const struct dcn_hubp2_shift hubp_shift = {
472 HUBP_MASK_SH_LIST_DCN401(__SHIFT)
473 };
474
475 static const struct dcn_hubp2_mask hubp_mask = {
476 HUBP_MASK_SH_LIST_DCN401(_MASK)
477 };
478
479 static struct dcn_hubbub_registers hubbub_reg;
480 #define hubbub_reg_init()\
481 HUBBUB_REG_LIST_DCN4_01_RI(0)
482
483 static const struct dcn_hubbub_shift hubbub_shift = {
484 HUBBUB_MASK_SH_LIST_DCN4_01(__SHIFT)
485 };
486
487 static const struct dcn_hubbub_mask hubbub_mask = {
488 HUBBUB_MASK_SH_LIST_DCN4_01(_MASK)
489 };
490
491 static struct dccg_registers dccg_regs;
492
493 #define dccg_regs_init()\
494 DCCG_REG_LIST_DCN401_RI()
495
496 static const struct dccg_shift dccg_shift = {
497 DCCG_MASK_SH_LIST_DCN401(__SHIFT)
498 };
499
500 static const struct dccg_mask dccg_mask = {
501 DCCG_MASK_SH_LIST_DCN401(_MASK)
502 };
503
504 #define SRII2(reg_name_pre, reg_name_post, id)\
505 .reg_name_pre ## _ ## reg_name_post[id] = BASE(reg ## reg_name_pre \
506 ## id ## _ ## reg_name_post ## _BASE_IDX) + \
507 reg ## reg_name_pre ## id ## _ ## reg_name_post
508
509
510 #define HWSEQ_DCN401_REG_LIST()\
511 SR(DCHUBBUB_GLOBAL_TIMER_CNTL), \
512 SR(DIO_MEM_PWR_CTRL), \
513 SR(ODM_MEM_PWR_CTRL3), \
514 SR(MMHUBBUB_MEM_PWR_CNTL), \
515 SR(DCCG_GATE_DISABLE_CNTL), \
516 SR(DCCG_GATE_DISABLE_CNTL2), \
517 SR(DCFCLK_CNTL),\
518 SR(DC_MEM_GLOBAL_PWR_REQ_CNTL), \
519 SRII(PIXEL_RATE_CNTL, OTG, 0), \
520 SRII(PIXEL_RATE_CNTL, OTG, 1),\
521 SRII(PIXEL_RATE_CNTL, OTG, 2),\
522 SRII(PIXEL_RATE_CNTL, OTG, 3),\
523 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 0),\
524 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 1),\
525 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 2),\
526 SRII(PHYPLL_PIXEL_RATE_CNTL, OTG, 3),\
527 SR(MICROSECOND_TIME_BASE_DIV), \
528 SR(MILLISECOND_TIME_BASE_DIV), \
529 SR(DISPCLK_FREQ_CHANGE_CNTL), \
530 SR(RBBMIF_TIMEOUT_DIS), \
531 SR(RBBMIF_TIMEOUT_DIS_2), \
532 SR(DCHUBBUB_CRC_CTRL), \
533 SR(DPP_TOP0_DPP_CRC_CTRL), \
534 SR(DPP_TOP0_DPP_CRC_VAL_B_A), \
535 SR(DPP_TOP0_DPP_CRC_VAL_R_G), \
536 SR(MPC_CRC_CTRL), \
537 SR(MPC_CRC_RESULT_GB), \
538 SR(MPC_CRC_RESULT_C), \
539 SR(MPC_CRC_RESULT_AR), \
540 SR(DOMAIN0_PG_CONFIG), \
541 SR(DOMAIN1_PG_CONFIG), \
542 SR(DOMAIN2_PG_CONFIG), \
543 SR(DOMAIN3_PG_CONFIG), \
544 SR(DOMAIN16_PG_CONFIG), \
545 SR(DOMAIN17_PG_CONFIG), \
546 SR(DOMAIN18_PG_CONFIG), \
547 SR(DOMAIN19_PG_CONFIG), \
548 SR(DOMAIN22_PG_CONFIG), \
549 SR(DOMAIN23_PG_CONFIG), \
550 SR(DOMAIN24_PG_CONFIG), \
551 SR(DOMAIN25_PG_CONFIG), \
552 SR(DOMAIN0_PG_STATUS), \
553 SR(DOMAIN1_PG_STATUS), \
554 SR(DOMAIN2_PG_STATUS), \
555 SR(DOMAIN3_PG_STATUS), \
556 SR(DOMAIN16_PG_STATUS), \
557 SR(DOMAIN17_PG_STATUS), \
558 SR(DOMAIN18_PG_STATUS), \
559 SR(DOMAIN19_PG_STATUS), \
560 SR(DOMAIN22_PG_STATUS), \
561 SR(DOMAIN23_PG_STATUS), \
562 SR(DOMAIN24_PG_STATUS), \
563 SR(DOMAIN25_PG_STATUS), \
564 SR(DC_IP_REQUEST_CNTL), \
565 SR(AZALIA_AUDIO_DTO), \
566 SR(HPO_TOP_HW_CONTROL),\
567 SR(AZALIA_CONTROLLER_CLOCK_GATING)
568
569 static struct dce_hwseq_registers hwseq_reg;
570
571 #define hwseq_reg_init()\
572 HWSEQ_DCN401_REG_LIST()
573
574 #define HWSEQ_DCN401_MASK_SH_LIST(mask_sh)\
575 HWSEQ_DCN_MASK_SH_LIST(mask_sh), \
576 HWS_SF(, DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, mask_sh), \
577 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
578 HWS_SF(, DOMAIN0_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
579 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
580 HWS_SF(, DOMAIN1_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
581 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
582 HWS_SF(, DOMAIN2_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
583 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
584 HWS_SF(, DOMAIN3_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
585 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
586 HWS_SF(, DOMAIN16_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
587 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
588 HWS_SF(, DOMAIN17_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
589 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
590 HWS_SF(, DOMAIN18_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
591 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
592 HWS_SF(, DOMAIN19_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
593 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
594 HWS_SF(, DOMAIN22_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
595 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
596 HWS_SF(, DOMAIN23_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
597 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
598 HWS_SF(, DOMAIN24_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
599 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_FORCEON, mask_sh), \
600 HWS_SF(, DOMAIN25_PG_CONFIG, DOMAIN_POWER_GATE, mask_sh), \
601 HWS_SF(, DOMAIN0_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
602 HWS_SF(, DOMAIN1_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
603 HWS_SF(, DOMAIN2_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
604 HWS_SF(, DOMAIN3_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
605 HWS_SF(, DOMAIN16_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
606 HWS_SF(, DOMAIN17_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
607 HWS_SF(, DOMAIN18_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
608 HWS_SF(, DOMAIN19_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
609 HWS_SF(, DOMAIN22_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
610 HWS_SF(, DOMAIN23_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
611 HWS_SF(, DOMAIN24_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
612 HWS_SF(, DOMAIN25_PG_STATUS, DOMAIN_PGFSM_PWR_STATUS, mask_sh), \
613 HWS_SF(, DC_IP_REQUEST_CNTL, IP_REQUEST_EN, mask_sh), \
614 HWS_SF(, AZALIA_AUDIO_DTO, AZALIA_AUDIO_DTO_MODULE, mask_sh), \
615 HWS_SF(, HPO_TOP_CLOCK_CONTROL, HPO_HDMISTREAMCLK_G_GATE_DIS, mask_sh), \
616 HWS_SF(, HPO_TOP_HW_CONTROL, HPO_IO_EN, mask_sh), \
617 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_UNASSIGNED_PWR_MODE, mask_sh), \
618 HWS_SF(, ODM_MEM_PWR_CTRL3, ODM_MEM_VBLANK_PWR_MODE, mask_sh)
619
620 static const struct dce_hwseq_shift hwseq_shift = {
621 HWSEQ_DCN401_MASK_SH_LIST(__SHIFT)
622 };
623
624 static const struct dce_hwseq_mask hwseq_mask = {
625 HWSEQ_DCN401_MASK_SH_LIST(_MASK)
626 };
627
628 #define vmid_regs_init(id)\
629 DCN20_VMID_REG_LIST_RI(id)
630
631 static struct dcn_vmid_registers vmid_regs[16];
632
633 static const struct dcn20_vmid_shift vmid_shifts = {
634 DCN20_VMID_MASK_SH_LIST(__SHIFT)
635 };
636
637 static const struct dcn20_vmid_mask vmid_masks = {
638 DCN20_VMID_MASK_SH_LIST(_MASK)
639 };
640
641 static const struct resource_caps res_cap_dcn4_01 = {
642 .num_timing_generator = 4,
643 .num_opp = 4,
644 .num_video_plane = 4,
645 .num_audio = 4,
646 .num_stream_encoder = 4,
647 .num_hpo_dp_stream_encoder = 4,
648 .num_hpo_dp_link_encoder = 4,
649 .num_pll = 4,
650 .num_dwb = 1,
651 .num_ddc = 4,
652 .num_vmid = 16,
653 .num_mpc_3dlut = 4,
654 .num_dsc = 4,
655 };
656
657 static const struct dc_plane_cap plane_cap = {
658 .type = DC_PLANE_TYPE_DCN_UNIVERSAL,
659 .per_pixel_alpha = true,
660
661 .pixel_format_support = {
662 .argb8888 = true,
663 .nv12 = true,
664 .fp16 = true,
665 .p010 = true,
666 .ayuv = false,
667 },
668
669 .max_upscale_factor = {
670 .argb8888 = 16000,
671 .nv12 = 16000,
672 .fp16 = 16000
673 },
674
675 // 6:1 downscaling ratio: 1000/6 = 166.666
676 .max_downscale_factor = {
677 .argb8888 = 167,
678 .nv12 = 167,
679 .fp16 = 167
680 },
681 64,
682 64
683 };
684
685 static const struct dc_debug_options debug_defaults_drv = {
686 .disable_dmcu = true,
687 .force_abm_enable = false,
688 .timing_trace = false,
689 .clock_trace = true,
690 .disable_pplib_clock_request = false,
691 .pipe_split_policy = MPC_SPLIT_AVOID,
692 .force_single_disp_pipe_split = false,
693 .disable_dcc = DCC_ENABLE,
694 .vsr_support = true,
695 .performance_trace = false,
696 .max_downscale_src_width = 7680,/*upto 8K*/
697 .disable_pplib_wm_range = false,
698 .scl_reset_length10 = true,
699 .sanity_checks = false,
700 .underflow_assert_delay_us = 0xFFFFFFFF,
701 .dwb_fi_phase = -1, // -1 = disable,
702 .dmub_command_table = true,
703 .enable_mem_low_power = {
704 .bits = {
705 .vga = false,
706 .i2c = false,
707 .dmcu = false, // This is previously known to cause hang on S3 cycles if enabled
708 .dscl = false,
709 .cm = false,
710 .mpc = false,
711 .optc = true,
712 }
713 },
714 .use_max_lb = true,
715 .force_disable_subvp = false,
716 .exit_idle_opt_for_cursor_updates = true,
717 .using_dml2 = true,
718 .using_dml21 = true,
719 .enable_single_display_2to1_odm_policy = true,
720
721 //must match enable_single_display_2to1_odm_policy to support dynamic ODM transitions
722 .enable_double_buffered_dsc_pg_support = true,
723 .enable_dp_dig_pixel_rate_div_policy = 1,
724 .allow_sw_cursor_fallback = false,
725 .alloc_extra_way_for_cursor = true,
726 .min_prefetch_in_strobe_ns = 60000, // 60us
727 .disable_unbounded_requesting = false,
728 .enable_legacy_fast_update = false,
729 .dcc_meta_propagation_delay_us = 10,
730 .fams2_config = {
731 .bits = {
732 .enable = true,
733 .enable_offload_flip = true,
734 .enable_stall_recovery = true,
735 }
736 },
737 .force_cositing = CHROMA_COSITING_TOPLEFT + 1,
738 };
739
dcn401_aux_engine_create(struct dc_context * ctx,uint32_t inst)740 static struct dce_aux *dcn401_aux_engine_create(
741 struct dc_context *ctx,
742 uint32_t inst)
743 {
744 struct aux_engine_dce110 *aux_engine =
745 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
746
747 if (!aux_engine)
748 return NULL;
749
750 #undef REG_STRUCT
751 #define REG_STRUCT aux_engine_regs
752 aux_engine_regs_init(0),
753 aux_engine_regs_init(1),
754 aux_engine_regs_init(2),
755 aux_engine_regs_init(3);
756
757 dce110_aux_engine_construct(aux_engine, ctx, inst,
758 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
759 &aux_engine_regs[inst],
760 &aux_mask,
761 &aux_shift,
762 ctx->dc->caps.extended_aux_timeout_support);
763
764 return &aux_engine->base;
765 }
766 #define i2c_inst_regs_init(id)\
767 I2C_HW_ENGINE_COMMON_REG_LIST_DCN30_RI(id)
768
769 static struct dce_i2c_registers i2c_hw_regs[5];
770
771 static const struct dce_i2c_shift i2c_shifts = {
772 I2C_COMMON_MASK_SH_LIST_DCN401(__SHIFT)
773 };
774
775 static const struct dce_i2c_mask i2c_masks = {
776 I2C_COMMON_MASK_SH_LIST_DCN401(_MASK)
777 };
778
dcn401_i2c_hw_create(struct dc_context * ctx,uint32_t inst)779 static struct dce_i2c_hw *dcn401_i2c_hw_create(
780 struct dc_context *ctx,
781 uint32_t inst)
782 {
783 struct dce_i2c_hw *dce_i2c_hw =
784 kzalloc(sizeof(struct dce_i2c_hw), GFP_KERNEL);
785
786 if (!dce_i2c_hw)
787 return NULL;
788
789 #undef REG_STRUCT
790 #define REG_STRUCT i2c_hw_regs
791 i2c_inst_regs_init(1),
792 i2c_inst_regs_init(2),
793 i2c_inst_regs_init(3),
794 i2c_inst_regs_init(4);
795
796 dcn2_i2c_hw_construct(dce_i2c_hw, ctx, inst,
797 &i2c_hw_regs[inst], &i2c_shifts, &i2c_masks);
798
799 return dce_i2c_hw;
800 }
801
dcn401_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)802 static struct clock_source *dcn401_clock_source_create(
803 struct dc_context *ctx,
804 struct dc_bios *bios,
805 enum clock_source_id id,
806 const struct dce110_clk_src_regs *regs,
807 bool dp_clk_src)
808 {
809 struct dce110_clk_src *clk_src =
810 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
811
812 if (!clk_src)
813 return NULL;
814
815 if (dcn401_clk_src_construct(clk_src, ctx, bios, id,
816 regs, &cs_shift, &cs_mask)) {
817 clk_src->base.dp_clk_src = dp_clk_src;
818 return &clk_src->base;
819 }
820
821 kfree(clk_src);
822 BREAK_TO_DEBUGGER();
823 return NULL;
824 }
825
dcn401_hubbub_create(struct dc_context * ctx)826 static struct hubbub *dcn401_hubbub_create(struct dc_context *ctx)
827 {
828 int i;
829
830 struct dcn20_hubbub *hubbub2 = kzalloc(sizeof(struct dcn20_hubbub),
831 GFP_KERNEL);
832
833 if (!hubbub2)
834 return NULL;
835
836
837 #undef REG_STRUCT
838 #define REG_STRUCT hubbub_reg
839 hubbub_reg_init();
840
841 #undef REG_STRUCT
842 #define REG_STRUCT vmid_regs
843 vmid_regs_init(0),
844 vmid_regs_init(1),
845 vmid_regs_init(2),
846 vmid_regs_init(3),
847 vmid_regs_init(4),
848 vmid_regs_init(5),
849 vmid_regs_init(6),
850 vmid_regs_init(7),
851 vmid_regs_init(8),
852 vmid_regs_init(9),
853 vmid_regs_init(10),
854 vmid_regs_init(11),
855 vmid_regs_init(12),
856 vmid_regs_init(13),
857 vmid_regs_init(14),
858 vmid_regs_init(15);
859
860 hubbub401_construct(hubbub2, ctx,
861 &hubbub_reg,
862 &hubbub_shift,
863 &hubbub_mask,
864 DCN4_01_DEFAULT_DET_SIZE, //nominal (default) detile buffer size in kbytes,
865 8, //dml2 ip_params_st.pixel_chunk_size_kbytes
866 DCN4_01_CRB_SIZE_KB); //dml2 ip_params_st.config_return_buffer_size_in_kbytes
867
868 for (i = 0; i < res_cap_dcn4_01.num_vmid; i++) {
869 struct dcn20_vmid *vmid = &hubbub2->vmid[i];
870
871 vmid->ctx = ctx;
872
873 vmid->regs = &vmid_regs[i];
874 vmid->shifts = &vmid_shifts;
875 vmid->masks = &vmid_masks;
876 }
877
878 return &hubbub2->base;
879 }
880
dcn401_hubp_create(struct dc_context * ctx,uint32_t inst)881 static struct hubp *dcn401_hubp_create(
882 struct dc_context *ctx,
883 uint32_t inst)
884 {
885 struct dcn20_hubp *hubp2 =
886 kzalloc(sizeof(struct dcn20_hubp), GFP_KERNEL);
887
888 if (!hubp2)
889 return NULL;
890
891 #undef REG_STRUCT
892 #define REG_STRUCT hubp_regs
893 hubp_regs_init(0),
894 hubp_regs_init(1),
895 hubp_regs_init(2),
896 hubp_regs_init(3);
897
898 if (hubp401_construct(hubp2, ctx, inst,
899 &hubp_regs[inst], &hubp_shift, &hubp_mask))
900 return &hubp2->base;
901
902 BREAK_TO_DEBUGGER();
903 kfree(hubp2);
904 return NULL;
905 }
906
dcn401_dpp_destroy(struct dpp ** dpp)907 static void dcn401_dpp_destroy(struct dpp **dpp)
908 {
909 kfree(TO_DCN401_DPP(*dpp));
910 *dpp = NULL;
911 }
912
dcn401_dpp_create(struct dc_context * ctx,uint32_t inst)913 static struct dpp *dcn401_dpp_create(
914 struct dc_context *ctx,
915 uint32_t inst)
916 {
917 struct dcn401_dpp *dpp401 =
918 kzalloc(sizeof(struct dcn401_dpp), GFP_KERNEL);
919
920 if (!dpp401)
921 return NULL;
922
923 #undef REG_STRUCT
924 #define REG_STRUCT dpp_regs
925 dpp_regs_init(0),
926 dpp_regs_init(1),
927 dpp_regs_init(2),
928 dpp_regs_init(3);
929
930 if (dpp401_construct(dpp401, ctx, inst,
931 &dpp_regs[inst], &tf_shift, &tf_mask))
932 return &dpp401->base;
933
934 BREAK_TO_DEBUGGER();
935 kfree(dpp401);
936 return NULL;
937 }
938
dcn401_mpc_create(struct dc_context * ctx,int num_mpcc,int num_rmu)939 static struct mpc *dcn401_mpc_create(
940 struct dc_context *ctx,
941 int num_mpcc,
942 int num_rmu)
943 {
944 struct dcn401_mpc *mpc401 = kzalloc(sizeof(struct dcn401_mpc),
945 GFP_KERNEL);
946
947 if (!mpc401)
948 return NULL;
949
950 #undef REG_STRUCT
951 #define REG_STRUCT mpc_regs
952 dcn_mpc_regs_init();
953
954 dcn401_mpc_construct(mpc401, ctx,
955 &mpc_regs,
956 &mpc_shift,
957 &mpc_mask,
958 num_mpcc,
959 num_rmu);
960
961 return &mpc401->base;
962 }
963
dcn401_opp_create(struct dc_context * ctx,uint32_t inst)964 static struct output_pixel_processor *dcn401_opp_create(
965 struct dc_context *ctx, uint32_t inst)
966 {
967 struct dcn20_opp *opp4 =
968 kzalloc(sizeof(struct dcn20_opp), GFP_KERNEL);
969
970 if (!opp4) {
971 BREAK_TO_DEBUGGER();
972 return NULL;
973 }
974
975 #undef REG_STRUCT
976 #define REG_STRUCT opp_regs
977 opp_regs_init(0),
978 opp_regs_init(1),
979 opp_regs_init(2),
980 opp_regs_init(3);
981
982 dcn20_opp_construct(opp4, ctx, inst,
983 &opp_regs[inst], &opp_shift, &opp_mask);
984 return &opp4->base;
985 }
986
987
dcn401_timing_generator_create(struct dc_context * ctx,uint32_t instance)988 static struct timing_generator *dcn401_timing_generator_create(
989 struct dc_context *ctx,
990 uint32_t instance)
991 {
992 struct optc *tgn10 =
993 kzalloc(sizeof(struct optc), GFP_KERNEL);
994
995 if (!tgn10)
996 return NULL;
997 #undef REG_STRUCT
998 #define REG_STRUCT optc_regs
999 optc_regs_init(0),
1000 optc_regs_init(1),
1001 optc_regs_init(2),
1002 optc_regs_init(3);
1003
1004 tgn10->base.inst = instance;
1005 tgn10->base.ctx = ctx;
1006
1007 tgn10->tg_regs = &optc_regs[instance];
1008 tgn10->tg_shift = &optc_shift;
1009 tgn10->tg_mask = &optc_mask;
1010
1011 dcn401_timing_generator_init(tgn10);
1012
1013 return &tgn10->base;
1014 }
1015
1016 static const struct encoder_feature_support link_enc_feature = {
1017 .max_hdmi_deep_color = COLOR_DEPTH_121212,
1018 .max_hdmi_pixel_clock = 600000,
1019 .hdmi_ycbcr420_supported = true,
1020 .dp_ycbcr420_supported = true,
1021 .fec_supported = true,
1022 .flags.bits.IS_HBR2_CAPABLE = true,
1023 .flags.bits.IS_HBR3_CAPABLE = true,
1024 .flags.bits.IS_TPS3_CAPABLE = true,
1025 .flags.bits.IS_TPS4_CAPABLE = true
1026 };
1027
dcn401_link_encoder_create(struct dc_context * ctx,const struct encoder_init_data * enc_init_data)1028 static struct link_encoder *dcn401_link_encoder_create(
1029 struct dc_context *ctx,
1030 const struct encoder_init_data *enc_init_data)
1031 {
1032 struct dcn20_link_encoder *enc20 =
1033 kzalloc(sizeof(struct dcn20_link_encoder), GFP_KERNEL);
1034
1035 if (!enc20)
1036 return NULL;
1037
1038 #undef REG_STRUCT
1039 #define REG_STRUCT link_enc_aux_regs
1040 aux_regs_init(0),
1041 aux_regs_init(1),
1042 aux_regs_init(2),
1043 aux_regs_init(3);
1044
1045 #undef REG_STRUCT
1046 #define REG_STRUCT link_enc_hpd_regs
1047 hpd_regs_init(0),
1048 hpd_regs_init(1),
1049 hpd_regs_init(2),
1050 hpd_regs_init(3);
1051 #undef REG_STRUCT
1052 #define REG_STRUCT link_enc_regs
1053 link_regs_init(0, A),
1054 link_regs_init(1, B),
1055 link_regs_init(2, C),
1056 link_regs_init(3, D);
1057
1058 dcn401_link_encoder_construct(enc20,
1059 enc_init_data,
1060 &link_enc_feature,
1061 &link_enc_regs[enc_init_data->transmitter],
1062 &link_enc_aux_regs[enc_init_data->channel - 1],
1063 &link_enc_hpd_regs[enc_init_data->hpd_source],
1064 &le_shift,
1065 &le_mask);
1066 return &enc20->enc10.base;
1067 }
1068
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)1069 static void read_dce_straps(
1070 struct dc_context *ctx,
1071 struct resource_straps *straps)
1072 {
1073 generic_reg_get(ctx, ctx->dcn_reg_offsets[regDC_PINSTRAPS_BASE_IDX] + regDC_PINSTRAPS,
1074 FN(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO), &straps->dc_pinstraps_audio);
1075
1076 }
1077
dcn401_create_audio(struct dc_context * ctx,unsigned int inst)1078 static struct audio *dcn401_create_audio(
1079 struct dc_context *ctx, unsigned int inst)
1080 {
1081
1082 #undef REG_STRUCT
1083 #define REG_STRUCT audio_regs
1084 audio_regs_init(0),
1085 audio_regs_init(1),
1086 audio_regs_init(2),
1087 audio_regs_init(3),
1088 audio_regs_init(4);
1089
1090 return dce_audio_create(ctx, inst,
1091 &audio_regs[inst], &audio_shift, &audio_mask);
1092 }
1093
dcn401_vpg_create(struct dc_context * ctx,uint32_t inst)1094 static struct vpg *dcn401_vpg_create(
1095 struct dc_context *ctx,
1096 uint32_t inst)
1097 {
1098 struct dcn31_vpg *vpg4 = kzalloc(sizeof(struct dcn31_vpg), GFP_KERNEL);
1099
1100 if (!vpg4)
1101 return NULL;
1102
1103
1104 #undef REG_STRUCT
1105 #define REG_STRUCT vpg_regs
1106 vpg_regs_init(0),
1107 vpg_regs_init(1),
1108 vpg_regs_init(2),
1109 vpg_regs_init(3),
1110 vpg_regs_init(4),
1111 vpg_regs_init(5),
1112 vpg_regs_init(6),
1113 vpg_regs_init(7),
1114 vpg_regs_init(8);
1115
1116 vpg31_construct(vpg4, ctx, inst,
1117 &vpg_regs[inst],
1118 &vpg_shift,
1119 &vpg_mask);
1120
1121 return &vpg4->base;
1122 }
1123
dcn401_afmt_create(struct dc_context * ctx,uint32_t inst)1124 static struct afmt *dcn401_afmt_create(
1125 struct dc_context *ctx,
1126 uint32_t inst)
1127 {
1128 struct dcn30_afmt *afmt401 = kzalloc(sizeof(struct dcn30_afmt), GFP_KERNEL);
1129
1130 if (!afmt401)
1131 return NULL;
1132
1133 #undef REG_STRUCT
1134 #define REG_STRUCT afmt_regs
1135 afmt_regs_init(0),
1136 afmt_regs_init(1),
1137 afmt_regs_init(2),
1138 afmt_regs_init(3),
1139 afmt_regs_init(4);
1140
1141 afmt3_construct(afmt401, ctx, inst,
1142 &afmt_regs[inst],
1143 &afmt_shift,
1144 &afmt_mask);
1145
1146 return &afmt401->base;
1147 }
1148
dcn401_apg_create(struct dc_context * ctx,uint32_t inst)1149 static struct apg *dcn401_apg_create(
1150 struct dc_context *ctx,
1151 uint32_t inst)
1152 {
1153 struct dcn31_apg *apg31 = kzalloc(sizeof(struct dcn31_apg), GFP_KERNEL);
1154
1155 if (!apg31)
1156 return NULL;
1157
1158 #undef REG_STRUCT
1159 #define REG_STRUCT apg_regs
1160 apg_regs_init(0),
1161 apg_regs_init(1),
1162 apg_regs_init(2),
1163 apg_regs_init(3);
1164
1165 apg31_construct(apg31, ctx, inst,
1166 &apg_regs[inst],
1167 &apg_shift,
1168 &apg_mask);
1169
1170 return &apg31->base;
1171 }
1172
dcn401_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1173 static struct stream_encoder *dcn401_stream_encoder_create(
1174 enum engine_id eng_id,
1175 struct dc_context *ctx)
1176 {
1177 struct dcn10_stream_encoder *enc1;
1178 struct vpg *vpg;
1179 struct afmt *afmt;
1180 int vpg_inst;
1181 int afmt_inst;
1182
1183 /* Mapping of VPG, AFMT, DME register blocks to DIO block instance */
1184 if (eng_id <= ENGINE_ID_DIGF) {
1185 vpg_inst = eng_id;
1186 afmt_inst = eng_id;
1187 } else
1188 return NULL;
1189
1190 enc1 = kzalloc(sizeof(struct dcn10_stream_encoder), GFP_KERNEL);
1191 vpg = dcn401_vpg_create(ctx, vpg_inst);
1192 afmt = dcn401_afmt_create(ctx, afmt_inst);
1193
1194 if (!enc1 || !vpg || !afmt || eng_id >= ARRAY_SIZE(stream_enc_regs)) {
1195 kfree(enc1);
1196 kfree(vpg);
1197 kfree(afmt);
1198 return NULL;
1199 }
1200 #undef REG_STRUCT
1201 #define REG_STRUCT stream_enc_regs
1202 stream_enc_regs_init(0),
1203 stream_enc_regs_init(1),
1204 stream_enc_regs_init(2),
1205 stream_enc_regs_init(3);
1206 //stream_enc_regs_init(4);
1207
1208 dcn401_dio_stream_encoder_construct(enc1, ctx, ctx->dc_bios,
1209 eng_id, vpg, afmt,
1210 &stream_enc_regs[eng_id],
1211 &se_shift, &se_mask);
1212 return &enc1->base;
1213 }
1214
dcn401_hpo_dp_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)1215 static struct hpo_dp_stream_encoder *dcn401_hpo_dp_stream_encoder_create(
1216 enum engine_id eng_id,
1217 struct dc_context *ctx)
1218 {
1219 struct dcn31_hpo_dp_stream_encoder *hpo_dp_enc31;
1220 struct vpg *vpg;
1221 struct apg *apg;
1222 uint32_t hpo_dp_inst;
1223 uint32_t vpg_inst;
1224 uint32_t apg_inst;
1225
1226 ASSERT((eng_id >= ENGINE_ID_HPO_DP_0) && (eng_id <= ENGINE_ID_HPO_DP_3));
1227 hpo_dp_inst = eng_id - ENGINE_ID_HPO_DP_0;
1228
1229 /* Mapping of VPG register blocks to HPO DP block instance:
1230 * VPG[6] -> HPO_DP[0]
1231 * VPG[7] -> HPO_DP[1]
1232 * VPG[8] -> HPO_DP[2]
1233 * VPG[9] -> HPO_DP[3]
1234 */
1235 vpg_inst = hpo_dp_inst + 5;
1236
1237 /* Mapping of APG register blocks to HPO DP block instance:
1238 * APG[0] -> HPO_DP[0]
1239 * APG[1] -> HPO_DP[1]
1240 * APG[2] -> HPO_DP[2]
1241 * APG[3] -> HPO_DP[3]
1242 */
1243 apg_inst = hpo_dp_inst;
1244
1245 /* allocate HPO stream encoder and create VPG sub-block */
1246 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_stream_encoder), GFP_KERNEL);
1247 vpg = dcn401_vpg_create(ctx, vpg_inst);
1248 apg = dcn401_apg_create(ctx, apg_inst);
1249
1250 if (!hpo_dp_enc31 || !vpg || !apg) {
1251 kfree(hpo_dp_enc31);
1252 kfree(vpg);
1253 kfree(apg);
1254 return NULL;
1255 }
1256
1257 #undef REG_STRUCT
1258 #define REG_STRUCT hpo_dp_stream_enc_regs
1259 hpo_dp_stream_encoder_reg_init(0),
1260 hpo_dp_stream_encoder_reg_init(1),
1261 hpo_dp_stream_encoder_reg_init(2),
1262 hpo_dp_stream_encoder_reg_init(3);
1263
1264 dcn31_hpo_dp_stream_encoder_construct(hpo_dp_enc31, ctx, ctx->dc_bios,
1265 hpo_dp_inst, eng_id, vpg, apg,
1266 &hpo_dp_stream_enc_regs[hpo_dp_inst],
1267 &hpo_dp_se_shift, &hpo_dp_se_mask);
1268
1269 return &hpo_dp_enc31->base;
1270 }
1271
dcn401_hpo_dp_link_encoder_create(uint8_t inst,struct dc_context * ctx)1272 static struct hpo_dp_link_encoder *dcn401_hpo_dp_link_encoder_create(
1273 uint8_t inst,
1274 struct dc_context *ctx)
1275 {
1276 struct dcn31_hpo_dp_link_encoder *hpo_dp_enc31;
1277
1278 /* allocate HPO link encoder */
1279 hpo_dp_enc31 = kzalloc(sizeof(struct dcn31_hpo_dp_link_encoder), GFP_KERNEL);
1280 if (!hpo_dp_enc31)
1281 return NULL; /* out of memory */
1282
1283 #undef REG_STRUCT
1284 #define REG_STRUCT hpo_dp_link_enc_regs
1285 hpo_dp_link_encoder_reg_init(0),
1286 hpo_dp_link_encoder_reg_init(1),
1287 hpo_dp_link_encoder_reg_init(2),
1288 hpo_dp_link_encoder_reg_init(3);
1289
1290 hpo_dp_link_encoder32_construct(hpo_dp_enc31, ctx, inst,
1291 &hpo_dp_link_enc_regs[inst],
1292 &hpo_dp_le_shift, &hpo_dp_le_mask);
1293
1294 return &hpo_dp_enc31->base;
1295 }
1296
dcn401_hwseq_create(struct dc_context * ctx)1297 static struct dce_hwseq *dcn401_hwseq_create(
1298 struct dc_context *ctx)
1299 {
1300 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
1301
1302 #undef REG_STRUCT
1303 #define REG_STRUCT hwseq_reg
1304 hwseq_reg_init();
1305
1306 if (hws) {
1307 hws->ctx = ctx;
1308 hws->regs = &hwseq_reg;
1309 hws->shifts = &hwseq_shift;
1310 hws->masks = &hwseq_mask;
1311 }
1312
1313 return hws;
1314 }
1315 static const struct resource_create_funcs res_create_funcs = {
1316 .read_dce_straps = read_dce_straps,
1317 .create_audio = dcn401_create_audio,
1318 .create_stream_encoder = dcn401_stream_encoder_create,
1319 .create_hpo_dp_stream_encoder = dcn401_hpo_dp_stream_encoder_create,
1320 .create_hpo_dp_link_encoder = dcn401_hpo_dp_link_encoder_create,
1321 .create_hwseq = dcn401_hwseq_create,
1322 };
1323
dcn401_dsc_destroy(struct display_stream_compressor ** dsc)1324 static void dcn401_dsc_destroy(struct display_stream_compressor **dsc)
1325 {
1326 kfree(container_of(*dsc, struct dcn401_dsc, base));
1327 *dsc = NULL;
1328 }
1329
dcn401_resource_destruct(struct dcn401_resource_pool * pool)1330 static void dcn401_resource_destruct(struct dcn401_resource_pool *pool)
1331 {
1332 unsigned int i;
1333
1334 for (i = 0; i < pool->base.stream_enc_count; i++) {
1335 if (pool->base.stream_enc[i] != NULL) {
1336 if (pool->base.stream_enc[i]->vpg != NULL) {
1337 kfree(DCN31_VPG_FROM_VPG(pool->base.stream_enc[i]->vpg));
1338 pool->base.stream_enc[i]->vpg = NULL;
1339 }
1340 if (pool->base.stream_enc[i]->afmt != NULL) {
1341 kfree(DCN30_AFMT_FROM_AFMT(pool->base.stream_enc[i]->afmt));
1342 pool->base.stream_enc[i]->afmt = NULL;
1343 }
1344 kfree(DCN10STRENC_FROM_STRENC(pool->base.stream_enc[i]));
1345 pool->base.stream_enc[i] = NULL;
1346 }
1347 }
1348
1349 for (i = 0; i < pool->base.hpo_dp_stream_enc_count; i++) {
1350 if (pool->base.hpo_dp_stream_enc[i] != NULL) {
1351 if (pool->base.hpo_dp_stream_enc[i]->vpg != NULL) {
1352 kfree(DCN31_VPG_FROM_VPG(pool->base.hpo_dp_stream_enc[i]->vpg));
1353 pool->base.hpo_dp_stream_enc[i]->vpg = NULL;
1354 }
1355 if (pool->base.hpo_dp_stream_enc[i]->apg != NULL) {
1356 kfree(DCN31_APG_FROM_APG(pool->base.hpo_dp_stream_enc[i]->apg));
1357 pool->base.hpo_dp_stream_enc[i]->apg = NULL;
1358 }
1359 kfree(DCN3_1_HPO_DP_STREAM_ENC_FROM_HPO_STREAM_ENC(pool->base.hpo_dp_stream_enc[i]));
1360 pool->base.hpo_dp_stream_enc[i] = NULL;
1361 }
1362 }
1363
1364 for (i = 0; i < pool->base.hpo_dp_link_enc_count; i++) {
1365 if (pool->base.hpo_dp_link_enc[i] != NULL) {
1366 kfree(DCN3_1_HPO_DP_LINK_ENC_FROM_HPO_LINK_ENC(pool->base.hpo_dp_link_enc[i]));
1367 pool->base.hpo_dp_link_enc[i] = NULL;
1368 }
1369 }
1370
1371 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
1372 if (pool->base.dscs[i] != NULL)
1373 dcn401_dsc_destroy(&pool->base.dscs[i]);
1374 }
1375
1376 if (pool->base.mpc != NULL) {
1377 kfree(TO_DCN20_MPC(pool->base.mpc));
1378 pool->base.mpc = NULL;
1379 }
1380 if (pool->base.hubbub != NULL) {
1381 kfree(TO_DCN20_HUBBUB(pool->base.hubbub));
1382 pool->base.hubbub = NULL;
1383 }
1384 for (i = 0; i < pool->base.pipe_count; i++) {
1385 if (pool->base.dpps[i] != NULL)
1386 dcn401_dpp_destroy(&pool->base.dpps[i]);
1387
1388 if (pool->base.ipps[i] != NULL)
1389 pool->base.ipps[i]->funcs->ipp_destroy(&pool->base.ipps[i]);
1390
1391 if (pool->base.hubps[i] != NULL) {
1392 kfree(TO_DCN20_HUBP(pool->base.hubps[i]));
1393 pool->base.hubps[i] = NULL;
1394 }
1395
1396 if (pool->base.irqs != NULL) {
1397 dal_irq_service_destroy(&pool->base.irqs);
1398 }
1399 }
1400
1401 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
1402 if (pool->base.engines[i] != NULL)
1403 dce110_engine_destroy(&pool->base.engines[i]);
1404 if (pool->base.hw_i2cs[i] != NULL) {
1405 kfree(pool->base.hw_i2cs[i]);
1406 pool->base.hw_i2cs[i] = NULL;
1407 }
1408 if (pool->base.sw_i2cs[i] != NULL) {
1409 kfree(pool->base.sw_i2cs[i]);
1410 pool->base.sw_i2cs[i] = NULL;
1411 }
1412 }
1413
1414 for (i = 0; i < pool->base.res_cap->num_opp; i++) {
1415 if (pool->base.opps[i] != NULL)
1416 pool->base.opps[i]->funcs->opp_destroy(&pool->base.opps[i]);
1417 }
1418
1419 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1420 if (pool->base.timing_generators[i] != NULL) {
1421 kfree(DCN10TG_FROM_TG(pool->base.timing_generators[i]));
1422 pool->base.timing_generators[i] = NULL;
1423 }
1424 }
1425
1426 for (i = 0; i < pool->base.res_cap->num_dwb; i++) {
1427 if (pool->base.dwbc[i] != NULL) {
1428 kfree(TO_DCN30_DWBC(pool->base.dwbc[i]));
1429 pool->base.dwbc[i] = NULL;
1430 }
1431 if (pool->base.mcif_wb[i] != NULL) {
1432 kfree(TO_DCN30_MMHUBBUB(pool->base.mcif_wb[i]));
1433 pool->base.mcif_wb[i] = NULL;
1434 }
1435 }
1436
1437 for (i = 0; i < pool->base.audio_count; i++) {
1438 if (pool->base.audios[i])
1439 dce_aud_destroy(&pool->base.audios[i]);
1440 }
1441
1442 for (i = 0; i < pool->base.clk_src_count; i++) {
1443 if (pool->base.clock_sources[i] != NULL) {
1444 dcn20_clock_source_destroy(&pool->base.clock_sources[i]);
1445 pool->base.clock_sources[i] = NULL;
1446 }
1447 }
1448
1449 for (i = 0; i < pool->base.res_cap->num_mpc_3dlut; i++) {
1450 if (pool->base.mpc_lut[i] != NULL) {
1451 dc_3dlut_func_release(pool->base.mpc_lut[i]);
1452 pool->base.mpc_lut[i] = NULL;
1453 }
1454 if (pool->base.mpc_shaper[i] != NULL) {
1455 dc_transfer_func_release(pool->base.mpc_shaper[i]);
1456 pool->base.mpc_shaper[i] = NULL;
1457 }
1458 }
1459
1460 if (pool->base.dp_clock_source != NULL) {
1461 dcn20_clock_source_destroy(&pool->base.dp_clock_source);
1462 pool->base.dp_clock_source = NULL;
1463 }
1464
1465 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1466 if (pool->base.multiple_abms[i] != NULL)
1467 dce_abm_destroy(&pool->base.multiple_abms[i]);
1468 }
1469
1470 if (pool->base.psr != NULL)
1471 dmub_psr_destroy(&pool->base.psr);
1472
1473 if (pool->base.dccg != NULL)
1474 dcn_dccg_destroy(&pool->base.dccg);
1475
1476 if (pool->base.oem_device != NULL) {
1477 struct dc *dc = pool->base.oem_device->ctx->dc;
1478
1479 dc->link_srv->destroy_ddc_service(&pool->base.oem_device);
1480 }
1481 }
1482
1483
dcn401_dwbc_create(struct dc_context * ctx,struct resource_pool * pool)1484 static bool dcn401_dwbc_create(struct dc_context *ctx, struct resource_pool *pool)
1485 {
1486 int i;
1487 uint32_t dwb_count = pool->res_cap->num_dwb;
1488
1489 for (i = 0; i < dwb_count; i++) {
1490 struct dcn30_dwbc *dwbc401 = kzalloc(sizeof(struct dcn30_dwbc),
1491 GFP_KERNEL);
1492
1493 if (!dwbc401) {
1494 dm_error("DC: failed to create dwbc401!\n");
1495 return false;
1496 }
1497
1498
1499 #undef REG_STRUCT
1500 #define REG_STRUCT dwbc401_regs
1501 dwbc_regs_dcn401_init(0);
1502
1503 dcn30_dwbc_construct(dwbc401, ctx,
1504 &dwbc401_regs[i],
1505 &dwbc401_shift,
1506 &dwbc401_mask,
1507 i);
1508
1509 pool->dwbc[i] = &dwbc401->base;
1510
1511 }
1512 return true;
1513 }
1514
dcn401_mmhubbub_create(struct dc_context * ctx,struct resource_pool * pool)1515 static bool dcn401_mmhubbub_create(struct dc_context *ctx, struct resource_pool *pool)
1516 {
1517 int i;
1518 uint32_t dwb_count = pool->res_cap->num_dwb;
1519
1520 for (i = 0; i < dwb_count; i++) {
1521 struct dcn30_mmhubbub *mcif_wb30 = kzalloc(sizeof(struct dcn30_mmhubbub),
1522 GFP_KERNEL);
1523
1524 if (!mcif_wb30) {
1525 dm_error("DC: failed to create mcif_wb30!\n");
1526 return false;
1527 }
1528
1529 #undef REG_STRUCT
1530 #define REG_STRUCT mcif_wb30_regs
1531 mcif_wb_regs_dcn3_init(0);
1532
1533 dcn32_mmhubbub_construct(mcif_wb30, ctx,
1534 &mcif_wb30_regs[i],
1535 &mcif_wb30_shift,
1536 &mcif_wb30_mask,
1537 i);
1538
1539 pool->mcif_wb[i] = &mcif_wb30->base;
1540 }
1541 return true;
1542 }
1543
dcn401_dsc_create(struct dc_context * ctx,uint32_t inst)1544 static struct display_stream_compressor *dcn401_dsc_create(
1545 struct dc_context *ctx, uint32_t inst)
1546 {
1547 struct dcn401_dsc *dsc =
1548 kzalloc(sizeof(struct dcn401_dsc), GFP_KERNEL);
1549
1550 if (!dsc) {
1551 BREAK_TO_DEBUGGER();
1552 return NULL;
1553 }
1554
1555 #undef REG_STRUCT
1556 #define REG_STRUCT dsc_regs
1557 dsc_regs_init(0),
1558 dsc_regs_init(1),
1559 dsc_regs_init(2),
1560 dsc_regs_init(3);
1561
1562 dsc401_construct(dsc, ctx, inst, &dsc_regs[inst], &dsc_shift, &dsc_mask);
1563 dsc401_set_fgcg(dsc,
1564 ctx->dc->debug.enable_fine_grain_clock_gating.bits.dsc);
1565
1566 //dsc->max_image_width = 6016;
1567 dsc->max_image_width = 5760;
1568
1569 return &dsc->base;
1570 }
1571
dcn401_destroy_resource_pool(struct resource_pool ** pool)1572 static void dcn401_destroy_resource_pool(struct resource_pool **pool)
1573 {
1574 struct dcn401_resource_pool *dcn401_pool = TO_DCN401_RES_POOL(*pool);
1575
1576 dcn401_resource_destruct(dcn401_pool);
1577 kfree(dcn401_pool);
1578 *pool = NULL;
1579 }
1580
1581 static struct dc_cap_funcs cap_funcs = {
1582 .get_dcc_compression_cap = dcn20_get_dcc_compression_cap
1583 };
1584
dcn401_update_bw_bounding_box(struct dc * dc,struct clk_bw_params * bw_params)1585 static void dcn401_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)
1586 {
1587 struct dml2_configuration_options *dml2_opt = &dc->dml2_tmp;
1588
1589 memcpy(dml2_opt, &dc->dml2_options, sizeof(dc->dml2_options));
1590
1591 DC_FP_START();
1592
1593 dcn401_update_bw_bounding_box_fpu(dc, bw_params);
1594
1595 dml2_opt->use_clock_dc_limits = false;
1596 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
1597 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2);
1598
1599 dml2_opt->use_clock_dc_limits = true;
1600 if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2_dc_power_source)
1601 dml2_reinit(dc, dml2_opt, &dc->current_state->bw_ctx.dml2_dc_power_source);
1602
1603 DC_FP_END();
1604 }
1605
dcn401_patch_unknown_plane_state(struct dc_plane_state * plane_state)1606 enum dc_status dcn401_patch_unknown_plane_state(struct dc_plane_state *plane_state)
1607 {
1608 plane_state->tiling_info.gfx_addr3.swizzle = DC_ADDR3_SW_64KB_2D;
1609 return DC_OK;
1610 }
1611
dcn401_validate_bandwidth(struct dc * dc,struct dc_state * context,bool fast_validate)1612 bool dcn401_validate_bandwidth(struct dc *dc,
1613 struct dc_state *context,
1614 bool fast_validate)
1615 {
1616 bool out = false;
1617 if (dc->debug.using_dml2)
1618 out = dml2_validate(dc, context,
1619 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2,
1620 fast_validate);
1621 return out;
1622 }
1623
dcn401_prepare_mcache_programming(struct dc * dc,struct dc_state * context)1624 void dcn401_prepare_mcache_programming(struct dc *dc,
1625 struct dc_state *context)
1626 {
1627 if (dc->debug.using_dml21)
1628 dml2_prepare_mcache_programming(dc, context,
1629 context->power_source == DC_POWER_SOURCE_DC ? context->bw_ctx.dml2_dc_power_source : context->bw_ctx.dml2);
1630 }
1631
dcn401_build_pipe_pix_clk_params(struct pipe_ctx * pipe_ctx)1632 static void dcn401_build_pipe_pix_clk_params(struct pipe_ctx *pipe_ctx)
1633 {
1634 const struct dc_stream_state *stream = pipe_ctx->stream;
1635 struct dc_link *link = stream->link;
1636 struct link_encoder *link_enc = NULL;
1637 struct pixel_clk_params *pixel_clk_params = &pipe_ctx->stream_res.pix_clk_params;
1638
1639 pixel_clk_params->requested_pix_clk_100hz = stream->timing.pix_clk_100hz;
1640
1641 link_enc = link_enc_cfg_get_link_enc(link);
1642 if (link_enc)
1643 pixel_clk_params->encoder_object_id = link_enc->id;
1644
1645 pixel_clk_params->signal_type = pipe_ctx->stream->signal;
1646 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1;
1647 /* TODO: un-hardcode*/
1648
1649 /* TODO - DP2.0 HW: calculate requested_sym_clk for UHBR rates */
1650
1651 pixel_clk_params->requested_sym_clk = LINK_RATE_LOW *
1652 LINK_RATE_REF_FREQ_IN_KHZ;
1653 pixel_clk_params->flags.ENABLE_SS = 0;
1654 pixel_clk_params->color_depth =
1655 stream->timing.display_color_depth;
1656 pixel_clk_params->flags.DISPLAY_BLANKED = 1;
1657 pixel_clk_params->pixel_encoding = stream->timing.pixel_encoding;
1658
1659 if (stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR422)
1660 pixel_clk_params->color_depth = COLOR_DEPTH_888;
1661
1662 if (stream->timing.timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
1663 pixel_clk_params->requested_pix_clk_100hz *= 2;
1664 if (dc_is_tmds_signal(stream->signal) &&
1665 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420)
1666 pixel_clk_params->requested_pix_clk_100hz /= 2;
1667
1668 pipe_ctx->clock_source->funcs->get_pix_clk_dividers(
1669 pipe_ctx->clock_source,
1670 &pipe_ctx->stream_res.pix_clk_params,
1671 &pipe_ctx->pll_settings);
1672
1673 pixel_clk_params->dio_se_pix_per_cycle = 1;
1674 if (dc_is_tmds_signal(stream->signal) &&
1675 stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) {
1676 pixel_clk_params->dio_se_pix_per_cycle = 2;
1677 } else if (dc_is_dp_signal(stream->signal)) {
1678 /* round up to nearest power of 2, or max at 8 pixels per cycle */
1679 if (pixel_clk_params->requested_pix_clk_100hz > 4 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1680 pixel_clk_params->dio_se_pix_per_cycle = 8;
1681 } else if (pixel_clk_params->requested_pix_clk_100hz > 2 * stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1682 pixel_clk_params->dio_se_pix_per_cycle = 4;
1683 } else if (pixel_clk_params->requested_pix_clk_100hz > stream->ctx->dc->clk_mgr->dprefclk_khz * 10) {
1684 pixel_clk_params->dio_se_pix_per_cycle = 2;
1685 } else {
1686 pixel_clk_params->dio_se_pix_per_cycle = 1;
1687 }
1688 }
1689 }
1690
1691 static struct resource_funcs dcn401_res_pool_funcs = {
1692 .destroy = dcn401_destroy_resource_pool,
1693 .link_enc_create = dcn401_link_encoder_create,
1694 .link_enc_create_minimal = NULL,
1695 .panel_cntl_create = dcn32_panel_cntl_create,
1696 .validate_bandwidth = dcn401_validate_bandwidth,
1697 .calculate_wm_and_dlg = NULL,
1698 .populate_dml_pipes = NULL,
1699 .acquire_free_pipe_as_secondary_dpp_pipe = dcn32_acquire_free_pipe_as_secondary_dpp_pipe,
1700 .acquire_free_pipe_as_secondary_opp_head = dcn32_acquire_free_pipe_as_secondary_opp_head,
1701 .release_pipe = dcn20_release_pipe,
1702 .add_stream_to_ctx = dcn30_add_stream_to_ctx,
1703 .add_dsc_to_stream_resource = dcn20_add_dsc_to_stream_resource,
1704 .remove_stream_from_ctx = dcn20_remove_stream_from_ctx,
1705 .populate_dml_writeback_from_context = dcn30_populate_dml_writeback_from_context,
1706 .set_mcif_arb_params = dcn30_set_mcif_arb_params,
1707 .find_first_free_match_stream_enc_for_link = dcn10_find_first_free_match_stream_enc_for_link,
1708 .acquire_post_bldn_3dlut = dcn32_acquire_post_bldn_3dlut,
1709 .release_post_bldn_3dlut = dcn32_release_post_bldn_3dlut,
1710 .update_bw_bounding_box = dcn401_update_bw_bounding_box,
1711 .patch_unknown_plane_state = dcn401_patch_unknown_plane_state,
1712 .update_soc_for_wm_a = dcn30_update_soc_for_wm_a,
1713 .add_phantom_pipes = dcn32_add_phantom_pipes,
1714 .prepare_mcache_programming = dcn401_prepare_mcache_programming,
1715 .build_pipe_pix_clk_params = dcn401_build_pipe_pix_clk_params,
1716 .calculate_mall_ways_from_bytes = dcn32_calculate_mall_ways_from_bytes,
1717 };
1718
read_pipe_fuses(struct dc_context * ctx)1719 static uint32_t read_pipe_fuses(struct dc_context *ctx)
1720 {
1721 uint32_t value = REG_READ(CC_DC_PIPE_DIS);
1722 /* DCN401 support max 4 pipes */
1723 value = value & 0xf;
1724 return value;
1725 }
1726
1727
dcn401_resource_construct(uint8_t num_virtual_links,struct dc * dc,struct dcn401_resource_pool * pool)1728 static bool dcn401_resource_construct(
1729 uint8_t num_virtual_links,
1730 struct dc *dc,
1731 struct dcn401_resource_pool *pool)
1732 {
1733 int i, j;
1734 struct dc_context *ctx = dc->ctx;
1735 struct irq_service_init_data init_data;
1736 struct ddc_service_init_data ddc_init_data = {0};
1737 uint32_t pipe_fuses = 0;
1738 uint32_t num_pipes = 4;
1739
1740 #undef REG_STRUCT
1741 #define REG_STRUCT bios_regs
1742 bios_regs_init();
1743
1744 #undef REG_STRUCT
1745 #define REG_STRUCT clk_src_regs
1746 clk_src_regs_init(0, A),
1747 clk_src_regs_init(1, B),
1748 clk_src_regs_init(2, C),
1749 clk_src_regs_init(3, D);
1750
1751 #undef REG_STRUCT
1752 #define REG_STRUCT abm_regs
1753 abm_regs_init(0),
1754 abm_regs_init(1),
1755 abm_regs_init(2),
1756 abm_regs_init(3);
1757
1758 #undef REG_STRUCT
1759 #define REG_STRUCT dccg_regs
1760 dccg_regs_init();
1761
1762 ctx->dc_bios->regs = &bios_regs;
1763
1764 pool->base.res_cap = &res_cap_dcn4_01;
1765
1766 /* max number of pipes for ASIC before checking for pipe fuses */
1767 num_pipes = pool->base.res_cap->num_timing_generator;
1768 pipe_fuses = read_pipe_fuses(ctx);
1769
1770 for (i = 0; i < pool->base.res_cap->num_timing_generator; i++)
1771 if (pipe_fuses & 1 << i)
1772 num_pipes--;
1773
1774 if (pipe_fuses & 1)
1775 ASSERT(0); //Unexpected - Pipe 0 should always be fully functional!
1776
1777 if (pipe_fuses & CC_DC_PIPE_DIS__DC_FULL_DIS_MASK)
1778 ASSERT(0); //Entire DCN is harvested!
1779
1780 pool->base.funcs = &dcn401_res_pool_funcs;
1781
1782 /*************************************************
1783 * Resource + asic cap harcoding *
1784 *************************************************/
1785 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1786 pool->base.timing_generator_count = num_pipes;
1787 pool->base.pipe_count = num_pipes;
1788 pool->base.mpcc_count = num_pipes;
1789 dc->caps.max_downscale_ratio = 600;
1790 dc->caps.i2c_speed_in_khz = 95;
1791 dc->caps.i2c_speed_in_khz_hdcp = 95; /*1.4 w/a applied by default*/
1792 /* TODO: Bring max cursor size back to 256 after subvp cursor corruption is fixed*/
1793 dc->caps.max_cursor_size = 64;
1794 dc->caps.cursor_not_scaled = true;
1795 dc->caps.min_horizontal_blanking_period = 80;
1796 dc->caps.dmdata_alloc_size = 2048;
1797 dc->caps.mall_size_per_mem_channel = 4;
1798 /* total size = mall per channel * num channels * 1024 * 1024 */
1799 dc->caps.mall_size_total = dc->caps.mall_size_per_mem_channel * dc->ctx->dc_bios->vram_info.num_chans * 1048576;
1800 dc->caps.cursor_cache_size = dc->caps.max_cursor_size * dc->caps.max_cursor_size * 8;
1801 dc->caps.cache_line_size = 64;
1802 dc->caps.cache_num_ways = 16;
1803
1804 /* Calculate the available MALL space */
1805 dc->caps.max_cab_allocation_bytes = dcn32_calc_num_avail_chans_for_mall(
1806 dc, dc->ctx->dc_bios->vram_info.num_chans) *
1807 dc->caps.mall_size_per_mem_channel * 1024 * 1024;
1808 dc->caps.mall_size_total = dc->caps.max_cab_allocation_bytes;
1809
1810 dc->caps.subvp_fw_processing_delay_us = 15;
1811 dc->caps.subvp_drr_max_vblank_margin_us = 40;
1812 dc->caps.subvp_prefetch_end_to_mall_start_us = 15;
1813 dc->caps.subvp_swath_height_margin_lines = 16;
1814 dc->caps.subvp_pstate_allow_width_us = 20;
1815 dc->caps.subvp_vertical_int_margin_us = 30;
1816 dc->caps.subvp_drr_vblank_start_margin_us = 100; // 100us margin
1817
1818 dc->caps.max_slave_planes = 2;
1819 dc->caps.max_slave_yuv_planes = 2;
1820 dc->caps.max_slave_rgb_planes = 2;
1821 dc->caps.post_blend_color_processing = true;
1822 dc->caps.force_dp_tps4_for_cp2520 = true;
1823 dc->caps.dp_hpo = true;
1824 dc->caps.dp_hdmi21_pcon_support = true;
1825 dc->caps.edp_dsc_support = true;
1826 dc->caps.extended_aux_timeout_support = true;
1827 dc->caps.dmcub_support = true;
1828 dc->caps.max_v_total = (1 << 15) - 1;
1829
1830 if (ASICREV_IS_GC_12_0_1_A0(dc->ctx->asic_id.hw_internal_rev))
1831 dc->caps.dcc_plane_width_limit = 7680;
1832
1833 /* Color pipeline capabilities */
1834 dc->caps.color.dpp.dcn_arch = 1;
1835 dc->caps.color.dpp.input_lut_shared = 0;
1836 dc->caps.color.dpp.icsc = 1;
1837 dc->caps.color.dpp.dgam_ram = 0; // must use gamma_corr
1838 dc->caps.color.dpp.dgam_rom_caps.srgb = 1;
1839 dc->caps.color.dpp.dgam_rom_caps.bt2020 = 1;
1840 dc->caps.color.dpp.dgam_rom_caps.gamma2_2 = 1;
1841 dc->caps.color.dpp.dgam_rom_caps.pq = 1;
1842 dc->caps.color.dpp.dgam_rom_caps.hlg = 1;
1843 dc->caps.color.dpp.post_csc = 1;
1844 dc->caps.color.dpp.gamma_corr = 1;
1845 dc->caps.color.dpp.dgam_rom_for_yuv = 0;
1846
1847 dc->caps.color.dpp.hw_3d_lut = 1;
1848 dc->caps.color.dpp.ogam_ram = 1;
1849 // no OGAM ROM on DCN2 and later ASICs
1850 dc->caps.color.dpp.ogam_rom_caps.srgb = 0;
1851 dc->caps.color.dpp.ogam_rom_caps.bt2020 = 0;
1852 dc->caps.color.dpp.ogam_rom_caps.gamma2_2 = 0;
1853 dc->caps.color.dpp.ogam_rom_caps.pq = 0;
1854 dc->caps.color.dpp.ogam_rom_caps.hlg = 0;
1855 dc->caps.color.dpp.ocsc = 0;
1856
1857 dc->caps.color.mpc.gamut_remap = 1;
1858 dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
1859 dc->caps.color.mpc.ogam_ram = 1;
1860 dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
1861 dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
1862 dc->caps.color.mpc.ogam_rom_caps.gamma2_2 = 0;
1863 dc->caps.color.mpc.ogam_rom_caps.pq = 0;
1864 dc->caps.color.mpc.ogam_rom_caps.hlg = 0;
1865 dc->caps.color.mpc.ocsc = 1;
1866 dc->config.use_spl = true;
1867 dc->config.prefer_easf = true;
1868 dc->config.dc_mode_clk_limit_support = true;
1869 dc->config.enable_windowed_mpo_odm = true;
1870 /* read VBIOS LTTPR caps */
1871 {
1872 if (ctx->dc_bios->funcs->get_lttpr_caps) {
1873 enum bp_result bp_query_result;
1874 uint8_t is_vbios_lttpr_enable = 0;
1875
1876 bp_query_result = ctx->dc_bios->funcs->get_lttpr_caps(ctx->dc_bios, &is_vbios_lttpr_enable);
1877 dc->caps.vbios_lttpr_enable = (bp_query_result == BP_RESULT_OK) && !!is_vbios_lttpr_enable;
1878 }
1879
1880 /* interop bit is implicit */
1881 {
1882 dc->caps.vbios_lttpr_aware = true;
1883 }
1884 }
1885
1886 if (dc->ctx->dce_environment == DCE_ENV_PRODUCTION_DRV)
1887 dc->debug = debug_defaults_drv;
1888
1889 // Init the vm_helper
1890 if (dc->vm_helper)
1891 vm_helper_init(dc->vm_helper, 16);
1892
1893 /*************************************************
1894 * Create resources *
1895 *************************************************/
1896
1897 /* Clock Sources for Pixel Clock*/
1898 pool->base.clock_sources[DCN401_CLK_SRC_PLL0] =
1899 dcn401_clock_source_create(ctx, ctx->dc_bios,
1900 CLOCK_SOURCE_COMBO_PHY_PLL0,
1901 &clk_src_regs[0], false);
1902 pool->base.clock_sources[DCN401_CLK_SRC_PLL1] =
1903 dcn401_clock_source_create(ctx, ctx->dc_bios,
1904 CLOCK_SOURCE_COMBO_PHY_PLL1,
1905 &clk_src_regs[1], false);
1906 pool->base.clock_sources[DCN401_CLK_SRC_PLL2] =
1907 dcn401_clock_source_create(ctx, ctx->dc_bios,
1908 CLOCK_SOURCE_COMBO_PHY_PLL2,
1909 &clk_src_regs[2], false);
1910 pool->base.clock_sources[DCN401_CLK_SRC_PLL3] =
1911 dcn401_clock_source_create(ctx, ctx->dc_bios,
1912 CLOCK_SOURCE_COMBO_PHY_PLL3,
1913 &clk_src_regs[3], false);
1914 // pool->base.clock_sources[DCN401_CLK_SRC_PLL4] =
1915 // dcn401_clock_source_create(ctx, ctx->dc_bios,
1916 // CLOCK_SOURCE_COMBO_PHY_PLL4,
1917 // &clk_src_regs[4], false);
1918
1919 pool->base.clk_src_count = DCN401_CLK_SRC_TOTAL;
1920
1921 /* todo: not reuse phy_pll registers */
1922 pool->base.dp_clock_source =
1923 dcn401_clock_source_create(ctx, ctx->dc_bios,
1924 CLOCK_SOURCE_ID_DP_DTO,
1925 &clk_src_regs[0], true);
1926
1927 for (i = 0; i < pool->base.clk_src_count; i++) {
1928 if (pool->base.clock_sources[i] == NULL) {
1929 dm_error("DC: failed to create clock sources!\n");
1930 BREAK_TO_DEBUGGER();
1931 goto create_fail;
1932 }
1933 }
1934
1935 /* DCCG */
1936 pool->base.dccg = dccg401_create(ctx, &dccg_regs, &dccg_shift, &dccg_mask);
1937 if (pool->base.dccg == NULL) {
1938 dm_error("DC: failed to create dccg!\n");
1939 BREAK_TO_DEBUGGER();
1940 goto create_fail;
1941 }
1942
1943 /* IRQ Service */
1944 init_data.ctx = dc->ctx;
1945 pool->base.irqs = dal_irq_service_dcn401_create(&init_data);
1946 if (!pool->base.irqs)
1947 goto create_fail;
1948
1949 /* HUBBUB */
1950 pool->base.hubbub = dcn401_hubbub_create(ctx);
1951 if (pool->base.hubbub == NULL) {
1952 BREAK_TO_DEBUGGER();
1953 dm_error("DC: failed to create hubbub!\n");
1954 goto create_fail;
1955 }
1956
1957 /* HUBPs, DPPs, OPPs, TGs, ABMs */
1958 for (i = 0, j = 0; i < pool->base.res_cap->num_timing_generator; i++) {
1959
1960 /* if pipe is disabled, skip instance of HW pipe,
1961 * i.e, skip ASIC register instance
1962 */
1963 if (pipe_fuses & 1 << i)
1964 continue;
1965
1966 pool->base.hubps[j] = dcn401_hubp_create(ctx, i);
1967 if (pool->base.hubps[j] == NULL) {
1968 BREAK_TO_DEBUGGER();
1969 dm_error(
1970 "DC: failed to create hubps!\n");
1971 goto create_fail;
1972 }
1973
1974 pool->base.dpps[j] = dcn401_dpp_create(ctx, i);
1975 if (pool->base.dpps[j] == NULL) {
1976 BREAK_TO_DEBUGGER();
1977 dm_error(
1978 "DC: failed to create dpps!\n");
1979 goto create_fail;
1980 }
1981
1982 pool->base.opps[j] = dcn401_opp_create(ctx, i);
1983 if (pool->base.opps[j] == NULL) {
1984 BREAK_TO_DEBUGGER();
1985 dm_error(
1986 "DC: failed to create output pixel processor!\n");
1987 goto create_fail;
1988 }
1989
1990 pool->base.timing_generators[j] = dcn401_timing_generator_create(
1991 ctx, i);
1992 if (pool->base.timing_generators[j] == NULL) {
1993 BREAK_TO_DEBUGGER();
1994 dm_error("DC: failed to create tg!\n");
1995 goto create_fail;
1996 }
1997
1998 pool->base.multiple_abms[j] = dmub_abm_create(ctx,
1999 &abm_regs[i],
2000 &abm_shift,
2001 &abm_mask);
2002 if (pool->base.multiple_abms[j] == NULL) {
2003 dm_error("DC: failed to create abm for pipe %d!\n", i);
2004 BREAK_TO_DEBUGGER();
2005 goto create_fail;
2006 }
2007
2008 /* index for resource pool arrays for next valid pipe */
2009 j++;
2010 }
2011
2012 /* PSR */
2013 pool->base.psr = dmub_psr_create(ctx);
2014 if (pool->base.psr == NULL) {
2015 dm_error("DC: failed to create psr obj!\n");
2016 BREAK_TO_DEBUGGER();
2017 goto create_fail;
2018 }
2019
2020 /* MPCCs */
2021 pool->base.mpc = dcn401_mpc_create(ctx, pool->base.res_cap->num_timing_generator, pool->base.res_cap->num_mpc_3dlut);
2022 if (pool->base.mpc == NULL) {
2023 BREAK_TO_DEBUGGER();
2024 dm_error("DC: failed to create mpc!\n");
2025 goto create_fail;
2026 }
2027
2028 /* DSCs */
2029 for (i = 0; i < pool->base.res_cap->num_dsc; i++) {
2030 pool->base.dscs[i] = dcn401_dsc_create(ctx, i);
2031 if (pool->base.dscs[i] == NULL) {
2032 BREAK_TO_DEBUGGER();
2033 dm_error("DC: failed to create display stream compressor %d!\n", i);
2034 goto create_fail;
2035 }
2036 }
2037
2038 /* DWB */
2039 if (!dcn401_dwbc_create(ctx, &pool->base)) {
2040 BREAK_TO_DEBUGGER();
2041 dm_error("DC: failed to create dwbc!\n");
2042 goto create_fail;
2043 }
2044
2045 /* MMHUBBUB */
2046 if (!dcn401_mmhubbub_create(ctx, &pool->base)) {
2047 BREAK_TO_DEBUGGER();
2048 dm_error("DC: failed to create mcif_wb!\n");
2049 goto create_fail;
2050 }
2051
2052 /* AUX and I2C */
2053 for (i = 0; i < pool->base.res_cap->num_ddc; i++) {
2054 pool->base.engines[i] = dcn401_aux_engine_create(ctx, i);
2055 if (pool->base.engines[i] == NULL) {
2056 BREAK_TO_DEBUGGER();
2057 dm_error(
2058 "DC:failed to create aux engine!!\n");
2059 goto create_fail;
2060 }
2061 pool->base.hw_i2cs[i] = dcn401_i2c_hw_create(ctx, i);
2062 if (pool->base.hw_i2cs[i] == NULL) {
2063 BREAK_TO_DEBUGGER();
2064 dm_error(
2065 "DC:failed to create hw i2c!!\n");
2066 goto create_fail;
2067 }
2068 pool->base.sw_i2cs[i] = NULL;
2069 }
2070
2071 /* Audio, HWSeq, Stream Encoders including HPO and virtual, MPC 3D LUTs */
2072 if (!resource_construct(num_virtual_links, dc, &pool->base,
2073 &res_create_funcs))
2074 goto create_fail;
2075
2076 /* HW Sequencer init functions and Plane caps */
2077 dcn401_hw_sequencer_init_functions(dc);
2078
2079 dc->caps.max_planes = pool->base.pipe_count;
2080
2081 for (i = 0; i < dc->caps.max_planes; ++i)
2082 dc->caps.planes[i] = plane_cap;
2083
2084 dc->cap_funcs = cap_funcs;
2085
2086 if (dc->ctx->dc_bios->fw_info.oem_i2c_present) {
2087 ddc_init_data.ctx = dc->ctx;
2088 ddc_init_data.link = NULL;
2089 ddc_init_data.id.id = dc->ctx->dc_bios->fw_info.oem_i2c_obj_id;
2090 ddc_init_data.id.enum_id = 0;
2091 ddc_init_data.id.type = OBJECT_TYPE_GENERIC;
2092 pool->base.oem_device = dc->link_srv->create_ddc_service(&ddc_init_data);
2093 } else {
2094 pool->base.oem_device = NULL;
2095 }
2096
2097 //For now enable SDPIF_REQUEST_RATE_LIMIT on DCN4_01 when vram_info.num_chans provided
2098 if (dc->config.sdpif_request_limit_words_per_umc == 0)
2099 dc->config.sdpif_request_limit_words_per_umc = 16;
2100
2101 dc->dml2_options.dcn_pipe_count = pool->base.pipe_count;
2102 dc->dml2_options.use_native_pstate_optimization = false;
2103 dc->dml2_options.use_native_soc_bb_construction = true;
2104 dc->dml2_options.minimize_dispclk_using_odm = true;
2105 dc->dml2_options.map_dc_pipes_with_callbacks = true;
2106 dc->dml2_options.force_tdlut_enable = true;
2107
2108 resource_init_common_dml2_callbacks(dc, &dc->dml2_options);
2109 dc->dml2_options.callbacks.can_support_mclk_switch_using_fw_based_vblank_stretch = &dcn30_can_support_mclk_switch_using_fw_based_vblank_stretch;
2110 dc->dml2_options.svp_pstate.callbacks.release_dsc = &dcn20_release_dsc;
2111 dc->dml2_options.svp_pstate.callbacks.calculate_mall_ways_from_bytes = pool->base.funcs->calculate_mall_ways_from_bytes;
2112
2113 dc->dml2_options.svp_pstate.subvp_fw_processing_delay_us = dc->caps.subvp_fw_processing_delay_us;
2114 dc->dml2_options.svp_pstate.subvp_prefetch_end_to_mall_start_us = dc->caps.subvp_prefetch_end_to_mall_start_us;
2115 dc->dml2_options.svp_pstate.subvp_pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
2116 dc->dml2_options.svp_pstate.subvp_swath_height_margin_lines = dc->caps.subvp_swath_height_margin_lines;
2117
2118 dc->dml2_options.svp_pstate.force_disable_subvp = dc->debug.force_disable_subvp;
2119 dc->dml2_options.svp_pstate.force_enable_subvp = dc->debug.force_subvp_mclk_switch;
2120
2121 dc->dml2_options.mall_cfg.cache_line_size_bytes = dc->caps.cache_line_size;
2122 dc->dml2_options.mall_cfg.cache_num_ways = dc->caps.cache_num_ways;
2123 dc->dml2_options.mall_cfg.max_cab_allocation_bytes = dc->caps.max_cab_allocation_bytes;
2124 dc->dml2_options.mall_cfg.mblk_height_4bpe_pixels = DCN3_2_MBLK_HEIGHT_4BPE;
2125 dc->dml2_options.mall_cfg.mblk_height_8bpe_pixels = DCN3_2_MBLK_HEIGHT_8BPE;
2126 dc->dml2_options.mall_cfg.mblk_size_bytes = DCN3_2_MALL_MBLK_SIZE_BYTES;
2127 dc->dml2_options.mall_cfg.mblk_width_pixels = DCN3_2_MBLK_WIDTH;
2128
2129 dc->dml2_options.max_segments_per_hubp = 20;
2130 dc->dml2_options.det_segment_size = DCN4_01_CRB_SEGMENT_SIZE_KB;
2131
2132 /* SPL */
2133 spl_init_easf_filter_coeffs();
2134 spl_init_blur_scale_coeffs();
2135
2136 return true;
2137
2138 create_fail:
2139
2140 dcn401_resource_destruct(pool);
2141
2142 return false;
2143 }
2144
dcn401_create_resource_pool(const struct dc_init_data * init_data,struct dc * dc)2145 struct resource_pool *dcn401_create_resource_pool(
2146 const struct dc_init_data *init_data,
2147 struct dc *dc)
2148 {
2149 struct dcn401_resource_pool *pool =
2150 kzalloc(sizeof(struct dcn401_resource_pool), GFP_KERNEL);
2151
2152 if (!pool)
2153 return NULL;
2154
2155 if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
2156 return &pool->base;
2157
2158 BREAK_TO_DEBUGGER();
2159 kfree(pool);
2160 return NULL;
2161 }
2162