1  /* SPDX-License-Identifier: MIT */
2  /*
3   * Copyright © 2019 Intel Corporation
4   */
5  
6  #ifndef __INTEL_DPIO_PHY_H__
7  #define __INTEL_DPIO_PHY_H__
8  
9  #include <linux/types.h>
10  
11  enum pipe;
12  enum port;
13  struct drm_i915_private;
14  struct intel_crtc_state;
15  struct intel_digital_port;
16  struct intel_encoder;
17  
18  enum dpio_channel {
19  	DPIO_CH0,
20  	DPIO_CH1,
21  };
22  
23  enum dpio_phy {
24  	DPIO_PHY0,
25  	DPIO_PHY1,
26  	DPIO_PHY2,
27  };
28  
29  #ifdef I915
30  void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
31  			     enum dpio_phy *phy, enum dpio_channel *ch);
32  void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
33  				    const struct intel_crtc_state *crtc_state);
34  void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
35  void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
36  bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
37  			     enum dpio_phy phy);
38  bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
39  			       enum dpio_phy phy);
40  u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
41  void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
42  				      u8 lane_lat_optim_mask);
43  u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder);
44  
45  enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port);
46  enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port);
47  enum dpio_phy vlv_pipe_to_phy(enum pipe pipe);
48  enum dpio_channel vlv_pipe_to_channel(enum pipe pipe);
49  
50  void chv_set_phy_signal_level(struct intel_encoder *encoder,
51  			      const struct intel_crtc_state *crtc_state,
52  			      u32 deemph_reg_value, u32 margin_reg_value,
53  			      bool uniq_trans_scale);
54  void chv_data_lane_soft_reset(struct intel_encoder *encoder,
55  			      const struct intel_crtc_state *crtc_state,
56  			      bool reset);
57  void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
58  			    const struct intel_crtc_state *crtc_state);
59  void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
60  				const struct intel_crtc_state *crtc_state);
61  void chv_phy_release_cl2_override(struct intel_encoder *encoder);
62  void chv_phy_post_pll_disable(struct intel_encoder *encoder,
63  			      const struct intel_crtc_state *old_crtc_state);
64  
65  void vlv_set_phy_signal_level(struct intel_encoder *encoder,
66  			      const struct intel_crtc_state *crtc_state,
67  			      u32 demph_reg_value, u32 preemph_reg_value,
68  			      u32 uniqtranscale_reg_value, u32 tx3_demph);
69  void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
70  			    const struct intel_crtc_state *crtc_state);
71  void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
72  				const struct intel_crtc_state *crtc_state);
73  void vlv_phy_reset_lanes(struct intel_encoder *encoder,
74  			 const struct intel_crtc_state *old_crtc_state);
75  #else
bxt_port_to_phy_channel(struct drm_i915_private * dev_priv,enum port port,enum dpio_phy * phy,enum dpio_channel * ch)76  static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
77  					   enum dpio_phy *phy, enum dpio_channel *ch)
78  {
79  }
bxt_dpio_phy_set_signal_levels(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)80  static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
81  						  const struct intel_crtc_state *crtc_state)
82  {
83  }
bxt_dpio_phy_init(struct drm_i915_private * dev_priv,enum dpio_phy phy)84  static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
85  {
86  }
bxt_dpio_phy_uninit(struct drm_i915_private * dev_priv,enum dpio_phy phy)87  static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
88  {
89  }
bxt_dpio_phy_is_enabled(struct drm_i915_private * dev_priv,enum dpio_phy phy)90  static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
91  					   enum dpio_phy phy)
92  {
93  	return false;
94  }
bxt_dpio_phy_verify_state(struct drm_i915_private * dev_priv,enum dpio_phy phy)95  static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
96  					     enum dpio_phy phy)
97  {
98  	return true;
99  }
bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)100  static inline u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
101  {
102  	return 0;
103  }
bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder * encoder,u8 lane_lat_optim_mask)104  static inline void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
105  						    u8 lane_lat_optim_mask)
106  {
107  }
bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder * encoder)108  static inline u8 bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
109  {
110  	return 0;
111  }
vlv_dig_port_to_channel(struct intel_digital_port * dig_port)112  static inline enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
113  {
114  	return DPIO_CH0;
115  }
vlv_dig_port_to_phy(struct intel_digital_port * dig_port)116  static inline enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
117  {
118  	return DPIO_PHY0;
119  }
vlv_pipe_to_phy(enum pipe pipe)120  static inline enum dpio_phy vlv_pipe_to_phy(enum pipe pipe)
121  {
122  	return DPIO_PHY0;
123  }
vlv_pipe_to_channel(enum pipe pipe)124  static inline enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
125  {
126  	return DPIO_CH0;
127  }
chv_set_phy_signal_level(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,u32 deemph_reg_value,u32 margin_reg_value,bool uniq_trans_scale)128  static inline void chv_set_phy_signal_level(struct intel_encoder *encoder,
129  					    const struct intel_crtc_state *crtc_state,
130  					    u32 deemph_reg_value, u32 margin_reg_value,
131  					    bool uniq_trans_scale)
132  {
133  }
chv_data_lane_soft_reset(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,bool reset)134  static inline void chv_data_lane_soft_reset(struct intel_encoder *encoder,
135  					    const struct intel_crtc_state *crtc_state,
136  					    bool reset)
137  {
138  }
chv_phy_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)139  static inline void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
140  					  const struct intel_crtc_state *crtc_state)
141  {
142  }
chv_phy_pre_encoder_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)143  static inline void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
144  					      const struct intel_crtc_state *crtc_state)
145  {
146  }
chv_phy_release_cl2_override(struct intel_encoder * encoder)147  static inline void chv_phy_release_cl2_override(struct intel_encoder *encoder)
148  {
149  }
chv_phy_post_pll_disable(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state)150  static inline void chv_phy_post_pll_disable(struct intel_encoder *encoder,
151  					    const struct intel_crtc_state *old_crtc_state)
152  {
153  }
154  
vlv_set_phy_signal_level(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state,u32 demph_reg_value,u32 preemph_reg_value,u32 uniqtranscale_reg_value,u32 tx3_demph)155  static inline void vlv_set_phy_signal_level(struct intel_encoder *encoder,
156  					    const struct intel_crtc_state *crtc_state,
157  					    u32 demph_reg_value, u32 preemph_reg_value,
158  					    u32 uniqtranscale_reg_value, u32 tx3_demph)
159  {
160  }
vlv_phy_pre_pll_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)161  static inline void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
162  					  const struct intel_crtc_state *crtc_state)
163  {
164  }
vlv_phy_pre_encoder_enable(struct intel_encoder * encoder,const struct intel_crtc_state * crtc_state)165  static inline void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
166  					      const struct intel_crtc_state *crtc_state)
167  {
168  }
vlv_phy_reset_lanes(struct intel_encoder * encoder,const struct intel_crtc_state * old_crtc_state)169  static inline void vlv_phy_reset_lanes(struct intel_encoder *encoder,
170  				       const struct intel_crtc_state *old_crtc_state)
171  {
172  }
173  #endif
174  
175  #endif /* __INTEL_DPIO_PHY_H__ */
176