1 /* 2 * Copyright 2022 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DML_DML_DCN3_SOC_BB__ 27 #define __DML_DML_DCN3_SOC_BB__ 28 29 #include "dml_top_soc_parameter_types.h" 30 31 static const struct dml2_soc_qos_parameters dml_dcn31_soc_qos_params = { 32 .derate_table = { 33 .system_active_urgent = { 34 .dram_derate_percent_pixel = 22, 35 .dram_derate_percent_vm = 0, 36 .dram_derate_percent_pixel_and_vm = 0, 37 .fclk_derate_percent = 76, 38 .dcfclk_derate_percent = 100, 39 }, 40 .system_active_average = { 41 .dram_derate_percent_pixel = 17, 42 .dram_derate_percent_vm = 0, 43 .dram_derate_percent_pixel_and_vm = 0, 44 .fclk_derate_percent = 57, 45 .dcfclk_derate_percent = 75, 46 }, 47 .dcn_mall_prefetch_urgent = { 48 .dram_derate_percent_pixel = 22, 49 .dram_derate_percent_vm = 0, 50 .dram_derate_percent_pixel_and_vm = 0, 51 .fclk_derate_percent = 76, 52 .dcfclk_derate_percent = 100, 53 }, 54 .dcn_mall_prefetch_average = { 55 .dram_derate_percent_pixel = 17, 56 .dram_derate_percent_vm = 0, 57 .dram_derate_percent_pixel_and_vm = 0, 58 .fclk_derate_percent = 57, 59 .dcfclk_derate_percent = 75, 60 }, 61 .system_idle_average = { 62 .dram_derate_percent_pixel = 17, 63 .dram_derate_percent_vm = 0, 64 .dram_derate_percent_pixel_and_vm = 0, 65 .fclk_derate_percent = 57, 66 .dcfclk_derate_percent = 100, 67 }, 68 }, 69 .writeback = { 70 .base_latency_us = 12, 71 .scaling_factor_us = 0, 72 .scaling_factor_mhz = 0, 73 }, 74 .qos_params = { 75 .dcn4x = { 76 .df_qos_response_time_fclk_cycles = 300, 77 .max_round_trip_to_furthest_cs_fclk_cycles = 350, 78 .mall_overhead_fclk_cycles = 50, 79 .meta_trip_adder_fclk_cycles = 36, 80 .average_transport_distance_fclk_cycles = 257, 81 .umc_urgent_ramp_latency_margin = 50, 82 .umc_max_latency_margin = 30, 83 .umc_average_latency_margin = 20, 84 .fabric_max_transport_latency_margin = 20, 85 .fabric_average_transport_latency_margin = 10, 86 87 .per_uclk_dpm_params = { 88 { 89 .minimum_uclk_khz = 97, 90 .urgent_ramp_uclk_cycles = 472, 91 .trip_to_memory_uclk_cycles = 827, 92 .meta_trip_to_memory_uclk_cycles = 827, 93 .maximum_latency_when_urgent_uclk_cycles = 72, 94 .average_latency_when_urgent_uclk_cycles = 61, 95 .maximum_latency_when_non_urgent_uclk_cycles = 827, 96 .average_latency_when_non_urgent_uclk_cycles = 118, 97 }, 98 { 99 .minimum_uclk_khz = 435, 100 .urgent_ramp_uclk_cycles = 546, 101 .trip_to_memory_uclk_cycles = 848, 102 .meta_trip_to_memory_uclk_cycles = 848, 103 .maximum_latency_when_urgent_uclk_cycles = 146, 104 .average_latency_when_urgent_uclk_cycles = 90, 105 .maximum_latency_when_non_urgent_uclk_cycles = 848, 106 .average_latency_when_non_urgent_uclk_cycles = 135, 107 }, 108 { 109 .minimum_uclk_khz = 731, 110 .urgent_ramp_uclk_cycles = 632, 111 .trip_to_memory_uclk_cycles = 874, 112 .meta_trip_to_memory_uclk_cycles = 874, 113 .maximum_latency_when_urgent_uclk_cycles = 232, 114 .average_latency_when_urgent_uclk_cycles = 124, 115 .maximum_latency_when_non_urgent_uclk_cycles = 874, 116 .average_latency_when_non_urgent_uclk_cycles = 155, 117 }, 118 { 119 .minimum_uclk_khz = 1187, 120 .urgent_ramp_uclk_cycles = 716, 121 .trip_to_memory_uclk_cycles = 902, 122 .meta_trip_to_memory_uclk_cycles = 902, 123 .maximum_latency_when_urgent_uclk_cycles = 316, 124 .average_latency_when_urgent_uclk_cycles = 160, 125 .maximum_latency_when_non_urgent_uclk_cycles = 902, 126 .average_latency_when_non_urgent_uclk_cycles = 177, 127 }, 128 }, 129 }, 130 }, 131 .qos_type = dml2_qos_param_type_dcn4x, 132 }; 133 134 static const struct dml2_soc_bb dml2_socbb_dcn31 = { 135 .clk_table = { 136 .uclk = { 137 .clk_values_khz = {97000, 435000, 731000, 1187000}, 138 .num_clk_values = 4, 139 }, 140 .fclk = { 141 .clk_values_khz = {300000, 2500000}, 142 .num_clk_values = 2, 143 }, 144 .dcfclk = { 145 .clk_values_khz = {200000, 1800000}, 146 .num_clk_values = 2, 147 }, 148 .dispclk = { 149 .clk_values_khz = {100000, 2000000}, 150 .num_clk_values = 2, 151 }, 152 .dppclk = { 153 .clk_values_khz = {100000, 2000000}, 154 .num_clk_values = 2, 155 }, 156 .dtbclk = { 157 .clk_values_khz = {100000, 2000000}, 158 .num_clk_values = 2, 159 }, 160 .phyclk = { 161 .clk_values_khz = {810000, 810000}, 162 .num_clk_values = 2, 163 }, 164 .socclk = { 165 .clk_values_khz = {300000, 1600000}, 166 .num_clk_values = 2, 167 }, 168 .dscclk = { 169 .clk_values_khz = {666667, 666667}, 170 .num_clk_values = 2, 171 }, 172 .phyclk_d18 = { 173 .clk_values_khz = {625000, 625000}, 174 .num_clk_values = 2, 175 }, 176 .phyclk_d32 = { 177 .clk_values_khz = {2000000, 2000000}, 178 .num_clk_values = 2, 179 }, 180 .dram_config = { 181 .channel_width_bytes = 2, 182 .channel_count = 16, 183 .transactions_per_clock = 16, 184 }, 185 }, 186 187 .qos_parameters = { 188 .derate_table = { 189 .system_active_urgent = { 190 .dram_derate_percent_pixel = 22, 191 .dram_derate_percent_vm = 0, 192 .dram_derate_percent_pixel_and_vm = 0, 193 .fclk_derate_percent = 76, 194 .dcfclk_derate_percent = 100, 195 }, 196 .system_active_average = { 197 .dram_derate_percent_pixel = 17, 198 .dram_derate_percent_vm = 0, 199 .dram_derate_percent_pixel_and_vm = 0, 200 .fclk_derate_percent = 57, 201 .dcfclk_derate_percent = 75, 202 }, 203 .dcn_mall_prefetch_urgent = { 204 .dram_derate_percent_pixel = 22, 205 .dram_derate_percent_vm = 0, 206 .dram_derate_percent_pixel_and_vm = 0, 207 .fclk_derate_percent = 76, 208 .dcfclk_derate_percent = 100, 209 }, 210 .dcn_mall_prefetch_average = { 211 .dram_derate_percent_pixel = 17, 212 .dram_derate_percent_vm = 0, 213 .dram_derate_percent_pixel_and_vm = 0, 214 .fclk_derate_percent = 57, 215 .dcfclk_derate_percent = 75, 216 }, 217 .system_idle_average = { 218 .dram_derate_percent_pixel = 17, 219 .dram_derate_percent_vm = 0, 220 .dram_derate_percent_pixel_and_vm = 0, 221 .fclk_derate_percent = 57, 222 .dcfclk_derate_percent = 100, 223 }, 224 }, 225 .writeback = { 226 .base_latency_us = 0, 227 .scaling_factor_us = 0, 228 .scaling_factor_mhz = 0, 229 }, 230 .qos_params = { 231 .dcn4x = { 232 .df_qos_response_time_fclk_cycles = 300, 233 .max_round_trip_to_furthest_cs_fclk_cycles = 350, 234 .mall_overhead_fclk_cycles = 50, 235 .meta_trip_adder_fclk_cycles = 36, 236 .average_transport_distance_fclk_cycles = 260, 237 .umc_urgent_ramp_latency_margin = 50, 238 .umc_max_latency_margin = 30, 239 .umc_average_latency_margin = 20, 240 .fabric_max_transport_latency_margin = 20, 241 .fabric_average_transport_latency_margin = 10, 242 243 .per_uclk_dpm_params = { 244 { 245 // State 1 246 .minimum_uclk_khz = 0, 247 .urgent_ramp_uclk_cycles = 472, 248 .trip_to_memory_uclk_cycles = 827, 249 .meta_trip_to_memory_uclk_cycles = 827, 250 .maximum_latency_when_urgent_uclk_cycles = 72, 251 .average_latency_when_urgent_uclk_cycles = 72, 252 .maximum_latency_when_non_urgent_uclk_cycles = 827, 253 .average_latency_when_non_urgent_uclk_cycles = 117, 254 }, 255 { 256 // State 2 257 .minimum_uclk_khz = 0, 258 .urgent_ramp_uclk_cycles = 546, 259 .trip_to_memory_uclk_cycles = 848, 260 .meta_trip_to_memory_uclk_cycles = 848, 261 .maximum_latency_when_urgent_uclk_cycles = 146, 262 .average_latency_when_urgent_uclk_cycles = 146, 263 .maximum_latency_when_non_urgent_uclk_cycles = 848, 264 .average_latency_when_non_urgent_uclk_cycles = 133, 265 }, 266 { 267 // State 3 268 .minimum_uclk_khz = 0, 269 .urgent_ramp_uclk_cycles = 564, 270 .trip_to_memory_uclk_cycles = 853, 271 .meta_trip_to_memory_uclk_cycles = 853, 272 .maximum_latency_when_urgent_uclk_cycles = 164, 273 .average_latency_when_urgent_uclk_cycles = 164, 274 .maximum_latency_when_non_urgent_uclk_cycles = 853, 275 .average_latency_when_non_urgent_uclk_cycles = 136, 276 }, 277 { 278 // State 4 279 .minimum_uclk_khz = 0, 280 .urgent_ramp_uclk_cycles = 613, 281 .trip_to_memory_uclk_cycles = 869, 282 .meta_trip_to_memory_uclk_cycles = 869, 283 .maximum_latency_when_urgent_uclk_cycles = 213, 284 .average_latency_when_urgent_uclk_cycles = 213, 285 .maximum_latency_when_non_urgent_uclk_cycles = 869, 286 .average_latency_when_non_urgent_uclk_cycles = 149, 287 }, 288 { 289 // State 5 290 .minimum_uclk_khz = 0, 291 .urgent_ramp_uclk_cycles = 632, 292 .trip_to_memory_uclk_cycles = 874, 293 .meta_trip_to_memory_uclk_cycles = 874, 294 .maximum_latency_when_urgent_uclk_cycles = 232, 295 .average_latency_when_urgent_uclk_cycles = 232, 296 .maximum_latency_when_non_urgent_uclk_cycles = 874, 297 .average_latency_when_non_urgent_uclk_cycles = 153, 298 }, 299 { 300 // State 6 301 .minimum_uclk_khz = 0, 302 .urgent_ramp_uclk_cycles = 665, 303 .trip_to_memory_uclk_cycles = 885, 304 .meta_trip_to_memory_uclk_cycles = 885, 305 .maximum_latency_when_urgent_uclk_cycles = 265, 306 .average_latency_when_urgent_uclk_cycles = 265, 307 .maximum_latency_when_non_urgent_uclk_cycles = 885, 308 .average_latency_when_non_urgent_uclk_cycles = 161, 309 }, 310 { 311 // State 7 312 .minimum_uclk_khz = 0, 313 .urgent_ramp_uclk_cycles = 689, 314 .trip_to_memory_uclk_cycles = 895, 315 .meta_trip_to_memory_uclk_cycles = 895, 316 .maximum_latency_when_urgent_uclk_cycles = 289, 317 .average_latency_when_urgent_uclk_cycles = 289, 318 .maximum_latency_when_non_urgent_uclk_cycles = 895, 319 .average_latency_when_non_urgent_uclk_cycles = 167, 320 }, 321 { 322 // State 8 323 .minimum_uclk_khz = 0, 324 .urgent_ramp_uclk_cycles = 716, 325 .trip_to_memory_uclk_cycles = 902, 326 .meta_trip_to_memory_uclk_cycles = 902, 327 .maximum_latency_when_urgent_uclk_cycles = 316, 328 .average_latency_when_urgent_uclk_cycles = 316, 329 .maximum_latency_when_non_urgent_uclk_cycles = 902, 330 .average_latency_when_non_urgent_uclk_cycles = 174, 331 }, 332 }, 333 }, 334 }, 335 .qos_type = dml2_qos_param_type_dcn4x, 336 }, 337 338 .power_management_parameters = { 339 .dram_clk_change_blackout_us = 400, 340 .fclk_change_blackout_us = 0, 341 .g7_ppt_blackout_us = 0, 342 .stutter_enter_plus_exit_latency_us = 50, 343 .stutter_exit_latency_us = 43, 344 .z8_stutter_enter_plus_exit_latency_us = 0, 345 .z8_stutter_exit_latency_us = 0, 346 }, 347 348 .vmin_limit = { 349 .dispclk_khz = 600 * 1000, 350 }, 351 352 .dprefclk_mhz = 700, 353 .xtalclk_mhz = 100, 354 .pcie_refclk_mhz = 100, 355 .dchub_refclk_mhz = 50, 356 .mall_allocated_for_dcn_mbytes = 64, 357 .max_outstanding_reqs = 512, 358 .fabric_datapath_to_dcn_data_return_bytes = 64, 359 .return_bus_width_bytes = 64, 360 .hostvm_min_page_size_kbytes = 0, 361 .gpuvm_min_page_size_kbytes = 256, 362 .phy_downspread_percent = 0, 363 .dcn_downspread_percent = 0, 364 .dispclk_dppclk_vco_speed_mhz = 4500, 365 .do_urgent_latency_adjustment = 0, 366 .mem_word_bytes = 32, 367 .num_dcc_mcaches = 8, 368 .mcache_size_bytes = 2048, 369 .mcache_line_size_bytes = 32, 370 .max_fclk_for_uclk_dpm_khz = 1250 * 1000, 371 }; 372 373 static const struct dml2_ip_capabilities dml2_dcn31_max_ip_caps = { 374 .pipe_count = 4, 375 .otg_count = 4, 376 .num_dsc = 4, 377 .max_num_dp2p0_streams = 4, 378 .max_num_hdmi_frl_outputs = 1, 379 .max_num_dp2p0_outputs = 4, 380 .rob_buffer_size_kbytes = 192, 381 .config_return_buffer_size_in_kbytes = 1152, 382 .meta_fifo_size_in_kentries = 22, 383 .compressed_buffer_segment_size_in_kbytes = 64, 384 .subvp_drr_scheduling_margin_us = 100, 385 .subvp_prefetch_end_to_mall_start_us = 15, 386 .subvp_fw_processing_delay = 15, 387 388 .fams2 = { 389 .max_allow_delay_us = 100 * 1000, 390 .scheduling_delay_us = 50, 391 .vertical_interrupt_ack_delay_us = 18, 392 .allow_programming_delay_us = 18, 393 .min_allow_width_us = 20, 394 .subvp_df_throttle_delay_us = 100, 395 .subvp_programming_delay_us = 18, 396 .subvp_prefetch_to_mall_delay_us = 18, 397 .drr_programming_delay_us = 18, 398 }, 399 }; 400 401 #endif /* __DML_DML_DCN3_SOC_BB__ */ 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